WO2022166093A1 - 半导体结构的制作方法及半导体结构 - Google Patents

半导体结构的制作方法及半导体结构 Download PDF

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WO2022166093A1
WO2022166093A1 PCT/CN2021/103885 CN2021103885W WO2022166093A1 WO 2022166093 A1 WO2022166093 A1 WO 2022166093A1 CN 2021103885 W CN2021103885 W CN 2021103885W WO 2022166093 A1 WO2022166093 A1 WO 2022166093A1
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dielectric layer
layer
semiconductor structure
doped
fabricating
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PCT/CN2021/103885
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English (en)
French (fr)
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张海龙
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长鑫存储技术有限公司
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Priority to US17/613,075 priority Critical patent/US20230369307A1/en
Publication of WO2022166093A1 publication Critical patent/WO2022166093A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Definitions

  • the present disclosure is based on the Chinese patent application with the application number of 202110162126.9 and the application date of February 5, 2021, and the application name is "Method for manufacturing semiconductor structure and semiconductor structure", and claims the priority of the Chinese patent application.
  • the entire contents of the application are hereby incorporated by reference into the present disclosure.
  • the present disclosure relates to, but is not limited to, a method for fabricating a semiconductor structure and a semiconductor structure.
  • Memory is a memory component used to store programs and various data information. According to the use type of memory, it can be divided into read-only memory and random access memory.
  • a memory typically includes a capacitor, which is used to store charge representing the stored information, and a transistor connected to the capacitor, which is a switch that controls the flow of charge into and out of the capacitor.
  • the present disclosure provides a method for fabricating a semiconductor structure and a semiconductor structure.
  • a first aspect of the present disclosure provides a method for fabricating a semiconductor structure, including: providing a substrate having a plurality of mutually spaced capacitive contact structures and a first support layer covering the capacitive contact structures; A first mask layer and a second mask layer are sequentially formed on the support layer, wherein the first mask layer at least includes a first dielectric layer and a second dielectric layer formed in sequence; an etching process is used to remove part of the first dielectric layer.
  • a mask layer, part of the second mask layer and part of the first support layer form a first capacitor hole exposing part of the capacitor contact structure; wherein, under the same etching conditions, the first capacitor
  • the lateral etching rate of the dielectric layer is lower than the lateral etching rate of the second dielectric layer; and a lower electrode layer is formed on the bottom and sidewalls of the first capacitor hole.
  • a second aspect of the present disclosure provides a semiconductor structure, which is fabricated by using the fabrication method of the semiconductor structure of the first aspect.
  • the first mask layer including at least the first dielectric layer and the second dielectric layer is formed on the first support layer, and then the part is removed by an etching process.
  • the lateral etching rate of the first dielectric layer under the same etching conditions is smaller than the lateral etching rate of the second dielectric layer, then within the same etching time, the width of the first dielectric layer removed by the etching process is smaller than the width of the second dielectric layer removed by etching, so that the first dielectric layer formed
  • the capacitor hole has a shape with a wide opening and a narrow bottom, which is beneficial to cover the lower electrode layer on the sidewall and bottom of the first capacitor hole later, so that the lower electrode layer located on the sidewall of the first mask layer and the top of the capacitor contact structure The angle between the lower electrode layers on
  • the dielectric layer When a dielectric layer is subsequently formed on the surface of the lower electrode layer, it is beneficial to ensure that the dielectric layer completely covers the obtuse angle, so as to avoid the upper electrode layer formed on the surface of the dielectric layer at the obtuse angle. It is in contact with the lower electrode layer to avoid short circuit between the lower electrode layer and the upper electrode layer, thereby helping to improve the electrical performance of the semiconductor structure.
  • the formed first capacitor hole has a wide opening and a narrow bottom, that is, the angle between the sidewall and the bottom of the first capacitor hole is an obtuse angle, so that the etching by-products generated by the etching process are not easy to The intersection of the bottom of the first capacitor hole and the sidewall gathers, which is beneficial to remove the etching by-products through the purging step.
  • the first mask layer may further include a third dielectric layer, the third dielectric layer is located between the first dielectric layer and the second dielectric layer, and under the same etching conditions, the first dielectric layer, the third dielectric layer.
  • the lateral etching rate of the layer and the second dielectric layer decreases layer by layer, and as the etching process progresses, it is beneficial to make the lateral etching rate of the first mask layer by the etching process more smoothly from the maximum value to the minimum value, which is favorable for forming the first capacitor hole with better etched topography.
  • FIG. 1 is a schematic cross-sectional structure diagram of a substrate provided in a method for fabricating a semiconductor structure provided in a first embodiment of the present disclosure
  • FIG. 2 is a schematic cross-sectional structural diagram of the structure shown in FIG. 1 after forming a first capacitor hole exposing part of the capacitor contact structure;
  • FIG. 3 is a schematic cross-sectional structure diagram of the structure shown in FIG. 2 after forming a lower electrode layer;
  • FIG. 4 is a schematic cross-sectional structural diagram of the structure shown in FIG. 3 after forming a second capacitor hole;
  • FIG. 5 is a schematic cross-sectional structure diagram of the structure shown in FIG. 4 after forming a dielectric layer
  • FIG. 6 is a schematic cross-sectional structural diagram of the semiconductor structure after forming the upper electrode layer in the structure shown in FIG. 5;
  • FIG. 7 is a schematic cross-sectional structural diagram of a substrate provided in a method for fabricating a semiconductor structure provided in a second embodiment of the present disclosure
  • FIG. 8 is a schematic cross-sectional structural diagram of the structure shown in FIG. 7 after forming a first capacitor hole exposing the capacitor contact structure;
  • FIG. 9 is a schematic cross-sectional structure diagram of the structure shown in FIG. 8 after forming a lower electrode layer on the bottom and sidewalls of the first capacitor hole.
  • a first mask layer and a second mask layer are usually formed on the first support layer in sequence, and the first mask layer is generally a single-layer structure. Etching part of the second mask layer, part of the first mask layer and part of the first support layer until the capacitor contact structure is exposed to form the capacitor hole, due to the gap between the mask used to form the capacitor hole and the capacitor contact structure It is easy to make the size of the opening at the bottom of the capacitor hole larger than the size of the opening at the top of the capacitor hole due to the alignment error and over-etching of the first support layer by the etching process.
  • the intersection of the side wall and the bottom of the capacitor hole is recessed toward the inside of the first support layer to form a thin slit.
  • the surface of the lower electrode layer cannot be completely covered. It is difficult for the dielectric layer to cover the surface of the lower electrode layer located at the slit, so that the lower electrode layer located at the slit is exposed, and the subsequently formed upper electrode layer can be in direct contact with the lower electrode layer at the slit, resulting in capacitor upper and lower electrodes. Shorting of layers, degrades the electrical properties of the semiconductor structure.
  • An embodiment of the present disclosure provides a method for fabricating a semiconductor structure, so that the first mask layer formed includes at least a first dielectric layer and a second dielectric layer, and the subsequent etching process used in forming the first capacitor hole compresses the first mask layer.
  • the lateral etching rate of the dielectric layer is smaller than the lateral etching rate of the second dielectric layer, then in the same etching time, in the direction perpendicular to the substrate surface, the width of the first dielectric layer to be etched is smaller than that of the second dielectric layer.
  • the width of the etching is such that the cross-sectional shape of the area where the first capacitor hole penetrates the first mask layer is an inverted trapezoid shape, so as to avoid the opening size at the bottom of the first capacitor hole being larger than the opening size at the top of the first capacitor hole, and avoiding the first capacitor hole.
  • Thin slits are formed at the intersection of the side wall and the bottom of the capacitor hole, which is beneficial for the subsequent lower electrode layer to completely cover the surface of the first capacitor hole.
  • the first embodiment of the present disclosure provides a method of fabricating a semiconductor structure.
  • the fabrication method of the conductor structure provided by the first embodiment will be described in detail below with reference to the accompanying drawings.
  • 1 to 6 are schematic cross-sectional structural diagrams corresponding to each step of the manufacturing method of the semiconductor structure provided by the first embodiment of the present disclosure.
  • a method of fabricating a semiconductor structure includes: providing a substrate 100 having a plurality of capacitive contact structures 110 spaced apart from each other and a first support layer 120 covering the capacitive contact structures 110 .
  • the substrate 100 further includes structures such as buried word lines, shallow trench isolation structures, active regions, and bit lines, which are omitted because they are irrelevant to this solution.
  • the capacitive contact structure 110 is electrically connected with the active region, and is also electrically connected with the lower electrode layer formed subsequently.
  • the material of the capacitive contact structure 110 includes conductive materials such as polysilicon, titanium nitride, titanium or tungsten.
  • the first support layer 120 is located between adjacent capacitive contact structures 110 , and the first support layer 120 is also located on the top surface of the capacitive contact structures 110 , so that the adjacent capacitive contact structures 110 are in an insulating state.
  • the material of the first support layer 120 includes silicon nitride or silicon boron nitride.
  • a first mask layer 101 and a second mask layer 102 are sequentially formed on the first support layer 120 , wherein the first mask layer 101 includes a first dielectric layer 111 and a second dielectric layer 121 formed in sequence.
  • the materials of the first dielectric layer 111 and the second dielectric layer 121 are both borophosphosilicate glass doped with boron ions, and the concentration of boron ions doped in the first dielectric layer 111 is lower than that doped in the second dielectric layer 121 the concentration of boron ions, so in the subsequent step of forming the first capacitor hole by an etching process, the lateral etching rate of the etching process for the first dielectric layer 111 is lower than the lateral etching rate for the second dielectric layer 121, there are It is beneficial to form the first capacitor hole with the shape of wide opening and narrow bottom.
  • the concentration difference between the boron ions doped in the first dielectric layer 111 and the boron ions doped in the second dielectric layer 121 is 8% ⁇ 10%. In one example, the concentration difference between the boron ions doped in the first dielectric layer 111 and the boron ions doped in the second dielectric layer 121 is 10%, so that when the first capacitor hole is formed, the etching process has no effect on the first capacitor hole. The difference between the lateral etching rate of the dielectric layer 111 and the lateral etching rate of the second dielectric layer 121 is moderate. In the direction of the first mask layer 101 pointing to the substrate 100, it is beneficial to make the opening size of the first capacitor hole formed. The reduction is relatively gentle, so that the sidewall of the first capacitor hole formed is smoother, that is, the first capacitor hole has a good etched appearance.
  • the concentration of boron ions doped in the first dielectric layer 111 is 0%-2%, and the concentration of boron ions doped in the second dielectric layer 121 is 9%-11%.
  • the concentration of doped boron ions in the first dielectric layer 111 is 0%, that is, the first dielectric layer 111 is not doped with boron ions, and the concentration of doped boron ions in the second dielectric layer 121 is 10% %.
  • the first dielectric layer 111 and the second dielectric layer 121 are both doped with phosphorus ions, and the first dielectric layer 111 and the second dielectric layer 121 are borophosphosilicate glass with different concentrations of doped boron ions.
  • the phosphorus ions in the first dielectric layer 111 are beneficial to enhance the fluidity of the first dielectric layer 111 at this time, so that the first dielectric layer 111 is attached to the top surface of the first support layer 120 , so that the top surface of the formed first dielectric layer 111 is flat.
  • the phosphorus ions in the second dielectric layer 121 are beneficial to enhance the fluidity of the second dielectric layer 121 at this time, so that the second dielectric layer 121 is attached to the top surface of the first dielectric layer 111 , so that the top surface of the formed second dielectric layer 121 is flat.
  • the concentrations of phosphorus ions doped in the first dielectric layer 111 and the second dielectric layer 121 are the same.
  • the concentration of phosphorus ions doped in 121 is different, which affects the etching rate of the first dielectric layer 111 and the second dielectric layer 121 by the etching process, and affects the morphology of the finally formed first capacitor hole.
  • the process of forming borophosphosilicate glass with different doped boron ion concentrations is simple and easy, and when the second capacitor hole is subsequently formed, the borophosphosilicate glass is easily etched, which is beneficial to the formation of the second capacitor hole. During the process, the borophosphosilicate glass is completely removed.
  • the process steps of forming the first dielectric layer 111 and the second dielectric layer 121 doped with boron ions and phosphorus ions in the chamber include:
  • the first stage Pour gaseous ethyl orthosilicate, gaseous triethyl phosphate, gaseous triethyl borate and ozone into the chamber, and adjust the temperature and air pressure in the chamber so that gaseous ethyl orthosilicate, gaseous triethyl phosphate and Ethyl ester, gaseous triethyl borate and ozone react on the surface of the first support layer 120 to form the first dielectric layer 111, and then the by-products in the chamber are removed through a purging step.
  • the second stage Pour gaseous ethyl orthosilicate, gaseous triethyl phosphate, gaseous triethyl borate and ozone into the chamber, and adjust the gas flow rate of gaseous triethyl borate introduced in the second stage to be greater than that of the first stage
  • the gas flow rate of the gaseous triethyl borate passed in adjusts the temperature and air pressure in the chamber, so that gaseous ethyl orthosilicate, gaseous triethyl phosphate, gaseous triethyl borate and ozone react on the surface of the first medium layer 111 , the second dielectric layer 121 is formed, and then by-products in the chamber are removed through a purging step.
  • the thickness of the first dielectric layer 111 is 440 nm ⁇ 480 nm. In one example, the thickness of the first dielectric layer 111 is 460 nm. Since the first dielectric layer 111 will be removed when the upper and lower electrode layers of the capacitor are subsequently formed, the thickness of the first dielectric layer 111 should not be too high to avoid additional preparations. In terms of cost, the thickness of the first dielectric layer 111 is set to 460 nm, which is beneficial to avoid high fabrication cost of the semiconductor structure while forming the first capacitor hole with the shape of wide opening and narrow bottom.
  • the second mask layer 102 includes a second support layer 112 , a fourth dielectric layer 122 and a third support layer 132 which are formed in sequence.
  • the second support layer 112 and the third support layer 132 are used to support the lower electrode layer formed subsequently, so as to prevent the lower electrode layer from tilting or collapsing.
  • Materials of the second support layer 112 and the third support layer 132 include silicon nitride or silicon carbonitride. In this embodiment, the materials of the second support layer 112 and the third support layer 132 are the same. In one example, due to the high hardness of silicon carbonitride, the supporting effect for the lower electrode layer is good, and the materials of the second support layer 112 and the third support layer 132 can be both silicon carbonitride. In other embodiments, the materials of the second support layer and the third support layer may be different.
  • the fourth dielectric layer 122 will be removed in a subsequent process of forming structures such as the dielectric layer and the upper electrode layer. For example, the material of the fourth dielectric layer 122 is borophosphosilicate glass.
  • first capacitor hole 11 exposing the capacitor contact structure 110 ; wherein, in the same Under the etching conditions, the lateral etching rate of the first dielectric layer 111 is lower than the lateral etching rate of the second dielectric layer 121 .
  • the first capacitor holes 11 are in one-to-one correspondence with the capacitor contact structures 110 .
  • the difference between the lateral etching rate of the second dielectric layer 121 and the lateral etching rate of the second mask layer 102 is small, so the first capacitor hole 11 penetrates the second mask
  • the size of the openings in the regions of the layer 102 and the second dielectric layer 121 are the same.
  • the lateral etching rate of the etching process for the first dielectric layer 111 is lower than that for the second dielectric layer 121 If the lateral etching rate is higher, then in the direction perpendicular to the surface of the substrate, the etched width of the first dielectric layer 111 is smaller than the etched width of the second dielectric layer 121, so that the first capacitor hole 11 penetrates the first mask layer.
  • the cross-sectional shape of the area of 101 is an inverted trapezoid, which is beneficial to cover the lower electrode layer on the sidewall and bottom of the first capacitor hole 11, so that the lower electrode layer located on the sidewall of the first mask layer and the lower electrode layer located on the sidewall of the first capacitor hole 11.
  • the included angle between the lower electrode layers at the bottom of the hole 11 is an obtuse angle.
  • the angle between the sidewall and the bottom of the first capacitor hole 11 is an obtuse angle, so that the etching by-products generated by the etching process are not easy to accumulate at the intersection of the bottom and the sidewall of the first capacitor hole 11 , It is beneficial to remove the etching by-products through the purging step.
  • the included angle at the intersection of the sidewall and the bottom of the first capacitor hole 11 is 95° ⁇ 120°.
  • a dielectric is formed on the surface of the lower electrode layer.
  • the electric layer due to the poor adhesion effect of the dielectric layer, it is still easy for the dielectric layer to not completely cover the lower electrode layer located at the included angle, so the included angle cannot avoid the contact between the lower electrode layer and the upper electrode layer.
  • the angle is too large, the area of the capacitor contact structure 110 exposed by the first capacitor hole 11 is too small, which will cause the resistance between the capacitor contact structure 110 and the lower electrode layer in the capacitor structure to be too large.
  • the included angle at the intersection of the side wall and the bottom of the first capacitor hole 11 is 110°, which is beneficial to ensure that the subsequent lower electrode layer evenly covers the intersection of the side wall and the bottom of the first capacitor hole 11, and there are also It is favorable for the subsequent dielectric layer to completely cover the intersection of the sidewall and the bottom of the lower electrode layer.
  • the capacitive contact structure 110 and the first mask layer 101 and the second mask layer 102 and the first support layer 120 all have high etching selectivity ratios, so part of the first mask layer is etched 101 , when part of the second mask layer 102 and part of the first support layer 120 , the capacitor contact structure 110 can be used as an etch stop layer to form the first capacitor hole 11 exposing the capacitor contact structure 110 .
  • a lower electrode layer 103 is formed on the bottom and sidewalls of the first capacitor hole 11 (refer to FIG. 2 ).
  • the deposition process is used to form the lower electrode layer 103
  • the lower electrode layer 103 also covers the top surface of the third support layer 132 away from the fourth dielectric layer 122
  • the material of the lower electrode layer 103 includes polysilicon, titanium nitride, titanium Or conductive materials such as tungsten.
  • the method for removing this part of the lower electrode layer 103 may be a chemical mechanical polishing process.
  • part of the third support layer 132 , part of the second support layer 112 , the first mask layer 101 and the fourth dielectric layer 122 are removed to form the second capacitor hole 13 , which is exposed
  • the first support layer 120 , the remaining second support layer 112 and the remaining third support layer 132 are located on the sidewalls of the lower electrode layer 103 .
  • Part of the third support layer 132 is removed by pattern-dry etching to expose the fourth dielectric layer 122 under the third support layer 132 .
  • the inner wall of the lower electrode layer 103 surrounds the through hole 12
  • the lower electrode layer 103 also has an outer wall away from the through hole 12
  • the remaining third support layer 132 is in contact with the outer wall of the lower electrode layer 103 for supporting
  • the lower electrode layer 103 avoids tilting or collapse of the lower electrode layer 103 .
  • the fourth dielectric layer 122 is removed by a wet etching process, and pattern-dry etching is used again to remove part of the second support layer 112 to expose the first mask layer 101 under the second support layer 112, and the remaining
  • the second support layer 112 is in contact with the outer wall of the lower electrode layer 103 for supporting the lower electrode layer 103 and preventing the lower electrode layer 103 from tilting or collapsing.
  • the first mask layer 101 is removed by a wet etching process again.
  • a dielectric layer 104 is formed, and the dielectric layer 104 covers the surface of the lower electrode layer 103 .
  • the method for forming the dielectric layer 104 may be a chemical vapor deposition process or an atomic layer deposition process, and the dielectric layer 104 also covers the remaining surface of the second supporting layer 112 , the remaining surface of the third supporting layer 132 and the first The top surface of the support layer 120 .
  • the dielectric constant of the material forming the dielectric layer 104 is greater than 20, which is beneficial to increase the capacitance of the subsequent capacitor structure composed of the lower electrode layer, the dielectric layer and the upper electrode layer.
  • an upper electrode layer 105 is formed, and the upper electrode layer 105 covers the surface of the dielectric layer 104 .
  • the method for forming the upper electrode layer 105 may also be a chemical vapor deposition process, and the material of the upper electrode layer 105 is the same as that of the lower electrode layer 103 .
  • the first mask layer 101 including the first dielectric layer 111 and the second dielectric layer 121 is formed on the first support layer 120 , and the concentration of boron ions doped in the first dielectric layer 111 is lower than that of the first dielectric layer 111 .
  • the concentration of boron ions doped in the second dielectric layer 121 is lower than that of the first dielectric layer 111 .
  • the lateral etching rate of the first dielectric layer 111 is smaller than the lateral etching rate of the second dielectric layer 121 , then within the same etching time, the width of the first dielectric layer 111 removed by the etching process is smaller than the width of the first dielectric layer 111 removed by the etching process.
  • the width of the second dielectric layer 121 is favorable for forming the first capacitor hole 11 with a wide opening and a narrow bottom.
  • the space between the lower electrode layer 103 located on the sidewall of the first mask layer 101 and the lower electrode layer 103 located on the top surface of the capacitor contact structure 110 is formed.
  • the included angle is an obtuse angle.
  • the dielectric layer 104 is subsequently formed on the surface of the lower electrode layer 103, it is beneficial to ensure that the dielectric layer 104 completely covers the obtuse angle, so as to avoid the subsequent formation of the upper electrode layer 105 on the surface of the dielectric layer 104 at the obtuse angle.
  • the electrode layers 103 are in contact with each other to avoid short circuit between the lower electrode layer 103 and the upper electrode layer 105 , thereby helping to improve the electrical performance of the semiconductor structure.
  • the second embodiment of the present disclosure further provides a method for fabricating a semiconductor structure.
  • This embodiment is substantially the same as the foregoing embodiment, and the main difference is that the process steps for forming the first mask layer are different.
  • the fabrication method of the semiconductor structure provided by the second embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that for the same or corresponding parts as those of the previous embodiments, reference may be made to the detailed descriptions of the previous embodiments, which are omitted here. Repeat.
  • FIG. 7 to 9 are schematic structural diagrams corresponding to each step of a method for fabricating a semiconductor structure provided by the second embodiment of the present disclosure.
  • a substrate 200 is provided, the substrate 200 has a plurality of mutually spaced capacitive contact structures 210 and a first support layer 220 covering the capacitive contact structures 210 , and a first mask layer 201 and a first mask layer 201 are sequentially formed on the first support layer 220
  • the second mask layer 202 includes a second support layer 212 , a fourth dielectric layer 222 and a third support layer 232 formed in sequence.
  • the first mask layer 201 also includes a third dielectric layer 231, and the third dielectric layer 231 is located in the first dielectric layer 211 and the second dielectric layer 221 and under the same etching conditions, the lateral etching rates of the first dielectric layer 211 , the third dielectric layer 231 and the second dielectric layer 221 decrease layer by layer.
  • the third dielectric layer 231 is further formed between the first dielectric layer 211 and the second dielectric layer 221, as the etching process proceeds, it is beneficial to enable the lateral etching of the first mask layer 101 by the etching process The rate decreases more gently from the maximum value to the minimum value, thereby facilitating the formation of the first capacitive hole with better etched topography.
  • the materials of the first dielectric layer 211 , the third dielectric layer 231 and the second dielectric layer 221 are all borophosphosilicate glass doped with boron ions, and the first dielectric layer 211 , the third dielectric layer 231 and the The concentration of the doped boron ions in the second dielectric layer 221 decreases layer by layer, so in the subsequent step of forming the first capacitor hole by an etching process, the etching process can affect the first dielectric layer 111 and the third dielectric layer.
  • the lateral etching rates of the 231 and the second dielectric layer 221 are gradually reduced layer by layer, which is favorable for forming the first capacitor hole with a wide opening and a narrow bottom.
  • the first mask layer may be a stacked structure including three or more dielectric layers, and in the direction of the second mask layer pointing to the substrate, the adjacent dielectric layers in the first mask layer are doped
  • the concentration of impurity boron ions decreases layer by layer. It should be noted that, this embodiment does not limit the number of dielectric layers included in the first mask layer.
  • the concentration difference between the boron ions doped in the third dielectric layer 231 and the boron ions doped in the first dielectric layer 211 is 4%-6%, and the boron ions doped in the third dielectric layer 231 and The concentration difference of boron ions doped in the second dielectric layer 221 is 4% ⁇ 6%.
  • the concentration difference between the boron ions doped in the third dielectric layer 231 and the boron ions doped in the first dielectric layer 211 is 5%, and the boron ions doped in the third dielectric layer 231 and the second The concentration difference of boron ions doped in the dielectric layer 221 is also 5%.
  • the difference in the concentration of boron ions doped between adjacent layers in the first mask layer 201 is small, which is beneficial to make the lateral etching rate of the first mask layer 201 in the subsequent etching process decrease more gently from the maximum value
  • the opening size of the formed first capacitor hole is further reduced gently, which further ensures that the first capacitor hole has a good etching profile.
  • the concentration of boron ions doped in the first dielectric layer 211 is 0%-2%
  • the concentration of boron ions doped in the third dielectric layer 231 is 4%-6%
  • the second dielectric layer 221 The concentration of boron ions doped in the medium is 9% to 11%.
  • the concentration of doped boron ions in the first dielectric layer 211 is 0%, that is, the first dielectric layer 211 is not doped with boron ions
  • the concentration of doped boron ions in the third dielectric layer 231 is 5% %
  • the concentration of boron ions doped in the second dielectric layer 221 is 10%.
  • the first dielectric layer 211 , the third dielectric layer 231 and the second dielectric layer 221 are all doped with phosphorus ions, and the first dielectric layer 211 , the third dielectric layer 231 and the second dielectric layer 221 are doped with phosphorus ions.
  • Borophosphosilicate glasses with different concentrations of dopant boron ions are also doped with Borophosphosilicate glasses with different concentrations of dopant boron ions.
  • phosphorus ions are beneficial to enhance the fluidity of the first dielectric layer 211, the third dielectric layer 231 and the second dielectric layer 221 at this time , so that the first dielectric layer 211 is attached to the top surface of the first support layer 220 , the third dielectric layer 231 is attached to the top surface of the first dielectric layer 211 , and the second dielectric layer 221 is attached to the top surface of the third dielectric layer 231 .
  • the top surfaces of the first dielectric layer 211 , the third dielectric layer 231 and the second dielectric layer 221 are all relatively flat.
  • the concentrations of phosphorus ions doped in the first dielectric layer 211 , the third dielectric layer 231 and the second dielectric layer 221 are the same.
  • the first dielectric layer 211 , the third dielectric layer 231 and the second dielectric layer 221 doped with boron ions and phosphorus ions are formed in the chamber.
  • the first stage Pour gaseous ethyl orthosilicate, gaseous triethyl phosphate, gaseous triethyl borate and ozone into the chamber, and adjust the temperature and air pressure in the chamber so that gaseous ethyl orthosilicate, gaseous triethyl phosphate and Ethyl ester, gaseous triethyl borate and ozone react on the surface of the first support layer 220 to form the first dielectric layer 211, and then the by-products in the chamber are removed through a purging step.
  • the second stage Pour gaseous ethyl orthosilicate, gaseous triethyl phosphate, gaseous triethyl borate and ozone into the chamber, and adjust the gas flow rate of gaseous triethyl borate introduced in the second stage to be greater than that of the first stage
  • the gas flow rate of the gaseous triethyl borate passed in adjusts the temperature and air pressure in the chamber, so that gaseous ethyl orthosilicate, gaseous triethyl phosphate, gaseous triethyl borate and ozone react on the surface of the first medium layer 211 , the third dielectric layer 231 is formed, and then by-products in the chamber are removed through a purging step.
  • the third stage Pour gaseous ethyl orthosilicate, gaseous triethyl phosphate, gaseous triethyl borate and ozone into the chamber, and adjust the gas flow rate of gaseous triethyl borate introduced in the third stage to be greater than that in the second stage
  • the gas flow rate of the gaseous triethyl borate passed in adjusts the temperature and air pressure in the chamber, so that gaseous ethyl orthosilicate, gaseous triethyl phosphate, gaseous triethyl borate and ozone react on the surface of the third medium layer 231 , the second dielectric layer 221 is formed, and then by-products in the chamber are removed through a purging step.
  • the total thickness of the first dielectric layer 211 and the third dielectric layer 231 is 440 nm ⁇ 480 nm. In one example, the first dielectric layer 211 and the third dielectric layer 231 The total thickness is 460nm.
  • part of the first mask layer 201 , part of the second mask layer 202 and part of the first support layer 220 are removed by an etching process to form a first capacitor hole 21 exposing the capacitor contact structure 210 ; wherein, in the same Under the etching conditions, the lateral etching rates of the first dielectric layer 211 , the third dielectric layer 231 and the second dielectric layer 221 decrease layer by layer.
  • the included angle at the intersection of the sidewall and the bottom of the first capacitor hole 21 is 95° ⁇ 120°.
  • the included angle is too small, after the lower electrode layer is subsequently formed at the included angle, the lower electrode layer When a dielectric layer is formed on the surface, due to the poor adhesion effect of the dielectric layer, it is still easy for the dielectric layer to not completely cover the lower electrode layer located at the included angle, and the included angle cannot avoid the lower electrode layer and the upper electrode layer.
  • the included angle at the intersection of the side wall and the bottom of the first capacitor hole 21 is 110°, which is beneficial to ensure that the subsequent lower electrode layer evenly covers the intersection of the side wall and the bottom of the first capacitor hole 21, and there are also It is favorable for the subsequent dielectric layer to completely cover the intersection of the sidewall and the bottom of the lower electrode layer.
  • a lower electrode layer 203 is formed on the bottom and sidewalls of the first capacitor hole 21 (refer to FIG. 8 ).
  • the lower electrode layer 203 also covers the top surface of the third support layer 232 away from the fourth dielectric layer 222 , and subsequently removes part of the third support layer 232 , part of the second support layer 212 , the fourth dielectric layer 222 and the third support layer 222 .
  • a mask layer 201 is used to remove the lower electrode layer 203 covering the top surface of the third support layer 232 before the dielectric layer and the upper electrode layer are sequentially formed on the surface of the lower electrode layer 203 .
  • the first mask layer 201 not only includes the first dielectric layer 211 and the second dielectric layer 221, but also has a third dielectric layer 231 formed between the first dielectric layer 211 and the second dielectric layer 221, and The concentrations of doped boron ions in the first dielectric layer 211 , the third dielectric layer 231 and the second dielectric layer 221 decrease layer by layer.
  • the concentration difference of boron ions doped between adjacent layers in the first mask layer 201 it is beneficial to make the lateral etching rate of the first mask layer 201 in the subsequent etching process more gently reduce from the maximum value to The minimum value, in the direction in which the first mask layer 201 points to the substrate 200 , the opening size of the first capacitor hole 21 to be formed is further reduced gently, and the first capacitor hole 21 is further ensured to have a shape with a wide opening and a narrow bottom. appearance.
  • the third embodiment of the present disclosure further provides a semiconductor structure, which is fabricated by the fabrication method provided in any of the foregoing embodiments.
  • the semiconductor structure includes: a substrate 100 with a plurality of capacitive contact structures 110 spaced from each other on the substrate 100 ; a first support layer 120 , the first support layer 120 covers the sidewalls and part of the upper surface of the capacitive contact structure 110 ;
  • the electrode layer 103 the bottom and sidewalls of the lower electrode layer 103 form a through hole, the bottom of the lower electrode layer 103 is in contact with a part of the top of the capacitor contact structure 110, and the part of the sidewall of the lower electrode layer 103 away from the through hole and the first support
  • the layers 120 abut against each other, and in a direction perpendicular to the surface of the substrate 100 , the size of the opening at the bottom of the via is smaller than the size of the opening at the top of the via.
  • the semiconductor structure further includes: a second support layer 112, the second support layer 112 is located above the substrate 100 and has a distance from the substrate; a third support layer 132, the third support layer 132 is located above the second support layer 112, And there is a distance from the second support layer 112, and both the second support layer 112 and the third support layer 132 are in contact with a part of the sidewall of the lower electrode layer 103 away from the through hole; the dielectric layer 104, the dielectric layer 104 is conformally Cover the surface of the structure formed by the lower electrode layer 103 , the second support layer 112 and the third support layer 132 ; the upper electrode layer 105 conformally covers the surface of the dielectric layer 104 .
  • the angle between the bottom and the sidewall of the through hole surrounded by the bottom of the lower electrode layer 103 and the sidewall is an obtuse angle, for example, the obtuse angle is 95° ⁇ 120°, which is beneficial for the dielectric layer 104
  • the surface of the lower electrode layer 103 is completely covered, so as to avoid the contact between the upper electrode layer 105 and the lower electrode layer 103, so as to improve the electrical performance of the semiconductor structure.
  • the first mask layer including at least the first dielectric layer and the second dielectric layer is formed on the first support layer, and then the part is removed by an etching process.
  • the lateral etching rate of the first dielectric layer under the same etching conditions is smaller than the lateral etching rate of the second dielectric layer, then within the same etching time, the width of the first dielectric layer removed by the etching process is smaller than the width of the second dielectric layer removed by etching, so that the first dielectric layer formed
  • the capacitor hole has a shape with a wide opening and a narrow bottom, which is beneficial to cover the lower electrode layer on the sidewall and bottom of the first capacitor hole later, so that the lower electrode layer located on the sidewall of the first mask layer and the top of the capacitor contact structure The angle between the lower electrode layers on
  • the dielectric layer When the dielectric layer is subsequently formed on the surface of the lower electrode layer, it is beneficial to ensure that the dielectric layer completely covers the obtuse angle, and avoids the subsequent formation of the upper electrode layer on the surface of the dielectric layer at the obtuse angle. It is in contact with the lower electrode layer to avoid short circuit between the lower electrode layer and the upper electrode layer, thereby helping to improve the electrical performance of the semiconductor structure.
  • the first capacitor hole formed has a wide opening and a narrow bottom, that is, the angle between the sidewall and the bottom of the first capacitor hole is an obtuse angle, so that the etching by-products generated by the etching process are not easy to The intersection of the bottom of the first capacitor hole and the sidewall gathers, which is beneficial to remove the etching by-products through the purging step.
  • the first mask layer may further include a third dielectric layer, the third dielectric layer is located between the first dielectric layer and the second dielectric layer, and under the same etching conditions, the first dielectric layer, the third dielectric layer The lateral etching rate of the layer and the second dielectric layer decreases layer by layer. As the etching process proceeds, it is beneficial to make the lateral etching rate of the first mask layer by the etching process more smoothly from the maximum value to the minimum value, which is favorable for forming the first capacitor hole with better etched topography.

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Abstract

本公开提供一种半导体结构的制作方法及半导体结构，半导体结构的制作方法包括：提供基底，基底具有多个相互间隔的电容接触结构和覆盖电容接触结构的第一支撑层；于第一支撑层上依次形成第一掩膜层和第二掩膜层，其中，第一掩膜层至少包括依次形成的第一介质层和第二介质层；利用刻蚀工艺去除部分第一掩膜层、部分第二掩膜层和部分第一支撑层，形成暴露部分电容接触结构的第一电容孔；其中，在相同的刻蚀条件下，第一介质层的横向刻蚀速率小于第二介质层的横向刻蚀速率；于第一电容孔的底部和侧壁形成下电极层。

Description

半导体结构的制作方法及半导体结构
本公开基于申请号为202110162126.9，申请日为2021年02月05日，申请名称为“半导体结构的制作方法及半导体结构”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种半导体结构的制作方法及半导体结构。
背景技术
存储器是用来存储程序和各种数据信息的记忆部件，按存储器的使用类型可分为只读存储器和随机存取存储器。存储器通常包括电容以及与电容连接的晶体管，电容用来存储代表存储信息的电荷，晶体管是控制电容的电荷流入和释放的开关。
随着存储器工艺节点的不断缩小，由于用于制作电容下电极的电容孔的深宽比逐渐变大，刻蚀形成电容孔时，电容孔的尺寸精度难以控制，容易在电容孔底部形成细缝，不利于后续在电容孔的基础上形成被介电层完全间隔开的电容上下电极，易导致电容上下电极之间短路，从而影响半导体结构的电学性能。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供一种半导体结构的制作方法及半导体结构。
本公开的第一方面提供一种半导体结构的制作方法，包括：提供基底，所述基底具有多个相互间隔的电容接触结构和覆盖所述电容接触结构的第一支撑层；于所述第一支撑层上依次形成第一掩膜层和第二掩膜层，其中，所述第一掩膜层至少包括依次形成的第一介质层和第二介质 层；利用刻蚀工艺去除部分所述第一掩膜层、部分所述第二掩膜层和部分所述第一支撑层，形成暴露部分所述电容接触结构的第一电容孔；其中，在相同的刻蚀条件下，所述第一介质层的横向刻蚀速率小于所述第二介质层的横向刻蚀速率；于所述第一电容孔的底部和侧壁形成下电极层。
本公开的第二方面提供一种半导体结构，所述半导体结构采用第一方面的半导体结构的制作方法制成。
本公开实施例所提供的半导体结构的制作方法及半导体结构中，通过在第一支撑层上形成至少包括第一介质层和第二介质层的第一掩膜层，后续利用刻蚀工艺去除部分第一掩膜层、部分第二掩膜层和部分第一支撑层，形成暴露部分电容接触结构的第一电容孔时，由于在相同的刻蚀条件下，第一介质层的横向刻蚀速率小于第二介质层的横向刻蚀速率，则相同刻蚀时间内，该刻蚀工艺刻蚀去除的第一介质层的宽度小于刻蚀去除的第二介质层的宽度，从而使得形成的第一电容孔呈开口宽、底部窄的形貌，有利于后续在第一电容孔的侧壁和底部均覆盖下电极层，使得位于第一掩膜层侧壁的下电极层与位于电容接触结构顶面的下电极层之间的夹角为钝角，后续在下电极层表面形成介电层时，有利于保证介电层完全覆盖该钝角，避免后续在介电层表面形成的上电极层在该钝角处与下电极层相接触，避免下电极层和上电极层之间短路，从而有利于提高半导体结构的电学性能。此外，由于形成的第一电容孔呈开口宽、底部窄的形貌，即第一电容孔的侧壁与底部之间的夹角为钝角，使刻蚀工艺产生的刻蚀副产物不容易在第一电容孔底部与侧壁相交处聚集，有利于通过吹扫步骤将刻蚀副产物去除干净。
另外，第一掩膜层中还可以包括第三介质层，第三介质层位于第一介质层和第二介质层之间，且在相同的刻蚀条件下，第一介质层、第三介质层和第二介质层的横向刻蚀速率逐层减小，随着刻蚀工艺的进行，有利于使得刻蚀工艺对第一掩膜层的横向刻蚀速率从最大值更平缓地减小到最小值，从而有利于形成刻蚀形貌更良好的第一电容孔。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1为本公开第一实施例提供的一种半导体结构的制作方法中提供的基底的剖面结构示意图；
图2为图1所示出的结构中形成暴露部分电容接触结构的第一电容孔后的剖面结构示意图；
图3为图2所示出的结构中形成下电极层后的剖面结构示意图；
图4为图3所示出的结构中形成第二电容孔后的剖面结构示意图；
图5为图4所示出的结构中形成介电层后的剖面结构示意图；
图6为图5所示出的结构中形成上电极层后的半导体结构的剖面结构示意图；
图7为本公开第二实施例提供的一种半导体结构的制作方法中提供的基底的剖面结构示意图；
图8为图7所示出的结构中形成暴露电容接触结构的第一电容孔后的剖面结构示意图；
图9为图8所示出的结构中于第一电容孔的底部和侧壁形成下电极层后的剖面结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
由背景技术可知，现有技术的半导体结构的良率和电学性能均有待提高。
经分析发现，为形成深宽比较大的电容孔，通常会在第一支撑层上依次形成第一掩膜层和第二掩膜层，且第一掩膜层一般为单层结构。刻蚀部分第二掩膜层，部分第一掩膜层和部分第一支撑层，直至露出电容接触结构，以形成电容孔时，由于用于形成电容孔的掩膜版与电容接触结构之间的对准误差和刻蚀工艺对第一支撑层的过刻蚀，容易使电容孔底部的开口尺寸大于电容孔顶部的开口尺寸。电容孔的侧壁与底部相交处会朝第一支撑层内部凹陷，形成细缝。后续在电容孔表面依次形成下电极层和高介电常数的介电层时，由于高介电常数的介电层的粘附性差，无法完全覆盖下电极层表面，例如，高介电常数的介电层难以覆盖位于细缝处的下电极层表面，使得位于细缝处的下电极层暴露出来，则后续形成的上电极层在细缝处可以与下电极层直接接触，造成电容上下电极层的短路，降低半导体结构的电学性能。
本公开实施例提供一种半导体结构的制作方法，使得形成的第一掩膜层至少包括第一介质层和第二介质层，且后续为形成第一电容孔时采用的刻蚀工艺对第一介质层的横向刻蚀速率小于对第二介质层的横向刻蚀速率，则相同刻蚀时间内，在垂直于基底表面的方向上，第一介质层被刻蚀的宽度小于第二介质层被刻蚀的宽度，使得第一电容孔贯穿第一掩膜层的区域的剖面形状为倒梯形形貌，从而避免第一电容孔底部的开口尺寸大于第一电容孔顶部的开口尺寸，避免第一电容孔的侧壁与底部相交处产生细缝，有利于后续下电极层完全覆盖第一电容孔表面。在形成下电极层之后，位于第一掩膜层侧壁的下电极层与位于第一电容孔底部的下电极层之间的夹角为钝角，后续在下电极层表面形成介电层时，有利于保证介电层完全覆盖该钝角，避免后续在介电层表面形成的上电极层在该钝角处与下电极层相接触，避免下电极层和上电极层之间短路，从而有利于提高半导体结构的电学性能。
本公开第一实施例提供一种半导体结构的制作方法，以下将结合附图对第一实施例提供的导体结构的制作方法进行详细说明。图1至图6为本公开第一实施例提供的半导体结构的制作方法各步骤对应的剖面结构示意图。
参考图1，半导体结构的制作方法包括：提供基底100，基底100具有多个相互间隔的电容接触结构110和覆盖电容接触结构110的第一支撑层120。
本实施例中，基底100内还包括埋入式字线、浅沟槽隔离结构、有源区和位线等结构，由于和本方案无关，故省略。电容接触结构110与有源区之 间电连接，且还与后续形成的下电极层之间电连接。例如，电容接触结构110的材料包括多晶硅、氮化钛、钛或者钨等导电材料。第一支撑层120位于相邻的电容接触结构110之间，且第一支撑层120还位于电容接触结构110的顶面，使得相邻的电容接触结构110之间处于绝缘状态。例如，第一支撑层120的材料包括氮化硅或者氮硼化硅。
于第一支撑层120上依次形成第一掩膜层101和第二掩膜层102，其中，第一掩膜层101包括依次形成的第一介质层111和第二介质层121。
第一介质层111和第二介质层121的材料均为掺杂有硼离子的硼磷硅玻璃，且第一介质层111中掺杂的硼离子的浓度小于第二介质层121中掺杂的硼离子的浓度，因而在后续采用刻蚀工艺形成第一电容孔的步骤中，该刻蚀工艺对第一介质层111的横向刻蚀速率小于对第二介质层121的横向刻蚀速率，有利于形成呈开口宽、底部窄的形貌的第一电容孔。
本实施例中，第一介质层111中掺杂的硼离子和第二介质层121中掺杂的硼离子的浓度差为8％～10％。在一个例子中，第一介质层111中掺杂的硼离子和第二介质层121中掺杂的硼离子的浓度差为10％，则使得形成第一电容孔时，刻蚀工艺对第一介质层111的横向刻蚀速率和对第二介质层121的横向刻蚀速率的差异适中，在第一掩膜层101指向基底100的方向上，有利于使得形成的第一电容孔的开口尺寸较平缓地减小，使得形成的第一电容孔的侧壁较平滑，即第一电容孔具有良好的刻蚀形貌。
本实施例中，第一介质层111中掺杂的硼离子的浓度为0％～2％，第二介质层121中掺杂的硼离子的浓度为9％～11％。在一个例子中，第一介质层111中掺杂的硼离子的浓度为0％，即第一介质层111中未掺杂硼离子，第二介质层121中掺杂的硼离子的浓度为10％。
本实施例中，第一介质层111和第二介质层121中均掺杂有磷离子，第一介质层111和第二介质层121为掺杂的硼离子浓度不同的硼磷硅玻璃。在形成第一介质层111的过程中，第一介质层111中的磷离子有利于增强此时第一介质层111的流动性，使得第一介质层111贴附于第一支撑层120顶面，使得形成的第一介质层111的顶面形貌平坦。在形成第二介质层121的过程中，第二介质层121中的磷离子有利于增强此时第二介质层121的流动性，使得第二介质层121贴附于第一介质层111顶面，使得形成的第二介质层121 的顶面形貌平坦。
本实施例中，第一介质层111和第二介质层121中掺杂的磷离子的浓度相同，后续采用刻蚀工艺形成第一电容孔时，避免由于第一介质层111和第二介质层121中掺杂的磷离子的浓度不同，影响刻蚀工艺对第一介质层111和第二介质层121的刻蚀速率，影响最终形成的第一电容孔的形貌。
本实施例中，形成掺杂的硼离子浓度不同的硼磷硅玻璃的工艺操作简便，且后续形成第二电容孔时，硼磷硅玻璃容易被刻蚀，有利于在形成第二电容孔的工艺中，将硼磷硅玻璃完全去除。
在腔室中形成掺杂有硼离子和磷离子的第一介质层111和第二介质层121的工艺步骤包括：
第一阶段：向腔室中通入气态正硅酸乙酯、气态磷酸三乙酯、气态硼酸三乙酯以及臭氧，调节腔室内的温度和气压，使得气态正硅酸乙酯、气态磷酸三乙酯、气态硼酸三乙酯以及臭氧在第一支撑层120表面发生反应，形成第一介质层111，然后通过吹扫步骤，去除腔室中的副产物。
第二阶段：向腔室中通入气态正硅酸乙酯、气态磷酸三乙酯、气态硼酸三乙酯以及臭氧，调节第二阶段通入的气态硼酸三乙酯的气体流量大于第一阶段通入的气态硼酸三乙酯的气体流量，调节腔室内的温度和气压，使得气态正硅酸乙酯、气态磷酸三乙酯、气态硼酸三乙酯以及臭氧在第一介质层111表面发生反应，形成第二介质层121，然后通过吹扫步骤，去除腔室中的副产物。
本实施例中，在垂直于基底100表面的方向上，第一介质层111的厚度为440nm～480nm。在一个例子中，第一介质层111的厚度为460nm，由于后续形成电容上下电极层时，会去除第一介质层111，所以第一介质层111的厚度不宜过高，以避免增加额外的制备成本，将第一介质层111的厚度设置为460nm，有利于在形成呈开口宽、底部窄形貌的第一电容孔的同时，避免半导体结构的制备成本过高。
本实施例中，第二掩膜层102包括依次形成的第二支撑层112、第四介质层122和第三支撑层132。
第二支撑层112和第三支撑层132用于支撑后续形成的下电极层，避免下电极层发生倾斜或坍塌。第二支撑层112和第三支撑层132的材料包括氮 化硅或者碳氮化硅。本实施例中，第二支撑层112和第三支撑层132的材料相同。在一个例子中，由于碳氮化硅的硬度较高，对下电极层的支撑效果好，第二支撑层112和第三支撑层132的材料可以均为碳氮化硅。在其他实施例中，第二支撑层和第三支撑层的材料可以不同。第四介质层122在后续形成介电层和上电极层等结构的过程中会被去除。例如，第四介质层122材料为硼磷硅玻璃。
参考图2，利用刻蚀工艺去除部分第一掩膜层101、部分第二掩膜层102和部分第一支撑层120，形成暴露电容接触结构110的第一电容孔11；其中，在相同的刻蚀条件下，第一介质层111的横向刻蚀速率小于第二介质层121的横向刻蚀速率。第一电容孔11与电容接触结构110一一对应。
本实施例中，相同刻蚀条件下，第二介质层121的横向刻蚀速率和第二掩膜层102的横向刻蚀速率之间差异较小，则第一电容孔11贯穿第二掩膜层102和第二介质层121的区域的开口尺寸一致。由于第一介质层111中掺杂的硼离子的浓度小于第二介质层121中掺杂的硼离子的浓度，刻蚀工艺对第一介质层111的横向刻蚀速率小于对第二介质层121的横向刻蚀速率，则在垂直于基底表面的方向上，第一介质层111被刻蚀的宽度小于第二介质层121被刻蚀的宽度，使得第一电容孔11贯穿第一掩膜层101的区域的剖面形状为倒梯形形貌，有利于后续在第一电容孔11的侧壁和底部均覆盖下电极层，使得位于第一掩膜层侧壁的下电极层与位于第一电容孔11底部的下电极层之间的夹角为钝角，后续在下电极层表面形成介电层时，有利于保证介电层完全覆盖该钝角，避免后续在介电层表面形成的上电极层在该钝角处与下电极层相接触，避免下电极层和上电极层之间短路，从而有利于提高半导体结构的电学性能。
本实施例中，第一电容孔11的侧壁与底部之间的夹角为钝角，使刻蚀工艺产生的刻蚀副产物不容易在第一电容孔11的底部与侧壁相交处聚集，有利于通过吹扫步骤将刻蚀副产物去除干净。
例如，第一电容孔11的侧壁与底部相交处的夹角为95°～120°，当该夹角角度过小时，后续在该夹角处形成下电极层后，在下电极层表面形成介电层时，由于介电层的贴附效果较差，仍然容易使得介电层无法完全覆盖位于该夹角处的下电极层，则该夹角起不到避免下电极层和上电极层之间短路 的作用；当该夹角角度过大时，第一电容孔11暴露的电容接触结构110的面积过小，会导致电容接触结构110和电容结构中的下电极层之间的电阻过大，影响半导体结构的电学性能。在一个例子中，第一电容孔11的侧壁与底部相交处的夹角为110°，有利于保证后续下电极层均匀地覆盖第一电容孔11的侧壁与底部的相交处，也有利于后续介电层完全覆盖下电极层的侧壁与底部的相交处。
本实施例中，电容接触结构110和第一掩膜层101、第二掩膜层102与第一支撑层120之间均具有较高的刻蚀选择比，因而刻蚀部分第一掩膜层101、部分第二掩膜层102和部分第一支撑层120时，能够以电容接触结构110为刻蚀停止层，以形成露出电容接触结构110的第一电容孔11。
参考图3，于第一电容孔11(参考图2)的底部和侧壁形成下电极层103。
本实施例中，采用沉积工艺形成下电极层103，下电极层103还覆盖第三支撑层132远离第四介质层122的顶面，且下电极层103的材料包括多晶硅、氮化钛、钛或者钨等导电材料。后续在去除部分第三支撑层132、部分第二支撑层112、第四介质层122和第一掩膜层101，以在下电极层103表面依次形成介电层和上电极层之前，去除覆盖在第三支撑层132顶面的下电极层103，例如，去除此部分下电极层103的方法可以为化学机械研磨工艺。
结合参考图3和图4，去除部分第三支撑层132、部分第二支撑层112、第一掩膜层101和第四介质层122，以形成第二电容孔13，第二电容孔13暴露第一支撑层120，剩余的第二支撑层112和剩余的第三支撑层132位于下电极层103的侧壁。
采用图案-干法刻蚀，去除部分第三支撑层132，以暴露出位于第三支撑层132下方的第四介质层122。本实施例中，下电极层103的内壁围成通孔12，下电极层103还具有远离通孔12的外壁，剩余的第三支撑层132与下电极层103的外壁相抵接，用于支撑下电极层103，避免下电极层103的倾斜或坍塌。
采用湿法刻蚀工艺去除第四介质层122，再次采用图案-干法刻蚀，去除部分第二支撑层112，以暴露出位于第二支撑层112下方的第一掩膜层101，剩余的第二支撑层112与下电极层103的外壁相抵接，用于支撑下电极层103，避免下电极层103的倾斜或坍塌。再次采用湿法刻蚀工艺去除第一掩膜层 101。
参考图5，形成介电层104，介电层104覆盖下电极层103的表面。本实施例中，形成介电层104的方法可以为化学气相沉积工艺或原子层沉积工艺，介电层104还覆盖剩余的第二支撑层112表面、剩余的第三支撑层132表面和第一支撑层120的顶面。
本实施例中，形成介电层104的材料的介电常数大于20，有利于提高后续由下电极层、介电层和上电极层构成的电容结构的电容量。
参考图6，形成上电极层105，上电极层105覆盖介电层104表面。本实施例中，形成上电极层105的方法也可以为化学气相沉积工艺，且上电极层105的材料与下电极层103的材料相同。
本实施例中，通过在第一支撑层120上形成包括第一介质层111和第二介质层121的第一掩膜层101，且第一介质层111中掺杂的硼离子的浓度小于第二介质层121中掺杂的硼离子的浓度。后续利用刻蚀工艺形成第一电容孔11时，由于第一介质层111中掺杂的硼离子的浓度小于第二介质层121中掺杂的硼离子的浓度，则在相同的刻蚀条件下，第一介质层111的横向刻蚀速率小于第二介质层121的横向刻蚀速率，则相同刻蚀时间内，该刻蚀工艺刻蚀去除的第一介质层111的宽度小于刻蚀去除的第二介质层121的宽度，有利于形成呈开口宽、底部窄形貌的第一电容孔11。后续在第一电容孔11的侧壁和底部均覆盖下电极层103时，位于第一掩膜层101侧壁的下电极层103与位于电容接触结构110顶面的下电极层103之间的夹角为钝角，后续在下电极层103表面形成介电层104时，有利于保证介电层104完全覆盖该钝角，避免后续在介电层104表面形成的上电极层105在该钝角处与下电极层103相接触，避免下电极层103和上电极层105之间短路，从而有利于提高半导体结构的电学性能。
本公开第二实施例还提供一种半导体结构的制作方法，该实施例与前述实施例大致相同，主要区别在于形成第一掩膜层的工艺步骤不同。以下将结合附图对本公开第二实施例提供的半导体结构的制作方法进行详细说明，需要说明的是，与前述实施例相同或者相应的部分，可参考前述实施例的详细描述，在此不再赘述。
图7至图9为本公开第二实施例提供的一种半导体结构的制作方法各步 骤对应的结构示意图。
参考图7，提供基底200，基底200具有多个相互间隔的电容接触结构210和覆盖电容接触结构210的第一支撑层220，于第一支撑层220上依次形成第一掩膜层201和第二掩膜层202，第二掩膜层202包括依次形成的第二支撑层212、第四介质层222和第三支撑层232。
其中，第一掩膜层201中除了包括第一介质层211和第二介质层221之外，还包括第三介质层231，第三介质层231位于第一介质层211和第二介质层221之间，且在相同的刻蚀条件下，第一介质层211、第三介质层231和第二介质层221的横向刻蚀速率逐层减小。由于在第一介质层211和第二介质层221之间还形成有第三介质层231，则随着刻蚀工艺的进行，有利于使得刻蚀工艺对第一掩膜层101的横向刻蚀速率从最大值更平缓地减小到最小值，从而有利于形成刻蚀形貌更良好的第一电容孔。
本实施例中，第一介质层211、第三介质层231和第二介质层221的材料均为掺杂有硼离子的硼磷硅玻璃，且第一介质层211、第三介质层231和第二介质层221中掺杂的硼离子的浓度逐层减小，因而在后续采用刻蚀工艺形成第一电容孔的步骤中，使得该刻蚀工艺对第一介质层111、第三介质层231和第二介质层221的横向刻蚀速率逐层平缓地减小，有利于形成呈开口宽、底部窄的形貌的第一电容孔。
在其他实施例中，第一掩膜层可以为包括三层以上的介质层的叠层结构，且在第二掩膜层指向基底的方向上，第一掩膜层中相邻介质层中掺杂的硼离子的浓度逐层减小。需要说明的是，本实施例对第一掩膜层包含的介质层的层数不做限制。
本实施例中，第三介质层231中掺杂的硼离子和第一介质层211中掺杂的硼离子的浓度差为4％～6％，第三介质层231中掺杂的硼离子和第二介质层221中掺杂的硼离子的浓度差为4％～6％。在一个例子中，第三介质层231中掺杂的硼离子和第一介质层211中掺杂的硼离子的浓度差为5％，且第三介质层231中掺杂的硼离子和第二介质层221中掺杂的硼离子的浓度差也为5％。则第一掩膜层201中相邻层之间掺杂的硼离子浓度差较小，有利于使得后续刻蚀工艺对第一掩膜层201的横向刻蚀速率从最大值更平缓地减小到最小值，则在第一掩膜层201指向基底200的方向上，进一步使得形成的第一电 容孔的开口尺寸平缓地减小，进一步保证第一电容孔具有良好的刻蚀形貌。
本实施例中，第一介质层211中掺杂的硼离子的浓度为0％～2％，第三介质层231中掺杂的硼离子的浓度为4％～6％，第二介质层221中掺杂的硼离子的浓度为9％～11％。在一个例子中，第一介质层211中掺杂的硼离子的浓度为0％，即第一介质层211中未掺杂硼离子，第三介质层231中掺杂的硼离子的浓度为5％，第二介质层221中掺杂的硼离子的浓度为10％。
本实施例中，第一介质层211、第三介质层231和第二介质层221中均掺杂有磷离子，且第一介质层211、第三介质层231和第二介质层221为掺杂的硼离子浓度不同的硼磷硅玻璃。在形成第一介质层211、第三介质层231和第二介质层221的过程中，磷离子有利于增强此时第一介质层211、第三介质层231和第二介质层221的流动性，使得第一介质层211贴附于第一支撑层220顶面，第三介质层231贴附于第一介质层211顶面，第二介质层221贴附于第三介质层231顶面，且形成的第一介质层211、第三介质层231和第二介质层221的顶面形貌均较为平坦。
本实施例中，第一介质层211、第三介质层231和第二介质层221中掺杂的磷离子的浓度相同。
本实施例中，在腔室中形成掺杂有硼离子和磷离子的第一介质层211、第三介质层231和第二介质层221。
第一阶段：向腔室中通入气态正硅酸乙酯、气态磷酸三乙酯、气态硼酸三乙酯以及臭氧，调节腔室内的温度和气压，使得气态正硅酸乙酯、气态磷酸三乙酯、气态硼酸三乙酯以及臭氧在第一支撑层220表面发生反应，形成第一介质层211，然后通过吹扫步骤，去除腔室中的副产物。
第二阶段：向腔室中通入气态正硅酸乙酯、气态磷酸三乙酯、气态硼酸三乙酯以及臭氧，调节第二阶段通入的气态硼酸三乙酯的气体流量大于第一阶段通入的气态硼酸三乙酯的气体流量，调节腔室内的温度和气压，使得气态正硅酸乙酯、气态磷酸三乙酯、气态硼酸三乙酯以及臭氧在第一介质层211表面发生反应，形成第三介质层231，然后通过吹扫步骤，去除腔室中的副产物。
第三阶段：向腔室中通入气态正硅酸乙酯、气态磷酸三乙酯、气态硼酸三乙酯以及臭氧，调节第三阶段通入的气态硼酸三乙酯的气体流量大于第二 阶段通入的气态硼酸三乙酯的气体流量，调节腔室内的温度和气压，使得气态正硅酸乙酯、气态磷酸三乙酯、气态硼酸三乙酯以及臭氧在第三介质层231表面发生反应，形成第二介质层221，然后通过吹扫步骤，去除腔室中的副产物。
本实施例中，在垂直于基底200表面的方向上，第一介质层211和第三介质层231的总厚度为440nm～480nm，在一个例子中，第一介质层211和第三介质层231的总厚度为460nm。
参考图8，利用刻蚀工艺去除部分第一掩膜层201、部分第二掩膜层202和部分第一支撑层220，形成暴露电容接触结构210的第一电容孔21；其中，在相同的刻蚀条件下，第一介质层211、第三介质层231和第二介质层221的横向刻蚀速率逐层减小。
本实施例中，第一电容孔21的侧壁与底部相交处的夹角为95°～120°，当该夹角角度过小时，后续在该夹角处形成下电极层后，在下电极层表面形成介电层时，由于介电层的贴附效果较差，仍然容易使得介电层无法完全覆盖位于该夹角处的下电极层，则该夹角起不到避免下电极层和上电极层之间短路的作用；当该夹角角度过大时，第一电容孔21暴露的电容接触结构210的面积过小，会导致电容接触结构210和电容结构中的下电极层之间的电阻过大，影响半导体结构的电学性能。在一个例子中，第一电容孔21的侧壁与底部相交处的夹角为110°，有利于保证后续下电极层均匀地覆盖第一电容孔21的侧壁与底部的相交处，也有利于后续介电层完全覆盖下电极层的侧壁与底部的相交处。
参考图9，于第一电容孔21(参考图8)的底部和侧壁形成下电极层203。本实施例中，下电极层203还覆盖第三支撑层232远离第四介质层222的顶面，后续在去除部分第三支撑层232、部分第二支撑层212、第四介质层222和第一掩膜层201，以在下电极层203表面依次形成介电层和上电极层之前，去除覆盖在第三支撑层232顶面的下电极层203。
本实施例中，第一掩膜层201除了包括第一介质层211和第二介质层221外，还在第一介质层211和第二介质层221之间形成有第三介质层231，且第一介质层211、第三介质层231和第二介质层221中掺杂的硼离子的浓度逐层减小。通过控制第一掩膜层201中相邻层之间掺杂的硼离子浓度差，有 利于使得后续刻蚀工艺对第一掩膜层201的横向刻蚀速率从最大值更平缓地减小到最小值，则在第一掩膜层201指向基底200的方向上，进一步使得形成的第一电容孔21的开口尺寸平缓地减小，进一步保证第一电容孔21呈开口宽、底部窄的形貌。
本公开第三实施例还提供一种半导体结构，该半导体结构上述任一实施例提供的制作方法制成。
参考图6，半导体结构包括：基底100，基底100上具有多个相互间隔的电容接触结构110；第一支撑层120，第一支撑层120覆盖电容接触结构110的侧壁和部分上表面；下电极层103，下电极层103的底部和侧壁围成通孔，下电极层103的底部与电容接触结构110的部分顶部相抵接，下电极层103远离通孔的部分侧壁与第一支撑层120相抵接，且在沿垂直于基底100表面的方向上，通孔底部的开口尺寸小于通孔顶部的开口尺寸。
其中，半导体结构还包括：第二支撑层112，第二支撑层112位于基底100的上方，且与基底具有间距；第三支撑层132，第三支撑层132位于第二支撑层112的上方，且与第二支撑层112具有间距，且第二支撑层112与第三支撑层132均与下电极层103远离通孔的部分侧壁相抵接；介电层104，介电层104共形地覆盖下电极层103、第二支撑层112和第三支撑层132共同构成的结构的表面；上电极层105，上电极层105共形地覆盖介电层104表面。
本实施例中，由于下电极层103的底部和侧壁围成的通孔的底部和侧壁之间的夹角为钝角，例如，该钝角为95°～120°，有利于介电层104完全覆盖下电极层103表面，从而避免上电极层105与下电极层103相接触，以提高半导体结构的电学性能。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的半导体结构的制作方法及半导体结构中，通过在第一支撑层上形成至少包括第一介质层和第二介质层的第一掩膜层，后续利用刻蚀工艺去除部分第一掩膜层、部分第二掩膜层和部分第一支撑层，形成暴露部分电容接触结构的第一电容孔时，由于在相同的刻蚀条件下，第一介质层的横向刻蚀速率小于第二介质层的横向刻蚀速率，则相同刻蚀时间内，该刻蚀工艺刻蚀去除的第一介质层的宽度小于刻蚀去除的第二介质层的宽 度，从而使得形成的第一电容孔呈开口宽、底部窄的形貌，有利于后续在第一电容孔的侧壁和底部均覆盖下电极层，使得位于第一掩膜层侧壁的下电极层与位于电容接触结构顶面的下电极层之间的夹角为钝角，后续在下电极层表面形成介电层时，有利于保证介电层完全覆盖该钝角，避免后续在介电层表面形成的上电极层在该钝角处与下电极层相接触，避免下电极层和上电极层之间短路，从而有利于提高半导体结构的电学性能。此外，由于形成的第一电容孔呈开口宽、底部窄的形貌，即第一电容孔的侧壁与底部之间的夹角为钝角，使刻蚀工艺产生的刻蚀副产物不容易在第一电容孔底部与侧壁相交处聚集，有利于通过吹扫步骤将刻蚀副产物去除干净。另外，第一掩膜层中还可以包括第三介质层，第三介质层位于第一介质层和第二介质层之间，且在相同的刻蚀条件下，第一介质层、第三介质层和第二介质层的横向刻蚀速率逐层减小，随着刻蚀工艺的进行，有利于使得刻蚀工艺对第一掩膜层的横向刻蚀速率从最大值更平缓地减小到最小值，从而有利于形成刻蚀形貌更良好的第一电容孔。

Claims (19)

  1. 一种半导体结构的制作方法，所示半导体结构的制作方法包括：
    提供基底，所述基底具有多个相互间隔的电容接触结构和覆盖所述电容接触结构的第一支撑层；
    于所述第一支撑层上依次形成第一掩膜层和第二掩膜层，其中，所述第一掩膜层至少包括依次形成的第一介质层和第二介质层；
    利用刻蚀工艺去除部分所述第一掩膜层、部分所述第二掩膜层和部分所述第一支撑层，形成暴露部分所述电容接触结构的第一电容孔；其中，在相同的刻蚀条件下，所述第一介质层的横向刻蚀速率小于所述第二介质层的横向刻蚀速率；
    于所述第一电容孔的底部和侧壁形成下电极层。
  2. 根据权利要求1所述的半导体结构的制作方法，其中，所述第一电容孔的侧壁与底部相交处的夹角为95°～120°。
  3. 根据权利要求1所述的半导体结构的制作方法，其中，所述第一介质层中掺杂的硼离子的浓度小于所述第二介质层中掺杂的硼离子的浓度。
  4. 根据权利要求3所述的半导体结构的制作方法，其中，所述第一介质层中掺杂的硼离子和所述第二介质层中掺杂的硼离子的浓度差为8％～10％。
  5. 根据权利要求4所述的半导体结构的制作方法，其中，所述第一介质层中掺杂的硼离子的浓度为0％～2％，所述第二介质层中掺杂的硼离子的浓度为9％～11％。
  6. 根据权利要求5所述的半导体结构的制作方法，其中，所示第一介质层和所述第二介质层中均掺杂有磷离子。
  7. 根据权利要求6所述的半导体结构的制作方法，其中，所述第一介质层和所述第二介质层中掺杂的磷离子的浓度相同。
  8. 根据权利要求1所述的半导体结构的制作方法，所述第一掩膜层还包括第三介质层，所述第三介质层位于所述第一介质层和所述第二介质层之间，且在相同的所述刻蚀条件下，所述第一介质层、所述第三介质层和所述第二介质层的横向刻蚀速率逐层减小。
  9. 根据权利要求8所述的半导体结构的制作方法，其中，所述第一介质 层、所述第三介质层和所述第二介质层中掺杂的硼离子的浓度逐层减小。
  10. 根据权利要求9所述的半导体结构的制作方法，其中，所述第一介质层、所述第三介质层和所述第二介质层中均掺杂有磷离子。
  11. 根据权利要求10所述的半导体结构的制作方法，其中，所述第一介质层、所述第三介质层和所述第二介质层中掺杂的磷离子的浓度相同。
  12. 根据权利要求9所述的半导体结构的制作方法，其中，所述第一介质层、所述第三介质层和所述第二介质层为掺杂有不同浓度的硼离子的硼磷硅玻璃。
  13. 根据权利要求9所述的半导体结构的制作方法，其中，所述第三介质层中掺杂的硼离子和所述第一介质层中掺杂的硼离子的浓度差为4％～6％，所述第三介质层中掺杂的硼离子和所述第二介质层中掺杂的硼离子的浓度差为4％～6％。
  14. 根据权利要求13所述的半导体结构的制作方法，其中，所述第一介质层中掺杂的硼离子的浓度为0％～2％，所述第三介质层中掺杂的硼离子的浓度为4％～6％，所述第二介质层中掺杂的硼离子的浓度为9％～11％。
  15. 根据权利要求1所述的半导体结构的制作方法，其中，所述第二掩膜层包括依次形成的第二支撑层、第四介质层和第三支撑层。
  16. 根据权利要求15所述的半导体结构的制作方法，其中，形成所述第二支撑层和所述第三支撑层的材料包括碳氮化硅或者氮化硅。
  17. 根据权利要求15所述的半导体结构的制作方法，于所述第一电容孔的底部和侧壁形成下电极层后还包括：
    去除部分所述第三支撑层、部分所述第二支撑层、所述第一掩膜层和所述第四介质层，以形成第二电容孔，所述第二电容孔暴露所述第一支撑层；
    形成介电层，所述介电层覆盖所述下电极层的表面；
    形成上电极层，所述上电极层覆盖所述介电层的表面。
  18. 根据权利要求17所述的半导体结构的制作方法，其中，形成所述介电层的材料的介电常数大于20。
  19. 一种半导体结构，采用如权利要求1至14任一所述的半导体结构的制作方法制成。
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