WO2022028164A1 - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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Publication number
WO2022028164A1
WO2022028164A1 PCT/CN2021/103705 CN2021103705W WO2022028164A1 WO 2022028164 A1 WO2022028164 A1 WO 2022028164A1 CN 2021103705 W CN2021103705 W CN 2021103705W WO 2022028164 A1 WO2022028164 A1 WO 2022028164A1
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Prior art keywords
isolation
bit line
layer
line structure
isolation layer
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PCT/CN2021/103705
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English (en)
French (fr)
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卢经文
洪海涵
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长鑫存储技术有限公司
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Priority to EP21853322.2A priority Critical patent/EP4191649A4/en
Publication of WO2022028164A1 publication Critical patent/WO2022028164A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines

Definitions

  • Embodiments of the present application relate to a semiconductor structure and a manufacturing method thereof.
  • the wire connection between the DRAM transistor and the capacitor is usually made by depositing polysilicon or metal. As the semiconductor process shrinks, the size of the capacitor contact hole connecting the DRAM transistor and the capacitor also shrinks. When the depth and width of the capacitor contact hole is compared When it is high, the filling of the capacitor contact hole is prone to void problems, which will greatly increase the resistance of the wire.
  • an embodiment of the present application provides a semiconductor structure, comprising: a substrate, a conductive contact region is formed in the substrate, and the conductive contact region is exposed by the substrate; a bit line structure and a structure on the side of the bit line structure wall isolation walls, a plurality of discrete bit line structures are located on the substrate, the isolation walls include at least one isolation layer and a space between the isolation layer and the bit line structures; capacitor contact holes , the area enclosed by the isolation walls between the adjacent bit line structures constitutes the capacitor contact hole, and the capacitor contact hole exposes the conductive contact area, parallel to the arrangement direction of the bit line structures , the top width of the capacitor contact hole is larger than the bottom width.
  • an embodiment of the present application further provides a method for fabricating a semiconductor structure, including: providing a substrate with a conductive contact area in the substrate, the substrate exposing the conductive contact area; forming on the substrate A plurality of discrete bit line structures, in a direction parallel to the arrangement direction of the bit line structures, the top width of the bit line structures is smaller than the bottom width; a sacrificial layer is formed on the side walls of the bit line structure and is located away from the sacrificial layer.
  • the area enclosed by the isolation walls between the bit line structures constitutes a capacitor contact hole.
  • 1 to 3 are schematic cross-sectional structural diagrams corresponding to each step of a method for fabricating a semiconductor structure
  • 4 to 16 are schematic cross-sectional structural diagrams corresponding to each step of a method for fabricating a semiconductor structure according to an embodiment of the present application;
  • 17 to 20 are schematic cross-sectional structural diagrams corresponding to each step of a method for fabricating a semiconductor structure provided by another embodiment of the present application;
  • FIG. 21 is a schematic cross-sectional structure diagram of a semiconductor structure provided by an embodiment of the present application.
  • a substrate 11 and a plurality of discrete bit line structures 13 on the substrate 11 are provided, the substrate 11 has a conductive contact region 12, and the bit line structure 13 exposes the conductive contact region 12; isolation walls 14, the isolation walls 14 are located in The side wall of the bit line structure 13; the capacitor contact hole 15, the capacitor contact hole 15 is formed by the area surrounded by the isolation wall 14 between the adjacent bit line structures 13, the capacitor contact hole 15 exposes the conductive contact area 12, the capacitor contact hole 15 15 is used to fill conductive material to form conductive plugs.
  • the capacitor contact holes 15 are filled with conductive material to form conductive plugs 16 .
  • the topography of the capacitor contact holes 15 depends on the topography of the sidewalls of the bit line structures 13 .
  • the top width of the capacitor contact hole 15 is equal to the bottom width.
  • the top opening of the capacitor contact hole 15 may be sealed in advance to form a conductive plug 16 with a cavity 17.
  • the existence of the cavity 17 will increase the conductive plug.
  • the conductive plug 16 is etched back to expose the cavity 17 (refer to FIG. 2 ); the conductive material is filled again to eliminate the cavity 17 and form the conductive plug 16 .
  • the conductive material may be oxidized due to exposure to an oxygen environment, and finally a non-conductive oxide layer 18 is formed.
  • the presence of the oxide layer 18 also increases the resistance of the conductive plug 16 , thereby affecting the conductivity of the conductive plug 16 .
  • the present application provides a semiconductor structure and a manufacturing method thereof.
  • the dielectric constant of the isolation wall is reduced, thereby reducing the parasitic capacitance between the subsequently formed conductive plug and the bit line structure;
  • Increasing the top width of the capacitor contact hole and expanding the process window of the capacitor contact hole is beneficial to avoid the top opening of the capacitor contact hole being sealed in advance during the material deposition process, and it is beneficial to ensure that the conductive material can fill the capacitor contact hole, thereby forming no voids or oxidation.
  • a conductive plug with a small resistance value of the layer is beneficial to avoid the top opening of the capacitor contact hole being sealed in advance during the material deposition process, and it is beneficial to ensure that the conductive material can fill the capacitor contact hole, thereby forming no voids or oxidation.
  • 4 to 16 are schematic cross-sectional structural diagrams corresponding to each step of a method for fabricating a semiconductor structure according to an embodiment of the present application.
  • a substrate 21 is provided, the substrate 21 has a conductive contact region 22 , and the substrate 21 exposes the conductive contact region 22 ; a plurality of discrete initial bit line structures 230 are formed on the substrate 21 and are arranged parallel to the initial bit line structures 230 In the direction, the top width of the initial bit line structure 230 is equal to the bottom width.
  • the initial bit line structure 230 includes a conductive contact layer 231 , a metal gate layer 232 and a top dielectric layer 233 arranged in sequence in a direction perpendicular to the substrate 21 .
  • the material of the conductive contact layer 231 includes polysilicon
  • the metal gate layer 232 includes titanium nitride.
  • -Tungsten-titanium nitride stack structure the material of the top dielectric layer 233 includes silicon nitride.
  • the top width of the initial bit line structure may also be larger or smaller than the bottom width.
  • a deposition process is performed to form a first isolation layer 24 on the sidewalls of the initial bit line structure 230 .
  • the first isolation layer 24 is used to protect the metal gate layer 232 in the initial bit line structure 230 to avoid damage to the metal gate layer 232 caused by subsequent etching or cleaning processes, so as to ensure that the metal gate layer 232 has good performance. Conductivity and signal transmission performance; when the conductive contact layer 231 has conductivity, the first isolation layer 24 is also used to protect the conductive contact layer 231 , thereby ensuring the conductivity of the initial bit line structure 230 .
  • the first isolation layer 24 is formed separately by a deposition process. Since the first isolation layer 24 needs to play a protective role and a sidewall support role, the first isolation layer 24 can be formed by an atomic layer deposition process, so that the first isolation layer 24 can be formed by an atomic layer deposition process.
  • the isolation layer 24 has higher density and better step coverage.
  • the material of the first isolation layer 24 is the same as that of the top dielectric layer 233 . In this way, in the subsequent etching process, a specific single etchant can be selected for the material of the first isolation layer 24, so that the etching process has a faster etching rate, which is beneficial to shorten the manufacturing cycle of the semiconductor structure; In other embodiments, the material of the first isolation layer 24 includes at least one of silicon nitride or silicon oxynitride.
  • a spacer layer 25 is formed.
  • the spacer layer 25 divides the trenches between adjacent initial bit line structures 230 into a plurality of discrete grooves, each of which is used to form a conductive plug.
  • the size of the parasitic capacitance is related to the resistance value of the conductive plug. The smaller the resistance value of the conductive plug, the smaller the parasitic capacitance. In addition, the size of the parasitic capacitance is also related to the dielectric constant of the intermediate isolation material. The smaller the parasitic capacitance.
  • the resistance value of the conductive plug is related to the bottom area of the conductive plug.
  • the larger the bottom area the smaller the resistance value; the resistance value of the conductive plug is also related to the structure and material of the conductive plug. or smaller voids, and with less dielectric material, the conductive plug has a smaller resistance.
  • the adjustment of the top structure of the initial bit line structure 230 and the formation of isolation walls on the sidewalls of the initial bit line structure 230 are mainly used as exemplary descriptions. In fact, in the embodiments of the present application, the same The top structure of the spacer layer 25 is adjusted accordingly, and isolation walls are formed on the sidewalls of the spacer layer 25 .
  • a first etching process is performed on the initial bit line structure 230 (refer to FIG. 5 ) and the first isolation layer 24 .
  • a dry etching process with an etching angle is performed on the first isolation layer 24 and the initial bit line structure 230 to form a bit line structure with a first chamfer angle ⁇ at the top 23.
  • the angle of the first chamfering angle ⁇ is the same as the etching angle, and the angle of the first chamfering angle ⁇ is 5° to 35°, for example, 10°, 15°, 20° or 30°.
  • the optimum angle of a chamfering angle ⁇ is 15°.
  • Forming the first chamfer angle ⁇ within this numerical range is beneficial to expand the process window of the capacitor contact hole formed subsequently, and avoid the capacitor contact hole being sealed in advance when the conductive material is deposited; in addition, the upper limit of the first chamfer angle ⁇ is set. , which is beneficial to reduce the difficulty of the process, avoid damage to the metal gate layer 232 caused by the dry etching process, and ensure the electrical conductivity of the bit line structure 23 .
  • the first etching process removes part of the material at the top corner of the top dielectric layer 233 , and the top dielectric layer 233 whose structure has been changed forms a new bit line structure 23 together with the metal gate layer 232 and the conductive contact layer 231 ; In addition, the first etching process also removes the first isolation layer 24 at the bottom of the groove between adjacent bit line structures 23 and the first isolation layer 24 at the top of the bit line structures 23 .
  • a mixed plasma of SF6, CF4, and O2 is used to perform the dry etching process, and an inert gas (eg, argon) is used to clean the residual gas.
  • an inert gas eg, argon
  • a deposition process is performed to form a sacrificial film 251 .
  • the material of the sacrificial film 251 includes silicon oxide; the sacrificial film 251 can be formed by an atomic layer deposition process. Specifically, the LTO 250 can be reacted with oxygen or N zero and oxygen to generate silicon oxide.
  • a second etching process is performed to etch the sacrificial film 251 (refer to FIG. 8 ) to form the sacrificial layer 25 .
  • the second etching process etches and removes the sacrificial film 251 located at the top of the bit line structures 23 , the sacrificial film 251 located at the bottom of the grooves between adjacent bit line structures 23 and the side walls of the bit line structures 23 .
  • part of the sacrificial film 251, the remaining sacrificial film 251 is used as the sacrificial layer 25, the sacrificial film 25 has a second chamfering angle ⁇ 1, and the second chamfering angle ⁇ 1 is larger than the first chamfering angle ⁇ . In this way, it is beneficial to further increase the process window of the capacitor contact hole formed subsequently.
  • removing the sacrificial film 251 at the bottom of the groove between the adjacent bit line structures 23 is beneficial to avoid the subsequent formation of the second isolation film covering the sacrificial film 251, and to ensure that the second isolation film at the bottom does not Collapse occurs because there is no support; in addition, it is beneficial to avoid exposing the gap formed by etching the sacrificial film 251 when removing the bottom second isolation layer, thereby preventing the conductive material used to form the conductive plug from entering the gap, thereby ensuring the final formation
  • the separation wall has a lower dielectric constant.
  • the second etching process can adjust the etching angle and the type of the etchant, so as to form a new etching chamfer and increase the etching rate.
  • a deposition process is performed to form a second isolation film 261 .
  • the material of the second isolation film 261 may be the same as that of the first isolation layer 24 , and the material of the second isolation film 261 includes silicon nitride or silicon oxynitride. In this way, when an etchant is subsequently used to etch the sacrificial layer 25, only the etch selection ratio of the material of the sacrificial layer 25 and the material of the first isolation layer 24 needs to be considered, which is beneficial to expand the selection range of the etchant.
  • a support material is deposited and etched back to form a support structure 27 exposing the second isolation film 261 .
  • the height difference d determines the position of the second isolation film 261 that can be removed by etching subsequently and the area of the sacrificial layer 25 exposed after the second isolation film 261 is etched.
  • the value of the height difference d ranges from 3 nm to 20 nm, for example, 5 nm, 10 nm or 15 nm. In the actual process, the optimal value of the height difference d is 10 nm. In this way, it can not only ensure that the sacrificial layer 25 has a high etching rate, but also help to prevent the sealing material from falling into the gaps formed subsequently, and to ensure that the gaps have a low dielectric constant.
  • the support structure 27 is used to support the second isolation film 261 to prevent the second isolation film 261 from collapsing due to lack of support after the sacrificial layer 25 is etched and removed, so as to ensure that the isolation wall can be formed smoothly.
  • the material of the support structure 27 includes photoresist.
  • the second isolation film 261 (refer to FIG. 11 ) on the top of the bit line structure 23 is etched to expose the sacrificial layer 25 and form the second isolation layer 26 .
  • the position of the removed second isolation film 261 can be adjusted according to actual needs.
  • the second isolation film exposed by the support structure may also be removed.
  • the sacrificial layer 25 (refer to FIG. 12) is etched to form a void 28, and the void 28 forms an isolation wall 281 together with the first isolation layer 24 and the second isolation layer 26 on both sides.
  • the dielectric material (nitride) of the isolation wall 281 in contact with the adjacent structures has a relatively high density.
  • High hardness plays the role of supporting the side walls, which is beneficial to avoid external stress from damaging the structure of the isolation wall 281; the dielectric material between the first isolation layer 24 and the second isolation layer 26 is air, and the air has a lower dielectric. It is beneficial to make the isolation wall 24 have a lower dielectric constant, thereby reducing the parasitic capacitance between the bit line structure 23 and the conductive plug.
  • the second isolation layer 26 will also be etched. is related to the etching selection ratio of the material, the smaller the etching selection ratio is, the higher the etching degree of the second isolation layer 26 is.
  • the height of the top surface of the etched second isolation layer 26 can either be higher than the height of the top surface of the support structure 27 , or be flush with or lower than the height of the top surface of the support structure 27 .
  • a sealing film 291 is formed, and the sealing film 291 blocks the top opening of the void 28 and covers the surface of the support structure 27 .
  • the sealing film 291 is formed before the support structure 27 is removed, which is beneficial to prevent process by-products from entering the voids 28 during the subsequent ashing process, thereby ensuring that the voids 28 and the isolation walls 281 have lower dielectric constants.
  • the material of the sealing film 291 may be the same as the material of the second isolation layer 26 . Since the connection strength between the same materials is relatively large, the same material as the second isolation layer 26 is used for sealing, which is beneficial to avoid problems such as subsequent collapse of the sealing film 291 .
  • the process of forming the sealing film 291 includes a low pressure chemical vapor deposition process.
  • the sealing film can also be formed after the support structure is removed.
  • the sealing film and the second isolation layer between the support structure and the substrate can be continuously etched with the same etchant, which is beneficial to improve the etching rate. speed and shorten the process time; in addition, the material of the parafilm can also be different from the material of the second isolation layer.
  • the sealing film 291 located on the support structure 27 is etched, and the remaining sealing film 291 is used as the sealing layer 29, and the sealing layer 29 blocks the top opening of the gap 28;
  • the support structure is removed by a wet etching process 27 (refer to FIG. 15 ), and etch the second isolation layer 27 at the bottom of the groove between adjacent bit line structures 23 to expose the conductive contact region 22 and form a capacitor contact hole 292 with a top width greater than the bottom width.
  • the top width of the capacitor contact hole 292 is larger than the bottom width, in the process of using the capacitor contact hole 292 to fill the conductive material to form the conductive plug, it is beneficial to avoid the capacitor contact hole 292 being sealed in advance, so as to ensure that the conductive material can be filled with the conductive material.
  • the capacitor contact hole 292 is filled to form a conductive plug with a smaller resistance value.
  • an isolation wall including a gap is formed, and the arrangement of the gap is beneficial to reduce the dielectric constant of the isolation wall, thereby reducing the parasitic capacitance between the conductive plug filled in the capacitor contact hole and the adjacent bit line structure;
  • the top width of the capacitor contact hole is larger than the bottom width, which is beneficial to ensure that when the capacitor contact hole is filled with conductive material to form a conductive plug, the conductive material can fill the capacitor contact hole, avoid the problem of voids, and ensure that the conductive plug has smaller resistance.
  • FIGS. 17 to 20 are schematic structural diagrams corresponding to each step of a method for fabricating a semiconductor structure provided by another embodiment of the present application. For the parts that are the same as or corresponding to the previous embodiment, reference may be made to the corresponding description of the previous embodiment, which will not be repeated below.
  • a first isolation layer 44 is formed, and a first ion doping process is performed on the first isolation layer 44 .
  • the first isolation layer 44 includes a first isolation portion close to the bit line structure 43 and a second isolation portion away from the bit line structure 43 , and the second isolation portion is ion-doped so that the first isolation layer 44
  • the dielectric constant of the second isolation portion is smaller than the dielectric constant of the first isolation portion. In this way, the hardness of the first isolation portion can be maintained, so that the first isolation portion can have a better sidewall support effect, and the isolation wall can have a lower dielectric constant without adding an additional film layer.
  • only the ion doping process is performed on the second isolation portion, which is beneficial to avoid damage to the metal gate layer 432 caused by the ion doping process, and ensure that the metal gate layer 432 has good electrical conductivity.
  • the first ion doping process not only performs ion doping on the second isolation portion of the first isolation layer 44 , but also performs ion doping on the top dielectric layer 433 exposed by the first isolation layer 44 .
  • it is only necessary to control the energy of the doping ions to control the doping depth, and it is not necessary to limit the doping position, which is beneficial to reduce the difficulty of doping.
  • the material of the first isolation layer 44 includes silicon nitride
  • the second isolation portion of the first isolation layer 24 is doped with oxygen ions by the first ion doping process
  • the material of the doped second isolation portion is Including silicon oxynitride
  • the silicon oxynitride layer has a lower dielectric constant relative to the silicon nitride layer.
  • oxygen or ozone is used as the oxygen source, and oxygen plasma is used to ion-dope silicon nitride.
  • the radio frequency power for forming oxygen plasma is 600W-2000W, for example, 800W, 1200W or 1600W.
  • the temperature is 800°C to 1000°C, for example, 850°C, 900°C or 950°C.
  • a sacrificial film 451 is formed on the side of the first isolation layer 44 facing away from the bit line structure 43 .
  • the material of the sacrificial film 451 includes silicon oxide; the sacrificial film 451 can be formed by an atomic layer deposition process, and specifically, silicon oxide can be generated by reacting LTO250 with oxygen or N zero and oxygen.
  • the sacrificial film 451 at the bottom of the groove between adjacent bit line structures 43 can be removed, thereby reducing the difficulty of removal.
  • a second ion doping process is performed on the second isolation portion of the sacrificial film 451 (refer to FIG. 19 ) to form a sacrificial layer 45 and a second isolation layer 46 , and the sacrificial layer 45 is the remaining sacrificial film 451 .
  • the sacrificial film 451 includes a first isolation part close to the bit line structure 43 and a second isolation part away from the bit line structure 43 , and the second isolation part of the sacrificial film 451 is ion-doped so that the sacrificial film 451 The hardness of the second isolation part is greater than the hardness of the first isolation part.
  • the second isolation portion of the sacrificial film 451 can have a higher sidewall support capacity without adding an additional film layer, which is beneficial to avoid the damage to the structure of the isolation wall caused by the stress originating from the adjacent structure; in addition, since the characteristics of the material of the second isolation portion are changed by the doping ions, when the material of the sacrificial film 451 is subsequently etched, only the sacrificial film 351 of the first isolation portion will be etched and removed, and the second isolation portion with doping ions can be The second isolation layer 46 may remain and function as a sidewall support.
  • the material of the sacrificial film 451 includes silicon oxide
  • the second ion doping process performs nitrogen ion doping on the second isolation portion of the sacrificial film 451
  • the material of the doped second isolation portion includes silicon nitride and/or Silicon oxynitride.
  • silicon nitride and silicon oxynitride have higher hardness and can play a supporting role for the side wall, which is beneficial to ensure that the isolation wall has higher structural stability.
  • nitrogen gas or ammonia gas can be used as the nitrogen source, and nitrogen plasma is used to ion-dope silicon oxide, and the radio frequency power for forming nitrogen plasma is 600W-2000W, such as 800W, 1200W or 1600W, and the nitrogen plasma
  • the temperature is 600°C to 800°C, for example, 650°C, 700°C or 750°C.
  • thermal shock resistance of silicon oxide is weaker than that of silicon nitride, using a lower plasma temperature for ion doping is beneficial to avoid stress concentration, cracking and Damage such as surface peeling ensures that the separation wall has high structural stability.
  • the second isolation layer 46 on the top of the bit line structure 43 is etched and removed to expose the sacrificial layer 45; after the sacrificial layer 45 is exposed, the sacrificial layer 45 is etched to form a gap,
  • the voids together with the first isolation layer 44 and the second isolation layer 46 constitute isolation walls.
  • an ion doping process is performed on the second isolation portion of the first isolation layer and an ion doping process is performed on the sacrificial film.
  • the doping ions can change the performance of the original material of the isolation layer, so as to achieve no need to add additional films.
  • the dielectric constant of the isolation wall is reduced; in addition, since there is no need to form an additional film layer, it is beneficial to avoid the problem of sidewall morphology when forming a multi-layer dielectric layer, and it is beneficial to reduce the thickness of the isolation wall, A larger space is reserved for the capacitor contact hole, so that the capacitor contact hole has a larger bottom area, thereby ensuring that the conductive plug filled in the capacitor contact hole has a smaller resistance value.
  • each dielectric layer has a corresponding minimum thickness, and at the same time, because the spacing between adjacent bit line structures is fixed Therefore, the smaller the number of dielectric layers, the larger the bottom area of the capacitor contact hole used to form the conductive plug, and the smaller the resistance value of the subsequently formed conductive plug.
  • the embodiments of the present application further provide a semiconductor structure, and the semiconductor structure can be fabricated by the above-mentioned fabrication method of the semiconductor structure.
  • the semiconductor structure includes: a substrate 41 having a conductive contact region 42 in the substrate 41 , the substrate 41 exposing the conductive contact region 42 ; a bit line structure 43 and isolation walls 48 on the sidewalls of the bit line structure 43 , a plurality of discrete
  • the bit line structure 43 is located on the substrate 41, and the isolation wall 48 includes at least one isolation layer and a space 47 between the isolation layer and the bit line structure 43; the capacitor contact hole 49, the isolation wall 48 between the adjacent bit line structures 43
  • the enclosed area constitutes a capacitor contact hole 49 , which exposes the conductive contact region 42 .
  • the top width of the capacitor contact hole 49 is greater than the bottom width in the arrangement direction parallel to the bit line structures 43 .
  • At least one isolation layer has doped ions, and the hardness of the isolation layer with doped ions is greater than that of the undoped isolation layer, or the dielectric constant of the isolation layer with doped ions is smaller than that of the undoped isolation layer.
  • the dielectric constant of the impurity isolation layer is greater than that of the undoped isolation layer, or the dielectric constant of the isolation layer with doped ions is smaller than that of the undoped isolation layer.
  • the isolation wall 48 includes a first isolation layer 44 , a second isolation layer 46 and a gap 47 between the first isolation layer 44 and the second isolation layer 46 , and the second isolation layer 46 facing away from the bit line structure 43 has a Doping ions, the thickness of the second isolation layer 46 is smaller than the thickness of the first isolation layer 44 in the direction parallel to the arrangement direction of the bit line structure 43 .
  • the material of the first isolation layer 44 includes silicon nitride, the second isolation portion of the first isolation layer 44 is doped with oxygen ions, and the dielectric constant of the oxygen-doped silicon nitride is smaller than that of silicon nitride; the second isolation The material of the layer 46 includes silicon oxide, the second isolation layer 46 is doped with nitrogen ions, and the hardness of the nitrogen-doped silicon oxide is greater than that of the silicon oxide.
  • the top of the bit line structure 43 has a sealing layer 491, the sealing layer 491 is connected to the bit line structure 43 and the second isolation layer 46, and the sealing layer 491 is used to seal the top of the gap 47; in the direction perpendicular to the surface of the substrate 41
  • the height of the top surface of the second isolation layer 46 is lower than that of the bit line structure 43 .
  • the top of the bit line structure 43 is chamfered, and the angle of the chamfer is 5° ⁇ 35°, for example, 10°, 15°, 20° or 30°.
  • the isolation wall includes a gap between the isolation layer and the bit line structure.
  • the setting of the gap is beneficial to reduce the dielectric constant of the isolation wall, thereby reducing the contact between the conductive plug filled in the capacitor contact hole and the adjacent bit line.

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Abstract

一种半导体结构及其制作方法，包括：基底（41），基底（41）内具有导电接触区域（42），基底（41）暴露出导电接触区域（42）；位线结构（43）和位于位线结构（43）侧壁的隔离墙（48），多个分立的位线结构（43）位于基底（41）上，隔离墙（48）包括至少一层隔离层和位于隔离层和位线结构（43）之间的空气隙（47）；电容接触孔（49），相邻位线结构（43）之间的隔离墙（48）围成的区域构成电容接触孔（49），电容接触孔（49）暴露导电接触区域（42），在平行于位线结构（43）的排列方向上，电容接触孔（49）的顶部宽度大于底部宽度。

Description

半导体结构及其制作方法
交叉引用
本申请要求于2020年8月5日递交的名称为“半导体结构及其制作方法”、申请号为202010776933.5的中国专利申请的优先权，其通过引用被全部并入本申请。
技术领域
本申请实施例涉及一种半导体结构及其制作方法。
背景技术
DRAM晶体管和电容器之间通常通过沉积多晶硅或金属来进行导线连接，随着半导体制程的微缩，连接DRAM晶体管和电容器之间的电容接触孔的尺寸也随之微缩，当电容接触孔的深宽比较高时，电容接触孔的填充容易出现空洞问题，这会极大地增大导线阻值。
发明内容
为解决上述问题，本申请实施例提供一种半导体结构，包括：基底，所述基底内具有导电接触区域，所述基底暴露出所述导电接触区域；位线结构和位于所述位线结构侧壁的隔离墙，多个分立的所述位线结构位于所述基底上，所述隔离墙包括至少一层隔离层和位于所述隔离层和所述位线结构之间的空隙；电容接触孔，相邻所述位线结构之间的所述隔离墙围成的区域构成所述电容接触孔，所述电容接触孔暴露所述导电接触区域，在平行于所述位线结构的排列方向上，所述电容接触孔的顶部宽度大于底部宽度。
根据本申请实施例，本申请实施例还提供一种半导体结构的制作方法，包括：提供基底，所述基底内具有导电接触区域，所述基底露出所述导电接触区域；在所述基底上形成多个分立的位线结构，在平行于所述位线结构排列方向上，所述位线结构的顶部宽度小于底部宽度；在所述位线结构侧壁形成牺牲层和位于所述牺牲层背离所述位线结构一侧的隔离层；去除所述牺牲层，形成隔离墙，所述隔离墙包括所述隔离层和位于所述隔离层和所述位线结构之间的空隙，相邻所述位线结构之间的所述隔离墙围成的区域构成电容接触孔。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1至图3为半导体结构的制作方法各步骤对应的剖面结构示意图；
图4至图16为本申请一实施例提供的半导体结构的制作方法各步骤对应的剖面结构示意图；
图17至图20为本申请又一实施例提供的半导体结构的制作方法各步骤对应的剖面结构示意图；
图21为本申请实施例提供的半导体结构的剖面结构示意图。
具体实施方式
参考图1，提供基底11和位于基底11上的多个分立的位线结构13，基底11内具有导电接触区域12，位线结构13暴露出导电接触区域12；隔离墙14，隔离墙14位于位线结构13侧壁；电容接触孔15，电容接触孔15由位于相邻位线结构13之间的隔离墙14围成的区域构成，电容接触孔15暴露出导电接触区域12，电容接触孔15用于填充导电材料以形成导电插塞。
参考图2，向电容接触孔15内填充导电材料以形成导电插塞16。
由于隔离墙14在垂直于位线结构13侧壁方向上的厚度通常是相等的，因此，电容接触孔15的轮廓形貌取决于位线结构13的侧壁形貌。在平行于位线结构13的排列方向上，位线结构13的顶部宽度等于底部宽度时，电容接触孔15的顶部宽度等于底部宽度。
当电容接触孔15的深宽比较大时，在填充导电材料的过程中，电容接触孔15顶部开口可能会提前封口，形成具有空洞17的导电插塞16，空洞17的存在会增大导电插塞16的阻值。
参考图3，对导电插塞16进行回刻，以暴露出空洞17(参考图2)；再次填充导电材料，以消除空洞17并形成导电插塞16。
在刻蚀导电插塞16以暴露出空洞17的过程中，导电材料可能会因为暴 露在氧气环境下，进而发生氧化，最终形成不导电的氧化层18。氧化层18的存在同样会增大导电插塞16的阻值，从而影响导电插塞16的导电性能。
为解决上述问题，本申请实施提供一种半导体结构及其制作方法，通过形成空隙降低隔离墙的介电常数，从而降低后续形成的导电插塞与位线结构之间的寄生电容；此外，通过增加电容接触孔的顶部宽度，扩大电容接触孔的工艺窗口，有利于避免电容接触孔顶部开口在材料沉积过程中提前封口，有利于保证导电材料能够填充满电容接触孔，进而形成没有空洞或氧化层的阻值较小的导电插塞。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
图4至图16为本申请一实施例提供的半导体结构的制作方法各步骤对应的剖面结构示意图。
参考图4，提供基底21，基底21内具有导电接触区域22，基底21暴露出导电接触区域22；在基底21上形成多个分立的初始位线结构230，在平行于初始位线结构230排列方向上，初始位线结构230的顶部宽度等于底部宽度。
初始位线结构230包括在垂直于基底21方向上依次排列的导电接触层231、金属栅极层232以及顶层介质层233，导电接触层231的材料包括多晶硅，金属栅极层232包括氮化钛-钨-氮化钛叠层结构，顶层介质层233的材料包括氮化硅。
在其他实施例中，初始位线结构的顶部宽度还可以大于或者小于底部宽度。
参考图5，进行沉积工艺，在初始位线结构230侧壁形成第一隔离层24。
第一隔离层24用于保护初始位线结构230中的金属栅极层232，避免后续进行的刻蚀或清洗等工艺对金属栅极层232造成损伤，从而保证金属栅极层232具有良好的导电性能和信号传输性能；当导电接触层231具有导电能力时， 第一隔离层24也用于保护导电接触层231，进而保证初始位线结构230的导电性能。
本实施例中，第一隔离层24采用沉积工艺单独形成，由于第一隔离层24需要起到保护作用以及侧壁支撑作用，因此可采用原子层沉积工艺形成第一隔离层24，使得第一隔离层24具有较高的致密性和较好的阶梯覆盖性。
本实施例中，第一隔离层24的材料与顶层介质层233的材料相同。如此，在后续的刻蚀工艺中，可针对第一隔离层24的材料选用特定的单一刻蚀剂，从而使得刻蚀工艺具有较快的刻蚀速率，有利于缩短半导体结构的制作周期；在其他实施例中，第一隔离层24的材料包括氮化硅或氮氧化硅中的至少一者。
参考图6，形成间隔层25，间隔层25将相邻初始位线结构230之间的沟槽分割为多个分立的凹槽，每一凹槽用于形成一导电插塞。
相邻凹槽内的导电插塞之间会有寄生电容，某一凹槽内的导电插塞与相邻初始位线结构中的金属栅极层之间也会有寄生电容。寄生电容的大小与导电插塞的阻值有关，导电插塞的阻值越小，寄生电容越小；此外，寄生电容的大小还与中间隔离材料的介电常数有关，介电常数越小，寄生电容越小。
导电插塞的阻值与导电插塞的底面积有关，底面积越大，阻值越小；导电插塞的阻值还与导电插塞的结构和材料有关，当导电插塞内具有较少或较小的空洞，以及具有较少的介质材料时，导电插塞具有较小的阻值。
需要说明的是，本文附图中主要以调整初始位线结构230的顶部结构和在初始位线结构230侧壁形成隔离墙作为示例性说明，实际上，在本申请实施例中，也同样对间隔层25的顶部结构做出相应调整，且在间隔层25的侧壁形成隔离墙。
参考图7，对初始位线结构230(参考图5)和第一隔离层24进行第一刻蚀工艺。
本实施例中，在形成第一隔离层24之后，对第一隔离层24和初始位线结构230进行具有刻蚀角度的干法刻蚀工艺，形成顶部具有第一倒角θ的位线结构23，第一倒角θ的角度与刻蚀角度相同，第一倒角θ的角度为5°～35°，例如为10°、15°、20°或30°，在实际工艺过程中，第一倒角θ的最佳角度 为15°。形成处于该数值范围内的第一倒角θ，有利于扩大后续形成的电容接触孔的工艺窗口，避免沉积导电材料时电容接触孔提前封口；此外，设定第一倒角θ的上限值，有利于降低工艺难度，以及避免干法刻蚀工艺对金属栅极层232造成损伤，保证位线结构23的导电性能。
本实施例中，第一刻蚀工艺去除了顶层介质层233顶部转角处的部分材料，结构发生改变的顶层介质层233与金属栅极层232和导电接触层231一同构成新的位线结构23；此外，第一刻蚀工艺还去除了位于相邻位线结构23之间的凹槽底部的第一隔离层24和位于位线结构23顶部的第一隔离层24。
本实施例中，采用SF6、CF4和O2三种气体的混合等离子体进行干法刻蚀工艺，并用惰性气体(例如氩气)进行残余气体的清扫。
参考图8，进行沉积工艺，形成牺牲膜251。
本实施例中，牺牲膜251的材料包括氧化硅；牺牲膜251可通过原子层沉积工艺形成，具体地，可采用LTO250与氧气或者N zero与氧气发生反应生成氧化硅。
在选用牺牲膜251的材料时，需要考虑牺牲膜251的材料与第一隔离层24的材料的刻蚀选择比，避免后续刻蚀牺牲膜251时刻穿第一隔离层24，从而避免对金属栅极层232造成损伤。
参考图9，进行第二刻蚀工艺，刻蚀牺牲膜251(参考图8)，形成牺牲层25。
本实施例中，第二刻蚀工艺刻蚀去除位于位线结构23顶部的牺牲膜251、去除位于相邻位线结构23之间的凹槽底部的牺牲膜251以及位于位线结构23侧壁的部分牺牲膜251，剩余的牺牲膜251作为牺牲层25，牺牲膜25具有第二倒角θ1，第二倒角θ1大于第一倒角θ。如此，有利于进一步增大后续形成的电容接触孔的工艺窗口。
需要说明的是，去除位于相邻位线结构23之间的凹槽底部的牺牲膜251，有利于避免后续形成的第二隔离膜覆盖在牺牲膜251上，保证底部的第二隔离膜不会因为没有支撑而发生坍塌；此外，有利于避免去除底部第二隔离层的时候暴露出刻蚀牺牲膜251形成的空隙，进而避免用于形成导电插塞的导电材料 进入空隙中，从而保证最终形成的隔离墙具有较低的介电常数。
本实施例中，第二刻蚀工艺相对于第一刻蚀工艺，可进行刻蚀角度和刻蚀剂类型的调整，以形成新的刻蚀倒角以及提高刻蚀速率。
参考图10，进行沉积工艺，形成第二隔离膜261。
本实施例中，第二隔离膜261的材料可以与第一隔离层24的材料相同，第二隔离膜261的材料包括氮化硅或氮氧化硅。如此，在后续选用刻蚀剂刻蚀牺牲层25时，仅需要考虑牺牲层25的材料与第一隔离层24的材料的刻蚀选择比，有利于扩大刻蚀剂的选择范围。
参考图11，沉积支撑材料并进行回刻，形成暴露第二隔离膜261的支撑结构27。
本实施例中，在垂直于基底21表面的方向上，支撑结构27顶面与第二隔离膜261顶面之间具有高度差d。高度差d的大小决定了后续可刻蚀去除的第二隔离膜261的位置以及刻蚀第二隔离膜261之后暴露出的牺牲层25的面积。牺牲层25的暴露面积越大，牺牲层25与刻蚀剂的接触面积越大，牺牲层25的刻蚀速率越快；此外，牺牲层25的暴露面积越大，后续需要进行封口的空隙的顶部开口宽度越大，封口难度越高。
本实施例中，高度差d的取值范围为3nm～20nm，例如为5nm、10nm或15nm，在实际工艺过程中，高度差d的最佳取值为10nm。如此，既可保证牺牲层25具有较高的刻蚀速率，又有利于避免封口材料落入后续形成的空隙中，保证空隙具有较低的介电常数。
本实施例中，支撑结构27用于支撑第二隔离膜261，避免在牺牲层25被刻蚀去除之后第二隔离膜261因没有支撑而发生坍塌，保证隔离墙能够顺利形成。其中，支撑结构27的材料包括光阻。
参考图12，刻蚀位于位线结构23顶部的第二隔离膜261(参考图11)，暴露出牺牲层25，形成第二隔离层26。
去除的第二隔离膜261的位置可以根据实际需要进行调整。在其他实施例中，还可以去除支撑结构暴露出的第二隔离膜。
参考图13，刻蚀牺牲层25(参考图12)，形成空隙28，空隙28与位于 两侧的第一隔离层24和第二隔离层26一同构成隔离墙281。
本实施例中，在平行于位线结构23的排列方向上，隔离墙281与相邻结构(例如位线结构23、导电插塞以及间隔层25)相接触的介质材料(氮化物)具有较高的硬度，起到侧壁支撑作用，有利于避免外部应力对隔离墙281的结构造成破坏；第一隔离层24与第二隔离层26之间的介质材料为空气，空气具有较低的介电常数，有利于使得隔离墙24具有较低的介电常数，从而降低位线结构23与导电插塞之间的寄生电容。
需要说明的是，在刻蚀牺牲层25形成空隙28的过程中，第二隔离层26也会被刻蚀，第二隔离层26的刻蚀程度与第二隔离层26的材料与牺牲层25的材料的刻蚀选择比有关，刻蚀选择比越小，第二隔离层26的刻蚀程度越高。刻蚀后的第二隔离层26的顶面高度既可以高于支撑结构27的顶面高度、也可以齐平于或者低于支撑结构27的顶面高度。
参考图14，形成封口膜291，所述封口膜291封堵空隙28的顶部开口并覆盖在支撑结构27表面。
本实施例中，在去除支撑结构27之前形成封口膜291，有利于避免后续进行灰化工艺时有工艺副产物进入空隙28中，从而保证空隙28以及隔离墙281具有较低的介电常数。
本实施例中，封口膜291的材料可以与第二隔离层26的材料相同。由于相同材料之间的连接强度较大，因此采用与第二隔离层26相同的材料进行封口，有利于避免封口膜291后续发生坍塌等问题。其中，形成封口膜291的工艺包括低压化学气相沉积工艺。
在其他实施例中，也可以在去除支撑结构之后形成封口膜，如此，后续能够采用同一刻蚀剂连续刻蚀封口膜以及位于支撑结构和基底之间的第二隔离层，有利于提高刻蚀速率和缩短工艺制程时间；此外，封口膜的材料也可以与第二隔离层的材料不同。
参考图15，刻蚀位于支撑结构27上的封口膜291，剩余的封口膜291作为封口层29，封口层29封堵空隙28的顶部开口；参考图16，采用湿法刻蚀工艺去除支撑结构27(参考图15)，并刻蚀位于相邻位线结构23之间的凹槽的底部的第二隔离层27，暴露出导电接触区域22，形成顶部宽度大于底部宽度的电 容接触孔292。
本实施例中，由于电容接触孔292的顶部宽度大于底部宽度，在利用电容接触孔292填充导电材料形成导电插塞的过程中，有利于避免电容接触孔292提前封口，从而保证导电材料能够填充满电容接触孔292，形成具有较小阻值的导电插塞。
本实施例中，形成包含空隙的隔离墙，空隙的设置有利于减小隔离墙的介电常数，从而降低填充于电容接触孔内的导电插塞与相邻位线结构之间的寄生电容；此外，电容接触孔的顶部宽度大于底部宽度，有利于保证在利用电容接触孔进行导电材料填充以形成导电插塞时，导电材料能够填充满电容接触孔，避免出现空洞问题，保证导电插塞具有较小的阻值。
本申请又一实施例还提供一种半导体结构的制作方法，与前一实施例不同的是，本实施例中，采用离子掺杂工艺形成牺牲层和第二隔离层。以下将结合图17至图10进行详细说明，图17至图20为本申请又一实施例提供的半导体结构的制作方法各步骤对应的结构示意图。与上一实施例相同或者相应的部分，可参考上一实施例的相应说明，以下不做赘述。
参考图17和图18，形成第一隔离层44，并对第一隔离层44进行第一离子掺杂工艺。
本实施例中，第一隔离层44包括靠近位线结构43的第一隔离部和背离位线结构43的第二隔离部，对第二隔离部进行离子掺杂，以使第一隔离层44中第二隔离部的介电常数小于第一隔离部的介电常数。如此，既能够维持第一隔离部的硬度，使得第一隔离部能够起到较好的侧壁支撑效果，又能够在不增加额外膜层的情况下，使得隔离墙具有较低的介电常数；此外，仅对第二隔离部进行离子掺杂工艺，有利于避免离子掺杂工艺对金属栅极层432造成损伤，保证金属栅极层432具有良好的导电性能。
本实施例中，第一离子掺杂工艺不仅对第一隔离层44的第二隔离部进行离子掺杂，还对第一隔离层44暴露出的顶层介质层433进行离子掺杂。如此，在进行第一离子掺杂工艺时，仅需要控制掺杂离子的能量以控制掺杂深度，无需限定掺杂位置，有利于降低掺杂难度。
本实施例中，第一隔离层44的材料包括氮化硅，第一离子掺杂工艺对第 一隔离层24的第二隔离部进行氧离子掺杂，掺杂后的第二隔离部的材料包括氮氧化硅，氮氧化硅层相对于氮化硅层具有较低的介电常数。
本实施例中，以氧气或臭氧作为氧源，采用氧等离子体对氮化硅进行离子掺杂，形成氧等离子体的射频功率为600W～2000W，例如为800W、1200W或1600W，氧等离子体的温度为800℃～1000℃，例如为850℃、900℃或950℃。
参考图19，在第一隔离层44背离位线结构43的一侧形成牺牲膜451。
本实施例中，牺牲膜451的材料包括氧化硅；牺牲膜451可通过原子层沉积工艺形成，具体地，可采用LTO250与氧气或者N zero与氧气发生反应生成氧化硅。
本实施例中，可在形成牺牲膜451之后，去除位于相邻位线结构43之间的凹槽底部的牺牲膜451，从而降低去除难度。
参考图20，对牺牲膜451(参考图19)的第二隔离部进行第二离子掺杂工艺，形成牺牲层45和第二隔离层46，牺牲层45为剩余的牺牲膜451。
本实施例中，牺牲膜451包括靠近位线结构43的第一隔离部和背离位线结构43的第二隔离部，对牺牲膜451的第二隔离部进行离子掺杂，以使牺牲膜451中第二隔离部的硬度大于第一隔离部的硬度。
如此，能够在不增加额外膜层的情况下，使得牺牲膜451的第二隔离部具有较高的侧壁支撑能力，有利于避免来源于相邻结构的应力对隔离墙的结构造成破坏；此外，由于第二隔离部的材料的特性被掺杂离子改变，后续刻蚀牺牲膜451的材料时，仅会刻蚀去除第一隔离部的牺牲膜351，具有掺杂离子的第二隔离部可作为第二隔离层46可保留下来并起到侧壁支撑作用。
具体地，牺牲膜451的材料包括氧化硅，第二离子掺杂工艺对牺牲膜451的第二隔离部进行氮离子掺杂，掺杂后的第二隔离部的材料包括氮化硅和/或氮氧化硅。氮化硅和氮氧化硅相对于氧化硅具有较高的硬度，可起到侧壁支撑作用，有利于保证隔离墙具有较高的结构稳定性。
本实施例中，可以氮气或者氨气作为氮源，采用氮等离子体对氧化硅进行离子掺杂，形成氮等离子体的射频功率为600W～2000W，例如为800W、1200W或1600W，氮等离子体的温度为600℃～800℃，例如为650℃、700℃或750℃。
由于氧化硅的抗热冲击能力弱于氮化硅，因此，采用更低的等离子体温度进行离子掺杂，有利于避免第二隔离层46因受到较大的热冲击而发生应力集中、断裂以及表层剥落等损伤，保证隔离墙具有较高的结构稳定性。
在形成牺牲层45和第二隔离层46之后，刻蚀去除位于位线结构43顶部的第二隔离层46，暴露出牺牲层45；在暴露牺牲层45之后，刻蚀牺牲45，形成空隙，空隙与第一隔离层44和第二隔离层46一同构成隔离墙。
本实施例中，对第一隔离层的第二隔离部进行离子掺杂工艺和对牺牲膜进行离子掺杂工艺，掺杂离子能够改变隔离层原有材料的性能，从而实现在不增加额外膜层的情况下，降低隔离墙的介电常数；此外，由于无需形成额外的膜层，有利于避免形成多层介质层时出现的侧壁形貌问题，以及有利于减薄隔离墙的厚度，为电容接触孔预留更大的空间，使得电容接触孔具有较大的底面积，进而保证填充于电容接触孔内的导电插塞具有较小的阻值。
需要说明的是，在实际工艺步骤中，每形成一层介质层都需要进行一道沉积工艺和一道刻蚀工艺，而多次沉积和多次刻蚀可能导致介质层侧壁形貌发生变化，进而不满足预设的性能要求；此外，在形成介质层的过程中，由于形成工艺本身的限制，每一介质层具有对应的最小厚度，同时，由于相邻位线结构之间的间距是固定的，因此介质层的层数越少，用于形成导电插塞的电容接触孔的底面积就越大，后续形成的导电插塞的阻值就越小。
相应地，本申请实施例还提供一种半导体结构，半导体结构可采用上述半导体结构的制作方法制成。
参考图21，半导体结构包括：基底41，基底41内具有导电接触区域42，基底41暴露出导电接触区域42；位线结构43和位于位线结构43侧壁的隔离墙48，多个分立的位线结构43位于基底41上，隔离墙48包括至少一层隔离层和位于隔离层和位线结构43之间的空隙47；电容接触孔49，相邻位线结构43之间的隔离墙48围成的区域构成电容接触孔49，电容接触孔49暴露导电接触区域42，在平行于位线结构43的排列方向上，电容接触孔49的顶部宽度大于底部宽度。
本实施例中，至少一隔离层内具有掺杂离子，具有掺杂离子的隔离层的硬度大于未掺杂的隔离层的硬度，或者，具有掺杂离子的隔离层的介电常数小 于未掺杂的隔离层的介电常数。
具体地，隔离墙48包括第一隔离层44、第二隔离层46以及位于第一隔离层44和第二隔离层46之间的空隙47，背离位线结构43的第二隔离层46内具有掺杂离子，在平行于位线结构43排列方向上，第二隔离层46的厚度小于第一隔离层44的厚度。
第一隔离层44的材料包括氮化硅，第一隔离层44的第二隔离部内掺杂有氧离子，掺氧的氮化硅的介电常数小于氮化硅的介电常数；第二隔离层46的材料包括氧化硅，第二隔离层46内掺杂有氮离子，掺氮的氧化硅的硬度大于氧化硅的硬度。
本实施例中，位线结构43顶端具有封口层491，封口层491与位线结构43和第二隔离层46连接，封口层491用于封堵空隙47顶部；在垂直于基底41表面的方向上，第二隔离层46的顶面高度低于位线结构43的顶面高度。
本实施例中，位线结构43顶部具有倒角，倒角的角度为5°～35°，例如为10°、15°、20°或30°。
本实施例中，隔离墙包括位于隔离层和位线结构之间的空隙，空隙的设置有利于减小隔离墙的介电常数，从而降低填充于电容接触孔内的导电插塞与相邻位线结构之间的寄生电容；此外，电容接触孔的顶部宽度大于底部宽度，有利于保证在利用电容接触孔进行导电材料填充以形成导电插塞时，导电材料能够填充满电容接触孔，避免出现空洞问题，保证导电插塞具有较小的阻值。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。

Claims (15)

  1. 一种半导体结构，包括：
    基底，所述基底内具有导电接触区域，所述基底暴露出所述导电接触区域；
    位线结构和位于所述位线结构侧壁的隔离墙，多个分立的所述位线结构位于所述基底上，所述隔离墙包括至少一层隔离层和位于所述隔离层和所述位线结构之间的空隙；
    电容接触孔，相邻所述位线结构之间的所述隔离墙围成的区域构成所述电容接触孔，所述电容接触孔暴露所述导电接触区域，在平行于所述位线结构的排列方向上，所述电容接触孔的顶部宽度大于底部宽度。
  2. 根据权利要求1所述的半导体结构，其中，至少一所述隔离层内具有掺杂离子，具有掺杂离子的所述隔离层的硬度大于未掺杂的隔离层的硬度，或者，具有掺杂离子的所述隔离层的介电常数小于未掺杂的隔离层的介电常数。
  3. 根据权利要求2所述的半导体结构，其中，所述隔离层包括氮化硅层，所述掺杂离子包括氧离子；或者，所述隔离层包括氧化硅层，所述掺杂离子包括氮离子。
  4. 根据权利要求2所述的半导体结构，其中，所述隔离墙包括两层所述隔离层以及位于两层所述隔离层之间的所述空隙，背离所述位线结构的所述隔离层内具有掺杂离子，在平行于所述位线结构排列方向上，背离所述位线结构的所述隔离层的厚度小于靠近所述位线结构的所述隔离层的厚度。
  5. 根据权利要求1至4中任一项所述的半导体结构，其中，所述隔离墙包括依次排列的第一隔离层、所述空隙和第二隔离层层，所述第一隔离层的材料包括氮化硅或氮氧化硅中的至少一者，所述第二隔离层的材料包括氮化硅或氮氧化硅中的至少一者。
  6. 根据权利要求1所述的半导体结构，其中，还包括：封口层，所述封口层与所述位线结构和所述隔离层连接，所述封口层用于封堵所述空隙顶部；在垂直于所述基底表面的方向上，与所述封口层连接的隔离层的顶面高度低于所述位线结构的顶面高度。
  7. 根据权利要求1所述的半导体结构，其中，所述位线结构顶部具有倒角，所 述倒角的角度为5°～35°。
  8. 一种半导体结构的制作方法，包括：
    提供基底，所述基底内具有导电接触区域，所述基底露出所述导电接触区域；
    在所述基底上形成多个分立的位线结构，在平行于所述位线结构排列方向上，所述位线结构的顶部宽度小于底部宽度；
    在所述位线结构侧壁形成牺牲层和位于所述牺牲层背离所述位线结构一侧的隔离层；
    去除所述牺牲层，形成隔离墙，所述隔离墙包括所述隔离层和位于所述隔离层和所述位线结构之间的空隙，相邻所述位线结构之间的所述隔离墙围成的区域构成电容接触孔。
  9. 根据权利要求8所述的半导体结构的制作方法，其中，形成所述位线结构的工艺步骤包括：形成多个分立的初始位线结构，在平行于所述初始位线结构的方向上，所述初始位线结构的顶部宽度大于或等于底部宽度；对所述初始位线结构进行具有刻蚀角度的干法刻蚀工艺，形成顶部具有倒角的所述位线结构，所述倒角的角度与所述刻蚀角度相同，所述倒角的角度为5°～35°。
  10. 根据权利要求8或9所述的半导体结构的制作方法，其中，形成所述牺牲层和所述隔离层的工艺步骤，包括：在所述位线结构侧壁形成牺牲膜，所述牺牲膜包括靠近所述位线结构的第一隔离部和背离所述位线结构的第二隔离部；对所述第二隔离部掺杂掺杂离子，以形成位于所述第一隔离部的牺牲层和位于所述第二隔离部的隔离层，所述隔离层的硬度大于所述牺牲层的硬度。
  11. 根据权利要求10所述的半导体结构的制作方法，其中，所述牺牲膜的材料包括氧化硅，所述掺杂离子包括氮离子。
  12. 根据权利要求10所述的半导体结构的制作方法，其中，形成所述隔离墙的工艺步骤，包括：在所述位线结构侧壁形成氮化硅层，所述氮化硅层包括靠近所述位线结构的第一隔离部和远离所述位线结构的第二隔离部；对所述氮化硅层的第二隔离部掺杂氧离子；在所述氮化硅层背离所述位线结构的侧壁形成氧化硅层，所述氧化硅层包括靠近所述位线结构的第一隔离部和远离所述位线结构的第二隔离部；对所述氧化硅层的第二隔离部掺杂氮离子；去除第 一隔离部的所述氧化硅层，形成所述空隙。
  13. 根据权利要求12所述的半导体结构的制作方法，其中，在掺杂所述氧离子的过程中，所述氧离子的温度为800℃～1000℃；在掺杂所述氮离子的过程中，所述氮离子的的温度为600℃～800℃。
  14. 根据权利要求8所述的半导体结构的制作方法，其中，在刻蚀所述牺牲层之前，填充所述电容接触孔，形成支撑结构，所述支撑结构与所述隔离层背离所述位线结构的侧壁相接触；在刻蚀所述牺牲层之后，去除所述支撑结构。
  15. 根据权利要求8所述的半导体结构的制作方法，其中，在形成所述空隙之后，进行沉积工艺，形成封堵所述空隙顶部开口的封口层。
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