WO2022183718A1 - 半导体结构的制造方法和半导体结构 - Google Patents

半导体结构的制造方法和半导体结构 Download PDF

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Publication number
WO2022183718A1
WO2022183718A1 PCT/CN2021/120250 CN2021120250W WO2022183718A1 WO 2022183718 A1 WO2022183718 A1 WO 2022183718A1 CN 2021120250 W CN2021120250 W CN 2021120250W WO 2022183718 A1 WO2022183718 A1 WO 2022183718A1
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layer
initial
semiconductor structure
contact
initial contact
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PCT/CN2021/120250
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English (en)
French (fr)
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刘忠明
白世杰
陈龙阳
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长鑫存储技术有限公司
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Priority to EP21928793.5A priority Critical patent/EP4235788A4/en
Priority to US17/545,213 priority patent/US20220278107A1/en
Publication of WO2022183718A1 publication Critical patent/WO2022183718A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate

Definitions

  • the embodiments of the present application relate to, but are not limited to, a method for fabricating a semiconductor structure and a semiconductor structure.
  • DRAM Dynamic Random Access Memory
  • bit binary bit
  • An embodiment of the present application provides a method for fabricating a semiconductor structure, including: providing a substrate having bit lines extending in a first direction and trenches between adjacent bit lines; forming and filling the an initial contact layer and an initial protective layer of the trench, the initial contact layer is in contact with the substrate, and the initial protective layer is located on the initial contact layer; patterning the initial contact layer and the initial protective layer processing to form mutually separated contact layers and mutually separated protective layers; a dielectric layer is formed between the adjacent contact layers, the dielectric layer is also located between the adjacent protective layers, and the dielectric layers are The material is different from that of the protective layer.
  • Embodiments of the present application further provide a semiconductor structure, comprising: a substrate having bit lines extending in a first direction on the substrate; and mutually discrete contact layers located between adjacent bit lines, and the contacts The layer is in contact with the substrate, and the top surface of the contact layer is lower than the top surface of the bit line; the dielectric layer is located between the adjacent contact layers, and the dielectric layer is also in contact with the substrate.
  • FIGS. 1-10 are schematic structural diagrams corresponding to each step in the manufacturing method of the semiconductor structure provided by the embodiments of the present application.
  • a DRAM usually includes structures such as a substrate, a bit line, a capacitor, and a contact layer, and the contact layer is used to realize the electrical connection between the substrate and the capacitor.
  • the sidewall of the contact layer is prone to concave morphology, and the concave sidewall morphology will reduce the volume of the contact layer, thereby increasing the resistance of the contact layer, thereby reducing the electrical conductivity of the contact layer. performance.
  • the method of forming the contact layer is usually: forming an initial contact material layer filling the trenches between adjacent bit lines; patterning the initial contact material layer to form mutually discrete contact layers, that is, using an etching process Part of the initial contact material layer is removed, and the remaining initial contact material layer is used as a contact layer.
  • the ratio of the height to width of the initial contact material layer becomes larger and larger; a larger aspect ratio will increase the etching difficulty of the initial contact material layer; in addition, the initial contact material layer is relatively
  • the large height also increases the etching time, thereby increasing the etching degree of the etching gas to the sidewall of the initial contact material layer, so that the finally formed contact layer has a concave sidewall morphology.
  • An embodiment of the present application provides a method for manufacturing a semiconductor structure.
  • FIGS. 1-10 are schematic structural diagrams corresponding to each step in the method for manufacturing a semiconductor structure provided by an embodiment of the present application, which will be described in detail below with reference to the accompanying drawings.
  • a substrate 100 is provided having bit lines 103 extending in a first direction X and trenches 107 between adjacent bit lines 103 thereon.
  • bit line 103 and the trench 107 both extend along the first direction X.
  • the substrate 100 includes a plurality of discrete active regions 101 , and each active region 101 has a source electrode and a drain electrode therein.
  • the subsequently formed capacitor needs to be electrically connected to the source/drain.
  • the material of the active region 101 may be single crystal silicon, and the single crystal silicon has doping ions such as boron or phosphorus.
  • the substrate 100 also includes isolation structures 102 for isolating adjacent active regions 101 .
  • the material of the isolation structure 102 is an insulating material, such as silicon dioxide, silicon carbide or silicon nitride.
  • the bit line 103 includes: a conductive layer 104 and an insulating capping layer 105 arranged in layers, and an isolation layer 106 covering the sidewalls of the conductive layer 104 and the insulating capping layer 105 .
  • the conductive layer 104 may include a bit line contact layer, a barrier layer, and a metal layer that are stacked.
  • the bit line contact layer is used to electrically connect the metal layer and the active region 101 of the substrate 100 , and its material may be polysilicon.
  • the barrier layer is used for blocking the interdiffusion between the metal layer and the bit line contact layer, and also for increasing the adhesion between the metal layer and the bit line contact layer, and the material can be titanium nitride or tantalum nitride.
  • the material of the metal layer may be tungsten or molybdenum.
  • the insulating cap layer 105 is used to prevent oxidation of the conductive layer, and its material is an insulating material.
  • the material of the insulating cap layer 105 is silicon nitride, which has greater hardness and density, and can improve the isolation effect.
  • the isolation layer 106 is also located on the top surface of the insulating cap layer 105 and the surface of the substrate 100 . In some embodiments of the present application, the isolation layer may only cover the sidewalls of the conductive layer. The isolation layer 106 can prevent the conductive layer 104 from being electrically connected to a subsequently formed contact layer.
  • the material of the isolation layer 106 may be silicon nitride or silicon oxynitride.
  • a contact layer will be formed in the trenches 107 later. Since the contact layer is used to realize the electrical connection between the source/drain and the capacitors formed later, each trench 107 exposes all the source/drain in the first direction X. Drain, so that the subsequently formed contact layer can be in contact with the source/drain.
  • an initial contact layer 108b and an initial protective layer 109b filling the trench 107 are formed, the initial contact layer 108b is in contact with the substrate 100, and the initial protective layer 109b is located on the initial contact layer 108b.
  • the material of the initial contact layer 108b is a conductive material, and in the embodiment of the present application, the material of the initial contact layer 108b is polysilicon.
  • the interface defect between the initial contact layer 108b of polysilicon material and the active region 101 of silicon material is less.
  • the material of the initial contact layer may also be polycrystalline germanium.
  • the initial protective layer 109b is located on the surface of the initial contact layer 108b away from the substrate 100 . It can be understood that, under the condition that the depth of the trench 107 remains unchanged, since the initial protective layer 109b occupies a certain space in the direction of the depth of the trench 107, correspondingly, compared with the initial contact layer 108b, the trench 107 is filled completely alone. , the stacked structure of the initial protective layer 109b and the initial contact layer 108b reduces the space occupied by the initial contact layer 108b in the direction of the depth of the trench 107 , that is, the height of the initial contact layer 108b decreases.
  • the difficulty of subsequent patterning of the initial contact layer 108b can be reduced; the etching time of the initial contact layer 108b can also be reduced, thereby reducing the degree of etching on the sidewall of the initial contact layer 108b to ensure the final formed contact layer It has a relatively vertical sidewall morphology, thereby improving the electrical properties of the contact layer.
  • the initial protective layer 109b and the initial contact layer 108b have a better interface contact state.
  • the interface has fewer defects such as voids, protrusions or depressions. It is understandable that in the process of patterning, when etching to the junction of the two, since there are few defects at the interface, it is difficult for the etching gas to enter the defects such as cavities, protrusions or depressions. Therefore, etching It is difficult for the gas to expand the volume of the defect, and it will not cause the interface and the sidewall corresponding to the interface to form uneven topography. That is, a good interface contact state between the initial protective layer 109b and the initial contact layer 108b can improve the uniformity of etching, thereby improving the precision of the pattern, and further improving the flatness of the sidewall corresponding to the interface.
  • the material of the initial protective layer 109b may be silicon oxide. In some embodiments of the present application, the material of the initial protective layer may also be silicon oxynitride.
  • the steps of forming the initial contact layer 108b and the initial protective layer 109b include:
  • an initial contact material layer 108a is formed that fills the trenches 107 (refer to FIG. 1).
  • the initial contact material layer 108a is formed by a low pressure chemical vapor deposition method.
  • the reaction gas for low pressure chemical vapor deposition may be H 3 SiN(C 3 H 7 ) 2 , Si 2 H 6 or SiH[N(CH 3 ) 2 ] 3 .
  • the temperature of the low pressure chemical vapor deposition is 380°C to 500°C, for example, 400°C, 450°C and 480°C.
  • the activity of the reactive gas can be increased, thereby accelerating the reaction rate and further increasing the formation rate of the initial contact material layer 108a.
  • the pressure of the low-pressure chemical vapor deposition is 1 Torr to 3 Torr, for example, 1.5 Torr or 2 Torr.
  • the gas diffusion coefficient can be increased, thereby accelerating the mass transfer rate of the gaseous reactants and by-products, thereby increasing the formation rate of the initial contact material layer 108a.
  • an atmospheric pressure chemical vapor deposition method can also be used to form the initial contact material layer.
  • the isolation layer 106 on the surface of the substrate 100 is removed, and part of the isolation structure 102 is removed, so as to increase the area of the exposed surface of the active region 101, so that the formed surface area can be increased.
  • chemical mechanical polishing is further performed on the top surface of the initial contact material layer 108a, so as to improve the flatness of the top surface of the initial contact material layer 108a.
  • the initial contact material layer 108a (refer to FIG. 2) is etched back so that the top surface of the remaining initial contact material layer 108a is lower than the top surface of the bit line 103, and the remaining initial contact material layer 108a is used as the initial contact layer 108b .
  • the ratio of the height of the initial contact layer 108b to the height of the bit line 103 is 1:3 ⁇ 2:3. It can be understood that if the height of the initial contact layer 108b is too large, the difficulty of subsequent patterning of the initial contact layer 108b will be increased accordingly. If the height of the initial contact layer 108b is too small, the resistance of the initial contact layer 108b will increase, thereby reducing the operating speed of the semiconductor structure. When the height of the initial contact layer 108b is within the above range, it can have a relatively low resistance, and at the same time, it can reduce the difficulty of the subsequent patterning process.
  • the top surface of the initial contact layer 108b is flush with the top surface of the conductive layer 104 .
  • an initial protective layer 109b is formed on the initial contact layer 108b, and the top surface of the initial protective layer 109b is not lower than the top surface of the bit line 103 .
  • the top surface of the initial protection layer 109b is flush with the top surface of the bit line 103 .
  • the top surface of the initial protective layer may also be higher than the top surface of the bit line.
  • the method for forming the initial protective layer 109b is a spin coating process.
  • the spin coating process can improve the uniformity of the initial protective layer 109b, and can also reduce the gaps formed in the initial protective layer 109b.
  • the spin coating process has high production efficiency and low cost.
  • chemical vapor deposition may also be used to form the initial protective layer.
  • chemical mechanical polishing is further performed on the top surface of the initial protective layer 109b, so as to improve the flatness of the top surface of the initial protective layer 109b.
  • FIG. 6 is a cross-sectional view along the direction A-A1 of FIG. 5 , the initial contact layer 108b (refer to FIG. 4 ) and the initial protective layer 109b (refer to FIG. 4 ) are patterned to form mutual Discrete contact layer 108 and mutually discrete protective layer 109 .
  • the initial contact layer 108b, the initial protective layer 109b and part of the insulating cap layer 105 are etched to form an isolation trench 110 spanning the initial protective layer 109b and the insulating cap layer 105; the isolation trench 110 also penetrates the initial contact layer 108b ; The bottom of the isolation trench 110 in the remaining insulating cap layer 105 is higher than the top of the conductive layer 104 .
  • part of the isolation layer 106 is also etched. That is, for the bit line 103, only a part of the insulating capping layer 105 and the isolation layer 106 are removed, while the entire conductive layer 104 and part of the insulating capping layer 105 and part of the isolation layer 106 remain.
  • the isolation trenches 110 extend in the second direction Y, which is different from the first direction X.
  • the second direction Y is perpendicular to the first direction X.
  • the included angle between the second direction and the first direction may be less than 90° and greater than or equal to 75°.
  • the remaining initial contact layer 108b serves as the contact layer 108
  • the remaining initial protective layer 109b serves as the protective layer 109 .
  • isolation trench 110 The formation methods of the isolation trench 110 , the contact layer 108 and the protective layer 109 will be described in detail below.
  • a mask layer extending in the second direction Y is formed on the preliminary protective layer 109b and the bit line 103 . Using the mask layer as a mask, the initial protective layer 109b is etched.
  • the material of the mask layer is carbon-containing material, such as diamond-like carbon or amorphous carbon.
  • the above-mentioned materials have greater hardness, and have a higher etching selectivity ratio to the initial protective layer 109b of silicon oxide. Therefore, the patterning process will not cause excessive consumption to the mask layer, nor will it cause over-etching of the initial protective layer 109b covered by the mask layer.
  • the radio frequency power may be set above 400W, and the etching temperature may be set at 40°C to 80°C. In this way, the remaining insulating capping layer 105 can be guaranteed to have a larger thickness to protect the conductive layer 104 .
  • the etching gas can be C 4 F 6 , C 4 F 8 , O 2 , Ar, CO, N 2 and other gases.
  • the etching is stopped.
  • the remaining initial protective layers 109b separated from each other serve as the protective layer 109 .
  • the mask layer is removed by a plasma ashing process, and the initial contact layer 108b (refer to FIG. 4) is patterned by using the protective layer 109 as a mask.
  • the reactive gas of the plasma ashing process may be a mixed gas of O 2 and N 2 .
  • a fluorine-containing gas can be used to remove the oxide layer to prevent the oxide layer from affecting the subsequent patterning of the initial contact layer 108b.
  • the etching selection ratio of the patterning process to the initial contact layer 108b and the insulating cap layer 105 is 3:1 ⁇ 50:1.
  • a dry etching process is used for patterning.
  • the temperature of dry etching is 20°C to 80°C, for example, it can be 40°C, 60°C or 70°C.
  • the temperature of dry etching will affect the reaction speed of the etching gas and the material to be etched. When the dry etching temperature is within the above range, a faster etching rate can be obtained.
  • the pressure of dry etching is 5 mTorr to 50 mTorr, for example, 10 mTorr, 30 mTorr or 40 mTorr.
  • the pressure here refers to the pressure of the process chamber. If the chamber pressure is small, the molecular density of the etching gas in the chamber will be smaller, and the physical etching of the plasma will be stronger. The eclipse selection ratio is smaller. Therefore, when the dry etching pressure is within the above-mentioned larger range, the etching selectivity ratio of the initial contact layer 108b and the insulating cap layer 105 can be improved to a certain extent.
  • the radio frequency power of dry etching is 400W to 1500W, for example, it can be 600W, 800W or 1000W.
  • the ion beam has sufficient energy, which can speed up the etching rate.
  • the etching gas for dry etching is C 4 F 6 .
  • the etching of polysilicon by the fluorine-containing gas has good isotropy, so that the finally formed contact layer 108 has a relatively vertical sidewall morphology, thereby improving the electrical performance of the contact layer 108 .
  • the gas for dry etching may also be CF 4 , CHF 3 , CH 2 F 2 , C 5 F 8 , C 4 F 8 , Cl 2 , HBr, Ar, He, CO, A combination of one or more gases of O 2 , N 2 .
  • a dielectric layer 111 is formed between adjacent contact layers 108 , and the dielectric layer 111 is also located between adjacent protective layers 109 .
  • the dielectric layer 111 is also located on the remaining insulating capping layer 105 . In other words, the dielectric layer 111 fills the isolation trench 110 (refer to FIG. 5 ).
  • the material of the dielectric layer 111 is different from that of the protective layer 109 . It can be understood that, when the material of the dielectric layer 111 is different from the material of the protective layer 109 , the degree of damage to the protective layer 109 can be reduced in the subsequent process of removing the protective layer 109 .
  • the material of the protective layer 109 is silicon oxide
  • the material of the dielectric layer 111 is silicon nitride. Since silicon nitride is harder than silicon oxide, silicon oxide is easier to remove than silicon nitride.
  • the material of the protective layer may be silicon oxycarbide
  • the material of the dielectric layer may be silicon oxynitride.
  • the protective layer 109 is removed (refer to FIG. 7).
  • the etching selection ratio of the material of the protective layer 109 to the material of the dielectric layer 111 in the etching process for removing the protective layer 109 is 1:10 ⁇ 1:100.
  • the protective layer 109 is easier to remove, while the dielectric layer 111 is more difficult to remove, so that the loss to the dielectric layer 111 can be reduced during the process of removing the protective layer 109, and the dielectric layer 111 can be removed. 111 maintains good isolation.
  • the protective layer 109 is removed by a wet etching method. In some embodiments of the present application, a dry etching method may also be used.
  • connection layer 112 is formed on the contact layer 108 , and the dielectric layer 111 is also located between adjacent connection layers 112 . That is, the position occupied by the connection layer 112 is the position of the original protective layer 109 (refer to FIG. 7 ).
  • connection layer 112 is used to electrically connect the contact layer 108 with the capacitors formed later.
  • the connection layer 112 has a lower resistance, so that the operating speed of the semiconductor structure can be increased.
  • the material of the connection layer 112 can be a low-resistance metal such as copper, tungsten, or gold.
  • the method for forming the connection layer 112 is a physical vapor deposition method.
  • the initial protective layer 109b is formed on the initial contact layer 108b. Since the height of the trench 110 remains unchanged, the initial protective layer 109b occupies a certain height in the trench 110. Correspondingly, compared with the initial contact layer 108b occupying the entire trench 110 alone, the stack of the initial protective layer 109b and the initial contact layer 108b The layer structure can reduce the height occupied by the initial contact layer 108b in the trench 110, thereby reducing the difficulty of patterning the initial contact layer 108b, avoiding the formation of concave sidewall topography, and improving the final formed contact layer 108. electrical properties.
  • FIG. 10 is a schematic diagram of the semiconductor structure provided by an embodiment of the present application.
  • the semiconductor structure includes: a substrate 100 having a bit line extending in the first direction X on the substrate 100 103; Discrete contact layers 108 located between adjacent bit lines 103, and the contact layer 108 is in contact with the substrate 100, the top surface of the contact layer 108 is lower than the top surface of the bit lines 103; located between adjacent contact layers 108
  • the dielectric layer 111 is also in contact with the substrate 100 .
  • the substrate 100 includes a plurality of mutually discrete active regions 101 , and isolation structures 102 for isolating adjacent active regions 101 .
  • the bit line 103 includes a conductive layer 104 and an insulating capping layer 105 that are stacked and disposed, and an isolation layer 106 covering the sidewalls of the conductive layer 104 and the insulating capping layer 105 .
  • the contact layers 108 are columnar structures that are separated from each other, and are located between adjacent bit lines 103 .
  • the contact layer 108 is a capacitor contact layer, which is used to electrically connect the active region 101 and the capacitor (not shown).
  • the material of the contact layer 108 is polysilicon. In some embodiments of the present application, the material of the contact layer may be polycrystalline germanium.
  • the sidewalls of the contact layer 108 are not recessed, which would increase the resistance of the contact layer 108 . Therefore, the relatively vertical sidewall profile of the contact layer 108 can improve the electrical properties of the contact layer 108, thereby increasing the operating speed of the semiconductor structure.
  • connection layer 112 is located directly above the contact layer 108 , and the connection layer 112 is also a columnar structure separated from each other.
  • the connection layer 112 is a conductive structure with low resistivity, and can be metal such as copper, tungsten, or gold.
  • the dielectric layers 111 are located between adjacent contact layers 108 and between adjacent connection layers 112 .
  • the dielectric layer 111 is used to isolate the adjacent contact layers 108 and the adjacent connection layers 112 .
  • the dielectric layer 111 is also located in the insulating cap layer 105 , and the insulating cap layer 105 exposes the top surface of the dielectric layer 111 . That is, the dielectric layer 111 spans the connection layer 112 and the insulating cap layer 105 and penetrates the connection layer 112 .
  • the dielectric layer 111 extends in the second direction Y, which is different from the first direction X.
  • the second direction Y is perpendicular to the first direction X.
  • the angle between the second direction and the first direction may also be less than 90° and greater than or equal to 75°.
  • the contact layer 108 has a relatively vertical sidewall morphology, so that the electrical performance of the contact layer 108 can be improved, thereby improving the performance of the semiconductor structure.
  • An embodiment of the present application provides a method for fabricating a semiconductor structure, including: providing a substrate having bit lines extending in a first direction and trenches between adjacent bit lines; forming and filling the an initial contact layer and an initial protective layer of the trench, the initial contact layer is in contact with the substrate, and the initial protective layer is located on the initial contact layer; patterning the initial contact layer and the initial protective layer processing to form mutually separated contact layers and mutually separated protective layers; a dielectric layer is formed between the adjacent contact layers, the dielectric layer is also located between the adjacent protective layers, and the dielectric layers are The material is different from that of the protective layer.
  • an initial contact layer filling the trench and an initial protective layer on the initial contact layer are first formed; since the initial protective layer needs to occupy a certain height in the trench, compared with the initial contact layer alone occupying the entire
  • the stacked structure of the trench, the initial protective layer and the initial contact layer can reduce the height of the initial contact layer; in the process of patterning the initial contact layer, the smaller height of the initial contact layer can reduce the difficulty of the process; in addition, The smaller height can also shorten the time of the patterning process, thereby reducing the degree of erosion of the sidewall of the initial contact layer to avoid the formation of recessed sidewall topography, thereby improving the electrical properties of the final formed contact layer.
  • the ratio of the height of the initial contact layer to the height of the bit line is 1:3 ⁇ 2:3.
  • the height of the initial contact layer is within the above-mentioned range, its resistance is relatively small, and at the same time, the difficulty of patterning processing of the subsequent initial contact layer can be further reduced.

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Abstract

本申请实施例提供一种半导体结构的制造方法和半导体结构，制造方法包括：提供基底，基底上具有在第一方向上延伸的位线以及位于相邻位线之间的沟槽；形成填充沟槽的初始接触层以及初始保护层，初始接触层与基底接触，初始保护层位于初始接触层上；对初始接触层以及初始保护层进行图形化处理，以形成相互分立的接触层和相互分立的保护层；在相邻接触层之间形成介质层，介质层还位于相邻保护层之间，且介质层的材料与保护层的材料不同。本申请实施例能够提高半导体结构的性能。

Description

半导体结构的制造方法和半导体结构
相关申请的交叉引用
本申请基于申请号为202110226832.5、申请日为2021年03月01日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请实施例涉及但不限于一种半导体结构的制造方法和半导体结构。
背景技术
半导体结构中的动态随机存取存储器(Dynamic Random Access Memory，简称DRAM)是一种广泛应用于计算机系统的半导体存储器。DRAM的主要作用原理是利用电容内存储电荷的多寡来代表一个二进制比特(bit)是1还是0。
然而，为提高半导体集成电路的集成度，DRAM的特征尺寸越来越小；从而使得DRAM的制作工艺难度越来越大，其性能也有待进一步提升。
发明内容
本申请实施例提供一种半导体结构的制造方法，包括：提供基底，所述基底上具有在第一方向上延伸的位线以及位于相邻所述位线之间的沟槽；形成填充所述沟槽的初始接触层以及初始保护层，所述初始接触层与所述基底接触，所述初始保护层位于所述初始接触层上；对所述初始接触层以及所述初始保护层进行图形化处理，以形成相互分立的接触层和相互分立的保护层；在相邻所述接触层之间形成介质层，所述介质层还位于相邻所述保护层之间，且所述介质层的材料与所述保护层的材料不同。
本申请实施例还提供一种半导体结构，包括：基底，所述基底上具有在第一方向上延伸的位线；位于相邻所述位线之间的相互分立的接触层，且所述接触层与所述基底接触，所述接触层的顶面低于所述位线的顶面；位于相邻所述接触层之间的介质层，所述介质层还与所述基底接触。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制。
图1-图10为本申请实施例提供的半导体结构的制造方法中各步骤对应的结构示意图。
具体实施方式
由背景技术可知，DRAM的制作工艺难度较大，其性能也有待进一步提升。DRAM通常包括基底、位线、电容以及接触层等结构，接触层用于实现基底与电容的电连接。经分析发现，现目前的接触层的制造工艺较为复杂，从而提高了DRAM的制作工艺难度；且接触层的电性能也较差，从而降低了DRAM的性能。进一步分析发现，在接触层的形成过程中，其侧壁容易产生凹陷的形貌，而凹陷的侧壁形貌会减小接触层的体积，进而提高接触层的电阻，从而降低接触层的电性能。
形成接触层的方法通常为：形成填充满相邻位线之间的沟槽的初始接触材料层；对初始接触材料层进行图形化处理，以形成相互分立的接触层，即采用刻蚀的工艺去除部分初始接触材料层，剩余的初始接触材料层作为接触层。然而，随着DRAM特征尺寸的不断缩小，初始接触材料层的高度与宽度的比值越来越大；较大的高宽比会提高初始接触材料层的刻蚀难度；另外，初始接触材料层较大的高度还会增加刻蚀时间，从而增大刻蚀气体对初始接触材料层侧壁的刻蚀程度，使得最终形成的接触层具有凹陷的侧壁形貌。
本申请实施例提供一种半导体结构的制造方法，先形成填充沟槽的初始接触层以及位于初始接触层上的初始保护层；由于初始保护层在沟槽中占据一定高度，相比于初始接触层独自占据整个沟槽，初始保护层和初始接触层的叠层结构会减小初始接触层的高度；在对初始接触层进行图形化处理的过程中，初始接触层较小的高度可以降低工艺难度；另外，较小的高度也可以缩短图形化处理的时间，从而降低对初始接触层侧壁的侵蚀程度，以避免形成凹陷的侧壁形貌，从而提高最终形成的接触层的电性能。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改， 也可以实现本申请所要求保护的技术方案。
本申请实施例提供一种半导体结构的制造方法，图1-图10为本申请实施例提供的半导体结构的制造方法中各步骤对应的结构示意图，以下将结合附图进行具体说明。
参考图1，提供基底100，基底100上具有在第一方向X上延伸的位线103以及位于相邻位线103之间的沟槽107。
本申请实施例中，位线103与沟槽107均沿第一方向X延伸。
基底100包括多个相互分立的有源区101，每一有源区101内具有源极和漏极。后续形成的电容需要与源极/漏极实现电连接。有源区101的材料可以为单晶硅，单晶硅中具有硼或磷等掺杂离子。
基底100还包括用于隔离相邻有源区101的隔离结构102。隔离结构102的材料为绝缘材料，比如可以为二氧化硅、碳化硅或氮化硅。
位线103包括：层叠设置的导电层104和绝缘盖层105，以及覆盖导电层104和绝缘盖层105侧壁的隔离层106。
本申请实施例中，导电层104可以包括层叠设置的位线接触层、阻挡层和金属层。位线接触层用于将金属层和基底100的有源区101电连接，其材料可以为多晶硅。阻挡层用于阻挡金属层与位线接触层的互扩散，还用于增大金属层与位线接触层的黏附性，其材料可以为氮化钛或氮化钽。金属层的材料可以为钨或钼。
绝缘盖层105用于防止导电层的氧化，其材料为绝缘材料。本申请实施例中，绝缘盖层105的材料为氮化硅，氮化硅具有较大的硬度和致密度，能够提高隔离的效果。
本申请实施例中，隔离层106还位于绝缘盖层105的顶面和基底100的表面。在本申请的一些实施例中，隔离层可以只覆盖导电层的侧壁。隔离层106可以防止导电层104与后续形成的接触层发生电连接。隔离层106的材料可以为氮化硅或氮氧化硅。
后续将在沟槽107内形成接触层，由于接触层用于实现源极/漏极与后续形成的电容的电连接，因此，每一沟槽107露出第一方向X上的所有的源极/漏极,以使后续形成的接触层能够与源极/漏极相接触。
参考图2-图4，形成填充沟槽107(参考图1)的初始接触层108b以及初始保护层109b，初始接触层108b与基底100接触，初始保护层109b位于初始接触层108b上。
本申请实施例中，初始接触层108b的材料为导电材料，本申请实施例中，初始接触层108b的材料为多晶硅。多晶硅材料的初始接触层108b与硅材料的有源区101的界面缺陷较少。在本申请的一些实施例中，初始接触层的材料也可以为多晶锗。
初始保护层109b位于初始接触层108b远离基底100的表面。可以理解的是，在沟槽107深度不变的情况下，由于初始保护层109b在沟槽107深度的方向上占据一定的空间，相应的，相比于初始接触层108b单独填充满沟槽107，初始保护层109b与初始接触层108b的叠层结构会减小初始接触层108b在沟槽107深度的方向上所占据的空间，即初始接触层108b的高度减小。如此，可以降低后续初始接触层108b的图形化处理的难度；还可以减少初始接触层108b的刻蚀时间，从而减小对初始接触层108b侧壁的刻蚀程度，以保证最终形成的接触层具有较为竖直的侧壁形貌，进而提高接触层的电性能。
初始保护层109b和初始接触层108b具有较好的界面接触状态。本申请实施例中，界面的空洞、凸起或凹陷等缺陷较少。可以理解的是，在图形化处理的过程中，当刻蚀到二者交界处时，由于界面的缺陷较少，刻蚀气体很难进入空洞、凸起或凹陷等缺陷处，因此，刻蚀气体很难扩大缺陷的体积，也不会导致界面以及界面所对应的侧壁形成凹凸不平的形貌。即初始保护层109b与初始接触层108b的良好的界面接触状态，可以提高刻蚀的均匀性，进而能够提高图形的精度，还能够进一步提高界面对应的侧壁的平整度。
氧化硅和多晶硅具有较好的亲和性，二者具有较好的界面接触状态。本 申请实施例中，初始保护层109b的材料可以为氧化硅。在本申请的一些实施例中，初始保护层的材料还可以为氮氧化硅。
在本申请的一些实施例中，形成初始接触层108b以及初始保护层109b的步骤包括：
参考图2，形成填充满沟槽107(参考图1)的初始接触材料层108a。
本申请实施例中，采用低压化学气相沉积法形成初始接触材料层108a。
低压化学气相沉积的反应气体可以为H 3SiN(C 3H 7) 2、Si 2H 6或者SiH[N(CH 3) 2] 3。
低压化学气相沉积的温度为380℃～500℃，比如可以为400℃、450℃和480℃。温度在上述范围内，能够提高反应气体的活性，从而加快反应速率，进而提高初始接触材料层108a的形成速率。
低压化学气相沉积的压强为1Torr～3Torr，比如可以为1.5Torr或2Torr。压强在上述范围内，能够增大气体扩散系数，从而使气态反应物和副产物的质量传输速率加快，进而提高初始接触材料层108a的形成速率。
在本申请的一些实施例中，也可以采用常压化学气相沉积法形成初始接触材料层。
本申请实施例中，在形成初始接触材料层108a之前，去除基底100表面的隔离层106，并去除部分隔离结构102，以增大有源区101露出的表面的面积，如此可以增大形成的初始接触层108b与有源区101的接触面积，从而降低接触电阻。
本申请实施例中，在形成初始接触材料层108a后，还对初始接触材料层108a的顶面进行化学机械研磨，以提高初始接触材料层108a顶面的平坦度。
参考图3，回刻初始接触材料层108a(参考图2)，以使剩余的初始接触材料层108a的顶面低于位线103的顶面，剩余的初始接触材料层108a作为初始接触层108b。
在垂直于沟槽107底部的方向上，初始接触层108b的高度与位线103的 高度的比值为1：3～2：3。可以理解的是，若初始接触层108b的高度过大，相应的，会提高后续图形化初始接触层108b的难度。若初始接触层108b的高度过小，则会提高初始接触层108b的电阻，从而降低半导体结构的运行速率。初始接触层108b的高度在上述范围内，可以具有较小的电阻，同时能够降低后续图形化处理的难度。
本申请实施例中，初始接触层108b的顶面与导电层104的顶面齐平。
参考图4，在初始接触层108b上形成初始保护层109b，且初始保护层109b顶面不低于位线103的顶面。
本申请实施例中，初始保护层109b的顶面与位线103的顶面齐平。在本申请的一些实施例，初始保护层的顶面还可以高于位线的顶面。
本申请实施例中，形成初始保护层109b的方法为旋转涂敷工艺。旋转涂敷工艺可以提高初始保护层109b的均匀性，还可以减少初始保护层109b中形成的缝隙。另外，旋转涂敷工艺的生产效率高，成本低。在本申请的一些实施例中，也可以使用化学气相沉积法形成初始保护层。
本申请实施例中，在形成初始保护层109b后，还对初始保护层109b的顶面进行化学机械研磨，以提高初始保护层109b顶面的平坦度。
参考图5-图6，图6为图5沿着A-A1方向的剖面图，对初始接触层108b(参考图4)以及初始保护层109b(参考图4)进行图形化处理，以形成相互分立的接触层108和相互分立的保护层109。
本申请实施例中，刻蚀初始接触层108b、初始保护层109b和部分绝缘盖层105，形成横跨初始保护层109b和绝缘盖层105的隔离槽110；隔离槽110还贯穿初始接触层108b；位于剩余绝缘盖层105内的隔离槽110的底部高于导电层104的顶部。
本申请实施例中，还刻蚀部分隔离层106。即对于位线103，只去除了部分厚度的绝缘盖层105和隔离层106，而保留整个导电层104以及部分厚度的绝缘盖层105和部分厚度的隔离层106。
隔离槽110在第二方向Y上延伸，第二方向Y与第一方向X不同。本申请实施例中，第二方向Y垂直于第一方向X。在本申请的一些实施例中，第二方向与第一方向的夹角可以小于90°，且大于或等于75°。
剩余的初始接触层108b作为接触层108，剩余的初始保护层109b作为保护层109。
以下将对隔离槽110、接触层108和保护层109的形成方法进行具体说明。
在初始保护层109b和位线103上形成沿第二方向Y延伸的掩膜层。以掩膜层为掩膜，刻蚀初始保护层109b。
掩膜层的材料为含碳材料，比如可以为类金刚石碳或非晶碳。上述材料具有较大的硬度，且与氧化硅的初始保护层109b具有较高的刻蚀选择比。因此，图形化处理的过程不会对掩膜层造成过度的消耗，也不会对掩膜层所覆盖的初始保护层109b造成过刻蚀。
由于部分绝缘盖层105和隔离层106未被掩膜覆盖，因此，在刻蚀初始保护层109b的过程中，也会刻蚀部分绝缘盖层105和隔离层106。为提高初始保护层109b与绝缘盖层105的选择刻蚀比，可以将射频功率设置在400W以上，将刻蚀温度设置为40℃～80℃。如此，可以保证剩余的绝缘盖层105具有较大的厚度以保护导电层104。
刻蚀气体可以为C 4F 6、C 4F 8、O 2、Ar、CO、N 2等气体。
本申请实施例中，将初始保护层109b(参考图4)贯穿时，即停止刻蚀。剩余的相互分立的初始保护层109b作为保护层109。
在初始保护层109b的刻蚀完成后，采用等离子体灰化工艺去除掩膜层，并以保护层109为掩膜对初始接触层108b(参考图4)进行图形化处理。
在本申请的一些实施例中，等离子体灰化处理的反应气体可以为O 2和N 2的混合气体。等离子灰化处理的过程中会在初始接触层108b的表面产生氧化层，可以采用含氟气体去除氧化层，以防止氧化层影响后续初始接触层108b的图形化处理。
图形化处理对初始接触层108b和绝缘盖层105的刻蚀选择比为3:1～50:1。当初始接触层108b和绝缘盖层105的刻蚀选择比较大时，能够避免未将初始接触层108b贯穿的问题，以及避免将整个绝缘盖层105去除并暴露出导电层104的问题。
本申请实施例中，采用干法刻蚀工艺进行图形化处理。且干法刻蚀的温度为20℃～80℃，比如可以为40℃、60℃或70℃。干法刻蚀的温度会影响刻蚀气体与被刻蚀材料的反应速度。当干法刻蚀的温度在上述范围内时，能够获得较快的刻蚀速率。
干法刻蚀的压力为5mTorr～50mTorr，比如可以为10mTorr、30mTorr或40mTorr。此处的压力是指工艺腔室的压力，若腔室压力较小，则腔室内刻蚀气体的分子密度就越小，那么等离子体的物理刻蚀就越强，相比而言，其刻蚀选择比越小。因此，当干法刻蚀的压力在上述较大的范围内时，能够在一定程度上提高初始接触层108b和绝缘盖层105的刻蚀选择比。
干法刻蚀的射频功率为400W～1500W，比如可以为600W、800W或1000W。射频功率在上述范围内时，离子束具有较充足的能量，能够加快刻蚀速率。
本申请实施例中，干法刻蚀的刻蚀气体为C 4F 6。含氟气体对多晶硅的刻蚀具有较好的各向同性，能够使得最终形成的接触层108具有较为竖直的侧壁形貌，进而能够提高接触层108的电性能。在本申请的一些实施例中，干法刻蚀的气体还可以为CF 4、CHF 3、CH 2F 2、C 5F 8、C 4F 8、Cl 2、HBr、Ar、He、CO、O 2、N 2中一种或多种气体的组合。
参考图7和图8，在相邻接触层108之间形成介质层111，介质层111还位于相邻保护层109之间。本申请实施例中介质层111还位于剩余的绝缘盖层105上。换句话说，介质层111填充隔离槽110(参考图5)。
介质层111的材料与保护层109的材料不同。可以理解的是，当介质层111的材料与保护层109的材料不同时，后续在去除保护层109的过程中可以减小对保护层109的损伤程度。本申请实施例中，保护层109的材料为氧化 硅，介质层111的材料为氮化硅。由于氮化硅的硬度比氧化硅的硬度大，因此，氧化硅比氮化硅更易去除。在本申请的一些实施例中，保护层的材料可以为碳氧化硅，介质层的材料可以为氮氧化硅。
参考图9，形成介质层111后，去除保护层109(参考图7)。
在本申请的一些实施例中，去除保护层109的刻蚀工艺对保护层109的材料与介质层111的材料的刻蚀选择比为1：10～1：100。当保护层109与介质层111的刻蚀选择比较大时，保护层109更易去除，而介质层111则较难去除，从而能够在去除保护层109过程降低对介质层111的损耗，使介质层111保持较好的隔离作用。
本申请实施例中，采用湿法刻蚀的方法去除保护层109。在本申请的一些实施例中，也可以采用干法刻蚀的方法。
参考图10，在接触层108上形成连接层112，且介质层111还位于相邻连接层112之间。即连接层112所占据的位置为原有保护层109(参考图7)的位置。
连接层112用于电连接接触层108与后续形成的电容。连接层112具有较低的电阻，从而可以提高半导体结构的运行速率。连接层112的材料可以为铜、钨或金等低电阻金属。本申请实施例中，形成连接层112的方法为物理气相沉积法。
综上所述，本申请实施例在初始接触层108b上形成初始保护层109b。由于沟槽110的高度不变，初始保护层109b在沟槽110中占据一定高度，相应的，相比于初始接触层108b独自占据整个沟槽110，初始保护层109b和初始接触层108b的叠层结构能够减小初始接触层108b在沟槽110中占据的高度，从而可以降低对初始接触层108b进行图形化处理的难度，避免形成凹陷的侧壁形貌，进而提高最终形成的接触层108的电性能。
本申请实施例还提供一种半导体结构，图10为本申请实施例提供的半导体结构的示意图，参考图10，半导体结构包括：基底100，基底100上具有 在第一方向X上延伸的位线103；位于相邻位线103之间的相互分立的接触层108，且接触层108与基底100接触，接触层108的顶面低于位线103的顶面；位于相邻接触层108之间的介质层111，介质层111还与基底100接触。
以下将结合附图进行具体说明。
基底100包括多个相互分立的有源区101，以及用于隔离相邻有源区101的隔离结构102。
位线103包括层叠设置的导电层104和绝缘盖层105，以及覆盖导电层104和绝缘盖层105侧壁的隔离层106。
有关基底100以及位线103的具体说明请参考前述内容，在此不再赘述。
接触层108为相互分立的柱状结构，且位于相邻位线103之间。本申请实施例中，接触层108为电容接触层，用于电连接有源区101和电容(未图示)。本申请实施例中，接触层108的材料为多晶硅。在本申请的一些实施例中，接触层的材料可以为多晶锗。
接触层108的侧壁没有凹陷，而凹陷会提高接触层108的电阻。因此，接触层108较为竖直的侧壁形貌可以提高接触层108的电性能，进而提高半导体结构的运行速率。
连接层112位于接触层108的正上方，连接层112也为相互分立的柱状结构。连接层112为导电结构，其具有较低的电阻率，可以为铜、钨或金等金属。
介质层111位于相邻接触层108之间，以及相邻连接层112之间。介质层111用于隔离相邻接触层108以及相邻连接层112。本申请实施例中，介质层111还位于绝缘盖层105内，且绝缘盖层105露出介质层111的顶面。即介质层111横跨连接层112和绝缘盖层105，并且贯穿连接层112。
介质层111在第二方向Y上延伸，第二方向Y与第一方向X不同。本申请实施例中，第二方向Y与第一方向X垂直，在本申请的一些实施例中，第二方向与第一方向的夹角也可以小于90°，且大于或等于75°。
综上所述，本申请实施例中，接触层108具有较为竖直的侧壁形貌，如此可以提高接触层108的电性能，进而提高半导体结构的性能。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。
工业实用性
本申请实施例提供一种半导体结构的制造方法，包括：提供基底，所述基底上具有在第一方向上延伸的位线以及位于相邻所述位线之间的沟槽；形成填充所述沟槽的初始接触层以及初始保护层，所述初始接触层与所述基底接触，所述初始保护层位于所述初始接触层上；对所述初始接触层以及所述初始保护层进行图形化处理，以形成相互分立的接触层和相互分立的保护层；在相邻所述接触层之间形成介质层，所述介质层还位于相邻所述保护层之间，且所述介质层的材料与所述保护层的材料不同。
可以看出，本申请实施例先形成填充沟槽的初始接触层以及位于初始接触层上的初始保护层；由于初始保护层需在沟槽中占据一定高度，相比于初始接触层独自占据整个沟槽，初始保护层和初始接触层的叠层结构能够减小初始接触层的高度；在对初始接触层进行图形化处理的过程中，初始接触层较小的高度可以降低工艺难度；另外，较小的高度也可以缩短图形化处理的时间，从而降低对初始接触层侧壁的侵蚀程度，以避免形成凹陷的侧壁形貌，从而提高最终形成的接触层的电性能。
另外，初始接触层的高度与位线的高度的比值为1：3～2：3。初始接触层的高度在上述范围内，其电阻较小，同时能够进一步降低后续初始接触层的图形化处理的难度。

Claims (17)

  1. 一种半导体结构的制造方法，包括：
    提供基底，所述基底上具有在第一方向上延伸的位线以及位于相邻所述位线之间的沟槽；
    形成填充所述沟槽的初始接触层以及初始保护层，所述初始接触层与所述基底接触，所述初始保护层位于所述初始接触层上；
    对所述初始接触层以及所述初始保护层进行图形化处理，以形成相互分立的接触层和相互分立的保护层；
    在相邻所述接触层之间形成介质层，所述介质层还位于相邻所述保护层之间，且所述介质层的材料与所述保护层的材料不同。
  2. 根据权利要求1所述的半导体结构的制造方法，其中，形成所述初始接触层以及所述初始保护层的步骤包括：
    形成填充满所述沟槽的初始接触材料层；
    回刻所述初始接触材料层，以使剩余的所述初始接触材料层的顶面低于所述位线的顶面，剩余的所述初始接触材料层作为所述初始接触层；
    在所述初始接触层上形成所述初始保护层，且所述初始保护层顶面不低于所述位线的顶面。
  3. 根据权利要求2所述的半导体结构的制造方法，其中，采用低压化学气相沉积法形成所述初始接触材料层，且所述低压化学气相沉积法的工艺参数包括：温度为380℃～500℃，气压为1Torr～3Torr。
  4. 根据权利要求2所述的半导体结构的制造方法，其中，形成所述初始保护层的方法包括：旋转涂敷工艺。
  5. 根据权利要求1所述的半导体结构的制造方法，其中，所述初始接触层的高度与所述位线的高度的比值为1：3～2：3。
  6. 根据权利要求1所述的半导体结构的制造方法，其中，所述位线包括 层叠设置的导电层以及绝缘盖层；
    所述图形化处理包括：刻蚀所述初始接触层、所述初始保护层和部分所述绝缘盖层，形成横跨所述初始保护层和所述绝缘盖层的隔离槽；所述隔离槽还贯穿所述初始接触层；位于剩余所述绝缘盖层内的所述隔离槽的底部高于所述导电层的顶部；
    剩余的所述初始接触层作为所述接触层，剩余的所述初始保护层作为所述保护层；
    所述隔离槽在第二方向上延伸，所述第二方向与所述第一方向不同；
    所述图形化处理后，还包括步骤：形成所述介质层以填充所述隔离槽。
  7. 根据权利要求6所述的半导体结构的制造方法，其中，所述图形化处理对所述初始接触层和所述绝缘盖层的刻蚀选择比为3:1～50:1。
  8. 根据权利要求7所述的半导体结构的制造方法，其中，所述初始接触层的材料包括多晶硅，所述绝缘盖层的材料包括氮化硅。
  9. 根据权利要求1所述的半导体结构的制造方法，其中，采用干法刻蚀工艺进行所述图形化处理，且所述干法刻蚀的工艺参数包括：温度为20℃～80℃，压力为5mTorr～50mTorr，射频功率为400W～1500W。
  10. 根据权利要求1所述的半导体结构的制造方法，其中，采用干法刻蚀工艺进行所述图形化处理，且所述干法刻蚀采用的刻蚀气体包括：C 4F 6、C 4F 8、Cl 2、HBr、Ar、He、CO、O 2、N 2中一种或多种气体的组合。
  11. 根据权利要求1所述的半导体结构的制造方法，其中，形成所述介质层后，还包括步骤：去除所述保护层。
  12. 根据权利要求11所述的半导体结构的制造方法，其中，去除所述保护层的刻蚀工艺对所述保护层的材料与所述介质层的材料的刻蚀选择比为1：10～1：100。
  13. 根据权利要求12所述的半导体结构的制造方法，其中，所述保护层的材料包括氧化硅；所述介质层的材料包括氮化硅。
  14. 根据权利要求11所述的半导体结构的制造方法，去除所述保护层后，还包括步骤：在所述接触层上形成连接层，且所述介质层还位于相邻所述连接层之间。
  15. 一种半导体结构，包括：
    基底，所述基底上具有在第一方向上延伸的位线；
    位于相邻所述位线之间的相互分立的接触层，且所述接触层与所述基底接触，所述接触层的顶面低于所述位线的顶面；
    位于相邻所述接触层之间的介质层，所述介质层还与所述基底接触。
  16. 根据权利要求15所述的半导体结构，其中，所述位线包括层叠设置的导电层和绝缘盖层；所述介质层还位于所述绝缘盖层内，且所述绝缘盖层露出所述介质层的顶面；所述介质层在第二方向上延伸，所述第二方向与所述第一方向不同。
  17. 根据权利要求15所述的半导体结构，还包括：位于所述接触层上的连接层，且所述介质层还位于相邻所述连接层之间。
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