WO2022217772A1 - 存储器的制作方法及存储器 - Google Patents

存储器的制作方法及存储器 Download PDF

Info

Publication number
WO2022217772A1
WO2022217772A1 PCT/CN2021/107453 CN2021107453W WO2022217772A1 WO 2022217772 A1 WO2022217772 A1 WO 2022217772A1 CN 2021107453 W CN2021107453 W CN 2021107453W WO 2022217772 A1 WO2022217772 A1 WO 2022217772A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
protective layer
hole
etching
memory
Prior art date
Application number
PCT/CN2021/107453
Other languages
English (en)
French (fr)
Inventor
陈龙阳
刘忠明
于业笑
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/460,272 priority Critical patent/US20220336467A1/en
Publication of WO2022217772A1 publication Critical patent/WO2022217772A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present application relates to the technical field of storage devices, and in particular, to a method for manufacturing a memory and a memory.
  • Dynamic Random Access Memory is a semiconductor memory that writes and reads data at high speed and randomly, and is widely used in data storage devices or devices.
  • Dynamic random access memory generally includes transistors and capacitors. The capacitor stores data information, and the transistor controls the reading and writing of the data information in the capacitor.
  • the DRAM includes a substrate, the substrate includes an active region, and the active region includes a first contact region and a second contact region.
  • Bit lines arranged at intervals and an isolation layer covering the outside of the bit lines are arranged on the substrate.
  • the bit line is electrically connected to the first contact area, the isolation layer is formed with a contact hole, and the contact hole extends to the substrate, the contact hole is filled with a wire, and the wire is used to electrically connect the capacitor and the second contact area.
  • the substrate is usually etched along the contact holes to form contact grooves in the substrate, the contact holes and the contact grooves form filling holes, and the filling holes are filled with wires.
  • the substrate is prone to over-etching phenomenon, resulting in larger voids in the subsequently formed wires and lower memory yields.
  • an embodiment of the present application provides a method for fabricating a memory, which includes: providing a substrate, the substrate is provided with a plurality of spaced active regions, the active regions include a first contact region and a second contact region a contact region; a plurality of spaced bit lines are formed on the substrate, and each of the bit lines is connected to at least one of the first contact regions; an isolation layer is formed on the bit lines, and the isolation layer covers the bit lines and the substrate, the isolation layer is further provided with a plurality of filling holes, and the plurality of filling holes are in one-to-one correspondence with the plurality of the second contact regions; the isolation layer and the a substrate, so that the filling hole extends into the substrate, and the filling hole exposes the second contact region; a first protective layer is formed on the second contact region exposed in the filling hole; etching Etching the first protective layer and the substrate located at the bottom of the filled hole until the bottom of the filled hole is located at a preset depth of the substrate; and
  • an embodiment of the present application further provides a memory, and the memory is formed by the above-mentioned manufacturing method of the memory.
  • FIG. 1 is a schematic diagram of substrate overetching in the related art
  • FIG. 2 is a flowchart of a method for manufacturing a memory in an embodiment of the present application
  • FIG. 3 is a schematic structural diagram after forming a bit line in an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram after forming an isolation layer in an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram after etching the isolation layer and the substrate along the filling hole in the embodiment of the present application;
  • FIG. 6 is a schematic structural diagram after forming the first protective layer in an embodiment of the present application.
  • FIG. 7 is a schematic view of the structure after etching the first protective layer and the substrate at the bottom of the filled hole in an embodiment of the present application;
  • FIG. 8 is a schematic structural diagram after removing the remaining first protective layer in an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram after forming a second protective layer in an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of etching the first protective layer and the substrate at the bottom of the filled hole after the second protective layer is formed in the embodiment of the application;
  • FIG. 11 is a schematic structural diagram of the embodiment of the present application after removing the second protective layer.
  • an isolation layer with an etching hole is usually provided first, and the bottom of the etching hole can be located in the isolation layer, and then the isolation layer and the substrate are etched along the etching hole to form a first preset contact hole.
  • the predetermined contact hole exposes the second contact region; removes etching byproducts; fills a protective gas, such as nitrogen; and etches the substrate along the first predetermined contact hole to form a second predetermined contact hole.
  • the above process of forming the second preset contact hole from the etching hole usually needs to be completed within 480 minutes.
  • a critical dimension (Critical Dimension, CD for short) detection is performed, and then a film thickness measurement is performed.
  • the substrate is then isotropically etched along the first predetermined contact hole to form the contact hole, so that the contact hole exposes more second contact areas.
  • the above process of forming the contact hole from the second preset contact hole usually needs to be completed within 120 minutes.
  • the upper part of the isolation layer 300 is etched more, and the substrate 100 is prone to over-etching phenomenon, such as the area shown by the dotted line in FIG. 1 , resulting in larger gaps, The yield of memory is low.
  • the above-mentioned process of fabricating the memory usually needs to be performed in different equipment, which is prone to the problem of timeout, resulting in a low yield of the memory.
  • an embodiment of the present application provides a method for fabricating a memory.
  • a first protective layer is formed on the second contact area.
  • the first protective layer can reduce or avoid the second contact area away from the bottom of the filled hole. is etched, thereby reducing the phenomenon of over-etching of the substrate, so as to improve the quality of the wires formed subsequently, thereby improving the yield rate of the memory.
  • an embodiment of the present application provides a method for fabricating a memory, and the fabrication method includes the following steps:
  • step S101 a substrate is provided, and a plurality of active regions are arranged at intervals in the substrate, and the active regions include a first contact region and a second contact region.
  • the substrate 100 is provided with active regions 110 , and the number of the active regions 110 may be multiple, and the multiple active regions 110 are arranged at intervals, for example, the multiple active regions 110 are arranged in an array.
  • a shallow trench isolation (STI for short) structure 120 is disposed between the plurality of active regions 110 , and the shallow trench isolation structure 120 may be filled with silicon oxide (eg, SiO 2 ).
  • the plurality of active regions 110 are isolated by the shallow trench isolation structure 120 .
  • the active area 110 may include a first contact area and a second contact area, and the first contact area and the second contact area may be adjacent.
  • the first contact area is connected to the bit line 200
  • the second contact area is connected to the capacitor, so that the bit line 200 can read data information in the capacitor or write data information into the capacitor.
  • the first contact area is located at the center of the active area 110
  • the second contact area is located at both ends of the active area 110, that is, there are two second contact areas, and the two second contact areas are respectively on both sides of the first contact area.
  • the material of the active region 110 may include silicon (Si).
  • the material of the active region 110 is not limited.
  • the material of the active region 110 may also be germanium (Ge), silicon on insulator (SOI for short), or the like.
  • Step S102 forming a plurality of spaced bit lines on the substrate, and each bit line is connected to at least one first contact region.
  • a plurality of bit lines 200 are formed on the substrate 100 , the plurality of bit lines 200 are arranged at intervals, and each bit line 200 is connected to at least one first contact region. As shown in FIG. 3 , the plurality of bit lines 200 are parallel to each other, and along the extending direction of the bit lines 200 , the bit lines 200 are connected to the plurality of first contact regions located in the direction.
  • a bit line contact window 130 is formed on the substrate 100 , and the bit line 200 is connected to the first contact region through the bit line contact window 130 .
  • a part of the upper surface of the substrate 100 is recessed downward to form the bit line contact window 130 .
  • a partial area of the bit line 200 is located on the bit line contact window 130 to be electrically connected to the first contact region.
  • An insulating layer 140 such as a first silicon nitride layer, may be provided.
  • the bit line 200 may include a first conductive layer 210 , a second conductive layer 220 , a third conductive layer 230 and a third protective layer 240 which are sequentially stacked.
  • the first conductive layer 210 is disposed on the substrate 100 , that is, the third protective layer 240 is far away from the substrate 100 .
  • the first conductive layer 210 may be a polycrystalline silicon layer
  • the second conductive layer 220 may be a titanium nitride (TiN) layer
  • the third conductive layer 230 may be a tungsten (W) layer
  • the third protective layer 240 may be a second silicon nitride layer.
  • Step S103 an isolation layer is formed on the bit line, the isolation layer covers the bit line and the substrate, and the isolation layer is further provided with a plurality of filling holes, and the plurality of filling holes correspond to the plurality of second contact regions one-to-one.
  • an isolation layer 300 is formed on the bit line 200 and the substrate 100 .
  • an isolation layer 300 is formed on the side surface and the upper surface of the bit line 200 and the upper surface of the substrate 100.
  • the isolation layer 300 may be formed by a deposition process.
  • the isolation layer 300 is formed by chemical vapor deposition (Chemical Vapor Deposition). , referred to as CVD), physical vapor deposition (Physical Vapor Deposition, referred to as PVD) or atomic layer deposition (Atomic Layer Deposition, referred to as ALD) and other processes.
  • CVD chemical vapor deposition
  • PVD Physical vapor deposition
  • ALD atomic layer deposition
  • a plurality of filling holes 310 are formed in the isolation layer 300 , and the plurality of filling holes 310 are in one-to-one correspondence with the plurality of second contact regions.
  • the plurality of filling holes 310 may be arranged in a square array in the isolation layer 300, and the orthographic projection of the filling holes 310 on the substrate 100 at least covers part of the second contact area. Referring to FIG. 4 , both the hole wall and the hole bottom of the filling hole 310 are the isolation layer 300 .
  • a plurality of oxide layers 320 may also be provided in the isolation layer 300 , and the extension direction of the oxide layers 320 is the same as that of the bit line 200 .
  • An oxide layer 320 is provided on both sides of each bit line 200 . It can be understood that, along the direction from the bit line 200 to the filling hole 310, that is, the X direction shown in FIG. -Nitride) structure.
  • Step S104 etching the isolation layer and the substrate along the filling hole, so that the filling hole extends into the substrate, and the filling hole exposes the second contact region.
  • the bottom of the filled hole 310 is etched along the filled hole 310 so that the bottom of the filled hole 310 is located in the substrate 100 and the filled hole 310 exposes the second contact region.
  • the hole bottom and the hole wall of the filled hole 310 formed after etching are smoothly transitioned, that is, the bottom of the filled hole 310 is in an arc shape, so as to facilitate the subsequent steps.
  • the bottom of the filling hole 310 is located in the substrate 100 .
  • directional etching may be used, for example, by controlling the plasma directionality, to etch the isolation layer 300 and the substrate 100 in a desired direction to expose the second contact region. It can be understood that the etching is performed along the vertical direction shown in FIG. 5 to reduce the etching in the horizontal direction, that is, reduce the lateral etching.
  • the process of etching the isolation layer 300 and the substrate 100 may be performed in an etching machine, and the first etching gas may include carbon tetrafluoride (CF 4 ), trifluoromethane (CHF 3 ), chlorine gas (Cl 2 ) ), oxygen (O 2 ) and argon (Ar), the first radio frequency power is 500W-1500W, the first radio frequency voltage is 50V-500V, and the first pressure is 4mT-30mT.
  • the first etching gas may include carbon tetrafluoride (CF 4 ), trifluoromethane (CHF 3 ), chlorine gas (Cl 2 ) ), oxygen (O 2 ) and argon (Ar)
  • the first radio frequency power is 500W-1500W
  • the first radio frequency voltage is 50V-500V
  • the first pressure is 4mT-30mT.
  • Step S105 forming a first protective layer on the second contact region exposed in the filling hole.
  • a first protective layer 400 is formed on the exposed second contact region, and the material of the first protective layer 400 may be silicon oxide.
  • the first protective layer 400 isolates and protects the second contact area, so that during subsequent etching, the etching liquid or etching gas will not directly contact the second contact area, thereby reducing the etching of the second contact area, especially It is to etch the upper sidewall of the second contact area, so as to reduce or avoid lateral over-etching of the second contact area.
  • the process of forming the first protective layer 400 may be performed in an etching machine.
  • the first protective layer 400 is formed on the second contact region exposed in the filling hole 310 through an in-situ oxidation process.
  • the oxidizing gas includes oxygen, argon and nitrogen (N 2 ), the second radio frequency power is 300W-2000W, and the second pressure is 10mT-100mT.
  • Step S106 etching the first protective layer and the substrate located at the bottom of the filled hole until the bottom of the filled hole is located at a preset depth of the substrate.
  • the bottom of the filled hole 310 is etched along the filled hole 310 , so that the bottom of the filled hole 310 is located at a predetermined depth of the substrate 100 .
  • the exposed area of the second contact area can be increased, thereby increasing the contact area between the second contact area and the subsequently formed wires, reducing the contact resistance between the second contact area and the wires, and improving the storage speed and storage speed of the memory. storage efficiency.
  • the portion of the first protective layer 400 near the bottom of the hole is removed, and the portion of the first protective layer 400 away from the bottom of the hole remains, that is, close to the upper surface of the substrate 100
  • the first protective layer 400 is still left in the part of the second contact region, which reduces the lateral etching of the upper part of the second contact region and avoids over-etching of the second contact region.
  • the process of etching the first protective layer 400 and the substrate 100 at the bottom of the filling hole 310 may be performed in an etching machine.
  • the second etching gas includes carbon tetrafluoride, chlorine gas, and the like.
  • Step S107 removing the remaining first protective layer.
  • the first protective layer 400 is removed to expose the second contact region and increase the exposed area of the second contact region. It can be understood that, when the remaining first protective layer 400 is removed, the bottom of the filling hole 310 can be modified by using stronger lateral etching, so that the filling hole 310 in the substrate 100 can form a relatively smooth arc shape. In addition, the surface area of the second contact region exposed in the filling hole 310 can be further increased.
  • the process of removing the remaining first protective layer 400 may be performed in an etching machine.
  • the remaining first protective layer 400 is dry-etched, and the third etching gas includes sulfur hexafluoride (SF 6 ), argon gas, oxygen and carbon tetrafluoride, etc.
  • the isolation layer 300 and the substrate 100 are etched along the filling hole 310 , the first protective layer 400 is formed on the second contact area exposed in the filling hole 310 , and the first protective layer 400 located at the bottom of the filling hole 310 is etched.
  • the protective layer 400 and the substrate 100 and the steps of removing the remaining first protective layer 400 may be performed in the same etching machine. That is, steps S104 to S107 can be performed in the same etching machine, which reduces the waiting time performed in different equipment, avoids process time-out, and further improves the yield of the memory.
  • the method for fabricating the memory in the embodiment of the present application includes: providing a substrate 100 , a plurality of active regions 110 arranged at intervals are arranged in the substrate 100 , and the active region 110 includes a first contact region and a second contact region; on the substrate 100 A plurality of bit lines 200 arranged at intervals are formed, and each bit line 200 is connected to at least one first contact region; an isolation layer 300 is formed on the bit line 200, the isolation layer 300 covers the bit line 200 and the substrate 100, and the isolation layer 300 is further provided with A plurality of filling holes 310, the plurality of filling holes 310 correspond to the plurality of second contact regions one-to-one; the isolation layer 300 and the substrate 100 are etched along the filling holes 310, so that the filling holes 310 extend into the substrate 100, and the filling holes 310 are exposed second contact area; forming a first protective layer 400 on the second contact area exposed in the filling hole 310 ; etching the first protective layer 400 and the substrate 100 at the bottom of the filling
  • the first protective layer 400 By forming the first protective layer 400 on the second contact area exposed in the filling hole 310, in the process of subsequent etching of the first protective layer 400 and the substrate 100 at the bottom of the filling hole 310, the first protective layer 400 can reduce or prevent the second contact region away from the bottom of the filling hole 310 from being etched, thereby reducing the phenomenon of over-etching of the substrate 100, so as to improve the quality of the subsequently formed wires, thereby improving the yield of the memory.
  • the isolation layer 300 and the substrate 100 are etched along the filling hole 310 so that the filling hole 310 extends into the substrate 100 .
  • the memory The manufacturing method may further include: forming a second protective layer 500 on a surface of the isolation layer 300 facing away from the substrate 100 .
  • a second protective layer 500 is formed on the upper surface of the isolation layer 300.
  • the second protective layer 500 protects the isolation layer 300. Reduce or avoid the isolation layer 300 from being etched, so that the height of the isolation layer 300 in the vertical direction (Y direction shown in FIG. 10 ) is constant or less reduced, thereby increasing the stability of the etching window and avoiding the isolation caused by etching
  • the third conductive layer 230 of the bit line 200 is exposed due to the layer 300 and the third protective layer 240 .
  • disposing the second protective layer 500 can also make the upper surface of the isolation layer 300 relatively flat.
  • the process of forming the second protective layer 500 may be performed in an etching machine.
  • the second protective layer 500 may be a carbon (C) layer, and the second protective layer 500 is formed on the surface of the isolation layer 300 away from the substrate 100 through an in-situ deposition process.
  • the reactive gas includes carbon tetrafluoride, helium (He), etc.
  • the third radio frequency power is 200W-1800W
  • the second radio frequency voltage is 0V
  • the third pressure is 5mT-100mT.
  • first protective layer 400 and the substrate 100 and the remaining first protective layer 400 are removed in the same etching machine, which further reduces the waiting time in different equipments and avoids process overtime.
  • the second protective layer 500 is located on the upper surface of the isolation layer 300 , and the hole walls and bottoms of the filled holes 310 are less or even without the second protective layer 500 .
  • the difficulty in the subsequent etching of the bottom of the filled hole 310 is reduced.
  • the manufacturing method of the memory may further include: removing the second protective layer 500 to expose the isolation Layer 300. As shown in FIG. 11 , before forming the first protective layer 400 , the second protective layer 500 is removed to expose the surface of the isolation layer 300 away from the substrate 100 .
  • the embodiments of the present application also provide a memory.
  • the memory is formed by the above-mentioned manufacturing method of the memory, and thus has less or no over-etching of the substrate 100 and less voids in the wires, which improves the memory performance. Yield. For specific effects, please refer to the above, which will not be repeated here.
  • references to the terms “one embodiment,” “some embodiments,” “illustrative embodiments,” “examples,” “specific examples,” or “some examples” and the like are meant to incorporate embodiments A particular feature, structure, material, or characteristic described or exemplified is included in at least one embodiment or example of the present application.
  • schematic representations of the above terms do not necessarily refer to the same embodiment or example.
  • the particular features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

本申请提供一种存储器的制作方法及存储器，涉及存储设备技术领域，用于解决存储器良率较低的技术问题，该制作方法包括：提供基底，基底内设多个有源区，有源区包括第一接触区和第二接触区；在基底上形成多条位线，每条位线连接至少一个第一接触区；在位线上形成覆盖位线和基底的隔离层，隔离层还设有于多个第二接触区一一对应的多个填充孔；沿填充孔刻蚀隔离层和基底，填充孔暴露第二接触区；在第二接触区上形成第一保护层；刻蚀位于填充孔的孔底的第一保护层和基底，直至填充孔的孔底位于基底的预设深度。

Description

存储器的制作方法及存储器
本申请要求于2021年04月15日提交中国专利局、申请号为202110408047.1、申请名称为“存储器的制作方法及存储器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及存储设备技术领域，尤其涉及一种存储器的制作方法及存储器。
背景技术
动态随机存储器(Dynamic Random Access Memory，简称DRAM)是一种高速地、随机地写入和读取数据的半导体存储器，被广泛地应用到数据存储设备或装置中。动态随机存储器一般包括晶体管和电容器。电容器存储数据信息，晶体管控制电容器中的数据信息的读写。
相关技术中，动态随机存储器包括基底，基底中包括有源区，有源区包括第一接触区和第二接触区。基底上设置有间隔排布的位线以及包覆于位线外的隔离层。位线与第一接触区电连接，隔离层形成有接触孔，且接触孔延伸至基底，接触孔中填充有导线，导线用于电连接电容器与第二接触区。为了增大导线与第二接触区的接触面积，通常沿接触孔刻蚀基底，以在基底中形成接触凹槽，接触孔和接触凹槽形成填充孔，填充孔中填充导线。
然而，在形成接触凹槽的过程中，基底易出现过刻蚀现象，导致后续形成的导线内具有较大空隙、存储器的良率较低。
发明内容
第一方面，本申请实施例提供一种存储器的制作方法，其包括：提供基底，所述基底内设有多个间隔设置的有源区，所述有源区包括第一接触区和第二接触区；在所述基底上形成多条间隔设置的位线，每条所述位线 连接至少一个所述第一接触区；在所述位线上形成隔离层，所述隔离层覆盖位线和所述基底，所述隔离层还设有多个填充孔，多个所述填充孔与多个所述第二接触区一一对应；沿所述填充孔刻蚀所述隔离层和所述基底，以使所述填充孔延伸至所述基底中，所述填充孔暴露所述第二接触区；在暴露于所述填充孔内的所述第二接触区上形成第一保护层；刻蚀位于所述填充孔的孔底的所述第一保护层和所述基底，直至所述填充孔的孔底位于所述基底的预设深度；去除剩余的所述第一保护层。
第二方面，本申请实施例还提供一种存储器，该存储器通过上述存储器的制作方法形成。
附图说明
图1为相关技术中的基底过刻蚀的示意图；
图2为本申请实施例中的存储器的制作方法的流程图；
图3为本申请实施例中的形成位线后的结构示意图；
图4为本申请实施例中的形成隔离层后的结构示意图；
图5为本申请实施例中的沿填充孔刻蚀隔离层和基底后的结构示意图；
图6为本申请实施例中的形成第一保护层后的结构示意图；
图7为本申请实施例中的刻蚀位于填充孔的孔底的第一保护层和基底后的结构示意图；
图8为本申请实施例中的去除剩余的第一保护层后的结构示意图；
图9为本申请实施例中的形成第二保护层后的结构示意图；
图10为本申请实施例中的形成第二保护层后，刻蚀位于填充孔的孔底的第一保护层和基底后的结构示意图；
图11为本申请实施例中的去除第二保护层后的结构示意图。
具体实施方式
相关技术中，制作存储器时，通常先提供具有刻蚀孔的隔离层，刻蚀孔的孔底可以位于隔离层中，再沿刻蚀孔刻蚀隔离层和基底，形成第一预设接触孔，预设接触孔暴露第二接触区；去除刻蚀副产物(byproduct)；填充保护气体，例如氮气；沿第一预设接触孔刻蚀基底，形成第二预设接 触孔。上述由刻蚀孔形成第二预设接触孔的工艺过程通常需要在480min内完成。
形成第二预设接触孔后，进行关键尺寸(Critical Dimension，简称CD)检测，之后进行膜厚测量等。经初步检测合格后，再沿第一预设接触孔各向同性(isotropic)刻蚀基底，以形成接触孔，使得接触孔暴露出较多的第二接触区。上述由第二预设接触孔形成接触孔的工艺过程通常需要在120min内完成。
然而，参照图1，形成的存储器中，隔离层300上部刻蚀较多，且基底100易出现过刻蚀现象，如图1中虚线所示区域，导致后续形成的导线内具有较大空隙、存储器的良率较低。此外，上述制作存储器的过程通常需要在不同的设备中进行，易出现超时的问题，导致存储器的良率较低。
为了提高存储器的良率，本申请实施例提供一种存储器的制作方法，在沿隔离层的填充孔刻蚀隔离层和基底，以使填充孔延伸至基底中后，在暴露于填充孔内的第二接触区上形成第一保护层，后续刻蚀位于填充孔的孔底的第一保护层和基底的过程中，第一保护层可以减少或者避免远离填充孔的孔底的第二接触区被刻蚀，从而减少基底出现过刻蚀现象，以提高后续形成的导线的质量，进而提高存储器的良率。
为了使本申请实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本申请保护的范围。
参照图2，本申请实施例提供一种存储器的制作方法，该制作方法包括以下步骤：
步骤S101、提供基底，基底内设有多个间隔设置的有源区，有源区包括第一接触区和第二接触区。
参照图3，基底100内设有有源区110，有源区110的数量可以设置为多个，多个有源区110间隔设置，例如多个有源区110呈阵列排布。多个有源区110之间设置浅槽隔离(Shallow Trench Isolation，简称STI)结构120，浅槽隔离结构120中可以填充有氧化硅(例如SiO 2)。通过浅槽隔 离结构120将多个有源区110之间隔离。
有源区110可以包括第一接触区和第二接触区，第一接触区和第二接触区可以相邻接。第一接触区连接位线200，第二接触区连接电容器，以使位线200能够读取电容器中的数据信息，或者将数据信息写入到电容器中。
在一种可能的示例中，第一接触区位于有源区110的中心，第二接触区位于有源区110的两端，即第二接触区设置有两个，两个第二接触区分别位于第一接触区的两侧。其中，有源区110的材质可以包括硅(Si)。当然，有源区110的材质不是限定的，例如，有源区110的材质还可以为锗(Ge)，绝缘体上硅(Silicon on Insulator，简称SOI)等。
步骤S102、在基底上形成多条间隔设置的位线，每条位线连接至少一个第一接触区。
继续参照图3，基底100上形成多条位线200，多条位线200之间间隔设置，每条位线200连接至少一个第一接触区。如图3所示，多条位线200之间相平行，沿位线200的延伸方向，位线200连接位于该方向上的多个第一接触区。
在一种可能的示例中，基底100上形成位线接触窗130，位线200通过位线接触窗130连接第一接触区。如图3所示，基底100的上表面的部分区域向下凹陷，形成位线接触窗130。位线200的部分区域位于位线接触窗130上，以与第一接触区电连接，位线200的部分区域位于基底100的上表面上，位线200的该部分区域与基底100之间还可以设置绝缘层140，例如第一氮化硅层。
位线200可以包括依次堆叠设置的第一导电层210、第二导电层220、第三导电层230和第三保护层240。其中，第一导电层210设置在基底100上，即第三保护层240远离基底100。
示例性的，第一导电层210可以为多晶硅(polycrystalline silicon)层，第二导电层220可以为氮化钛(TiN)层，第三导电层230可以为钨(W)层，第三保护层240可以为第二氮化硅层。
步骤S103、在位线上形成隔离层，隔离层覆盖位线和基底，隔离层还设有多个填充孔，多个填充孔与多个第二接触区一一对应。
参照图4，位线200和基底100上形成隔离层300。如图4所示，位线 200的侧表面和上表面，以及基底100的上表面上形成隔离层300，隔离层300可以通过沉积工艺形成，例如，隔离层300通过化学气相沉积(Chemical Vapor Deposition，简称CVD)、物理气相沉积(Physical Vapor Deposition，简称PVD)或者原子层沉积(Atomic Layer Deposition，简称ALD)等工艺形成。
隔离层300中形成多个填充孔310，多个填充孔310与多个第二接触区一一对应。示例性的，多个填充孔310可以在隔离层300中呈方阵排布，填充孔310在基底100上的正投影至少覆盖部分第二接触区。参照图4，填充孔310的孔壁和孔底均为隔离层300。
如图4所示，隔离层300中还可以设置多个氧化物层320，氧化物层320的延伸方向与位线200的延伸方向相同。每条位线200的两侧均设有一个氧化物层320。可以理解的是，沿位线200至填充孔310的方向，即图4所示X方向，位线200外依次设有氮化物层-氧化物层-氮化物层，即形成NON(Nitride-Oxide-Nitride)结构。
步骤S104、沿填充孔刻蚀隔离层和基底，以使填充孔延伸至基底中，填充孔暴露第二接触区。
参照图5，沿填充孔310刻蚀填充孔310的孔底，以使填充孔310的孔底位于基底100中，填充孔310暴露第二接触区。刻蚀后形成的填充孔310的孔底和孔壁圆滑过渡，即填充孔310的底部呈弧状，以便于后续步骤的进行。如图5所示，填充孔310的底部位于基底100中。
刻蚀时，可以采用方向性刻蚀，例如，通过对等离子方向性的控制，以沿所需的方向刻蚀隔离层300和基底100，以暴露第二接触区。可以理解的是，沿着图5所示竖直方向进行刻蚀，以减少水平方向的刻蚀，即减少侧向刻蚀。
示例性的，刻蚀隔离层300和基底100的过程可以在刻蚀机内进行，第一刻蚀气体可以包括四氟化碳(CF 4)、三氟甲烷(CHF 3)、氯气(Cl 2)、氧气(O 2)和氩气(Ar)，第一射频功率为500W-1500W，第一射频电压为50V-500V，第一压力为4mT-30mT。
步骤S105、在暴露于填充孔内的第二接触区上形成第一保护层。
参照图6，在暴露的第二接触区上形成第一保护层400，第一保护层400的材质可以为氧化硅。第一保护层400对第二接触区进行隔离和保护， 以在后续刻蚀时，刻蚀液体或者刻蚀气体不会直接接触第二接触区，从而减少对第二接触区的刻蚀，尤其是对第二接触区的上部侧壁的刻蚀，减少或者避免第二接触区侧向过刻蚀。
形成第一保护层400的过程可以在刻蚀机内进行，示例性的，通过原位氧化工艺在暴露于填充孔310内的第二接触区上形成第一保护层400。氧化气体包括氧气、氩气和氮气(N 2)，第二射频功率为300W-2000W，第二压力为10mT-100mT。
步骤S106、刻蚀位于填充孔的孔底的第一保护层和基底，直至填充孔的孔底位于基底的预设深度。
参照图7，沿填充孔310刻蚀填充孔310的孔底，以使填充孔310的孔底位于基底100的预设深度处。通过该次刻蚀，可以增加第二接触区暴露的面积，从而增加第二接触区与后续形成的导线的接触面积，减少第二接触区与导线之间的接触电阻，提高存储器的存储速度和存储效率。
如图7所示，在对填充孔310进行刻蚀时，第一保护层400中靠近孔底的部分被去除，第一保护层400中远离孔底的部分保留，即靠近基底100的上表面的部分第二接触区仍留有第一保护层400，减少了对第二接触区的上部分的侧向刻蚀，避免第二接触区过刻蚀。
刻蚀位于填充孔310的孔底的第一保护层400和基底100的过程可以在刻蚀机内进行，示例性的，干法刻蚀位于填充孔310的孔底的第一保护层400和基底100，第二刻蚀气体包括四氟化碳和氯气等。
步骤S107、去除剩余的第一保护层。
参照图8，去除第一保护层400，以暴露第二接触区，增大第二接触区暴露的面积。可以理解的是，去除剩余的第一保护层400时，可以采用侧向刻蚀较强的蚀刻对填充孔310的底部进行修饰，以使位于基底100内的填充孔310形成较为光滑的弧状。此外，还可以进一步增加第二接触区暴露在填充孔310内的表面积。
去除剩余的第一保护层400的过程可以在刻蚀机内进行，示例性的，干法刻蚀剩余的第一保护层400，第三刻蚀气体包括六氟化硫(SF 6)、氩气、氧气和四氟化碳等。
需要说明的是，沿填充孔310刻蚀隔离层300和基底100、在暴露于填充孔310内的第二接触区上形成第一保护层400、刻蚀位于填充孔310 的孔底的第一保护层400和基底100和去除剩余的第一保护层400的步骤可以在同一刻蚀机内进行。即步骤S104至步骤S107可以在同一刻蚀机内进行，减少了在不同设备中进行的等待时间，避免制程超时，进一步提高存储器的良率。
本申请实施例中的存储器的制作方法包括：提供基底100，基底100内设有多个间隔设置的有源区110，有源区110包括第一接触区和第二接触区；在基底100上形成多条间隔设置的位线200，每条位线200连接至少一个第一接触区；在位线200上形成隔离层300，隔离层300覆盖位线200和基底100，隔离层300还设有多个填充孔310，多个填充孔310与多个第二接触区一一对应；沿填充孔310刻蚀隔离层300和基底100，以使填充孔310延伸至基底100中，填充孔310暴露第二接触区；在暴露于填充孔310内的第二接触区上形成第一保护层400；刻蚀位于填充孔310的孔底的第一保护层400和基底100，直至填充孔310的孔底位于基底100的预设深度；去除剩余的第一保护层400。通过在暴露于填充孔310内的第二接触区上形成第一保护层400，以使后续刻蚀位于填充孔310的孔底的第一保护层400和基底100的过程中，第一保护层400可以减少或者避免远离填充孔310的孔底的第二接触区被刻蚀，从而减少基底100出现过刻蚀现象，以提高后续形成的导线的质量，进而提高存储器的良率。
需要说明的是，参照图9和图10，沿填充孔310刻蚀隔离层300和基底100，以使填充孔310延伸至基底100中，填充孔310暴露第二接触区的步骤之前，存储器的制作方法还可以包括：在隔离层300背离基底100的表面上形成第二保护层500。
如图9和图10所示，在隔离层300的上表面形成第二保护层500，在沿填充孔310刻蚀隔离层300和基底100时，第二保护层500对隔离层300进行保护，减少或者避免隔离层300被刻蚀，使得隔离层300沿垂直方向(图10所示Y方向)的高度不变或者高度较少减小，从而增加刻蚀窗口的稳定性，避免因刻穿隔离层300和第三保护层240而导致位线200的第三导电层230裸露。此外，设置第二保护层500也可以使得隔离层300的上表面较为平整。
形成第二保护层500的过程可以在刻蚀机内进行。示例性的，第二保护层500可以为碳(C)层，通过原位沉积工艺在隔离层300背离基底100 的表面上形成第二保护层500。反应气体包括四氟化碳和氦气(He)等，第三射频功率为200W-1800W，第二射频电压为0V，第三压力为5mT-100mT。
形成第二保护层500与沿填充孔310刻蚀隔离层300和基底100、在暴露于填充孔310内的第二接触区上形成第一保护层400、刻蚀位于填充孔310的孔底的第一保护层400和基底100和去除剩余的第一保护层400在同一刻蚀机内进行，进一步减少在不同设备中进行的等待时间，避免制程超时。
如图9和图10所示，形成第二保护层500后，第二保护层500位于隔离层300的上表面，填充孔310的孔壁和孔底较少甚至没有第二保护层500，从而减少了后续刻蚀填充孔310的孔底时的难度。
需要说明的是，参照图11，在暴露于填充孔310内的第二接触区上形成第一保护层400的步骤之前，存储器的制作方法还可以包括：去除第二保护层500，以暴露隔离层300。如图11所示，形成第一保护层400之前，去除第二保护层500，以暴露隔离层300远离基底100的表面。
本申请实施例还提供了一种存储器，如图11和所示，该存储器通过上述存储器的制作方法形成，因而具有基底100过刻蚀较少甚至没有，导线内空隙较少，提高了存储器的良率。具体效果请参照上文，在此不再赘述。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进 行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (16)

  1. 一种存储器的制作方法，其中，包括：
    提供基底，所述基底内设有多个间隔设置的有源区，所述有源区包括第一接触区和第二接触区；
    在所述基底上形成多条间隔设置的位线，每条所述位线连接至少一个所述第一接触区；
    在所述位线上形成隔离层，所述隔离层覆盖位线和所述基底，所述隔离层还设有多个填充孔，多个所述填充孔与多个所述第二接触区一一对应；
    沿所述填充孔刻蚀所述隔离层和所述基底，以使所述填充孔延伸至所述基底中，所述填充孔暴露所述第二接触区；
    在暴露于所述填充孔内的所述第二接触区上形成第一保护层；
    刻蚀位于所述填充孔的孔底的所述第一保护层和所述基底，直至所述填充孔的孔底位于所述基底的预设深度；
    去除剩余的所述第一保护层。
  2. 根据权利要求1所述的存储器的制作方法，其中，沿所述填充孔刻蚀所述隔离层和所述基底、在暴露于所述填充孔内的所述第二接触区上形成第一保护层、刻蚀位于所述填充孔的孔底的所述第一保护层和所述基底和去除剩余的所述第一保护层的步骤在同一刻蚀机内进行。
  3. 根据权利要求1所述的存储器的制作方法，其中，沿所述填充孔刻蚀所述隔离层和所述基底时，第一刻蚀气体包括四氟化碳、三氟甲烷、氯气、氧气和氩气。
  4. 根据权利要求3所述的存储器的制作方法，其中，沿所述填充孔刻蚀所述隔离层和所述基底时，第一射频功率为500W-1500W，第一射频电压为50V-500V，第一压力为4mT-30mT。
  5. 根据权利要求1所述的存储器的制作方法，其中，通过原位氧化工艺在暴露于所述填充孔内的所述第二接触区上形成第一保护层。
  6. 根据权利要求5所述的存储器的制作方法，其中，氧化气体包括氧气、氩气和氮气。
  7. 根据权利要求5所述的存储器的制作方法，其中，所述原位氧化工艺中，第二射频功率为300W-2000W，第二压力为10mT-100mT。
  8. 根据权利要求1所述的存储器的制作方法，其中，刻蚀位于所述填充孔的孔底的所述第一保护层和所述基底时，第二刻蚀气体包括四氟化碳和氯气。
  9. 根据权利要求1所述的存储器的制作方法，其中，去除剩余的所述第一保护层时，第三刻蚀气体包括六氟化硫、氩气、氧气和四氟化碳。
  10. 根据权利要求1所述的存储器的制作方法，其中，沿所述填充孔刻蚀所述隔离层和所述基底，以使所述填充孔延伸至基底中，所述填充孔暴露所述第二接触区的步骤中，所述填充孔的孔底和孔壁圆弧过渡。
  11. 根据权利要求1所述的存储器的制作方法，其中，沿所述填充孔刻蚀所述隔离层和所述基底，以使所述填充孔延伸至所述基底中，所述填充孔暴露所述第二接触区的步骤之前，所述存储器的制作方法还包括：
    在所述隔离层背离所述基底的表面上形成第二保护层。
  12. 根据权利要求11所述的存储器的制作方法，其中，所述第二保护层为碳层，所述第二保护层通过原位沉积工艺形成。
  13. 根据权利要求12所述的存储器的制作方法，其中，所述原位沉积工艺中，反应气体包括四氟化碳和氦气。
  14. 根据权利要求12所述的存储器的制作方法，其中，所述原位沉积工艺中，第三射频功率为200W-1800W，第二射频电压为0V，第三压力为5mT-100mT。
  15. 根据权利要求11所述的存储器的制作方法，其中，在暴露于所述填充孔内的所述第二接触区上形成第一保护层的步骤之前，所述存储器的制作方法还包括：
    去除所述第二保护层，以暴露所述隔离层。
  16. 一种存储器，其中，所述存储器通过权利要求1所述的存储器的制作方法形成。
PCT/CN2021/107453 2021-04-15 2021-07-20 存储器的制作方法及存储器 WO2022217772A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/460,272 US20220336467A1 (en) 2021-04-15 2021-08-29 Method for fabricating memory and memory

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110408047.1 2021-04-15
CN202110408047.1A CN115223943A (zh) 2021-04-15 2021-04-15 存储器的制作方法及存储器

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/460,272 Continuation US20220336467A1 (en) 2021-04-15 2021-08-29 Method for fabricating memory and memory

Publications (1)

Publication Number Publication Date
WO2022217772A1 true WO2022217772A1 (zh) 2022-10-20

Family

ID=83604156

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/107453 WO2022217772A1 (zh) 2021-04-15 2021-07-20 存储器的制作方法及存储器

Country Status (2)

Country Link
CN (1) CN115223943A (zh)
WO (1) WO2022217772A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060003530A1 (en) * 2004-06-30 2006-01-05 Hynix Semiconductor Inc. Semiconductor memory device and method for fabricating the same
CN101335231A (zh) * 2007-06-28 2008-12-31 海力士半导体有限公司 半导体器件的制造方法
CN109860050A (zh) * 2017-11-30 2019-06-07 台湾积体电路制造股份有限公司 半导体制作方法
CN111463205A (zh) * 2020-04-08 2020-07-28 福建省晋华集成电路有限公司 存储器及其形成方法
CN111584488A (zh) * 2020-05-28 2020-08-25 福建省晋华集成电路有限公司 存储器及其形成方法
CN112563208A (zh) * 2019-09-26 2021-03-26 长鑫存储技术有限公司 半导体存储器及其制备方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060003530A1 (en) * 2004-06-30 2006-01-05 Hynix Semiconductor Inc. Semiconductor memory device and method for fabricating the same
CN101335231A (zh) * 2007-06-28 2008-12-31 海力士半导体有限公司 半导体器件的制造方法
CN109860050A (zh) * 2017-11-30 2019-06-07 台湾积体电路制造股份有限公司 半导体制作方法
CN112563208A (zh) * 2019-09-26 2021-03-26 长鑫存储技术有限公司 半导体存储器及其制备方法
CN111463205A (zh) * 2020-04-08 2020-07-28 福建省晋华集成电路有限公司 存储器及其形成方法
CN111584488A (zh) * 2020-05-28 2020-08-25 福建省晋华集成电路有限公司 存储器及其形成方法

Also Published As

Publication number Publication date
CN115223943A (zh) 2022-10-21

Similar Documents

Publication Publication Date Title
US10074654B1 (en) Dynamic random access memory
US8766343B2 (en) Integrated circuit capacitors having sidewall supports
US11139304B2 (en) Manufacturing method of semiconductor memory device
TW201727874A (zh) 具有增大記憶胞接觸區域的半導體記憶體裝置及其製作方法
US10840182B2 (en) Method of forming semiconductor memory device with bit line contact structure
US9209193B2 (en) Method of manufacturing device
WO2022028164A1 (zh) 半导体结构及其制作方法
WO2022193602A1 (zh) 一种半导体器件的制作方法
US11398392B2 (en) Integrated circuit device and method of manufacturing the same
US10825722B1 (en) Method of manufacturing a semiconductor structure
TW201535682A (zh) 半導體配置及其形成方法
US20230171947A1 (en) Semiconductor structure and manufacturing method thereof
WO2022217772A1 (zh) 存储器的制作方法及存储器
US20220359526A1 (en) Memory device, and semiconductor structure and forming method thereof
WO2022193480A1 (zh) 存储器的制作方法及存储器
US20220336467A1 (en) Method for fabricating memory and memory
WO2022205664A1 (zh) 存储器的制作方法及存储器
EP4092741B1 (en) Memory manufacturing method and memory
KR20110082901A (ko) 커패시터의 형성 방법 및 이를 이용한 디램 소자의 제조 방법
WO2023159679A1 (zh) 半导体结构及其制作方法
WO2022213514A1 (zh) 存储器的制作方法及存储器
WO2022205672A1 (zh) 存储器的制作方法
US20220045066A1 (en) Semiconductor structure and method of manufacturing same
WO2023015593A1 (zh) 半导体结构的形成方法及半导体结构
TWI799144B (zh) 半導體裝置及其製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21936644

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21936644

Country of ref document: EP

Kind code of ref document: A1