WO2022205672A1 - 存储器的制作方法 - Google Patents

存储器的制作方法 Download PDF

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Publication number
WO2022205672A1
WO2022205672A1 PCT/CN2021/106117 CN2021106117W WO2022205672A1 WO 2022205672 A1 WO2022205672 A1 WO 2022205672A1 CN 2021106117 W CN2021106117 W CN 2021106117W WO 2022205672 A1 WO2022205672 A1 WO 2022205672A1
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WO
WIPO (PCT)
Prior art keywords
trench
layer
isolation layer
conductive layer
isolation
Prior art date
Application number
PCT/CN2021/106117
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English (en)
French (fr)
Inventor
刘忠明
陈龙阳
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP21881352.5A priority Critical patent/EP4092725B1/en
Priority to US17/411,098 priority patent/US12089398B2/en
Publication of WO2022205672A1 publication Critical patent/WO2022205672A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

Definitions

  • the present application relates to the technical field of storage devices, and in particular, to a method for fabricating a memory.
  • DRAM Dynamic Random Access Memory
  • a dynamic random access memory generally includes a substrate, the substrate is provided with a plurality of active areas, a plurality of bit lines arranged at intervals are arranged on the substrate, and the active area of each row is in contact with a bit line.
  • the substrate and the bit line are also provided with an isolation layer, the isolation layer has a plurality of through holes, the plurality of through holes correspond to the active regions one-to-one, and one active region is exposed in each through hole, and the bit line is not exposed in the through hole middle.
  • the substrate is usually etched along the through hole to form a groove, and the groove and the through hole are filled with wires, and the wires electrically connect the capacitor and the active region.
  • An embodiment of the present application provides a method for fabricating a memory, including providing a substrate, where the substrate includes a plurality of spaced active regions, the active regions include a first contact region and a second contact region; and forming a plurality of active regions on the substrate Bit lines arranged at intervals, each bit line is connected to at least one of the first contact regions; a first isolation layer is formed on the bit line, and a first isolation layer is formed between two adjacent first isolation layers.
  • a first trench extending in the direction; etching the bottom of the first trench along the first trench to form a second trench, the bottom of the second trench is located in the substrate, and The second contact region is exposed in the second trench; a first conductive layer is formed in the first trench and the second trench; a part of the first conductive layer is removed to form a plurality of a first through hole, a plurality of the first through holes separate the first conductive layer into a plurality of wires, each of the wires is connected to one of the second contact areas; a first through hole is formed in the first through hole Two isolation layers.
  • the manufacturing method of the memory includes: firstly providing a substrate, the substrate includes a plurality of active regions arranged at intervals, and the active regions include a first contact region and a second contact region; forming a plurality of spaced apart on the substrate bit lines, each bit line is connected to at least one first contact region; a first isolation layer is formed on the bit line, and a first trench extending along the first direction is formed between two adjacent first isolation layers; A trench etches the bottom of the first trench to form a second trench, the bottom of the second trench is located in the substrate, and the second contact area is exposed in the second trench; the first trench and A first conductive layer is formed in the second trench; part of the first conductive layer is removed to form a plurality of first through holes, the plurality of first through holes separate the first conductive layer into a plurality of wires, each wire is connected to a first through hole Two contact areas; a second isolation layer is formed in the first through hole.
  • the aspect ratio of the second trench is reduced, so that the second trench is The loading effect is reduced, and at the same time, the alignment between the second trench and the first trench is better, and the yield of the memory is improved;
  • the filling difficulty is small, so as to improve the yield of the memory; by removing part of the first conductive layer, a plurality of first through holes are formed in the first conductive layer, the remaining first conductive layer is formed into wires, and the first through holes are formed in the first conductive layer.
  • the second isolation layer is formed in the hole.
  • the area enclosed by the first isolation layer and the second isolation layer needs to be etched to fill the wires.
  • the second isolation layer is formed, no further steps are required.
  • the etching reduces the risk of damaging the first isolation layer by etching, thereby reducing the possibility of etching through the first isolation layer, and further improving the yield of the memory.
  • FIG. 1 is a flowchart of a method for manufacturing a memory in an embodiment of the present application
  • FIG. 2 is a cross-sectional view after forming a bit line in an embodiment of the present application
  • FIG. 3 is a perspective view after forming a first isolation layer in an embodiment of the present application.
  • FIG. 4 is a top view after forming a first isolation layer in an embodiment of the present application.
  • FIG. 5 is a cross-sectional view after forming a first isolation layer in an embodiment of the present application.
  • FIG. 6 is a cross-sectional view after forming a first nitride layer in an embodiment of the present application
  • FIG. 7 is a cross-sectional view after forming a second nitride layer in an embodiment of the present application.
  • FIG. 8 is a perspective view after forming a second trench in an embodiment of the present application.
  • FIG. 9 is a top view after forming the second trench in an embodiment of the present application.
  • FIG. 10 is a cross-sectional view after forming a second trench in an embodiment of the application.
  • FIG. 11 is a perspective view after forming a first conductive layer in an embodiment of the present application.
  • FIG. 12 is a top view after forming the first conductive layer in an embodiment of the application.
  • FIG. 13 is a cross-sectional view after forming a first conductive layer in an embodiment of the application.
  • FIG. 14 is a perspective view after the third trench is formed in the embodiment of the application.
  • 15 is a cross-sectional view after forming a third trench in an embodiment of the application.
  • 16 is a perspective view after forming an intermediate layer in an embodiment of the application.
  • 17 is a cross-sectional view after forming an intermediate layer in an embodiment of the application.
  • FIG. 18 is a cross-sectional view of the intermediate layer before planarization processing in an embodiment of the present application.
  • FIG. 21 is a top view after forming a fourth trench in an embodiment of the application.
  • FIG. 22 is a perspective view after forming the second isolation layer in the embodiment of the application.
  • 25 is a top view after removing the intermediate layer in an embodiment of the application.
  • FIG. 26 is a cross-sectional view of an embodiment of the present application after removing the intermediate layer.
  • a plurality of bit lines and a first isolation layer covering each bit line are usually first formed on a substrate; wherein, the substrate includes a plurality of spaced active regions, and the active regions include a first contact region and a first isolation layer.
  • each bit line is connected to at least one first contact region, and the first isolation layer between two adjacent bit lines forms a first trench; an intermediate layer is deposited in the first trench, and the intermediate layer is filled a first trench; the intermediate layer is etched to form a first through hole, the remaining intermediate layer forms a plurality of columnar structures arranged at intervals, and each columnar structure corresponds to a second contact area; a second isolation is deposited in the first through hole removing the remaining intermediate layer to form a second through hole; etching the substrate along the second through hole to form a groove, and the groove exposes the second contact region; and filling the groove and the second through hole with wires.
  • the substrate when the substrate is etched along the second through hole, the first isolation layer outside the bit line is easily etched through, which leads to conduction between the wire and the bit line, thereby causing the memory to fail and the yield of the memory to be low.
  • the intermediate layer is etched and removed twice, the removal process is complicated, and the residual of the intermediate layer will also lead to a low yield of the memory.
  • an embodiment of the present application provides a method for manufacturing a memory.
  • the groove bottom is formed by first etching the bottom of the first trench along the first trench formed by the first isolation layer.
  • a second trench located in the substrate, the second trench exposes the active area of the substrate, and then a first conductive layer is formed in the first trench and the second trench to reduce the difficulty of filling the first conductive layer;
  • a first through hole is formed in the first conductive layer, the remaining first conductive layer forms a wire, and a second isolation layer is filled in the first through hole.
  • an embodiment of the present application provides a method for fabricating a memory, and the fabrication method specifically includes the following steps:
  • Step S101 providing a substrate, the substrate includes a plurality of spaced active regions, and the active regions include a first contact region and a second contact region.
  • an active region 110 is provided in the substrate 100 . As shown in FIG. 2 , the active region 110 is not exposed to the surface of the substrate 100 .
  • the number of active regions 110 may be multiple, and the multiple active regions 110 are arranged at intervals.
  • a shallow trench isolation (STI for short) structure 120 is provided between the multiple active regions 110, and silicon oxide (SiO 2 ) is provided in the shallow trench isolation structure 120, so that the multiple active regions 110 isolation between.
  • STI shallow trench isolation
  • a plurality of active regions 110 may be arranged in an array.
  • Each active area 110 may include a first contact area 111 and a second contact area 112 adjoining the first contact area 111 and the second contact area 112 .
  • the first contact area 111 is connected to the bit line 200, and the second contact area 112 is connected to a capacitor, eg, the second contact area 112 is connected to the capacitor through a wire and a capacitive contact pad in turn.
  • the first contact region 111 is located in the center of the active region 110
  • the second contact region 112 is located on both sides of the active region 110 , that is, the second contact region 112 is located in the first
  • the material of the active region 110 may include silicon (Si).
  • Step S102 forming a plurality of spaced bit lines on the substrate, and each bit line is connected to at least one first contact region.
  • bit lines 200 are formed on the substrate 100 at intervals, and bit line contact windows may be formed in the substrate 100 , and the first contact regions 111 of the active regions 110 are exposed in the bit line contact windows.
  • the bit line 200 is connected to the at least one first contact region 111 through the bit line contact window.
  • each bit line 200 is connected to the first contact regions 111 of the plurality of active regions 110 in the same row, that is, the first contact regions 111 of the plurality of active regions 110 in the same row can be connected to the same bit line 200, and each Only one bit line 200 is connected to one first contact region 111 .
  • bit lines 200 are arranged vertically, the plurality of bit lines 200 are parallel to each other, the active regions 110 are arranged obliquely, and the plurality of active regions 110 are parallel to each other.
  • the same bit line 200 may pass through a plurality of active regions 110 .
  • the bit line 200 may include a second conductive layer 210 , a third conductive layer 220 and a fourth conductive layer 230 which are stacked in sequence.
  • the fourth conductive layer 230 is located on the substrate 100 and is connected to the substrate 100 .
  • the active region 110 is electrically connected.
  • the material of the second conductive layer 210 may include polycrystalline silicon
  • the material of the third conductive layer 220 may include titanium nitride (TiN)
  • the material of the fourth conductive layer 230 may include tungsten (W).
  • Step S103 forming a first isolation layer on the bit line, and forming a first trench extending along the first direction between two adjacent first isolation layers.
  • a first isolation layer 300 is formed on the bit line 200 , and the first isolation layer 300 covers the bit line 200 .
  • a first isolation layer 300 is formed on the upper surface and side surface of each bit line 200, and the material of the first isolation layer 300 may be an insulating material, such as silicon nitride (Si 3 N 4 ), so as to align the Line 200 is protected and electrically isolated.
  • a first trench 310 is formed between two adjacent first isolation layers 300 , that is, two sidewalls of the first trench 310 are the first isolation layer 300 . As shown in FIG. 3 , the first trench 310 extends along the first direction. It can be understood that the extending direction of the first trench 310 is the same as the extending direction of the bit line 200 .
  • a plurality of first sacrificial layers 320 may also be provided in the first isolation layer 300 , as shown in FIG.
  • a first sacrificial layer 320 is disposed on both sides of the bit line 200 .
  • the first sacrificial layer 320 extends along the first direction, that is, the extending direction of the first sacrificial layer 320 is the same as the extending direction of the bit line 200 .
  • the material of the first sacrificial layer 320 may include oxide, eg, silicon oxide (SiO 2 ). It can be understood that, along the direction from the bit line 200 to the first trench 310 , Nitride-Oxide-Nitride (English full name Nitride-Oxide-Nitride, abbreviated as NON) is sequentially formed outside the bit line 200 .
  • Nitride-Oxide-Nitride English full name Nitride-Oxide-Nitride, abbreviated as NON
  • the first isolation layer 300 may be formed by the following steps:
  • a first nitride layer 330 is formed on the sidewalls and the top surface of the bit line 200 .
  • a second predetermined conductive layer, a third predetermined conductive layer, a fourth predetermined conductive layer and a first predetermined nitride layer are sequentially formed on the substrate 100 .
  • the third preset conductive layer, the fourth preset conductive layer and the first preset nitride layer are etched to form the second conductive layer 210 , the third conductive layer 220 and the fourth conductive layer 230 as shown in FIG. 6
  • the first nitride layer 330 , the second conductive layer 210 , the third conductive layer 220 , and the fourth conductive layer 230 constitute the bit line 200 .
  • the first sacrificial layer 320 and the second nitride layer 340 are formed. As shown in FIG. 7 , the first sacrificial layer 320 is formed on both sides of the bit line 200 and the first nitride layer 330 , the second nitride layer 340 covers the first sacrificial layer 320 , the first nitride layer 330 and the bit line 200 .
  • Step S104 etching the bottom of the first trench along the first trench to form a second trench, the bottom of the second trench is located in the substrate, and the second contact region is exposed in the second trench.
  • the bottom of the first trench 310 is etched along the first trench 310 to form the second trench 130 , and the bottom of the second trench 130 is located in the substrate 100 as shown in FIG. 8 . .
  • the depth-to-width ratio of the second trench 130 is small, the load effect is reduced, the formation of the second trench 130 is facilitated, and the alignment problem of the overlay mark between the via hole and the active region 110 in the related art is avoided.
  • the second contact region 112 is exposed in the second trench 130 .
  • the solid line of the active region 110 is partially broken, and the solid line is shown as the second contact region 112 exposed in the second trench 130 .
  • the contact area 112 is shown by the dotted line as the first contact area 111 shielded by the first isolation layer 300 , or the first contact area 111 and part of the second contact area 112 shielded by the first isolation layer 300 .
  • the first trench 310 exposes the substrate 100 , when the bottom of the first trench 310 is etched along the first trench 310 , the substrate 100 is etched, and a second trench is formed in the substrate 100 130 , the second contact region 112 of the active region 110 is exposed by the second trench 130 .
  • the first isolation layer 300 covers the bit line 200 and the substrate 100 , that is, the first isolation layer 300 is exposed in the first trench 310 , and the first trench 310 is etched along the first trench 310 When the trench bottom is formed, the first isolation layer 300 and the substrate 100 are etched to form the second trench 130. As shown in FIG. 10, the trench bottom of the second trench 130 is located in the substrate 100, and the second trench 130 is exposed. The second contact region 112 of the active region 110 is removed.
  • the first sacrificial layer 320 is further disposed in the first isolation layer 300 , and part of the first isolation layer 300 is also removed when the first isolation layer 300 and the substrate 100 are etched along the first trench 310 . , so that the first sacrificial layer 320 is exposed on the surface of the first isolation layer 300 away from the substrate 100 , so as to facilitate subsequent removal of the first sacrificial layer 320 to form a first air gap. As shown in FIG. 10 , a partial region above the first isolation layer 300 is removed, so that the first sacrificial layer 320 is exposed on the upper surface of the first isolation layer 300 .
  • Step S105 forming a first conductive layer 400 in the first trench 310 and the second trench 130 .
  • a first conductive layer 400 eg, a polysilicon layer, is deposited in the first trench 310 and the second trench 130 .
  • the first conductive layer 400 covers a part of the second contact region 112 of the active region 110 , so that the subsequent formation of wires is electrically connected to the active region 110 .
  • the filling space of the first trench 310 and the second trench 130 is larger, the filling difficulty is lower, and the filling quality is better, so as to reduce the occurrence of voids in the first conductive layer 400 due to uneven filling. ) and/or seams to improve the formation quality of the first conductive layer 400 .
  • the first conductive layer 400 can be formed on the first conductive layer by a chemical vapor deposition (Chemical Vapor Deposition, CVD for short) process, a physical vapor deposition (Physical Vapor Deposition, PVD for short) process, or an atomic layer deposition (Atomic Layer Deposition, ALD for short) process, etc. in the trench 310 and the second trench 130 .
  • CVD chemical Vapor Deposition
  • PVD Physical Vapor Deposition
  • ALD atomic layer deposition
  • Step S106 removing part of the first conductive layer to form a plurality of first through holes, the plurality of first through holes separate the first conductive layer into a plurality of wires, each wire is connected to a second contact area.
  • the first conductive layer 400 is etched to remove part of the first conductive layer 400, and the remaining first conductive layer 400 and the first isolation layer 300 are surrounded by a plurality of first through holes, and the plurality of first through holes can be etched at one time eroded formation.
  • a plurality of first through holes separate the first conductive layer 400 into a plurality of wires, that is, the remaining first conductive layer 400 forms a plurality of wires arranged at intervals, and each wire is connected to a second contact area 112 to connect with the active area 110 Electrical connection.
  • one active area 110 may be connected to two wires, and one active area 110 may be connected to only one wire.
  • Step S107 forming a second isolation layer in the first through hole.
  • the second isolation layer may be formed by a deposition process, and the material of the second isolation layer may be an insulating material, such as silicon nitride, so as to electrically isolate the wires together with the first isolation layer 300 . That is, the wires are separated by the first isolation layer 300 and the second isolation layer to prevent conduction between two adjacent wires, thereby ensuring the normal operation of the memory.
  • the second isolation layer After the second isolation layer is formed, there is no need to etch the surrounding area between the first isolation layer 300 and the second isolation layer, which reduces the risk of damage to the first isolation layer 300 by etching, thereby reducing the risk of damage to the first isolation layer 300.
  • the possibility of cutting through the isolation layer 300 prevents the conducting wire and the bit line 200 from conducting, thereby improving the yield of the memory.
  • the manufacturing method of the memory includes: providing a substrate 100, the substrate 100 includes a plurality of active regions 110 arranged at intervals, and the active region 110 includes a first contact region 111 and a second contact region 112; on the substrate 100 A plurality of bit lines 200 arranged at intervals are formed, and each bit line 200 is connected to at least one first contact region 111; a first isolation layer 300 is formed on the bit line 200, and two adjacent first isolation layers 300 are formed along the first The first trench 310 extends in the direction; the bottom of the first trench 310 is etched along the first trench 310 to form the second trench 130, the bottom of the second trench 130 is located in the substrate 100, and the second trench A second contact region 112 is exposed in the trench 130; a first conductive layer 400 is formed in the first trench 310 and the second trench 130; a plurality of first through holes 520 are formed in the first conductive layer 400, a plurality of The first through holes 520 separate the first conductive layer 400 into a plurality of
  • the aspect ratio of the second trench 130 is reduced , so that the load effect of the second trench 130 is reduced, and at the same time, the alignment between the second trench 130 and the first trench 310 is better, and the yield of the memory is improved;
  • the first conductive layer 400 is formed in 130, which is less difficult to fill; by removing part of the first conductive layer 400, a plurality of first through holes 520 are formed in the first conductive layer 400, and the remaining first conductive layer 400 forms wires 410 , and the second isolation layer 600 is formed in the first through hole 520.
  • the area surrounded by the first isolation layer 300 and the second isolation layer 600 needs to be etched
  • the second isolation layer 600 there is no need to perform etching, which reduces the risk of damage to the first isolation layer 300 by etching, thereby reducing the possibility of the first isolation layer 300 being etched through.
  • the yield of the memory is further improved.
  • the manufacturing method of the memory further includes:
  • Part of the first conductive layer is removed to form a third trench extending along the first direction.
  • the first conductive layer 400 located on the upper portion of the first trench 310 is removed to form the third trench 420 , that is, the third trench 420 is a part of the first trench 310 .
  • the sidewall of the third trench 420 is the first isolation layer 300
  • the bottom of the third trench 420 is the first conductive layer 400
  • the bottom of the third trench 420 may be located at the bottom of the bit line 200 . above.
  • an intermediate layer 500 is formed in the third trench 420 and on the first isolation layer 300 .
  • the intermediate layer 500 fills the third trench 420 and covers the first conductive layer 400 .
  • the upper portion of the first trench 310 is filled with the intermediate layer 500
  • the lower portion of the first trench 310 is filled with the first conductive layer 400 .
  • the intermediate layer 500 is formed in the third trench 420.
  • the height of the first conductive layer 400 is reduced.
  • the etching depth of the first conductive layer 400 is reduced, thereby reducing by-products during etching, so that the contour of the first conductive layer 400 after etching is better.
  • the selection ratio of the first conductive layer 400 to the first isolation layer 300 is not easy to improve.
  • the intermediate layer 500 the selection ratio of the intermediate layer 500 to the first isolation layer 300 is higher.
  • the intermediate layer 500 is subsequently etched, the The first isolation layer 300 is less etched.
  • disposing the intermediate layer 500 can also prevent the diffusion of the first conductive layer 400 .
  • the intermediate layer 500 may be a spin-on dielectric (Spin on Dielectrics, SOD for short), and after spin-coating the liquid insulating medium, a high temperature treatment is performed to cure the liquid insulating medium, The intermediate layer 500 is formed.
  • the intermediate layer 500 may be an oxide, such as silicon oxide.
  • the intermediate layer 500 covers the first isolation layer 300 and the first conductive layer 400, and the side of the intermediate layer 500 away from the first conductive layer 400 is planarized. As shown in FIG. The upper surface is flattened.
  • the upper surface of the intermediate layer 500 exposes the first isolation layer 300 and the first conductive layer 400 .
  • the intermediate layer 500 may be planarized by chemical mechanical polishing (CMP for short).
  • CMP chemical mechanical polishing
  • the method of the planarization treatment is not limited, for example, the planarization treatment can also be performed through a multi-layer photoresist process.
  • removing part of the first conductive layer to form a plurality of first vias may include the following steps:
  • Step S1061 removing part of the intermediate layer and part of the first isolation layer to form a fourth trench extending along the second direction, and the first conductive layer and the first isolation layer are exposed in the fourth trench.
  • the intermediate layer 500 and the first isolation layer 300 are etched to form a fourth trench 510, the fourth trench 510 extends along a second direction, and the second direction may be perpendicular to the first direction, as shown in FIG. 21 As shown, the fourth trench 510 is arranged horizontally. It can be understood that part of the sidewall of the fourth trench 510 is the first isolation layer 300 , part of the sidewall of the fourth trench 510 is the intermediate layer 500 , and the intermediate layer 500 and the first isolation layer 300 alternate.
  • part of the first conductive layer 400 is also removed, so that the groove bottom of the fourth trench 510 is located at the first in the conductive layer 400 .
  • the third trench 420 is easy to form, and on the other hand, the height of the first conductive layer 400 is further reduced, thereby reducing the depth of the subsequent etching of the first conductive layer 400 .
  • the bottom of the fourth trench 510 is located above the bit line 200 , that is, the bit line 200 is not exposed in the fourth trench 510 to prevent damage to the bit line 200 .
  • Step S1062 removing the first conductive layer at the bottom of the fourth trench to form a plurality of first through holes.
  • the bottom of the fourth trench 510 is the first isolation layer 300 and the first conductive layer 400 alternately, that is, the fourth trench 510 exposes the first isolation layer layer 300 and first conductive layer 400 .
  • the first conductive layer 400 exposed in the fourth trench 510 is removed by etching to form a plurality of first through holes 520 , the first conductive layer 400 under the intermediate layer 500 is retained, and the remaining first conductive layer 400 is Layer 400 forms a plurality of spaced-apart conductors 410 , each conductor 410 being in contact with one of the second contact areas 112 .
  • the step of forming the second isolation layer 600 in the first through hole 520 may include: depositing the second isolation layer 600 in the first through hole 520 and the fourth trench 510, The second isolation layer 600 is filled in the first through hole 520 and the fourth trench 510 . As shown in FIGS. 22 and 23 , the second isolation layer 600 and the first isolation layer 300 electrically isolate the wires 410 .
  • the manufacturing method of the memory further includes: removing the intermediate layer 500 to expose the wires 410 .
  • the intermediate layer 500 is removed by wet etching until the wires 410 are exposed.
  • the intermediate layer is removed to form a second through hole 610 in which the wire 410 is exposed.
  • the first sacrificial layer 320 is also removed while the intermediate layer 500 is removed to form the first air gap.
  • the first sacrificial layer 320 is removed by vapor etching.
  • the material of the first sacrificial layer 320 may be the same as the material of the intermediate layer 500, so that the first sacrificial layer 320 can be removed by prolonging the etching time.
  • the first sacrificial layer 320 is etched, the first sacrificial layer 320 may also be removed by etching with a high selectivity ratio, so as to reduce the etching of other materials.
  • the manufacturing method of the memory further includes: forming a second sacrificial layer on the side surface of the wire 410 .
  • the material of the second sacrificial layer may include oxide, for example, the second sacrificial layer is a silicon oxide layer.
  • a second sacrificial layer may be formed on both of the exposed opposite side surfaces of the wire 410 .
  • the middle layer 500 is removed and the second sacrificial layer is also removed to form a second air gap on both sides of the wire 410 .
  • the second sacrificial layer is removed by high selectivity vapor etch.
  • the intermediate layer 500 , the first sacrificial layer 320 and the second sacrificial layer are removed by one etching to reduce the number of etchings.
  • the materials of the intermediate layer 500, the first sacrificial layer 320 and the second sacrificial layer are the same to facilitate etching.
  • the peripheral circuit region on the substrate 100 is usually etched, and the peripheral circuit region usually includes an insulating layer and a protective layer , the insulating layer is made of oxide, and the protective layer is made of nitride. Since the first isolation layer 300 and/or the second isolation layer 600 will not be etched when the first sacrificial layer 320 and/or the second sacrificial layer are etched, the protective layer of the peripheral circuit area will not be damaged, Therefore, it is avoided that the insulating layer of the peripheral circuit region is cut through and the peripheral circuit fails.
  • references to the terms “one embodiment,” “some embodiments,” “illustrative embodiments,” “examples,” “specific examples,” or “some examples” and the like are meant to incorporate embodiments A particular feature, structure, material, or characteristic described or exemplified is included in at least one embodiment or example of the present application.
  • schematic representations of the above terms do not necessarily refer to the same embodiment or example.
  • the particular features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

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Abstract

本申请提供一种存储器的制作方法，涉及存储设备技术领域，用于解决存储器的良率较低的技术问题。该存储器的制作方法包括：提供基底，基底包括多个间隔设置的有源区，有源区包括第一接触区和第二接触区；在基底上形成多条间隔设置的位线；在位线上形成第一隔离层，第一隔离层形成第一沟槽；沿第一沟槽刻蚀第一沟槽的槽底，形成暴露出第二接触区的第二沟槽；在第一沟槽和第二沟槽中形成第一导电层；去除部分第一导电层，形成多个第一通孔，以将第一导电层分成多个导线，每个导线连接一个第二接触区；在第一通孔中形成第二隔离层。形成第二隔离层后无需再进行刻蚀，减少对第一隔离层的损伤，以避免第一隔离层刻穿，提高存储器的良率。

Description

存储器的制作方法
本申请要求于2021年03月30日提交中国专利局、申请号为202110343663.3、申请名称为“存储器的制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及存储设备技术领域，尤其涉及一种存储器的制作方法。
背景技术
随着半导体技术和存储技术不断发展，电子设备不断向小型化、集成化方向发展，动态随机存储器(Dynamic Random Access Memory，简称DRAM)因其具有较高的存储密度以及较快的读写速度被广泛地应用在各种电子设备中。
动态随机存储器一般包括基底，基底设置有多个有源区(Active Area)，基底上设置有多条间隔排布的位线，每一行的有源区与一条位线接触。基底和位线上还设置有隔离层，隔离层具有多个通孔，多个通孔与有源区一一对应，每个通孔中暴露一个有源区，且位线不暴露在通孔中。相关技术中，制作存储器时，在形成通孔后，通常沿通孔刻蚀基底，以形成凹槽，在凹槽和通孔中填充导线，导线将电容器与有源区电连接。
然而，在形成凹槽的过程中，易将位线外的隔离层刻穿，导致填充在凹槽中的导线与位线导通，进而导致存储器失效，存储器的良率较低。
发明内容
本申请实施例提供一种存储器的制作方法，包括提供基底，基底包括多个间隔设置的有源区，所述有源区包括第一接触区和第二接触区；在所述基底上形成多条间隔设置的位线，每条位线连接至少一个所述第一接触区；在所述位线上形成第一隔离层，相邻的两个所述第一隔离层之间形成沿第一方向延伸的第一沟槽；沿所述第一沟槽刻蚀所述第一沟槽的槽底， 以形成第二沟槽，所述第二沟槽的槽底位于所述基底中，且所述第二沟槽中暴露有所述第二接触区；在所述第一沟槽和所述第二沟槽中形成第一导电层；去除部分所述第一导电层，以形成多个第一通孔，多个所述第一通孔将所述第一导电层分隔成多个导线，每个所述导线连接一个所述第二接触区；在所述第一通孔中形成第二隔离层。
本申请实施例提供的存储器的制作方法具有如下优点：
本申请实施例提供的存储器的制作方法包括：先提供基底，基底包括多个间隔设置的有源区，有源区包括第一接触区和第二接触区；在基底上形成多条间隔设置的位线，每条位线连接至少一个第一接触区；在位线上形成第一隔离层，相邻的两个第一隔离层之间形成沿第一方向延伸的第一沟槽；沿第一沟槽刻蚀第一沟槽的槽底，以形成第二沟槽，第二沟槽的槽底位于基底中，且第二沟槽中暴露有第二接触区；在第一沟槽和第二沟槽中形成第一导电层；去除部分第一导电层，以形成多个第一通孔，多个第一通孔将第一导电层分隔成多个导线，每个导线连接一个第二接触区；在第一通孔中形成第二隔离层。通过先形成第一隔离层，第一隔离层形成有第一沟槽，并刻蚀第一沟槽的槽底形成第二沟槽，第二沟槽的深宽比降低，使得第二沟槽的负载效应(Loading effect)降低，同时，第二沟槽与第一沟槽的对准较好，提高了存储器的良率；通过在第一沟槽和第二沟槽中形成第一导电层，填充难度较小，以提高存储器的良率；通过去除部分第一导电层，以在第一导电层中形成多个第一通孔，保留的第一导电层形成导线，并在第一通孔中形成第二隔离层，相较于现有技术中还需刻蚀第一隔离层和第二隔离层围合成的区域以填充导线，本申请实施例中形成第二隔离层后无需再进行刻蚀，减少了刻蚀损伤第一隔离层的风险，从而减少了第一隔离层刻穿的可能性，进一步提高了存储器的良率。
附图说明
图1为本申请实施例中的存储器的制作方法的流程图；
图2为本申请实施例中的形成位线后的剖视图；
图3为本申请实施例中的形成第一隔离层后的立体图；
图4为本申请实施例中的形成第一隔离层后的俯视图；
图5为本申请实施例中的形成第一隔离层后的剖视图；
图6为本申请实施例中的形成第一氮化物层后的剖视图；
图7为本申请实施例中的形成第二氮化物层后的剖视图；
图8为本申请实施例中的形成第二沟槽后的立体图；
图9为本申请实施例中的形成第二沟槽后的俯视图；
图10为本申请实施例中的形成第二沟槽后的剖视图；
图11为本申请实施例中的形成第一导电层后的立体图；
图12为本申请实施例中的形成第一导电层后的俯视图；
图13为本申请实施例中的形成第一导电层后的剖视图；
图14为本申请实施例中的形成第三沟槽后的立体图；
图15为本申请实施例中的形成第三沟槽后的剖视图；
图16为本申请实施例中的形成中间层后的立体图；
图17为本申请实施例中的形成中间层后的剖视图；
图18为本申请实施例中的对中间层平坦化处理前的剖视图；
图19为本申请实施例中的形成多个第一通孔的流程图；
图20为本申请实施例中的形成第四沟槽后的立体图；
图21为本申请实施例中的形成第四沟槽后的俯视图；
图22为本申请实施例中的形成第二隔离层后的立体图；
图23为本申请实施例中的形成第二隔离层后的俯视图；
图24为本申请实施例中的去除中间层后的立体图；
图25为本申请实施例中的去除中间层后的俯视图；
图26为本申请实施例中的去除中间层后的剖视图。
具体实施方式
相关技术中，制作存储器时，通常先在基底上形成多条位线和覆盖各位线的第一隔离层；其中，基底包括多个间隔设置的有源区，有源区包括第一接触区和第二接触区，每条位线连接至少一个第一接触区，相邻两条位线之间的第一隔离层形成第一沟槽；在第一沟槽中沉积中间层，中间层填满第一沟槽；刻蚀中间层形成第一通孔，保留的中间层形成多个间隔设置的柱状结构，且每个柱状结构对应一个第二接触区；在第一通孔中沉积第二隔离层；去除剩余的中间层，形成第二通孔；沿第二通孔刻蚀基底， 形成凹槽，凹槽暴露出第二接触区；在凹槽和第二通孔中填充导线。
在上述制作过程中，沿第二通孔刻蚀基底时，易将位线外的第一隔离层刻穿，导致导线与位线导通，进而导致存储器失效，存储器的良率较低。此外，中间层分两次刻蚀去除，去除过程复杂，中间层残留也会导致存储器的良率较低。
为了解决存储器的良率较低的技术问题，本申请实施例提供一种存储器的制作方法，通过先沿第一隔离层形成的第一沟槽刻蚀第一沟槽的槽底，形成槽底位于基底中的第二沟槽，第二沟槽暴露基底的有源区，然后在第一沟槽和第二沟槽中形成第一导电层，以减少第一导电层的填充难度；通过在第一导电层中形成第一通孔，保留的第一导电层形成导线，并在第一通孔内填充第二隔离层，形成第二隔离层后无需再进行刻蚀，从而减小了第一隔离层被刻穿的可能性，提高存储器的良率。
为了使本申请实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本申请保护的范围。
参照图1，本申请实施例提供一种存储器的制作方法，该制作方法具体包括以下步骤：
步骤S101、提供基底，基底包括多个间隔设置的有源区，有源区包括第一接触区和第二接触区。
参照图2至图5，基底100中设置有源区110。如图2所示，有源区110未暴露于基底100的表面。有源区110的数量可以设置有多个，多个有源区110间隔设置。示例性的，多个有源区110之间设置浅槽隔离(Shallow Trench Isolation，简称STI)结构120，浅槽隔离结构120中设置有氧化硅(SiO 2)，以使多个有源区110之间隔离。
多个有源区110可以呈阵列排布。每个有源区110可以包括第一接触区111和第二接触区112，第一接触区111和第二接触区112邻接。第一接触区111连接位线200，第二接触区112连接电容器，例如，第二接触区112依次通过导线和电容接触垫连接电容器。
在一种可能的示例中，如图4所示，第一接触区111位于有源区110的中心，第二接触区112位于有源区110的两侧，即第二接触区112位于第一接触区111的两侧，有源区110的材质可以包括硅(Si)。
步骤S102、在基底上形成多条间隔设置的位线，每条位线连接至少一个第一接触区。
参照图3至图5，基底100上形成多条间隔设置的位线200，基底100中可以形成有位线接触窗，位线接触窗中暴露有源区110的第一接触区111，每条位线200通过位线接触窗连接至少一个第一接触区111。例如，每条位线200连接同一行的多个有源区110的第一接触区111，即同一行的多个有源区110的第一接触区111可以连接同一条位线200，且每个第一接触区111仅连接一条位线200。
可以理解的是，位线200在基底100上的正投影与有源区110在基底100上的正投影之间具有一定角度，即这两个正投影不平行。示例性的，以图4中所示方位，位线200竖直设置，多条位线200之间相互平行，有源区110倾斜设置，多个有源区110之间相互平行。同一条位线200可以穿过多个有源区110。
如图3至图5所示，位线200可以包括依次堆叠设置的第二导电层210、第三导电层220和第四导电层230，第四导电层230位于基底100上，且与基底100的有源区110电连接。
示例性的，第二导电层210的材质可以包括多晶硅(polycrystalline silicon)，第三导电层220的材质可以包括氮化钛(TiN)，第四导电层230的材质可以包括钨(W)。
步骤S103、在位线上形成第一隔离层，相邻的两个第一隔离层之间形成沿第一方向延伸的第一沟槽。
继续参照图3至图5，形成位线200后，在位线200上形成第一隔离层300，第一隔离层300覆盖位线200。可以理解的是，每个位线200的上表面和侧面上形成有第一隔离层300，第一隔离层300的材质可以为绝缘材质，例如氮化硅(Si 3N 4)，以对位线200进行保护以及电气隔离。
相邻的两个第一隔离层300之间形成第一沟槽310，即第一沟槽310的两个侧壁为第一隔离层300。如图3所示，第一沟槽310沿第一方向延伸，可以理解的是，第一沟槽310的延伸方向与位线200的延伸方向相同。
在一种可能的示例中，如图3和图5所示，第一隔离层300中还可以设置有多个第一牺牲层320，如图5所示垂直于位线200的剖面中，每个位线200的两侧设置有一个第一牺牲层320。第一牺牲层320沿第一方向延伸，即第一牺牲层320的延伸方向与位线200的延伸方向相同。
第一牺牲层320的材质可以包括氧化物，例如，氧化硅(SiO 2)。可以理解的是，沿位线200至第一沟槽310的方向，位线200外依次形成有氮化物-氧化物-氮化物(英文全称Nitride-Oxide-Nitride，简称为NON)。
在一些可能的示例中，参照图6和图7，第一隔离层300可以通过以下步骤形成：
在位线200的侧壁和顶面上形成第一氮化物层330。例如，如图6所示，在基底100上依次形成第二预设导电层、第三预设导电层、第四预设导电层和第一预设氮化物层，对第二预设导电层、第三预设导电层、第四预设导电层和第一预设氮化物层进行刻蚀，形成如图6所示的第二导电层210、第三导电层220、第四导电层230和第一氮化物层330，第二导电层210、第三导电层220、第四导电层230构成位线200。
形成第一氮化物层330后，再形成第一牺牲层320和第二氮化物层340，如图7所示，形成第一牺牲层320位于位线200和第一氮化物层330的两侧，第二氮化物层340覆盖第一牺牲层320、第一氮化物层330和位线200。
步骤S104、沿第一沟槽刻蚀第一沟槽的槽底，以形成第二沟槽，第二沟槽的槽底位于基底中，且第二沟槽中暴露有第二接触区。
参照图8至图10，沿第一沟槽310刻蚀第一沟槽310的槽底，以形成第二沟槽130，第二沟槽130的槽底如图8所示的位于基底100中。第二沟槽130的深宽比较小，负载效应降低，便于形成第二沟槽130，同时还避免了相关技术中通孔与有源区110套刻(overlay)标记的对准问题。
参照图9，第二沟槽130中暴露有第二接触区112，如图9所示的有源区110部分实线部分虚线，实线所示为暴露在第二沟槽130中的第二接触区112，虚线所示为被第一隔离层300遮挡的第一接触区111，或者被第一隔离层300遮挡的第一接触区111和部分第二接触区112。
在一种可能的示例中，第一沟槽310暴露出基底100，沿第一沟槽310刻蚀第一沟槽310的槽底时，刻蚀基底100，在基底100中形成第二沟槽130，第二沟槽130暴露出有源区110的第二接触区112。
在另一种可能的示例中，第一隔离层300覆盖位线200和基底100，即第一沟槽310中暴露有第一隔离层300，沿第一沟槽310刻蚀第一沟槽310的槽底时，刻蚀第一隔离层300和基底100，以形成第二沟槽130，如图10所示，第二沟槽130的槽底位于基底100中，且第二沟槽130暴露出有源区110的第二接触区112。
在上述示例中，参照图10，第一隔离层300中还设置有第一牺牲层320，沿第一沟槽310刻蚀第一隔离层300和基底100时，还去除部分第一隔离层300，以使第一牺牲层320暴露于第一隔离层300远离基底100的表面，以便于后续去除第一牺牲层320，形成第一空气隙。如图10所示，去除第一隔离层300的上方的部分区域，以使第一牺牲层320暴露于第一隔离层300的上表面。
步骤S105、在第一沟槽310和第二沟槽130中形成第一导电层400。
参照图11至图13，在第一沟槽310和第二沟槽130中沉积第一导电层400，例如，沉积多晶硅层。形成第一导电层400后，如图12所示，第一导电层400覆盖有源区110的部分第二接触区112，以使得后续形成导线电连接有源区110。
形成第一导电层400时，第一沟槽310和第二沟槽130的填充空间较大，填充难度较低，填充质量较好，减少第一导电层400因填充不均匀而产生空洞(void)和/或缝隙(seam)，提高第一导电层400的形成质量。
第一导电层400可以通过化学气相沉积(Chemical Vapor Deposition，简称CVD)工艺、物理气相沉积(Physical Vapor Deposition，简称PVD)工艺或者原子层沉积(Atomic Layer Deposition，简称ALD)工艺等形成在第一沟槽310和第二沟槽130中。
步骤S106、去除部分第一导电层，以形成多个第一通孔，多个第一通孔将第一导电层分隔成多个导线，每个导线连接一个第二接触区。
刻蚀第一导电层400，以去除部分第一导电层400，保留的第一导电层400与第一隔离层300围设成多个第一通孔，多个第一通孔可以通过一次刻蚀形成。
多个第一通孔将第一导电层400分隔成多个导线，即保留的第一导电层400形成多个间隔设置的导线，每个导线连接一个第二接触区112，以与有源区110电连接。示例性的，一个有源区110可以连接两个导线，一 个有源区110也可以只连接一个导线。
步骤S107、在第一通孔中形成第二隔离层。
第二隔离层可以通过沉积工艺形成，第二隔离层的材质可以为绝缘材质，例如氮化硅，以与第一隔离层300共同对导线进行电气隔离。即各导线之间由第一隔离层300和第二隔离层隔开，以防止相邻的两个导线导通，从而保证存储器正常工作。
形成第二隔离层后，无需再对第一隔离层300和第二隔离层之间的围设成的区域进行刻蚀，减少了刻蚀损伤第一隔离层300的风险，从而减少了第一隔离层300刻穿的可能性，进而避免导线与位线200导通，提高了存储器的良率。
本申请实施例提供的存储器的制作方法包括：提供基底100，基底100包括多个间隔设置的有源区110，有源区110包括第一接触区111和第二接触区112；在基底100上形成多条间隔设置的位线200，每条位线200连接至少一个第一接触区111；在位线200上形成第一隔离层300，相邻的两个第一隔离层300形成沿第一方向延伸的第一沟槽310；沿第一沟槽310刻蚀第一沟槽310的槽底，以形成第二沟槽130，第二沟槽130的槽底位于基底100中，且第二沟槽130中暴露有第二接触区112；在第一沟槽310和第二沟槽130中形成第一导电层400；在第一导电层400中形成多个第一通孔520，多个第一通孔520将第一导电层400分隔成多个导线410，每个导线410连接一个第二接触区112；在第一通孔520中形成第二隔离层600。通过先形成第一隔离层300，第一隔离层300形成有第一沟槽310，并刻蚀第一沟槽310的槽底形成第二沟槽130，第二沟槽130的深宽比降低，使得第二沟槽130的负载效应降低，同时，第二沟槽130与第一沟槽310的对准较好，提高了存储器的良率；通过在第一沟槽310和第二沟槽130中形成第一导电层400，填充难度较小；通过去除部分第一导电层400，以在第一导电层400中形成多个第一通孔520，保留的第一导电层400形成导线410，并在第一通孔520中形成第二隔离层600，相较于现有技术中形成第二隔离层600后，还需刻蚀第一隔离层300和第二隔离层600围合成的区域以填充导线410，本申请实施例中形成第二隔离层600后无需再进行刻蚀，减少了刻蚀损伤第一隔离层300的风险，从而减少了第一隔离层300刻穿的可能性，进一步提高了存储器的良率。
需要说明的是，参照图14至图18，在第一沟槽和第二沟槽中形成第一导电层的步骤之后，存储器的制作方法还包括：
去除部分第一导电层，形成沿第一方向延伸的第三沟槽。示例性的，参照图14和图15，去除位于第一沟槽310上部分的第一导电层400，形成第三沟槽420，即第三沟槽420为第一沟槽310的一部分。如图15所示，第三沟槽420的侧壁为第一隔离层300，第三沟槽420的槽底为第一导电层400，第三沟槽420的槽底可以位于位线200的上方。
形成第三沟槽420后，在第三沟槽420中以及第一隔离层300上形成中间层500，中间层500填充于第三沟槽420中且覆盖第一导电层400。参照图16和图17，第一沟槽310的上部分填充中间层500，第一沟槽310的下部分填充第一导电层400。
可以理解的是，回刻第一导电层400形成第三沟槽420后，在第三沟槽420中形成中间层500，一方面，减少了第一导电层400的高度，在后续刻蚀第一导电层400时，减少了第一导电层400的刻蚀深度，从而减少了刻蚀时的副产品(by-product)，使得刻蚀后的第一导电层400的轮廓较好。另一方面，第一导电层400与第一隔离层300的选择比不易提升，通过设置中间层500，中间层500相对第一隔离层300的选择比较高，在后续刻蚀中间层500时，第一隔离层300较少刻蚀。此外，设置中间层500还可以阻止第一导电层400的扩散。
在一些可能的示例中，参照图18，中间层500可以为旋涂绝缘介质(Spin on Dielectrics，简称SOD)，通过旋涂液态的绝缘介质后，进行高温处理，以使液态的绝缘介质固化，形成中间层500。中间层500可以为氧化物，例如为氧化硅。形成中间层500后，中间层500覆盖第一隔离层300和第一导电层400，对中间层500背离第一导电层400的一侧进行平坦化处理，如图18所示，对中间层500的上表面进行平坦化处理。
平坦化处理后，中间层500的上表面暴露出第一隔离层300和第一导电层400。中间层500可以通过机械化学研磨(Chemical Mechanical Polishing简称CMP)进行平坦化处理。当然，平坦化处理的方式并不是限定的，例如，还可以通过多层光刻胶工艺进行平坦化处理。
本实施方式及以下各实施方式以第三沟槽420中形成有中间层500为例进行详述。参照图19，去除部分第一导电层，以形成多个第一通孔可以 包括以下步骤：
步骤S1061、去除部分中间层和部分第一隔离层，形成沿第二方向延伸的第四沟槽，第四沟槽中暴露有第一导电层和第一隔离层。
参照图20和图21，刻蚀中间层500和第一隔离层300，形成第四沟槽510，第四沟槽510沿第二方向延伸，第二方向可以与第一方向垂直，如图21所示，第四沟槽510水平设置。可以理解的是，第四沟槽510的部分侧壁为第一隔离层300，第四沟槽510部分侧壁为中间层500，且中间层500和第一隔离层300交替。
在一种可能的示例中，如图20所示，去除部分中间层500和部分第一隔离层300时，还去除部分第一导电层400，以使第四沟槽510的槽底位于第一导电层400中。如此设置，一方面第三沟槽420易于形成，另一方面进一步减少第一导电层400的高度，从而减少后续刻蚀第一导电层400时的深度。如图20所示，第四沟槽510的槽底位于位线200的上方，即位线200并未暴露在第四沟槽510中，以防止损伤位线200。
步骤S1062、去除位于第四沟槽的槽底的第一导电层，以形成多个第一通孔。
继续参照图20和图21，形成第四沟槽510后，第四沟槽510的槽底为交替的第一隔离层300和第一导电层400，即第四沟槽510暴露出第一隔离层300和第一导电层400。
如图21所示，刻蚀去除暴露在第四沟槽510中的第一导电层400，形成多个第一通孔520，保留中间层500下方的第一导电层400，保留的第一导电层400形成多个间隔设置的导线410，每个导线410与一个第二接触区112相接触。
需要说明的是，参照图22和图23，在第一通孔520中形成第二隔离层600的步骤可以包括：在第一通孔520和第四沟槽510中沉积第二隔离层600，第二隔离层600填充于第一通孔520和第四沟槽510中。如图22和图23所示，第二隔离层600和第一隔离层300将各导线410电气隔离。
需要说明的是，参照图24至图26，在第一通孔520中形成第二隔离层600的步骤之后，存储器的制作方法还包括：去除中间层500，以暴露导线410。示例性的，通过湿法刻蚀去除中间层500，直至暴露导线410。如图24所示，去除中间层，形成第二通孔610，导线410暴露在第二通孔 610中。
当第一隔离层300中设置有第一牺牲层320时，去除中间层500的同时，还去除第一牺牲层320，以形成第一空气隙。例如，通过蒸汽刻蚀去除第一牺牲层320。第一牺牲层320的材质可以与中间层500的材质相同，以便于通过延长刻蚀时间将第一牺牲层320去除。刻蚀第一牺牲层320时还可以通过高选择比刻蚀去除第一牺牲层320，以减小对其他材料的刻蚀。
需要说明的是，在第一通孔520中形成第二隔离层600的步骤之前，存储器的制作方法还包括：在导线410的侧表面上形成第二牺牲层。第二牺牲层的材质可以包括氧化物，例如，第二牺牲层为氧化硅层。导线410暴露的两个相对侧表面上均可以形成第二牺牲层。
当导线410的侧表面上形成有第二牺牲层时，去除中间层500的同时，还去除第二牺牲层，以在导线410的两侧形成第二空气隙。例如，通过高选择比蒸汽刻蚀去除第二牺牲层。
在一种可能的示例中，中间层500、第一牺牲层320和第二牺牲层通过一次刻蚀去除，以减少刻蚀次数。例如，中间层500、第一牺牲层320和第二牺牲层的材质相同，以便于刻蚀。
刻蚀第一牺牲层320形成第一空气隙和/或刻蚀第二牺牲层形成第二空气隙时，通常还刻蚀基底100上的外围电路区，外围电路区通常包括绝缘层和保护层，绝缘层的材质为氧化物，保护层的材质为氮化物。由于刻蚀第一牺牲层320和/或刻蚀第二牺牲层时，不会对第一隔离层300和/或第二隔离层600进行刻蚀，因而不会损伤外围电路区的保护层，从而避免刻穿外围电路区的绝缘层导致外围电路失效。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
本领域技术人员应理解的是，在本申请的揭露中，术语“纵向”、“横向”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系是基于附图所示的方位或位置关系，其仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的系统或元件必须具有特定的方位、以特定的方位构造和操作，因此上述术语不能理解为对本申请的限制。
在本说明书的描述中，参考术“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (19)

  1. 一种存储器的制作方法，包括：
    提供基底，基底包括多个间隔设置的有源区，所述有源区包括第一接触区和第二接触区；
    在所述基底上形成多条间隔设置的位线，每条位线连接至少一个所述第一接触区；
    在所述位线上形成第一隔离层，相邻的两个所述第一隔离层之间形成沿第一方向延伸的第一沟槽；
    沿所述第一沟槽刻蚀所述第一沟槽的槽底，以形成第二沟槽，所述第二沟槽的槽底位于所述基底中，且所述第二沟槽中暴露有所述第二接触区；
    在所述第一沟槽和所述第二沟槽中形成第一导电层；
    去除部分所述第一导电层，以形成多个第一通孔，多个所述第一通孔将所述第一导电层分隔成多个导线，每个所述导线连接一个所述第二接触区；
    在所述第一通孔中形成第二隔离层。
  2. 根据权利要求1所述的存储器的制作方法，其中，在所述第一沟槽和所述第二沟槽中形成第一导电层的步骤之后，所述存储器的制作方法还包括：
    去除部分所述第一导电层，形成沿第一方向延伸的第三沟槽；
    在所述第三沟槽中以及第一隔离层上形成中间层，所述中间层填充于所述第三沟槽中且覆盖所述第一导电层。
  3. 根据权利要求2所述的存储器的制作方法，其中，去除部分所述第一导电层，形成沿第一方向延伸的第三沟槽的步骤包括：
    去除位于所述第一沟槽上部分的所述第一导电层，以形成所述第三沟槽。
  4. 根据权利要求2所述的存储器的制作方法，其中，所述第三沟槽的槽底位于所述位线的上方。
  5. 根据权利要求2所述的存储器的制作方法，其中，在所述第三沟槽中以及第一隔离层上形成中间层的步骤之后，所述存储器的制作方法还包括：
    对所述中间层背离所述第一隔离层的一侧进行平坦化处理。
  6. 根据权利要求2所述的存储器的制作方法，其中，去除部分所述第一导电层，以形成多个第一通孔的步骤包括：
    去除部分所述中间层和部分所述第一隔离层，形成沿第二方向延伸的第四沟槽，所述第四沟槽中暴露有所述第一导电层和所述第一隔离层；
    去除位于所述第四沟槽的槽底的所述第一导电层，以形成多个所述第一通孔。
  7. 根据权利要求6所述的存储器的制作方法，其中，所述第二方向与所述第一方向垂直。
  8. 根据权利要求6所述的存储器的制作方法，其中，去除部分所述中间层和部分所述第一隔离层的步骤还包括：
    去除部分所述第一导电层，以使所述第四沟槽的槽底位于所述第一导电层中。
  9. 根据权利要求6所述的存储器的制作方法，其中，在所述第一通孔中形成第二隔离层的步骤包括：
    在所述第一通孔和所述第四沟槽中沉积所述第二隔离层，所述第二隔离层填充于所述第一通孔和所述第四沟槽中。
  10. 根据权利要求2所述的存储器的制作方法，其中，在所述第一通孔中形成第二隔离层的步骤之后，所述存储器的制作方法还包括：
    去除所述中间层，以暴露所述导线。
  11. 根据权利要求10所述的存储器的制作方法，其中，所述第一隔离层覆盖所述位线和所述基底；
    沿所述第一沟槽刻蚀所述第一沟槽的槽底的步骤包括：沿所述第一沟槽刻蚀所述第一隔离层和所述基底，以形成所述第二沟槽。
  12. 根据权利要求11所述的存储器的制作方法，其中，所述第一隔离层中还设置有多个沿所述第一方向延伸的第一牺牲层，每条所述位线的两侧设置有所述第一牺牲层；
    沿所述第一沟槽刻蚀所述第一隔离层和所述基底的步骤还包括：去除部分所述第一隔离层，以使所述第一牺牲层暴露于所述第一隔离层远离所述基底的表面。
  13. 根据权利要求12所述的存储器的制作方法，其中，去除所述中间 层的步骤还包括：
    去除所述第一牺牲层，以形成第一空气隙。
  14. 根据权利要求13所述的存储器的制作方法，其中，通过蒸汽刻蚀去除所述第一牺牲层。
  15. 根据权利要求12所述的存储器的制作方法，其中，在所述第一通孔中形成第二隔离层的步骤之前，所述存储器的制作方法还包括：
    在所述导线的侧表面上形成第二牺牲层。
  16. 根据权利要求15所述的存储器的制作方法，其中，去除所述中间层的步骤还包括：
    去除所述第一牺牲层和所述第二牺牲层，以形成第二空气隙。
  17. 根据权利要求16所述的存储器的制作方法，其中，所述第一牺牲层、所述第二牺牲层和所述中间层通过一次刻蚀去除。
  18. 根据权利要求16所述的存储器的制作方法，其中，所述第一牺牲层、所述第二牺牲层和所述中间层的材质包括氧化物，所述中间层为旋涂绝缘介质。
  19. 根据权利要求1所述的存储器的制作方法，其中，所述第一导电层的材质包括多晶硅，所述第一隔离层和所述第二隔离层的材质包括氮化硅。
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