WO2022183660A1 - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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WO2022183660A1
WO2022183660A1 PCT/CN2021/106516 CN2021106516W WO2022183660A1 WO 2022183660 A1 WO2022183660 A1 WO 2022183660A1 CN 2021106516 W CN2021106516 W CN 2021106516W WO 2022183660 A1 WO2022183660 A1 WO 2022183660A1
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Prior art keywords
isolation layer
substrate
bit line
layer
semiconductor structure
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PCT/CN2021/106516
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English (en)
French (fr)
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王景皓
辛欣
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长鑫存储技术有限公司
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Priority to US17/602,960 priority Critical patent/US20230055202A1/en
Publication of WO2022183660A1 publication Critical patent/WO2022183660A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0387—Making the trench
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

Definitions

  • the present disclosure relates to, but is not limited to, a semiconductor structure and a method of fabricating the same.
  • DRAM Dynamic Random Access Memory
  • bit binary bit
  • An embodiment of the present disclosure provides a method for fabricating a semiconductor structure, including: providing a substrate and a bit line structure on the substrate; forming a first isolation layer, the first isolation layer being located on sidewalls of the bit line structure; on the substrate; forming a second isolation layer, the second isolation layer covering the first isolation layer located on the sidewall of the bit line structure, and exposing the first isolation layer located on the substrate; removing the first isolation layer exposed by the second isolation layer and a part of the first isolation layer directly under the second isolation layer, so that the remaining first isolation layer is compared with the second isolation layer
  • the isolation layer is concave toward the side wall of the bit line structure to form a groove; a third isolation layer is formed to fill the groove, and the third isolation layer covers the surface of the first isolation layer exposed by the groove , and the material of the third isolation layer is different from the material of the first isolation layer; the substrate between the adjacent second isolation layers is etched to form a trench, and the trench is located in Between adjacent bit line structures; forming a capaci
  • Embodiments of the present disclosure further provide a semiconductor structure, including: a substrate and a bit line structure on the substrate; a first isolation layer, where the first isolation layer is located on sidewalls of the bit line structure and the substrate; a second isolation layer, the second isolation layer covers the first isolation layer located on the sidewall of the bit line structure, and the second isolation layer is also located on the substrate; compared with the second isolation layer located on the substrate For the second isolation layer, the first isolation layer located on the substrate is concave toward the side wall of the bit line structure, and the concave part has a groove; the third isolation layer located in the groove, The third isolation layer covers the surface of the first isolation layer exposed by the groove, and the material of the first isolation layer is different from the material of the third isolation layer; There is a trench in the substrate between the two, and the trench is located between adjacent bit line structures; a capacitive contact layer located in the trench; the capacitive contact layer fills the trench and is located adjacent to between the bit line structures.
  • FIG. 1 is a schematic diagram of a semiconductor structure corresponding to a step of forming a first isolation layer in a method for manufacturing a semiconductor structure
  • FIG. 2 is a schematic diagram of the semiconductor structure corresponding to the steps of removing part of the first isolation layer on the substrate and reducing the thickness of the remaining first isolation layer in a method for manufacturing a semiconductor structure;
  • FIG. 3 is a schematic diagram of a semiconductor structure corresponding to a step of cleaning the semiconductor structure with a dilute sulfuric acid hydrogen peroxide mixture in a method for manufacturing a semiconductor structure;
  • Fig. 4 is the schematic diagram of the semiconductor structure corresponding to the step that adopts sulfuric acid hydrogen peroxide mixed solution to clean the semiconductor structure in the manufacture method of a kind of semiconductor structure;
  • FIG. 5 is a schematic diagram of a semiconductor structure corresponding to a step of forming a second isolation layer in a method for manufacturing a semiconductor structure
  • FIG. 6 is a schematic diagram of a semiconductor structure corresponding to a step of forming a trench in a method for manufacturing a semiconductor structure
  • FIG. 7 is a schematic diagram of a semiconductor structure corresponding to a step of cleaning the semiconductor structure in a method for manufacturing a semiconductor structure
  • FIG. 8 is a schematic diagram of a semiconductor structure corresponding to a step of forming a capacitive contact layer in a method for manufacturing a semiconductor structure
  • FIG. 9 is a schematic diagram of a semiconductor structure corresponding to a step of providing a substrate and a bit line structure on the substrate according to an embodiment of the disclosure.
  • FIG. 10 is a schematic diagram of a semiconductor structure corresponding to a step of removing part of the initial second isolation layer on the substrate according to an embodiment of the disclosure
  • FIG. 11 is a schematic diagram of a semiconductor structure corresponding to a step of removing the first isolation layer exposed by the second isolation layer and a part of the first isolation layer directly below the second isolation layer according to an embodiment of the disclosure;
  • FIG. 12 is a schematic diagram of a semiconductor structure corresponding to a step of forming an initial third isolation layer according to an embodiment of the disclosure
  • FIG. 13 is a schematic diagram of a semiconductor structure corresponding to a step of forming a trench according to an embodiment of the disclosure
  • FIG. 14 is a schematic diagram of a semiconductor structure corresponding to a step of forming a capacitive contact layer according to an embodiment of the disclosure.
  • FIG. 1-FIG. 8 are schematic structural diagrams corresponding to each step in a manufacturing method of a semiconductor structure.
  • the semiconductor structure in the above figure is a DRAM, and the DRAM generally includes structures such as a substrate 200 , a bit line structure 203 , an insulating cap layer 206 , a first isolation layer 207 , and a capacitive contact layer 210 .
  • the substrate 200 includes an isolation structure 202 and an active region 201;
  • the bit line structure 203 includes a bit line contact layer 204 and a bit line conductive layer 205; an insulating cap layer 206 is located on the bit line conductive layer 205, and is also located on the bit line contact layer 204 and the bit line conductive layer 205.
  • the sidewall of the line conductive layer 205, the insulating cap layer 206 also covers the surface of the substrate 200; the first isolation layer 207 is located on the sidewall of the bit line structure 203, the first isolation layer 207 can prevent the bit line structure 203 and the capacitor contact layer 210. leakage or short circuit occurs.
  • a first isolation layer 207 is formed on the sidewall of the bit line structure 203 and the substrate 200.
  • the first isolation layer 207 also covers the insulating cap layer 206; Referring to FIG. 2, dry etching is used to remove the substrate 200. part of the first isolation layer 207, and reduce the thickness of the remaining first isolation layer 207. It can be understood that, in order to reduce the size of the DRAM, the first isolation layer 207 should have a smaller thickness; with reference to FIG. 3 and FIG. 4 , the semiconductor structure is cleaned to remove impurities remaining in the etching. Referring to FIG.
  • DSP Dilute Sulfuric Peroxide
  • the bit line conductive layer 205 is easily damaged, thereby causing the bit line conductive layer 205 to fail, thereby affecting the yield of the semiconductor structure;
  • SPM sulfuric acid hydrogen peroxide mixture
  • a second isolation layer 208 is formed on the surface of the first isolation layer 207 and the surface of the substrate 200 ; referring to FIG.
  • the substrate 200 between adjacent bit line structures 203 is etched to form trenches 209 .
  • the trench 209 easily exposes the first isolation layer 207 ; referring to FIG. 7 , the semiconductor structure is cleaned to remove impurities generated by the etching. Since the first isolation layer 207 is exposed, during the cleaning process, the exposed first isolation layer 207 is easily removed, resulting in voids (circled by dotted lines); referring to FIG. 8 , formed between adjacent bit line structures 203 Capacitive contact layer 210 .
  • the material of the capacitor contact layer 210 is likely to enter the void, thereby causing leakage or short circuit between the bit line structure 203 and the capacitor contact layer 210 .
  • An embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, the manufacturing method includes: forming a first isolation layer, the first isolation layer is located on the sidewall and the substrate of the bit line structure; forming a second isolation layer, the second isolation layer is located on the The first isolation layer on the sidewall of the bit line structure is exposed, and the first isolation layer on the substrate is exposed.
  • the semiconductor structure Since the second isolation layer is formed directly after the first isolation layer is formed, and the part of the first isolation layer on the substrate is not removed by etching, the semiconductor structure does not need to be cleaned to remove the semiconductor structure before the second isolation layer is formed
  • the impurities generated by the etching, correspondingly, the sidewalls and the bit line structure of the first isolation layer will not be damaged during the cleaning process; the first isolation layer exposed by the second isolation layer and directly under the second isolation layer are removed.
  • the third isolation layer can protect the first isolation layer from being exposed during the process of etching to form the trench, thereby preventing the first isolation layer from being damaged And voids are generated, thereby avoiding leakage or short circuit between the material of the capacitor contact layer and the bit line structure through the voids.
  • FIGS. 9-14 are schematic structural diagrams corresponding to each step in the fabrication method provided in this embodiment. The following will be described in detail with reference to the accompanying drawings.
  • a substrate 100 and a bit line structure 103 on the substrate 100 are provided.
  • the substrate 100 includes a plurality of discrete active regions 101 , and each active region 101 has a source electrode and a drain electrode therein.
  • the bit line structure 103 is electrically connected to the source/drain.
  • the material of the active region 101 may be single crystal silicon, and the single crystal silicon has doping ions such as boron or phosphorus.
  • the substrate 100 also includes isolation structures 102 for isolating adjacent active regions 101 .
  • the material of the isolation structure 102 is an insulating material, such as silicon dioxide, silicon carbide or silicon nitride.
  • the bit line structure 103 includes: a bit line contact layer 104 and a bit line conductive layer 105 arranged in layers. In this embodiment, the bit line structure 103 further includes a barrier layer between the bit line contact layer 104 and the bit line conductive layer 105 .
  • the bit line contact layer 104 is used to electrically connect the bit line conductive layer 105 and the active region 101, and its material can be polysilicon.
  • the bit line conductive layer 105 has lower resistance, and its material can be tungsten or molybdenum.
  • the barrier layer is used to block the interdiffusion of the bit line conductive layer 105 and the bit line contact layer 104, and is also used to increase the adhesion between the bit line conductive layer 105 and the bit line contact layer 104, and its material can be titanium nitride or nitride Tantalum.
  • the bit line conductive layer 105 also has an insulating cap layer 106 , and the insulating cap layer 106 is also located on the side walls of the bit line contact layer 104 and the bit line conductive layer 105 , and on the surface of the substrate 100 .
  • the insulating capping layer 106 is used to prevent oxidation of the bit line conductive layer 105, and its material is an insulating material, such as silicon nitride.
  • a first isolation layer 107 is formed, and the first isolation layer 107 is located on the sidewall of the bit line structure 103 and the substrate 100 .
  • the first isolation layer 107 also covers the surface of the insulating cap layer 106 .
  • the first isolation layer 107 has a lower dielectric constant, which can reduce the parasitic capacitance between adjacent bit line structures 103, thereby increasing the operating speed of the semiconductor structure.
  • the material of the first isolation layer 107 is silicon oxide. In other embodiments, the material of the first isolation layer may be silicon oxycarbide.
  • the atomic layer deposition process is used to form the first isolation layer 107 .
  • the atomic layer deposition process can improve the uniformity and density of the formed film.
  • the chemical vapor deposition process can also be used to form the first isolation layer.
  • the first isolation layer 107 since the second isolation layer will be formed directly on the first isolation layer 107 later, that is, the first isolation layer 107 will not be etched to reduce its thickness, correspondingly, the first isolation layer 107 is formed by a deposition process. , the thickness of the first isolation layer 107 should be appropriately reduced to prevent the first isolation layer 107 from occupying a large space.
  • a second isolation layer 108 is formed, the second isolation layer 108 covers the first isolation layer 107 located on the sidewall of the bit line structure 103 and exposes the first isolation layer 107 located on the substrate 100 .
  • the second isolation layer 108 has greater hardness and density, which can improve the isolation effect to avoid electrical connection between the bit line structure 103 and the subsequently formed capacitive contact layer, thereby avoiding problems such as short circuit or leakage.
  • the second isolation layer 108 has better corrosion resistance, so that damage during cleaning can be avoided.
  • the material of the second isolation layer 108 is silicon nitride. In other embodiments, the material of the second isolation layer may be silicon oxynitride.
  • the second isolation layer 108 is directly formed on the first isolation layer 107 , and the first isolation layer 107 is not etched before the second isolation layer 108 is formed Therefore, it is not necessary to clean the semiconductor structure to remove impurities generated by the etching, so that the cleaning agent can avoid damage to the sidewall of the first isolation layer 107 and the bit line conductive layer 105, so that the semiconductor structure can be improved. structural yield.
  • the semiconductor structure is subsequently cleaned, since the second isolation layer 108 covers part of the first isolation layer 107 , the second isolation layer 108 can provide protection for the first isolation layer 107 .
  • the thickness ratio of the first isolation layer 107 to the second isolation layer 108 on the substrate 100 is 0.3 ⁇ 4.
  • the thickness of the first isolation layer 107 is 3-8 nm, such as 5 nm, 6 nm or 7 nm;
  • the thickness of the second isolation layer 108 is 2-10 nm, such as 3 nm, 6 nm or 8 nm.
  • a preliminary second isolation layer 108 a is formed, and the preliminary second isolation layer 108 a covers the surface of the first isolation layer 107 .
  • an atomic layer deposition process is used to form the initial second isolation layer 108a.
  • the atomic layer deposition process can improve the uniformity and density of the formed film.
  • a chemical vapor deposition process can also be used to form the initial second isolation layer.
  • a portion of the initial second isolation layer 108 a (refer to FIG. 9 ) on the substrate 100 is removed to expose the first isolation layer 107 on the substrate 100 , and the remaining initial second isolation layer 108 a serves as the second isolation layer 108 .
  • the initial second isolation layer 108a on the top surface of the insulating cap layer 106 is also removed, and the first isolation layer 107 on the top surface of the insulating cap layer 106 is exposed.
  • a dry etching process is used to remove part of the second isolation layer 108a.
  • the first isolation layer 107 exposed by the second isolation layer 108 and a part of the first isolation layer 107 directly under the second isolation layer 108 are removed, so that the remaining first isolation layer 107 is compared with the second isolation layer 108 is recessed toward the sidewall of the bit line structure 103 to form a groove (circled by the dotted line).
  • a third isolation layer will be formed to fill the groove, and the third isolation layer can protect the first isolation layer 107 exposed by the groove, so as to avoid damage to the first isolation layer 107 caused by the cleaning agent during the cleaning process.
  • a dry etching process is used to remove the first isolation layer 107 exposed by the second isolation layer 108 and a part of the first isolation layer 107 directly below the second isolation layer 108 .
  • the etching selection ratio of the dry etching process to the first isolation layer 107 and the second isolation layer 108 is 5:1 ⁇ 10:1, for example, 7:1, 8:1 or 9:1.
  • the second isolation layer 108 is not easily damaged, so that the final formed groove can be guaranteed to have good firmness and avoid collapse. question.
  • the dry etching process has good anisotropy, and in this embodiment, the dry etching of the first isolation layer 107 needs to have etching rates in both lateral and vertical directions. That is, in this embodiment, the anisotropy of dry etching needs to be appropriately reduced, and the isotropy of dry etching needs to be appropriately increased.
  • Dry etching includes physical etching and chemical etching.
  • Physical etching uses glow discharge to ionize the gas into charged ions, and then uses bias voltage to accelerate the ions and sputter on the surface of the etched object. The process is completely physical ability transfer, so it has good directionality, that is, it has anisotropy; chemical etching uses plasma to ionize the etching gas and form charged ions, molecules and highly reactive atomic groups. After they diffuse to the surface of the etched film, they react with the surface atoms of the etched film to generate volatile reaction products, which are evacuated from the reaction chamber by vacuum equipment. This process completely utilizes chemical reactions, so it is less directional, that is, isotropic. Usually, physical etching and chemical etching are used in combination, and the size of the physical and chemical effects is adjusted according to the specific conditions of the process.
  • the chemical effect in the dry etching can be appropriately increased, and the physical effect in the dry etching can be reduced.
  • the first isolation layer may also be etched only by chemical etching.
  • the distance from the surface of the first isolation layer 107 exposed by the groove to the sidewall of the bitline structure 103 is the first distance
  • the second isolation layer 108 is far away from the bitline structure 103
  • the distance from the side wall to the side wall of the line structure 103 is the second distance.
  • the difference between the first distance and the second distance is the width of the groove in a direction parallel to the surface of the substrate.
  • the aforementioned ratio of the lateral etching rate to the vertical etching rate can determine the difference between the first distance and the second distance, that is, the width of the groove.
  • the width of the groove can be adjusted by adjusting the ratio of the lateral etching rate to the vertical etching rate.
  • the subsequently formed third isolation layer cannot easily fill the groove; if the width of the groove is too narrow, the subsequently formed third isolation layer has a smaller width.
  • the groove has a suitable width. In this way, the filling difficulty and process time of the third isolation layer can be reduced, and the third isolation layer can also be The isolation layer provides sufficient protection.
  • the width of the first isolation layer 107 removed by dry etching is 3 nm ⁇ 8 nm, such as 5 nm, 6 nm or 7 nm.
  • the second isolation layer 108 is also slightly etched, and the width of the second isolation layer 108 removed by the etching is less than 2 nm.
  • the process parameters of the dry etching process include: the radio frequency power is 300W-1500W, such as 400W, 500W or 1000W; the etching time is 10s-60s, such as 20s, 30s or 50s; etching
  • the temperature ranges from 30°C to 50°C, for example, it can be 35°C, 40°C or 45°C.
  • the RF power is within the above range, the ion beam has sufficient energy, which can speed up the etching rate.
  • the etching time is within the above range, a relatively suitable groove width can be obtained, and at the same time, excessive damage to the semiconductor structure can be avoided.
  • the increase of the etching temperature can increase the activity of the etching gas, thereby increasing the degree of chemical etching, so that an appropriate lateral etching rate and vertical etching rate can be obtained.
  • the etching gases used in the dry etching process include nitrogen trifluoride, hydrogen and nitrogen, and the above gases have a larger etching selectivity ratio for the first isolation layer 107 and the second isolation layer 108 .
  • the flow ratio of nitrogen trifluoride, hydrogen and nitrogen is (5 ⁇ 10):(200 ⁇ 500):(2000 ⁇ 5000), for example, it can be 7:250:3000, 8:300:3600 or 9:400:4300 .
  • the flow rate is within the above range, the etching rate can be accelerated and the process time can be shortened.
  • a third isolation layer 109 is formed to fill the groove, the third isolation layer 109 covers the surface of the first isolation layer 107 exposed by the groove, and the material of the third isolation layer 109 is the same as that of the first isolation layer 107 Materials are different.
  • the third isolation layer 109 is used to protect the first isolation layer 107 exposed by the groove. During the subsequent cleaning process, the first isolation layer 107 will not be damaged by the cleaning agent, and the capacitor contact layer formed subsequently will not be damaged from the cleaning agent. The damaged portion of the first isolation layer 107 is short-circuited or leaked with the bit line structure 103, thereby improving the yield of the semiconductor structure.
  • the formed third isolation layer 109 fills the trench, and the third isolation layer 109 is also located on the sidewall of the second isolation layer 108 . In this way, the third isolation layer 109 can protect the first isolation layer 107 and the bit line structure 103 to a greater extent. In other embodiments, the third isolation layer may only fill the trenches.
  • the third isolation layer 109 has greater hardness and density, which can improve the isolation effect. In addition, the third isolation layer 109 has better corrosion resistance, so that damage during cleaning can be avoided.
  • the material of the third isolation layer 109 is the same as the material of the second isolation layer 108 , so that the adhesion between the third isolation layer 109 and the second isolation layer 108 can be increased.
  • the material of the third isolation layer 109 is silicon nitride. In other embodiments, the material of the third isolation layer may also be silicon oxynitride.
  • a preliminary third isolation layer 109a is formed, which is located on the second isolation layer surface 108 and the substrate 100, and also fills the grooves.
  • the initial third isolation layer 109 a is also located on the top surface of the insulating cap layer 106 .
  • an atomic layer deposition process is used to form the initial third isolation layer 109a.
  • the atomic layer deposition process can deposit substances on the semiconductor structure layer by layer in the form of a single atomic film, so the atomic layer deposition process can fill the grooves more tightly.
  • a chemical vapor deposition process can also be used to form the initial third isolation layer.
  • the initial third isolation layer 109 a (refer to FIG. 12 ) on the substrate 100 is removed, and the remaining initial third isolation layer 109 a serves as the third isolation layer 109 .
  • the initial third isolation layer 109a on the top surface of the insulating cap layer 106 is also removed.
  • a dry etching method is used to remove part of the initial third isolation layer 109a.
  • the substrate 100 located between adjacent second isolation layers 108 is etched to form trenches 110 , and the trenches 110 are located between adjacent bit line structures 103 .
  • the trench 110 can increase the area of the exposed surface of the active region 101 , so that the subsequently formed capacitive contact layer has a larger contact area with the active region 101 , thereby reducing the contact resistance.
  • the formation of the trench 110 and the removal of part of the initial third isolation layer 109a are performed in the same etching process.
  • the first isolation layer 107 will not be exposed. Therefore, the first isolation layer 107 will not be damaged in the subsequent cleaning process.
  • a capacitive contact layer 111 is formed, and the capacitive contact layer 111 fills the trenches 110 (refer to FIG. 13 ) and is located between adjacent bit line structures 103 .
  • the material of the capacitive contact layer 111 is a conductive material with low resistance, such as polysilicon.
  • the capacitor contact layer 111 is formed by a chemical vapor deposition process.
  • the chemical vapor deposition process has a faster deposition rate and can shorten the process time.
  • the method further includes the step of: performing wet cleaning on the surface of the trench 110 to remove impurities on the surface of the trench 110 . Since the first isolation layer 107 is not exposed, the first isolation layer 107 will not be in direct contact with the cleaning agent, nor will it be corroded by the cleaning agent. In this way, the material of the capacitor contact layer 111 cannot be electrically connected to the bit line structure 103 from the damaged part of the first isolation layer 107, so that problems such as leakage or short circuit can be avoided, thereby improving the yield of the semiconductor structure.
  • a groove of the first isolation layer 107 relative to the second isolation layer 108 is formed, and the third isolation layer 109 is filled in the groove; the third isolation layer 109 can expose the first isolation layer 107
  • the third isolation layer 109 can protect the first isolation layer 107, and the first isolation layer 107 will not be damaged; in this way, the material of the capacitive contact layer
  • the damaged portion of the first isolation layer 107 cannot be electrically connected to the bit line structure 103, thereby avoiding the problem of leakage or short circuit and improving the performance of the semiconductor structure.
  • FIG. 14 is a schematic diagram of the semiconductor structure provided in this embodiment.
  • the semiconductor structure includes: a substrate 100 and a bit line structure 103 on the substrate 100 ; a first isolation layer 107, the first isolation layer 107 is located on the side wall of the bit line structure 103 and the substrate 100; the second isolation layer 108, the second isolation layer 108 covers the first isolation layer 107 located on the side wall of the bit line structure 103, the second isolation layer 108 Also located on the substrate 100; compared with the second isolation layer 108 located on the substrate 100, the first isolation layer 107 located on the substrate 100 is concave toward the side wall of the bit line structure 103, and the concave has a groove; located in the concave The third isolation layer 109 in the groove, the third isolation layer 109 covers the surface of the first isolation layer 107 exposed by the groove, and the material of the first isolation layer 107 is different from the material of the third isolation layer 109; the adjacent second isolation layer
  • the substrate 100 includes a plurality of mutually discrete active regions 101 , and isolation structures 102 for isolating adjacent active regions 101 .
  • the bit line structure 103 includes: a bit line contact layer 104 and a bit line conductive layer 105 arranged in layers.
  • the bit line conductive layer 105 also has an insulating cap layer 106 , and the insulating cap layer 106 is also located on the side walls of the bit line contact layer 104 and the bit line conductive layer 105 , and on the surface of the substrate 100 .
  • the first isolation layer 107 has a lower dielectric constant, which can reduce the parasitic capacitance between adjacent bit line structures 103, thereby increasing the operating speed of the semiconductor structure.
  • the material of the first isolation layer 107 is silicon oxide. In other embodiments, the material of the first isolation layer may be silicon oxycarbide.
  • the second isolation layer 108 has greater hardness and density, which can improve the isolation effect, so as to avoid problems such as short circuit or leakage between the bit line structure 103 and the capacitor contact layer 111 .
  • the second isolation layer 108 has better corrosion resistance, so that damage during cleaning can be avoided.
  • the material of the second isolation layer 108 is silicon nitride. In other embodiments, the material of the second isolation layer may also be silicon oxynitride or silicon carbonitride.
  • the third isolation layer 109 is used to protect the first isolation layer 107 on the sidewall of the groove, so that during the cleaning process, the first isolation layer 107 will not be damaged by the cleaning agent, and the capacitive contact layer 111 will not be isolated from the first isolation layer 107.
  • the damaged portion of the layer 107 is short-circuited or leaked with the bit line structure 103, thereby improving the yield of the semiconductor structure.
  • the third isolation layer 109 is also located on the sidewall of the second isolation layer 108 . In this way, the protection effect of the third isolation layer 109 on the first isolation layer 107 and the bit line structure 103 is further improved.
  • the material of the second isolation layer 108 and the material of the third isolation layer 109 are the same. As such, the adhesion between the third isolation layer 109 and the second isolation layer 108 can be increased.
  • the material of the third isolation layer 109 is silicon nitride. In other embodiments, the material of the third isolation layer may also be silicon oxynitride or silicon carbonitride.
  • the third isolation layer 109 covers the first isolation layer 107 in the inner recess, so that the first isolation layer 107 can be prevented from being damaged during cleaning, and thus the capacitive contact layer 111 can be prevented from passing through the damaged area.
  • a short circuit or leakage occurs with the bit line structure 103, thereby improving the performance of the semiconductor structure.
  • the third isolation layer in the process of etching to form the trench, can protect the first isolation layer from being exposed, thereby preventing the first isolation layer from being damaged and generating voids, Thus, leakage or short circuit between the material of the capacitor contact layer and the bit line structure through the void is avoided.

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Abstract

本公开实施例提供一种半导体结构及其制造方法。制造方法包括：提供基底以及位于基底上的位线结构；形成第一隔离层，第一隔离层位于位线结构的侧壁以及基底上；形成第二隔离层，第二隔离层覆盖位于位线结构侧壁的第一隔离层，且露出位于基底上的第一隔离层；去除被第二隔离层暴露的第一隔离层以及位于第二隔离层正下方的部分第一隔离层，以使剩余第一隔离层相较于第二隔离层朝向位线结构侧壁方向内凹以形成凹槽；形成填充凹槽的第三隔离层，第三隔离层覆盖凹槽露出的第一隔离层表面，且第三隔离层的材料与第一隔离层的材料不同；刻蚀位于相邻第二隔离层之间的基底，以形成沟槽；形成电容接触层。

Description

半导体结构及其制造方法
本公开要求在2021年03月04日提交中国专利局、申请号为202110240323.8、发明名称为“半导体结构及其制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及但不限于一种半导体结构及其制造方法。
背景技术
半导体结构中的动态随机存取存储器(Dynamic Random Access Memory，简称DRAM)是一种广泛应用于计算机系统的半导体存储器。DRAM的主要作用原理是利用电容内存储电荷的多寡来代表一个二进制比特(bit)是1还是0。
然而，为提高半导体集成电路的集成度，DRAM的特征尺寸越来越小；从而使得DRAM的制作工艺难度越来越大，其性能也有待进一步提升。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种半导体结构的制造方法，包括：提供基底以及位于所述基底上的位线结构；形成第一隔离层，所述第一隔离层位于所述位线结构的侧壁以及所述基底上；形成第二隔离层，所述第二隔离层覆盖位于所述位线结构侧壁的所述第一隔离层，且露出位于所述基底上的所述第一隔离层；去除被所述第二隔离层暴露的所述第一隔离层以及位于所述第二隔离层正下方的部分所述第一隔离层，以使剩余所述第一隔离层相较于所述第二隔离层朝向所述位线结构侧壁方向内凹以形成凹槽；形成填充所述凹槽的第三隔离层，所述第三隔离层覆盖所述凹槽露出的所述第一隔离层表面，且所述第三隔离层的材料与所述第一隔离层的材料不同；刻蚀位于相邻所述第二隔 离层之间的所述基底，以形成沟槽，且所述沟槽位于相邻位线结构之间；形成电容接触层，所述电容接触层填充满所述沟槽且位于相邻位线结构之间。
本公开实施例还提供一种半导体结构，包括：基底以及位于所述基底上的位线结构；第一隔离层，所述第一隔离层位于所述位线结构侧壁以及所述基底上；第二隔离层，所述第二隔离层覆盖位于所述位线结构侧壁的所述第一隔离层，所述第二隔离层还位于所述基底上；相较于位于所述基底上的第二隔离层，位于所述基底上的所述第一隔离层朝向所述位线结构侧壁方向内凹，所述内凹处具有凹槽；位于所述凹槽内的第三隔离层，所述第三隔离层覆盖所述凹槽露出的所述第一隔离层表面，且所述第一隔离层的材料与所述第三隔离层的材料不同；相邻所述第二隔离层之间的所述基底内具有沟槽，且所述沟槽位于相邻位线结构之间；位于所述沟槽内的电容接触层；所述电容接触层填充满所述沟槽且位于相邻位线结构之间。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本申请的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1为一种半导体结构的制造方法中形成第一隔离层的步骤对应的半导体结构的示意图；
图2为一种半导体结构的制造方法中去除基底上的部分第一隔离层，并减小剩余的第一隔离层的厚度的步骤对应的半导体结构的示意图；
图3为一种半导体结构的制造方法中采用稀硫酸双氧水混合液对半导体结构进行清洗的步骤对应的半导体结构的示意图；
图4为一种半导体结构的制造方法中采用硫酸双氧水混合液对半导体结 构进行清洗的步骤对应的半导体结构的示意图；
图5为一种半导体结构的制造方法中形成第二隔离层的步骤对应的半导体结构的示意图；
图6为一种半导体结构的制造方法中形成沟槽的步骤对应的半导体结构的示意图；
图7为一种半导体结构的制造方法中半导体结构进行清洗的步骤对应的半导体结构的示意图；
图8为一种半导体结构的制造方法中形成电容接触层的步骤对应的半导体结构的示意图；
图9为本公开一实施例的提供基底以及位于基底上的位线结构的步骤对应的半导体结构的示意图；
图10为本公开一实施例的去除位于基底上的部分初始第二隔离层的步骤对应的半导体结构的示意图；
图11为本公开一实施例的去除被第二隔离层暴露的第一隔离层以及位于第二隔离层正下方的部分第一隔离层的步骤对应的半导体结构的示意图；
图12为本公开一实施例的形成初始第三隔离层的步骤对应的半导体结构的示意图；
图13为本公开一实施例的形成沟槽的步骤对应的半导体结构的示意图；
图14为本公开一实施例的形成电容接触层的步骤对应的半导体结构的示意图。
具体实施方式
由背景技术可知，DRAM的性能有待进一步提高。
参考图1-图8，图1-图8为一种半导体结构的制造方法中各步骤对应的结构示意图。上图中的半导体结构为DRAM，DRAM通常包括基底200、位线结构203、绝缘盖层206、第一隔离层207和电容接触层210等结构。基底200包括隔离结构202以及有源区201；位线结构203包括位线接触层204以及位线导电层205；绝缘盖层206位于位线导电层205上，还位于位线接触层204以及位线导电层205的侧壁，绝缘盖层206还覆盖基底200的表面；第一隔离层207位于位线结构203的侧壁，第一隔离层207能够防止位线结构203与电容接触层210之间发生漏电或短路。
参考图1，在位线结构203的侧壁，以及基底200上形成第一隔离层207，第一隔离层207还覆盖绝缘盖层206；参考图2，采用干法刻蚀以去除基底上200的部分第一隔离层207，并减小剩余的第一隔离层207的厚度。可以理解的是，为缩小DRAM尺寸，第一隔离层207应当具有较小的厚度；参考图3和图4，对半导体结构进行清洗，以去除刻蚀所残留的杂质。参考图3，若采用稀硫酸双氧水混合液(DSP，Dilute Sulfuric Peroxide)对半导体结构进行清洗时，由于第一隔离层207的厚度较小，因此其容易受到损伤，从而产生漏电的风险。参考图4，若采用硫酸双氧水混合液(SPM，Sulfuric Peroxide Mixture)对半导体结构进行清洗时，还容易损伤位线导电层205，从而导致位线导电层205失效，进而影响半导体结构的良率；参考图5，在第一隔离层207的表面以及基底200表面形成第二隔离层208；参考图6，刻蚀位于相邻位线结构203之间的基底200，以形成沟槽209。在刻蚀的过程中，沟槽209容易将第一隔离层207露出；参考图7，对半导体结构进行清洗，以去除刻蚀产生的杂质。由于第一隔离层207被露出，因此，在清洗过程中，露出的第一隔离层207容易被去除，从而产生空洞(虚线圆圈处)；参考图8，在相邻位线结构203之间形成电容接触层210。电容接触层210的材料容易进入空洞，从而导致位线结构203与电容接触层210之间发生漏电或短路。
本公开实施例提供一种半导体结构的制造方法，制造方法包括：形成第一隔离层，第一隔离层位于位线结构的侧壁以及基底上；形成第二隔离层，第二隔离层覆盖位于位线结构侧壁的第一隔离层，且露出位于基底上的第一隔离层。由于在第一隔离层形成后直接形成第二隔离层，而未采用刻蚀的方法去除位于基底上的部分第一隔离层，因此，在形成第二隔离层之前无需对半导体结构进行清洗以去除刻蚀所产生的杂质，相应的，第一隔离层的侧壁和位线结构不会在清洗过程中受到损伤；去除被第二隔离层暴露的第一隔离层以及位于第二隔离层正下方的部分第一隔离层，以使剩余第一隔离层相较于第二隔离层朝向位线结构侧壁方向内凹以形成凹槽；形成填充凹槽的第三隔离层，第三隔离层覆盖凹槽露出的第一隔离层表面；刻蚀位于相邻第二隔离层之间的基底，以形成沟槽；形成填充沟槽的电容接触层。由于第三隔离层将凹槽露出的第一隔离层覆盖，因此，在刻蚀形成沟槽的过程中，第三隔 离层能够保护第一隔离层不被露出，从而避免第一隔离层受到损伤并产生空洞，进而避免电容接触层的材料通过空洞与位线结构发生漏电或短路。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
本公开一实施例提供一种半导体结构的制造方法，图9-图14为本实施例提供的制造方法中各步骤对应的结构示意图。以下将结合附图进行具体说明。
参考图9，提供基底100以及位于基底100上的位线结构103。
基底100包括多个相互分立的有源区101，每一有源区101内具有源极和漏极。位线结构103与源极/漏极电连接。有源区101的材料可以为单晶硅，单晶硅中具有硼或磷等掺杂离子。
基底100还包括用于隔离相邻有源区101的隔离结构102。隔离结构102的材料为绝缘材料，比如可以为二氧化硅、碳化硅或氮化硅。
位线结构103包括：层叠设置的位线接触层104和位线导电层105。本实施例中，位线结构103还包括位于位线接触层104以及位线导电层105之间的阻挡层。
其中，位线接触层104用于将位线导电层105和有源区101电连接，其材料可以为多晶硅。位线导电层105具有较低的电阻，其材料可以为钨或钼。阻挡层用于阻挡位线导电层105与位线接触层104的互扩散，还用于增大位线导电层105与位线接触层104的黏附性，其材料可以为氮化钛或氮化钽。
位线导电层105上还具有绝缘盖层106，绝缘盖层106还位于位线接触层104和位线导电层105的侧壁，以及基底100的表面。绝缘盖层106用于防止位线导电层105的氧化，其材料为绝缘材料，比如可以为氮化硅。
继续参考图9，形成第一隔离层107，第一隔离层107位于位线结构103的侧壁以及基底100上。本实施例中，第一隔离层107还覆盖绝缘盖层106的表面。
第一隔离层107具有较低的介电常数，能够降低相邻位线结构103之间 的寄生电容，从而提高半导体结构的运行速率。本实施例中，第一隔离层107的材料为氧化硅。在其他实施例中，第一隔离层的材料可以为碳氧化硅。
本实施例中，采用原子层沉积工艺形成第一隔离层107。原子层沉积工艺可以提高形成的膜层的均匀性和致密度。在其他实施例中，也可以采用化学气相沉积工艺形成第一隔离层。
其中，由于后续将直接在第一隔离层107上形成第二隔离层，即不会对第一隔离层107进行刻蚀以减小其厚度，相应的，在采用沉积工艺形成第一隔离层107时，应适当地减小第一隔离层107的厚度，以避免第一隔离层107占据较大的空间位置。
结合参考图9-图10，形成第二隔离层108，第二隔离层108覆盖位于位线结构103侧壁的第一隔离层107，且露出位于基底100上的第一隔离层107。
第二隔离层108具有较大的硬度和致密度，能够提高隔离的效果，以避免位线结构103与后续形成的电容接触层发生电连接，从而避免产生短路或漏电等问题。另外，第二隔离层108具有较好的抗腐蚀能力，如此，可以避免在清洗过程中受到损伤。本实施例中，第二隔离层108的材料为氮化硅。在其他实施例中，第二隔离层的材料可以为氮氧化硅。
本实施例中，在形成了第一隔离层107后，直接在第一隔离层107上形成了第二隔离层108，而在形成第二隔离层108之前并未对第一隔离层107进行刻蚀处理，因此，也不需要对半导体结构进行清洗以去除刻蚀所产生的杂质，由此可以避免清洗剂对第一隔离层107的侧壁及位线导电层105造成损伤，从而可以提高半导体结构的良率。另外，后续对半导体结构进行清洗处理时，由于第二隔离层108覆盖了部分第一隔离层107，因此，第二隔离层108能够为第一隔离层107提供保护作用。
在垂直于基底100表面的方向上，位于基底100上的第一隔离层107与第二隔离层108的厚度之比为0.3～4。其中，第一隔离层107的厚度为3～8nm，比如可以为5nm、6nm或7nm；第二隔离层108的厚度为2～10nm，比如可以为3nm、6nm或8nm。第一隔离层107与第二隔离层108的厚度之比在上述范围内时，既可以降低后续形成凹槽的工艺难度，还可以使得后续 形成的凹槽具有较好的牢固性，从而避免第二隔离层108在凹槽处发生坍塌。
以下将对第二隔离层108的形成步骤进行详细说明。
参考图9，形成初始第二隔离层108a，初始第二隔离层108a覆盖第一隔离层107表面。
本实施例中，采用原子层沉积工艺形成初始第二隔离层108a。原子层沉积工艺可以提高形成的膜层的均匀性和致密度。在其他实施例中，也可以采用化学气相沉积工艺形成初始第二隔离层。
参考图10，去除位于基底100上的部分初始第二隔离层108a(参考图9)，以露出位于基底100上的第一隔离层107，剩余的初始第二隔离层108a作为第二隔离层108。
本实施例中，还去除了位于绝缘盖层106顶面上的初始第二隔离层108a，并露出了位于绝缘盖层106顶面上的第一隔离层107。
本实施例中，采用干法刻蚀的工艺去除部分第二隔离层108a。
参考图11，去除被第二隔离层108暴露的第一隔离层107以及位于第二隔离层108正下方的部分第一隔离层107，以使剩余第一隔离层107相较于第二隔离层108朝向位线结构103侧壁方向内凹以形成凹槽(虚线圆圈处)。
后续将形成第三隔离层以填充凹槽，第三隔离层可以保护凹槽所露出的第一隔离层107，以避免在清洗过程中清洗剂对第一隔离层107造成损伤。
采用干法刻蚀工艺，去除被第二隔离层108暴露出的第一隔离层107以及位于第二隔离层108正下方的部分第一隔离层107。干法刻蚀工艺对第一隔离层107与第二隔离层108的刻蚀选择比为5:1～10:1，比如可以为7：1、8：1或9：1。当第一隔离层107与第二隔离层108的刻蚀选择比较大时，第二隔离层108不容易受到损伤，如此，可以保证最终形成的凹槽具有较好的牢固性，避免发生坍塌的问题。
一般地，干法刻蚀工艺具有较好的各向异性，而本实施例中，对第一隔离层107的干法刻蚀需具有横向和竖向两个方向上的刻蚀速率。即本实施例中，需适当地降低干法刻蚀的各向异性，而适当地增加干法刻蚀的各向同性。
干法刻蚀包括物理性刻蚀和化学性刻蚀。物理性刻蚀是利用辉光放电将 气体电离成带电离子，再利用偏压将离子加速，溅击在被刻蚀物的表面。该过程完全是物理上的能力转移，因而具有良好的方向性，即具有各向异性；化学性刻蚀是利用等离子体将刻蚀气体电离并形成带电离子、分子以及反应性很强的原子团，它们扩散到被刻蚀薄膜表面后与被刻蚀薄膜的表面原子反应生成具有挥发性的反应产物，并被真空设备抽离反应腔。这种过程完全利用化学反应，因而其方向性较差，即具有各向同性。通常将物理性刻蚀和化学性刻蚀结合使用，并根据工艺的具体情况，对物理作用和化学作用的大小进行调节。
由于需要获得竖向的刻蚀速率和横向的刻蚀速率，因此，本实施例中，可以适当地增大干法刻蚀中的化学作用，并降低干法刻蚀中的物理作用。在其他实施例中，也可以只采用化学性刻蚀的方法对第一隔离层进行刻蚀。
在形成凹槽之后，在平行于基底100表面的方向上，凹槽露出的第一隔离层107的表面到位线结构103侧壁的距离为第一距离，第二隔离层108远离位线结构103的侧面到位线结构103侧壁的距离为第二距离。第一距离与第二距离的差值为凹槽在平行于基底表面的方向的宽度。前述的横向刻蚀速率和竖向的刻蚀速率的比值能够决定第一距离与第二距离的差值大小，即能够决定凹槽的宽度。若比值越大，则横向的刻蚀程度越小，凹槽的宽度越小；若比值越小，则横向的刻蚀程度越大，凹槽的宽度越大。因此，可以通过调节横向刻蚀速率和竖向刻蚀速率的比值来调节凹槽的宽度。
其中，若凹槽的宽度过宽，则后续形成的第三隔离层不容易填充满凹槽；若凹槽的宽度过窄，则后续形成的第三隔离层的宽度较小。当第一距离与第二距离的差值为3nm～10nm时，凹槽具有较为合适的宽度，如此，可以降低第三隔离层的填充难度以及工艺时间，还可以使得第三隔离层对第一隔离层起到充分的保护作用。
本实施例中，在平行于基底100表面的方向上，即横向上，干法刻蚀所去除的第一隔离层107的宽度为3nm～8nm，比如可以为5nm、6nm或7nm。另外，在第一隔离层107的刻蚀过程中，也会对第二隔离层108造成轻微的刻蚀，且刻蚀所去除的第二隔离层108的宽度小于2nm。
本实施例中，干法刻蚀工艺的工艺参数包括：射频功率为300W-1500W，比如可以为400W、500W或1000W；刻蚀时间为10s～60s， 比如可以为20s、30s或50s；刻蚀温度为30℃～50℃，比如可以为35℃、40℃或45℃。射频功率在上述范围内时，离子束具有较充足的能量，能够加快刻蚀速率。另外，刻蚀时间在上述范围内时，能够获得较为合适的凹槽宽度，同时能够避免对半导体结构造成过多的损伤。另外，刻蚀温度的提高，可以增大刻蚀气体的活性，从而增大化学性刻蚀的程度，如此，可以获得适当的横向刻蚀速率和竖向刻蚀速率。
干法刻蚀工艺采用的刻蚀气体包括三氟化氮、氢气和氮气，上述气体对第一隔离层107和第二隔离层108具有较大的刻蚀选择比。三氟化氮、氢气和氮气的流量比为(5～10)：(200～500)：(2000～5000)，比如可以为7：250：3000、8：300：3600或9：400：4300。当流量在上述范围内时，能够加快刻蚀速率，缩短工艺时间。
参考图12-图13，形成填充凹槽的第三隔离层109，第三隔离层109覆盖凹槽露出的第一隔离层107表面，且第三隔离层109的材料与第一隔离层107的材料不同。
第三隔离层109用于保护被凹槽所露出的第一隔离层107，在后续的清洗过程中，第一隔离层107不会被清洗剂所损伤，后续形成的电容接触层也不会从第一隔离层107的损伤处与位线结构103发生短路或漏电，从而提高了半导体结构的良率。
本实施例中，形成的第三隔离层109填充满沟槽，且第三隔离层109还位于第二隔离层108的侧壁。如此，第三隔离层109能够在更大程度地保护第一隔离层107以及位线结构103。在其他实施例中，第三隔离层也可以只填充沟槽。
第三隔离层109具有较大的硬度和致密度，能够提高隔离的效果。另外，第三隔离层109具有较好的抗腐蚀能力，如此，可以避免在清洗过程中受到损伤。本实施例中，第三隔离层109的材料与第二隔离层108的材料相同，如此，可以增大第三隔离层109与第二隔离层108之间的粘附性。本实施例中，第三隔离层109的材料为氮化硅。在其他实施例中，第三隔离层的材料也可以为氮氧化硅。
以下将对第三隔离层109的形成步骤进行具体说明。
参考图12，形成初始第三隔离层109a，初始第三隔离层109a位于第二 隔离层表面108以及基底100上，且还填充凹槽。初始第三隔离层109a还位于绝缘盖层106的顶面。
本实施例中，采用原子层沉积工艺形成初始第三隔离层109a。原子层沉积工艺能够将物质以单原子膜形式一层一层的镀在半导体结构上，因此，采用原子层沉积工艺能够将凹槽填充地更为紧密。在其他实施例中，也可以采用化学气相沉积工艺形成初始第三隔离层。
参考图13，去除位于基底100上的初始第三隔离层109a(参考图12)，剩余的初始第三隔离层109a作为第三隔离层109。本实施例中，还去除了位于绝缘盖层106顶面上的初始第三隔离层109a。
本实施例中，采用干法刻蚀的方法去除部分初始第三隔离层109a。
继续参考图13，刻蚀位于相邻第二隔离层108之间的基底100，以形成沟槽110，且沟槽110位于相邻位线结构103之间。
沟槽110可以增加有源区101被露出的表面的面积，如此，后续形成的电容接触层与有源区101具有较大的接触面积，从而可以降低接触电阻。
本实施例中，沟槽110的形成与部分初始第三隔离层109a(参考图12)的去除在同一刻蚀的工艺中进行。
在刻蚀的过程中，由于初始第三隔离层109a将第一隔离层107覆盖，第一隔离层107不会被暴露，因此，第一隔离层107在后续的清洗过程中不会受到损伤。
参考图14，形成电容接触层111，电容接触层111填充满沟槽110(参考图13)且位于相邻位线结构103之间。
电容接触层111的材料为导电材料，且具有较低的电阻，比如可以为多晶硅。
本实施例中，采用化学气相沉积工艺形成电容接触层111。化学气相沉积工艺具有较快的沉积速度，能够缩短工艺时间。
在形成电容接触层111前，还包括步骤：对沟槽110表面进行湿法清洗，以去除沟槽110表面的杂质。由于第一隔离层107未被暴露，因此，第一隔离层107不会与清洗剂直接接触，也不会受到清洗剂的腐蚀。如此，电容接触层111的材料也无法从第一隔离层107的损伤处与位线结构103发生电连接，从而能够避免漏电或短路等问题，进而能够提高半导体结构的良 率。
综上所述，本实施例形成第一隔离层107相对于第二隔离层108的凹槽，并在凹槽中填充第三隔离层109；第三隔离层109能够将第一隔离层107露出的表面覆盖，在后续的刻蚀和清洗过程中，第三隔离层109均能起到对第一隔离层107的保护作用，第一隔离层107不会受到损伤；如此，电容接触层的材料无法通过第一隔离层107的损伤处与位线结构103发生电连接，从而避免了漏电或短路的问题，提高了半导体结构的性能。
本公开另一实施例提供一种半导体结构，图14为本实施例提供的半导体结构的示意图，参考图14，半导体结构包括：基底100以及位于基底100上的位线结构103；第一隔离层107，第一隔离层107位于位线结构103侧壁以及基底100上；第二隔离层108，第二隔离层108覆盖位于位线结构103侧壁的第一隔离层107，第二隔离层108还位于基底100上；相较于位于基底100上的第二隔离层108，位于基底100上的第一隔离层107朝向位线结构103侧壁方向内凹，内凹处具有凹槽；位于凹槽内的第三隔离层109，第三隔离层109覆盖凹槽露出的第一隔离层107表面，且第一隔离层107的材料与第三隔离层109的材料不同；相邻第二隔离层108之间的基底100内具有沟槽，且沟槽位于相邻位线结构103之间；位于沟槽内的电容接触层111；电容接触层111填充满沟槽且位于相邻位线结构103之间。
以下将结合附图进行具体说明。
参考图14，基底100包括多个相互分立的有源区101，以及用于隔离相邻有源区101的隔离结构102。
位线结构103包括：层叠设置的位线接触层104和位线导电层105。位线导电层105上还具有绝缘盖层106，绝缘盖层106还位于位线接触层104和位线导电层105的侧壁，以及基底100的表面。
关于基底100以及位线结构103的具体说明请参考前一实施例，在此不再赘述。
第一隔离层107具有较低的介电常数，能够降低相邻位线结构103之间的寄生电容，从而提高半导体结构的运行速率。本实施例中，第一隔离层107的材料为氧化硅。在其他实施例中，第一隔离层的材料可以为碳氧化硅。
第二隔离层108具有较大的硬度和致密度，能够提高隔离的效果，以避免位线结构103与电容接触层111之间产生短路或漏电等问题。另外，第二隔离层108具有较好的抗腐蚀能力，如此，可以避免在清洗过程中受到损伤。本实施例中，第二隔离层108的材料为氮化硅。在其他实施例中，第二隔离层的材料也可以为氮氧化硅或碳氮化硅。
第三隔离层109用于保护凹槽侧壁的第一隔离层107，如此，在清洗过程中，第一隔离层107不会被清洗剂所损伤，电容接触层111也不会从第一隔离层107的损伤处与位线结构103发生短路或漏电，从而提高了半导体结构的良率。
本实施例中，第三隔离层109还位于第二隔离层108的侧壁。如此，更一步提高第三隔离层109对第一隔离层107和位线结构103的保护作用。
本实施例中，第二隔离层108的材料和第三隔离层109的材料相同。如此，可以增大第三隔离层109与第二隔离层108之间的粘附性。本实施例中，第三隔离层109的材料为氮化硅。在其他实施例中，第三隔离层的材料也可以为氮氧化硅或碳氮化硅。
综上所述，本实施例中，第三隔离层109覆盖内凹处的第一隔离层107，如此可以避免第一隔离层107在清洗中受到损伤，进而可以避免电容接触层111通过损伤处与位线结构103发生短路或漏电，从而提高半导体结构的性能。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的 方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的半导体结构及其制造方法，在刻蚀形成沟槽的过程中，第三隔离层能够保护第一隔离层不被露出，从而避免第一隔离层受到损伤并产生空洞，进而避免电容接触层的材料通过空洞与位线结构发生漏电或短路。

Claims (15)

  1. 一种半导体结构的制造方法，所述制造方法包括：
    提供基底以及位于所述基底上的位线结构；
    形成第一隔离层，所述第一隔离层位于所述位线结构的侧壁以及所述基底上；
    形成第二隔离层，所述第二隔离层覆盖位于所述位线结构侧壁的所述第一隔离层，且露出位于所述基底上的所述第一隔离层；
    去除被所述第二隔离层暴露的所述第一隔离层以及位于所述第二隔离层正下方的部分所述第一隔离层，以使剩余所述第一隔离层相较于所述第二隔离层朝向所述位线结构侧壁方向内凹以形成凹槽；
    形成填充所述凹槽的第三隔离层，所述第三隔离层覆盖所述凹槽露出的所述第一隔离层表面，且所述第三隔离层的材料与所述第一隔离层的材料不同；
    刻蚀位于相邻所述第二隔离层之间的所述基底，以形成沟槽，且所述沟槽位于相邻位线结构之间；
    形成电容接触层，所述电容接触层填充满所述沟槽且位于相邻所述位线结构之间。
  2. 根据权利要求1所述的半导体结构的制造方法，其中，采用干法刻蚀工艺，去除被所述第二隔离层暴露出的所述第一隔离层以及位于所述第二隔离层正下方的部分所述第一隔离层；其中，所述干法刻蚀工艺对所述第一隔离层与所述第二隔离层的刻蚀选择比为5:1～10:1。
  3. 根据权利要求2所述的半导体结构的制造方法，其中，所述干法刻蚀工艺采用的刻蚀气体包括三氟化氮、氢气和氮气；所述三氟化氮、所述氢气和所述氮气的流量比为(5～10)：(200～500)：(2000～5000)。
  4. 根据权利要求2所述的半导体结构的制造方法，其中，所述干法刻蚀工艺的工艺参数包括：射频功率为300W-1500W，刻蚀时间为10s～60s，刻蚀温度为30℃～50℃。
  5. 根据权利要求2所述的半导体结构的制造方法，其中，在形成所述凹槽之后，在平行于所述基底表面的方向上，所述凹槽露出的所述第一隔离层 的表面到所述位线结构侧壁的距离为第一距离，所述第二隔离层远离所述位线结构的侧面到所述位线结构侧壁的距离为第二距离，所述第一距离与所述第二距离的差值为3nm～10nm。
  6. 根据权利要求2所述的半导体结构的制造方法，其中，在垂直于所述基底表面的方向上，位于所述基底上的所述第一隔离层与所述第二隔离层的厚度之比为0.3～4。
  7. 根据权利要求1所述的半导体结构的制造方法，其中，形成所述第二隔离层的步骤包括：
    形成初始第二隔离层，所述初始第二隔离层覆盖所述第一隔离层表面；
    去除位于所述基底上的部分所述初始第二隔离层，以露出位于所述基底上的所述第一隔离层，剩余的所述初始第二隔离层作为所述第二隔离层。
  8. 根据权利要求1所述的半导体结构的制造方法，其中，所述第三隔离层还位于所述第二隔离层的侧壁，形成所述第三隔离层的步骤包括：
    形成初始第三隔离层，所述初始第三隔离层位于所述第二隔离层表面以及所述基底上，且还填充所述凹槽；
    去除位于所述基底上的所述初始第三隔离层，剩余的所述初始第三隔离层作为所述第三隔离层。
  9. 根据权利要求8所述的半导体结构的制造方法，其中，采用原子层沉积工艺形成所述初始第三隔离层。
  10. 根据权利要求1所述的半导体结构的制造方法，在形成所述电容接触层前，所述制造方法还包括步骤：对所述沟槽表面进行湿法清洗，以去除所述沟槽表面的杂质。
  11. 一种半导体结构，所述半导体结构包括：
    基底以及位于所述基底上的位线结构；
    第一隔离层，所述第一隔离层位于所述位线结构侧壁以及所述基底上；
    第二隔离层，所述第二隔离层覆盖位于所述位线结构侧壁的所述第一隔离层，所述第二隔离层还位于所述基底上；
    相较于位于所述基底上的所述第二隔离层，位于所述基底上的所述第一隔离层朝向所述位线结构侧壁方向内凹，所述内凹处具有凹槽；
    位于所述凹槽内的第三隔离层，所述第三隔离层覆盖所述凹槽露出的所 述第一隔离层表面，且所述第一隔离层的材料与所述第三隔离层的材料不同；
    相邻所述第二隔离层之间的所述基底内具有沟槽，且所述沟槽位于相邻所述位线结构之间；
    位于所述沟槽内的电容接触层；所述电容接触层填充满所述沟槽且位于相邻所述位线结构之间。
  12. 根据权利要求11所述的半导体结构，其中，所述第三隔离层还位于所述第二隔离层的侧壁。
  13. 根据权利要求11所述的半导体结构，其中，所述第二隔离层的材料和所述第三隔离层的材料相同。
  14. 根据权利要求13所述的半导体结构，其中，所述第二隔离层的材料包括氮化硅、氮氧化硅或碳氮化硅；所述第三隔离层的材料包括氮化硅、氮氧化硅或碳氮化硅。
  15. 根据权利要求11所述的半导体结构，其中，所述第一隔离层的材料包括氧化硅。
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