WO2022188295A1 - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

Info

Publication number
WO2022188295A1
WO2022188295A1 PCT/CN2021/101943 CN2021101943W WO2022188295A1 WO 2022188295 A1 WO2022188295 A1 WO 2022188295A1 CN 2021101943 W CN2021101943 W CN 2021101943W WO 2022188295 A1 WO2022188295 A1 WO 2022188295A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
forming
semiconductor structure
isolation
bit line
Prior art date
Application number
PCT/CN2021/101943
Other languages
English (en)
French (fr)
Inventor
于业笑
刘忠明
方嘉
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/465,744 priority Critical patent/US11984398B2/en
Publication of WO2022188295A1 publication Critical patent/WO2022188295A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor

Definitions

  • the present application relates to the technical field of semiconductor manufacturing, and in particular, to a semiconductor structure and a manufacturing method thereof.
  • DRAM Dynamic Random Access Memory
  • DRAM Dynamic Random Access Memory
  • the gate of the transistor is electrically connected to the word line
  • the source is electrically connected to the bit line
  • the drain is electrically connected to the capacitor.
  • the word line voltage on the word line can control the opening and closing of the transistor, so that the memory can be read through the bit line. Data information in the capacitor, or write data information into the capacitor.
  • bit line (BL) in the dense array area (Array) is very important.
  • the current process of forming the bit line is that after the mask pattern is formed, the pattern is transferred down step by step, and finally the bit line pattern is obtained.
  • the mask pattern is easily distorted in the process of downward transfer, resulting in poor morphology of the finally formed bit line structure, such as uneven sidewalls of the formed bit line,
  • the overall inclination and the like not only affect the performance of the semiconductor device finally formed, but even lead to the scrapping of the device in severe cases, thereby increasing the production cost of the semiconductor device.
  • one aspect of the present application provides a method for fabricating a semiconductor structure, comprising the following steps:
  • a substrate which includes a polysilicon layer, a first conductive layer, a first dielectric layer, a mask layer and a sacrificial layer formed in sequence; wherein the sacrificial layer has a plurality of first trenches distributed at intervals and the polysilicon layer is electrically connected to the active region in the substrate;
  • first insulating layer on the sacrificial layer, the first insulating layer covering the top surface of the sacrificial layer, the bottom and sidewalls of the first trench;
  • first pattern layer as a mask to remove part of the first dielectric layer, part of the first conductive layer and part of the polysilicon layer to form a bit line structure.
  • another aspect of the present application also provides a semiconductor structure, comprising:
  • the bit line structure is located on the surface of the substrate, and the bit line structure is formed by the method for fabricating a semiconductor structure according to any one of claims 1-14.
  • the protective layer only covers the first insulating layer on the top surface of the sacrificial layer, so that the first insulating layer at the bottom of the first trench is subsequently removed.
  • the insulating layer damage to the top surface of the sacrificial layer and the first insulating layer of the sidewalls of the first trench can be avoided, so that after the pattern in the sacrificial layer is transferred downward, the sidewalls can be flat.
  • the smooth and vertical bit line structure improves the uniformity and consistency of the bit line morphology in the semiconductor structure, and helps to improve the electrical properties of the semiconductor structure.
  • FIG. 1 is a flowchart of a method for fabricating a semiconductor structure in an embodiment of the present application
  • 2A-2N are schematic cross-sectional views of main processes in the process of fabricating a semiconductor structure in an embodiment of the present application.
  • FIG. 1 is a flowchart of the method for fabricating the semiconductor structure in the embodiment of the present application
  • FIGS. 2A-2N are the main processes in the process of fabricating the semiconductor structure in the embodiment of the present application. Schematic cross section. As shown in FIG. 1, FIG. 2A-FIG. 2N, the manufacturing method of the semiconductor structure provided by this embodiment includes the following steps:
  • Step S11 providing a substrate 20, which includes a polysilicon layer 221, a first conductive layer 223, a first dielectric layer 23, a mask layer 40 and a sacrificial layer 41 formed in sequence; wherein, the sacrificial layer 41 has A plurality of spaced first trenches 261 and the polysilicon layer 221 are electrically connected to the active region 42 in the substrate 20, as shown in FIG. 2A.
  • the substrate 20 may be a Si substrate, a Ge substrate, a SiGe substrate, SOI (Silicon On Insulator, silicon on insulator) or GOI (Germanium On Insulator, germanium on insulator) or the like.
  • the substrate 20 is an Si substrate as an example for description.
  • the substrate 20 has a plurality of active areas (Active Area, AA) 42 arranged in an array, and the adjacent active areas 42 are separated by a shallow trench isolation structure (Shallow Trench Isolation, STI) 203. Electrical isolation.
  • the shallow trench isolation structure 203 is formed by forming a groove inside the substrate 20 and filling the interior of the groove with an insulating material.
  • the material of the shallow trench isolation structure 203 may be, but not limited to, an oxide material.
  • This embodiment is described by taking the active region 42 including the first active region 201 and the second active region 202 as an example, and the first active region 201 and the second active region 202 are in the The substrates 20 are alternately arranged inside. In other embodiments, those skilled in the art can also make the active region 42 only include the first active region 201 or only the second active region 202 according to actual needs.
  • the substrate 20 further includes:
  • a metal barrier layer 222 is located between the polysilicon layer 221 and the first conductive layer 223 .
  • the active region and the shallow trench isolation structure 203 may be formed by performing steps such as etching, filling, and doping on the substrate 20 .
  • steps such as etching, filling, and doping on the substrate 20 .
  • polysilicon material, metal barrier material, first conductive material, first dielectric material, mask material and sacrificial material are sequentially deposited on the surface of the substrate 20 .
  • a second dielectric material eg, silicon nitride
  • the spacer layer 21 and part of the substrate 20 are etched, and after exposing the active region 42 inside the substrate 20, polysilicon material is deposited to form the polysilicon layer 221, which is connected to the polysilicon layer 221.
  • the active region 42 inside the substrate 20 directly contacts and covers the surface of the spacer layer 21 .
  • a metal barrier material such as TiN is deposited on the surface of the polysilicon layer 221 to form a metal barrier layer 222 .
  • a metal conductive material such as W is deposited on the surface of the metal barrier layer 222 to form a first conductive layer 223 .
  • the metal barrier layer 222 is not only used to prevent the metal particles in the first conductive layer 223 from diffusing into the polysilicon layer 221 , but also can increase the distance between the first conductive layer 223 and the polysilicon layer 221 . Adhesion.
  • the mask layer 40 includes two mask layers, the first mask layer 24 and the second mask layer 25 , and the sacrificial layer 41 includes the first sacrificial layer 26 and the second sacrificial layer 27 .
  • Two sacrificial layers are taken as an example for description.
  • a first mask material is deposited on the surface of the first conductive layer 223 to form the first mask layer 24 .
  • a second mask material is deposited on the surface of the first mask layer 24 to form a second mask layer 25 .
  • the material of the first mask layer 24 may be ACL (amorphous carbon), and the material of the second mask layer 25 may be SION.
  • a first sacrificial material is deposited on the surface of the second mask layer 25 to form the first sacrificial layer 26 .
  • Those skilled in the art may also deposit a second sacrificial material on the first sacrificial layer 26 before etching the first sacrificial layer 26 to form the first trench 261 to form a covering of the first sacrificial layer 26 of the second sacrificial layer 27 .
  • the second mask layer 25 as an etch stop layer, the second sacrificial layer 27 and the first sacrificial layer 26 are etched along the direction perpendicular to the substrate 20 to form the first sacrificial layer 27 Groove 261 .
  • the first trench 261 continuously penetrates the second sacrificial layer 27 and the first sacrificial layer 26 in a direction perpendicular to the substrate 20 .
  • the mask layer 40 only include one mask layer according to actual needs.
  • the sacrificial layer 41 only include one sacrificial layer according to actual needs.
  • the material of the first sacrificial layer 26 may be SOH (spin coating hard mask material), and the material of the second sacrificial layer 27 may be SION (silicon oxynitride).
  • the material of the first sacrificial layer 26 is silicon oxynitride, and the material of the second sacrificial layer 27 is different from that of the first sacrificial layer 26 .
  • Step S12 forming a first insulating layer 28 on the sacrificial layer 41, the first insulating layer 28 covering the top surface of the sacrificial layer 41, the bottom and sidewalls of the first trench 261, as shown in FIG. 2A shown.
  • the fabrication method of the semiconductor structure includes:
  • the method of forming the first insulating layer 28 is atomic layer deposition.
  • an atomic layer deposition process may be used to deposit a first insulating material to form the first insulating layer 28 .
  • the first insulating layer 28 covers the inner wall of the first trench 261 and the top surface of the second sacrificial layer 27 (that is, the surface of the second sacrificial layer 27 facing away from the substrate 20).
  • the atomic layer deposition method can precisely control the thickness of the first insulating layer 28 , and can control the thickness of the first insulating layer 28 to be the same at each position, so as to meet the process requirements.
  • the material of the first insulating layer 28 may be silicon dioxide. The process of forming silicon dioxide is simple, the cost is low, and the formed silicon dioxide is closely attached to the sidewall surface of the first trench 261, so that the morphology of the subsequently formed semiconductor structure meets the requirements.
  • step S13 a protective layer 29 is formed, and the protective layer 29 only covers the surface of the first insulating layer 28 located above the top surface of the sacrificial layer 41 , as shown in FIG. 2B .
  • the protective layer 29 covers and only covers the first insulating layer 28 on the top surface of the second sacrificial layer 27, located in the first trench
  • the first insulating layer 28 on the inner wall of the first trench 261 (including the bottom wall and the side wall of the first trench 261 ) is not covered with the protective layer 29 .
  • a high etching selectivity ratio should be provided between the protective layer 29 and the first insulating layer 28, for example, Under the same etching conditions, the etching selectivity ratio between the protective layer 29 and the first insulating layer 28 is greater than 10.
  • the fabrication method of the semiconductor structure includes:
  • a carbon material is deposited on the surface of the first insulating layer 28 above the top surface of the sacrificial layer 41 to form the protective layer 29 .
  • the step of forming the protective layer 29 includes:
  • the CH 4 is decomposed into a carbon layer through plasma reaction, and deposited on the surface of the first insulating layer 26 above the top surface of the sacrificial layer 41 .
  • a plasma-enhanced chemical vapor deposition process is used to form the carbon layer.
  • a carbon-based gas such as CH 4 is transferred into the reaction chamber, and the carbon-based gas such as CH 4 is under the conditions of low temperature, low pressure, and vacuum Under the alternating electric field, by setting a suitable radio frequency voltage, the carbon-based gas such as CH4 can be decomposed into a carbon layer by plasma reaction, and the reaction is as follows:
  • carbon-containing radical groups such as CH3, ⁇ CH2, ⁇ CH, ⁇ C ⁇ with relatively light molecular weight are only deposited on the first insulating layer on the top surface of the second sacrificial layer 27 28, so that the formed protective layer 29 covers and only covers the first insulating layer 28 located on the top surface of the second sacrificial layer 27, and there will be no CH3,
  • the entry of carbon-containing radical groups such as CH 2 , CH , and C that is, no carbon layer will be deposited inside the first trench 261 .
  • the low pressure mentioned in this embodiment refers to a pressure between 2 mTorr and 100 mTorr.
  • low temperature is meant a temperature between 20°C and 40°C.
  • the protective layer 29 covers the first insulating layer 28 on the entire top surface of the sacrificial layer 41 .
  • the first insulating layer 28 on the sidewall of the first trench 261 can be effectively protected.
  • Step S14 removing the first insulating layer 28 at the bottom of the first trench 261, as shown in FIG. 2C .
  • removing the first insulating layer 28 at the bottom of the first trench 261 includes:
  • the first insulating layer 28 located at the bottom of the first trench 261 is etched by an etching process.
  • the protective layer 29 covering only the first insulating layer 28 on the top surface of the second sacrificial layer 27 .
  • damage to the first insulating layer 28 on the sidewall of the first trench 261 can be avoided, so as to ensure that the bottom of the first trench 261 is etched completely.
  • the first insulating layer 28 on the sidewall of the first trench 261 is not damaged, and has a relatively flat, smooth and vertical morphology, which improves the subsequent downward transfer pattern. topography, thereby ensuring that the sidewall topography of the subsequently formed bit line is flat and smooth.
  • the thickness of the protective layer 29 is greater than the thickness of the first insulating layer 28 .
  • the thickness of the protective layer 29 is set is greater than the thickness of the first insulating layer 28, so that even if the protective layer 29 is partially etched, in the process of removing the first insulating layer 28 at the bottom of the first trench 261, all the The protective layer 29 is always covered on the first insulating layer 28 on the top surface of the second sacrificial layer 27 , so as to better protect the first insulating layer 28 on the sidewalls of the first trench 261 .
  • the fabrication method of the semiconductor structure includes:
  • the step of removing the first insulating layer 28 at the bottom of the first trench 261 is performed in-situ after the step of forming the protective layer 29 .
  • the step of forming the protective layer 29 and the step of removing the first insulating layer 28 located at the bottom of the first trench 261 are completed in the same machine, and it is not necessary to install the semiconductor structure in different machines.
  • the transfer between them simplifies the fabrication steps of the semiconductor structure, avoids possible contamination of the semiconductor structure during the transfer process, and ensures the yield of the semiconductor structure.
  • Step S15 removing the protective layer 29, part of the first insulating layer 28, the sacrificial layer 41 and part of the mask layer 40 to form a first pattern layer.
  • the step of forming the first pattern layer includes:
  • the protective layer 29 is removed by an etching process, as shown in FIG. 2D ;
  • the first insulating layer 28 above the top surface of the sacrificial layer 41 is removed by a planarization process, as shown in FIG. 2E ;
  • the sacrificial layer 41 and part of the mask layer 40 are removed by an etching process.
  • the remaining protective layer 29 is peeled off by an etching process to expose the top surface of the second sacrificial layer 27
  • the first insulating layer 28 is shown in FIG. 2D .
  • the second sacrificial layer 27 as a polishing stop layer, the insulating layer 28 located on the top surface of the second sacrificial layer 27 is removed by a planarization process such as chemical mechanical polishing, and the second sacrificial layer 27 is exposed.
  • the second sacrificial layer 27 and the first sacrificial layer 26 are etched away by a wet etching process or a dry etching process.
  • the location of the sacrificial layer 26 forms a second trench 262, as shown in FIG. 2F.
  • the first trenches 261 and the second trenches 262 are alternately arranged, and the first insulating layer 28 is used to isolate the adjacent first trenches 261.
  • a trench 261 and the second trench 262 .
  • the width of the first groove 261 and the width of the second groove 262 may be the same or different.
  • the width of the first groove 261 refers to the inner diameter of the first groove 261
  • the width of the second groove 262 refers to the inner diameter of the second groove 262 .
  • the second mask layer 25 is etched by using the first trench 261 and the second trench 262 as a mask pattern , extending the first trench 261 and the second trench 262 into the second mask layer 25, so that the first trench 261 and the second trench 262 are both perpendicular to the The direction of the substrate 20 penetrates the second mask layer 25 to form a structure as shown in FIG. 2G .
  • a fifth trench 241 corresponding to the first trench 261 is formed in the first mask layer 24
  • the sixth groove 242 corresponds to the second groove 262 .
  • the first pattern layer in this embodiment is the first mask layer 24 including the fifth trench 241 and the sixth trench 242 . Since the first trench 261 and the second trench 262 have flat and vertical sidewall topography, the fifth trench 241 and all the fifth trenches formed in the first mask layer 24 The sixth trench 242 also has a flat and vertical sidewall profile, which avoids the distortion problem of the first pattern layer.
  • Step S16 using the first pattern layer as a mask to remove part of the first dielectric layer 23, part of the first conductive layer 223, and part of the polysilicon layer 221 to form a bit line structure, as shown in FIG. 2K .
  • the first dielectric layer 23 is etched along the fifth trench 241 and the sixth trench 242 in the first mask layer 24 , and the first dielectric layer 23 is etched. forming a third trench 301 corresponding to the first trench 261 and a fourth trench 302 corresponding to the second trench 262, as shown in FIG. 2I;
  • the first conductive layer 223 and the metal barrier layer 222 are sequentially etched along the third trench 301 and the fourth trench 302 in the first dielectric layer 23 , and the third The trenches 301 and the fourth trenches 302 extend to the inside of the first conductive layer 223 and the metal barrier layer 222, that is, the third trenches 301 and the fourth trenches 302 are both perpendicular to the The direction of the substrate 20 runs through the first conductive layer 223 and the metal barrier layer 222, and after the first mask layer 24 is peeled off, the structure shown in FIG. 2J is obtained.
  • This embodiment is described by taking the step-by-step etching of the first conductive layer 223 , the metal barrier layer 222 and the polysilicon layer 221 as an example.
  • those skilled in the art can also select a suitable etchant according to the materials of the first conductive layer 223, the metal barrier layer 222 and the polysilicon layer 221, and etch the first conductive layer 221 in one step.
  • a conductive layer 223 , the metal barrier layer 222 and the polysilicon layer 221 so as to simplify the fabrication method of the semiconductor structure.
  • the active region 42 in the substrate 20 includes a first active region 201 and a second active region 202; the step of forming the bit line structure includes:
  • the first dielectric layer 23, the first conductive layer 223, the metal barrier layer 222 and the polysilicon layer 221 are etched along the first trench 261 and the second trench 262 to form the The third trench 301 corresponding to the first trench 261 and the fourth trench 302 corresponding to the second trench 262, the third trench 301 and the fourth trench 302
  • the dielectric layer 23, the first conductive layer 223, the metal barrier layer 222 and the polysilicon layer 221 are divided into a first bit line structure 32 and a second bit line structure 33, and the first bit line structure 32 is connected to the The first active region 201 is in contact, and the second bit line structure 33 is not in contact with the second active region 202 .
  • the sidewalls of the first bit line structure 32 and the second bit line structure 33 formed in this embodiment are flat and smooth, and the topography of the first bit line structure 32 and the second bit line structure 33 is vertical .
  • bit line structure after the step of forming the bit line structure, it further includes:
  • bit line isolation layer is formed, and the bit line isolation layer covers at least sidewalls of the bit line structure.
  • the step of forming the bit line isolation layer includes:
  • first isolation layer 311 at least covers the sidewall of the bit line structure, as shown in FIG. 2L;
  • the first isolation layer 311 , the second isolation layer 312 and the third isolation layer 313 constitute the bit line isolation layer.
  • a first isolation material is simultaneously deposited on the surface of the first bit line structure 32 and the second bit line structure 33 , the exposed surface of the substrate 20 , and the surface of the spacer layer 21 to form a first spacer layer 311 , as shown in FIG. 2L .
  • a second isolation material is deposited on the surface of the first isolation layer 311 to form a second isolation layer 312 completely covering the first isolation layer 311 , as shown in FIG. 2M .
  • a third isolation material is deposited on the surface of the second isolation layer 312 to form a third isolation layer 313 completely covering the second isolation layer 312 , as shown in FIG. 2N .
  • the bit line isolation layer is not only used to separate the adjacent bit line structures, but also can avoid oxidation of the sidewalls of the bit line structures and ensure the electrical performance of the bit line structures.
  • the method for fabricating the semiconductor structure further includes:
  • the density of the material forming the first isolation layer 311 is greater than the density of the material forming the second isolation layer 312 and the dielectric constant of the material forming the first isolation layer 311 is greater than that of the second isolation layer 312 The dielectric constant of the material.
  • the material for forming the first isolation layer 311 may be the same as the material for forming the third isolation layer 313, however, the material for forming the first isolation layer 311 or the material for forming the third isolation layer 313 should be the same as the material for forming the third isolation layer 313.
  • the materials of the second isolation layer 312 are different.
  • the material for forming the first isolation layer 311 may be a nitride material (such as silicon nitride)
  • the material for forming the second isolation layer 312 may be an oxide material (such as silicon oxide), and all the materials forming the N-O-N structure The bit line isolation layer.
  • the thickness relationship among the first isolation layer 311 , the second isolation layer 312 and the third isolation layer 313 can be determined according to the thickness of the first isolation layer 311 , the second isolation layer 312 and the The dielectric constant of the material of the third isolation layer 313 is determined. For example, when the material for forming the first isolation layer 311 and the material for forming the third isolation layer 313 are both silicon nitride, and the material for forming the second isolation layer 312 is silicon oxide, the first isolation layer 312 is formed of silicon oxide.
  • the thickness of the layer 311 is the same as the thickness of the third isolation layer 313 , and the thickness of the first isolation layer 311 is greater than that of the second isolation layer 312 .
  • this embodiment also provides a semiconductor structure.
  • the semiconductor structure provided in this embodiment may be formed by the fabrication method of the semiconductor structure shown in FIG. 1 and FIG. 2A- FIG. 2N .
  • FIG. 2N For a schematic diagram of the semiconductor structure provided in this embodiment, see FIG. 2N .
  • the semiconductor structure provided by this embodiment includes:
  • the bit line structure is located on the surface of the substrate 20 , and the bit line structure is formed by using the fabrication method of the semiconductor structure described in any one of the above.
  • the protective layer covers and only covers the first insulating layer located on the top surface of the sacrificial layer, so that the first insulating layer at the bottom of the first trench is subsequently removed.
  • damage to the top surface of the first sacrificial layer and the first insulating layer of the sidewalls of the first trench can be avoided, so that after the pattern in the sacrificial layer is transferred downward, sidewalls can be obtained.
  • the bit line with flat and smooth walls and vertical morphology improves the uniformity and consistency of the morphology of the bit line in the semiconductor structure, and helps to improve the electrical properties of the semiconductor structure.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Element Separation (AREA)

Abstract

本申请实施例涉及一种半导体结构及其制作方法。所述半导体结构的制作方法包括：提供衬底，所述衬底上包括依次形成的多晶硅层、第一导电层、第一介质层、掩膜层和牺牲层；其中，所述牺牲层具有多个间隔分布的第一沟槽；于所述牺牲层上形成第一绝缘层；形成保护层，所述保护层仅覆盖位于所述牺牲层顶面上方的所述第一绝缘层的表面；去除位于所述第一沟槽底部的所述第一绝缘层；去除所述保护层、部分所述第一绝缘层、所述牺牲层和部分所述掩膜层，形成第一图案层；以所述第一图案层为掩膜去除部分所述第一介质层、部分所述第一导电层、部分所述多晶硅层，以形成位线结构。本申请实施例能够得到侧壁平坦且形貌竖直的位线结构。

Description

半导体结构及其制作方法
相关申请引用说明
本申请要求于2021年3月8日递交的中国专利申请号202110250796.6、申请名为“半导体结构及其制作方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本申请涉及半导体制造技术领域，尤其涉及一种半导体结构及其制作方法。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)是计算机等电子设备中常用的半导体装置，其由多个存储单元构成，每个存储单元通常包括晶体管和电容器。所述晶体管的栅极与字线电连接、源极与位线电连接、漏极与电容器电连接，字线上的字线电压能够控制晶体管的开启和关闭，从而通过位线能够读取存储在电容器中的数据信息，或者将数据信息写入到电容器中。
随着半导体集成电路器件的特征尺寸不断缩小，对DRAM等半导体器件的制造工艺的要求越来越高，其中，对密集阵列区(Array)中位线(Bit Line，BL)的设计十分重要。当前形成位线的工艺是在形成掩膜图形之后，将图形一步步的向下转移，最终得到位线图形。但是，由于当前工艺的限制，掩膜图形在向下转移的过程中极易发生扭曲，从而导致最终形成的位线结构形貌较差，例如在形成的位线的侧壁凹凸不平、位线整体倾斜等，不仅对最终形成的半导体器件的性能造成影响，严重时甚至导致器件的报废，从而增加了半导体器件的生产成本。
因此，如何改善位线形貌，从而提高半导体结构的电性能，是当前亟待解决的技术问题。
发明内容
根据一些实施例，本申请一方面提供了一种半导体结构的制作方法，包括如下步骤：
提供衬底，所述衬底上包括依次形成的多晶硅层、第一导电层、第一介质 层、掩膜层和牺牲层；其中，所述牺牲层具有多个间隔分布的第一沟槽且所述多晶硅层与所述衬底内的有源区电连接；
于所述牺牲层上形成第一绝缘层，所述第一绝缘层覆盖所述牺牲层的顶面、所述第一沟槽的底部和侧壁；
形成保护层，所述保护层仅覆盖位于所述牺牲层顶面上方的所述第一绝缘层的表面；
去除位于所述第一沟槽底部的所述第一绝缘层；
去除所述保护层、部分所述第一绝缘层、所述牺牲层和部分所述掩膜层，形成第一图案层；
以所述第一图案层为掩膜去除部分所述第一介质层、部分所述第一导电层、部分所述多晶硅层，以形成位线结构。
根据一些实施例，本申请另一方面还提供了一种半导体结构，包括：
衬底；
位线结构，位于所述衬底表面，所述位线结构采用如权利要求1-14中任一项所述的半导体结构的制作方法形成。
本申请实施例提供的半导体结构及其制作方法，通过形成保护层，所述保护层仅覆盖位于牺牲层的顶面的第一绝缘层，使得后续在去除第一沟槽底部的所述第一绝缘层时，能够避免损伤所述牺牲层顶面以及所述第一沟槽侧壁的所述第一绝缘层，使得将所述牺牲层中的图形向下转移之后，能够得到侧壁平坦、光滑、且形貌竖直的位线结构，提高了半导体结构中位线形貌的均匀性、一致性，有助于改善半导体结构的电性能。
附图说明
附图1是本申请实施例中半导体结构的制作方法流程图；
附图2A-2N是本申请实施例中在制作半导体结构的过程中主要的工艺截面示意图。
具体实施方式
下面结合附图对本申请实施例提供的半导体结构及其制作方法做详细说明。
本实施例提供了一种半导体结构的制作方法，附图1是本申请实施例中半 导体结构的制作方法流程图，附图2A-2N是本申请实施例在制作半导体结构的过程中主要的工艺截面示意图。如图1、图2A-图2N所示，本实施例提供的半导体结构的制作方法，包括如下步骤：
步骤S11，提供衬底20，所述衬底上包括依次形成的多晶硅层221、第一导电层223、第一介质层23、掩膜层40和牺牲层41；其中，所述牺牲层41具有多个间隔分布的第一沟槽261且所述多晶硅层221与所述衬底20内的有源区42电连接，如图2A所示。
作为示例，所述衬底20可以为Si衬底、Ge衬底、SiGe衬底、SOI(Silicon On Insulator，绝缘体上硅)或者GOI(Germanium On Insulator，绝缘体上锗)等。本实施例中以所述衬底20为Si衬底为例进行说明。所述衬底20内具有呈阵列排布的多个有源区(Active Area，AA)42，相邻所述有源区42之间通过浅沟槽隔离结构(Shallow Trench Isolation，STI)203进行电性隔离。所述浅沟槽隔离结构203是通过在所述衬底20内部形成凹槽，并于所述凹槽内部填充绝缘材料形成。所述浅沟槽隔离结构203的材料可以是但不限于氧化物材料。
本实施例以所述有源区42包括第一有源区201和第二有源区202为例进行说明，且所述第一有源区201和所述第二有源区202在所述衬底20内部交替排布。在其他实施例中，本领域技术人员也可以根据实际需要使得所述有源区42仅包括第一有源区201或者仅包括第二有源区202。
可选的，所述衬底20上还包括：
金属阻挡层222，所述金属阻挡层222位于所述多晶硅层221和所述第一导电层223之间。
在本实施例中，提供所述衬底20之后，可以通过对所述衬底20进行刻蚀、填充、掺杂等步骤形成所述有源区和所述浅沟槽隔离结构203。之后，依次沉积多晶硅材料、金属阻挡材料、第一导电材料、第一介质材料、掩膜材料和牺牲材料于所述衬底20表面。作为示例，首先，沉积第二介质材料(例如氮化硅)于所述衬底20表面，形成间隔层21。接着，刻蚀所述间隔层21和部分所述衬底20，在暴露所述衬底20内部的所述有源区42之后沉积多晶硅材料，形成所述多晶硅层221，所述多晶硅层221与所述衬底20内部的所述有源区42 直接接触并覆盖所述间隔层21的表面。之后，沉积TiN等金属阻挡材料于所述多晶硅层221表面，形成金属阻挡层222。最后，沉积W等金属导电材料于所述金属阻挡层222表面，形成第一导电层223。所述金属阻挡层222不仅用于阻挡所述第一导电层223中的金属粒子向所述多晶硅层221中扩散，还能够增大所述第一导电层223与所述多晶硅层221之间的粘附性。
本实施例以所述掩膜层40包括第一掩膜层24和第二掩膜层25这两层掩膜层、且所述牺牲层41包括第一牺牲层26和第二牺牲层27这两层牺牲层为例进行说明。作为示例，在形成所述第一导电层223之后，沉积第一掩膜材料于所述第一导电层223表面，形成所述第一掩膜层24。之后，沉积第二掩膜材料于所述第一掩膜层24表面，形成第二掩膜层25。所述第一掩膜层24的材料可以是ACL(无定形碳)，所述第二掩膜层25的材料可以为SION。接着，在所述第二掩膜层25表面沉积第一牺牲材料，形成所述第一牺牲层26。本领域技术人员还可以在刻蚀所述第一牺牲层26形成所述第一沟槽261之前，在所述第一牺牲层26之上沉积第二牺牲材料，形成覆盖所述第一牺牲层26的第二牺牲层27。之后，以所述第二掩膜层25为刻蚀停止层，沿垂直于所述衬底20的方向刻蚀所述第二牺牲层27和所述第一牺牲层26，形成所述第一沟槽261。所述第一沟槽261沿垂直于所述衬底20的方向连续贯穿所述第二牺牲层27和所述第一牺牲层26。本领域技术人员也可以根据实际需要使得所述掩膜层40仅包括一层掩膜层。本领域技术人员也可以根据实际需要使得所述牺牲层41仅包括一层牺牲层。
所述第一牺牲层26的材料可以为SOH(旋涂硬掩模材料)，所述第二牺牲层27的材料可以为SION(氮氧化硅)。或者，所述第一牺牲层26的材料为氮氧化硅，所述第二牺牲层27的材料与所述第一牺牲层26不同。
步骤S12，于所述牺牲层41上形成第一绝缘层28，所述第一绝缘层28覆盖所述牺牲层41的顶面、所述第一沟槽261的底部和侧壁，如图2A所示。
可选的，所述半导体结构的制作方法，包括：
形成所述第一绝缘层28的方法为原子层沉积法。
作为示例，在形成所述第一沟槽261之后，可以采用原子层沉积工艺沉积第一绝缘材料，形成所述第一绝缘层28。所述第一绝缘层28覆盖于所述第一 沟槽261的内壁和所述第二牺牲层27的顶面(即所述第二牺牲层27背离所述衬底20的表面)。原子层沉积法相较于其他沉积方法能够精确控制所述第一绝缘层28的厚度，并可以控制第一绝缘层28在各个位置的厚度相同，从而达到工艺要求。所述第一绝缘层28的材料可以为二氧化硅。形成二氧化硅的工艺简单，成本较低，且形成的二氧化硅紧密贴附于所述第一沟槽261的侧壁表面，从而使后续形成的半导体结构的形貌符合要求。
步骤S13，形成保护层29，所述保护层29仅覆盖位于所述牺牲层41顶面上方的所述第一绝缘层28的表面，如图2B所示。
本领域技术人员可以根据实际需要选择合适的方式使得所述保护层29覆盖且仅覆盖于所述第二牺牲层27顶面的所述第一绝缘层28之上，位于所述第一沟槽261内壁(包括所述第一沟槽261的底壁和侧壁)上的所述第一绝缘层28未覆盖有所述保护层29。为了更好的保护所述第一沟槽261侧壁的所述第一绝缘层28，所述保护层29与所述第一绝缘层28之间应该具有较高的刻蚀选择比，例如，在相同的刻蚀条件下，所述保护层29与所述第一绝缘层28之间的刻蚀选择比大于10。
可选的，所述半导体结构的制作方法，包括：
沉积碳材料于所述牺牲层41顶面上方的所述第一绝缘层28的表面，形成所述保护层29。
可选的，所述形成保护层29的步骤包括：
使CH 4经过等离子体反应分解成碳层，并沉积于所述牺牲层41顶面上方的所述第一绝缘层26的表面。
本实施例采用等离子体增强化学气相沉积工艺形成所述碳层。作为示例，将如图2A所示的衬底20置于所述反应腔室之后，传输CH 4等碳基气体至所述反应腔室内，CH 4等碳基气体在低温、低压、真空的条件下经过交变电场，通过设置合适的射频电压，使得CH 4等碳基气体发生等离子体反应分解成碳层，反应如下所示：
CH 4→CH 3·+H
CH 4→CH 2·+2H
CH 4→CH·+3H
CH 4→C·+4H
在低温、低压条件下，相对分子质量较轻的CH3、·CH2、·CH、·C·等含碳自由基基团仅沉积在所述第二牺牲层27顶面的所述第一绝缘层28之上，从而使得形成的所述保护层29覆盖且仅覆盖位于所述第二牺牲层27的顶面的所述第一绝缘层28，所述第一沟槽261内部不会有CH3、·CH2、·CH、·C·等含碳自由基基团的进入，即所述第一沟槽261内部不会沉积碳层。
本实施例中所述的低压是指压力在2毫托到100毫托之间。所述低温是指温度在20℃到40℃之间。
本实施例是以CH 4作为反应气体生成碳层为例进行说明，本领域技术人员也可以根据实际需要选择其他的烃类气体来形成所述碳层，例如C 2H 6、C 2H 2等。
可选的，所述保护层29覆盖所述牺牲层41的整个顶面之上的所述第一绝缘层28。本实施例通过精确控制所述保护层29的覆盖位置，能够对所述第一沟槽261侧壁的所述第一绝缘层28进行有效的保护。
步骤S14，去除位于所述第一沟槽261底部的所述第一绝缘层28，如图2C所示。
可选的，去除位于所述第一沟槽261底部的所述第一绝缘层28包括：
以所述保护层29为掩膜，利用蚀刻工艺刻蚀位于所述第一沟槽261底部的所述第一绝缘层28。
作为示例，形成仅覆盖位于所述第二牺牲层27的顶面的所述第一绝缘层28之上的所述保护层29之后，再对所述第一沟槽261底部的所述第一绝缘层28进行刻蚀的过程中，可以避免对所述第一沟槽261侧壁的所述第一绝缘层28的损伤，从而能够确保刻蚀完所述第一沟槽261底部的所述第一绝缘层28之后，所述第一沟槽261侧壁的所述第一绝缘层28不受损伤，具有较为平坦、顺滑、竖直的形貌，改善了后续向下转移的图案的形貌，从而确保了后续形成的位线的侧壁形貌平坦、光滑。
可选的，所述保护层29的厚度大于所述第一绝缘层28的厚度。
作为示例，在刻蚀所述第一沟槽261底部的所述第一绝缘层28的过程中，会造成对部分所述保护层29的刻蚀，因此，将所述保护层29的厚度设置为大 于所述第一绝缘层28的厚度，使得即便是对所述保护层29进行了部分刻蚀，在所述第一沟槽261底部的所述第一绝缘层28去除的过程中，所述第二牺牲层27顶面的所述第一绝缘层28之上一直覆盖有所述保护层29，从而更好的保护所述第一沟槽261侧壁的所述第一绝缘层28。
可选的，所述半导体结构的制作方法，包括：
所述形成保护层29的步骤之后原位进行所述去除位于所述第一沟槽261底部的所述第一绝缘层28的步骤。
作为示例，所述形成保护层29的步骤与所述去除位于所述第一沟槽261底部的所述第一绝缘层28的步骤在同一机台内部完成，不仅无需将半导体结构在不同机台之间进行转移，简化了半导体结构的制作步骤，而且避免了转移过程中对半导体结构可能造成的污染，确保了半导体结构的良率。
步骤S15，去除所述保护层29、部分所述第一绝缘层28、所述牺牲层41和部分所述掩膜层40，形成第一图案层。
可选的，去除所述保护层29、部分所述第一绝缘层28、所述牺牲层41和部分所述掩膜层40，形成第一图案层的步骤包括：
利用刻蚀工艺去除所述保护层29，如图2D所示；
利用平坦化工艺去除所述牺牲层41顶面上方的所述第一绝缘层28，如图2E所示；
利用刻蚀工艺去除所述牺牲层41和部分所述掩膜层40。
作为示例，在打开所述第一沟槽261底部的所述第一绝缘层28之后，利用刻蚀工艺剥离残留的所述保护层29，暴露位于所述第二牺牲层27顶面之上的所述第一绝缘层28，如图2D所示。接着，以所述第二牺牲层27为研磨截止层，采用化学机械研磨工艺等平坦化工艺去除位于所述第二牺牲层27顶面之上的所述绝缘层28，暴露所述第二牺牲层27，如图2E所示。
在暴露所述第二牺牲层27之后，采用湿法刻蚀工艺或干法刻蚀工艺刻蚀掉所述第二牺牲层27和所述第一牺牲层26，于图2E中所述第一牺牲层26的位置形成第二沟槽262，如图2F所示。在沿平行于所述衬底20表面的方向上，所述第一沟槽261与所述第二沟槽262交替排布，且所述第一绝缘层28用于隔离相邻的所述第一沟槽261和所述第二沟槽262。所述第一沟槽261的宽度 与所述第二沟槽262的宽度可以相同，也可以不同。所述第一沟槽261的宽度是指所述第一沟槽261的内径，所述第二沟槽262的宽度是指所述第二沟槽262的内径。
在形成所述第一沟槽261和所述第二沟槽262之后，先以所述第一沟槽261和所述第二沟槽262为掩膜图形刻蚀所述第二掩膜层25，延伸所述第一沟槽261和所述第二沟槽262至所述第二掩膜层25中，即使得所述第一沟槽261和所述第二沟槽262均沿垂直于所述衬底20的方向贯穿所述第二掩膜层25，形成如图2G所示的结构。接着，继续向下转移图案，通过刻蚀部分的所述第一掩膜层24，于所述第一掩膜层24中形成与所述第一沟槽261对应的第五沟槽241、以及与所述第二沟槽262对应的第六沟槽242。剥离所述第一掩膜层24上方残留的所述第一绝缘层28和所述第二掩膜层25之后，得到如图2H所示结构。本实施例中所述的第一图案层即为包括所述第五沟槽241和第六沟槽242的所述第一掩膜层24。由于所述第一沟槽261和所述第二沟槽262具有平坦、竖直的侧壁形貌，因此，在所述第一掩膜层24中形成的所述第五沟槽241和所述第六沟槽242也具有平坦、竖直的侧壁形貌，避免了所述第一图案层的扭曲问题。
步骤S16，以所述第一图案层为掩膜去除部分所述第一介质层23、部分所述第一导电层223、部分所述多晶硅层221，以形成位线结构，如图2K所示。
作为示例，首先，沿所述第一掩膜层24中的所述第五沟槽241和所述第六沟槽242刻蚀所述第一介质层23，于所述第一介质层23中形成与所述第一沟槽261对应的第三沟槽301和与所述第二沟槽262对应的第四沟槽302，如图2I所示；
接着，沿所述第一介质层23中的所述第三沟槽301和所述第四沟槽302依次刻蚀所述第一导电层223和所述金属阻挡层222，将所述第三沟槽301和所述第四沟槽302延伸至所述第一导电层223和所述金属阻挡层222内部，即所述第三沟槽301和所述第四沟槽302均沿垂直于所述衬底20的方向贯穿所述第一导电层223和所述金属阻挡层222，在剥离所述第一掩膜层24之后，得到如图2J所示的结构。
之后，继续向下刻蚀所述多晶硅层221，延伸所述第三沟槽301和所述第 四沟槽302均至所述衬底20内部或者所述衬底20表面，形成如图2K所示的结构。
本实施例是以分步刻蚀所述第一导电层223、所述金属阻挡层222和所述多晶硅层221为例进行说明。在其他实施例中，本领域技术人员也可以根据所述第一导电层223、所述金属阻挡层222和所述多晶硅层221的材料，选择合适的刻蚀剂，通过一步刻蚀所述第一导电层223、所述金属阻挡层222和所述多晶硅层221，以简化半导体结构的制作方法。
可选的，所述衬底20内的有源区42包括第一有源区201和第二有源区202；形成位线结构的步骤包括：
沿所述第一沟槽261和所述第二沟槽262刻蚀所述第一介质层23、所述第一导电层223、所述金属阻挡层222和所述多晶硅层221，形成与所述第一沟槽261对应的第三沟槽301和与所述第二沟槽262对应的第四沟槽302，所述第三沟槽301和所述第四沟槽302将所述第一介质层23、所述第一导电层223、所述金属阻挡层222和所述多晶硅层221分割为第一位线结构32和第二位线结构33，所述第一位线结构32与所述第一有源区201接触，所述第二位线结构33与所述第二有源区202不接触。
本实施例形成的所述第一位线结构32和所述第二位线结构33的侧壁平坦光滑，且所述第一位线结构32和所述第二位线结构33形貌竖直。
可选的，在所述形成位线结构的步骤之后还包括：
形成位线隔离层，所述位线隔离层至少覆盖所述位线结构的侧壁。
可选的，所述形成位线隔离层的步骤包括：
形成第一隔离层311，所述第一隔离层311至少覆盖所述位线结构的侧壁，如图2L所示；
形成第二隔离层312，所述第二隔离层312覆盖所述第一隔离层311的表面，如图2M所示；
形成第三隔离层313，所述第三隔离层313覆盖所述第二隔离层312的表面，如图2N所示；
其中，所述第一隔离层311、所述第二隔离层312和所述第三隔离层313构成所述位线隔离层。
作为示例，在形成所述第一位线结构32和所述第二位线结构33之后，同时沉积第一隔离材料于所述第一位线结构32的表面、所述第二位线结构33的表面、暴露的所述衬底20表面、以及所述间隔层21表面，形成第一隔离层311，如图2L所示。接着，沉积第二隔离材料于所述第一隔离层311表面，形成完整覆盖所述第一隔离层311的第二隔离层312，如图2M所示。之后，沉积第三隔离材料于所述第二隔离层312表面，形成完整覆盖所述第二隔离层312的第三隔离层313，如图2N所示。所述位线隔离层不仅用于分隔相邻的所述位线结构，还能够避免所述位线结构的侧壁氧化，确保所述位线结构的电性能。
为了同时获得减小寄生电容和保护位线结构的功能，可选的，所述半导体结构的制作方法，还包括：
形成所述第一隔离层311的材料的致密度大于形成所述第二隔离层312的材料的致密度且形成所述第一隔离层311的材料的介电常数大于形成所述第二隔离层312的材料的介电常数。
形成所述第一隔离层311的材料可以与形成所述第三隔离层313的材料相同，但是，形成所述第一隔离层311的材料或者形成所述第三隔离层313的材料应与形成所述第二隔离层312的材料不同。例如，形成所述第一隔离层311的材料可以为氮化物材料(例如氮化硅)，形成所述第二隔离层312的材料可以为氧化物材料(例如氧化硅)，形成N-O-N结构的所述位线隔离层。
所述第一隔离层311、所述第二隔离层312和所述第三隔离层313之间的厚度关系，可以根据形成所述第一隔离层311、形成所述第二隔离层312和形成所述第三隔离层313的材料的介电常数确定。例如，当形成所述第一隔离层311的材料和形成所述第三隔离层313的材料均为氮化硅，形成所述第二隔离层312的材料为氧化硅时，所述第一隔离层311的厚度与所述第三隔离层313的厚度相同，且所述第一隔离层311的厚度大于所述第二隔离层312的厚度。
不仅如此，本实施例还提供了一种半导体结构。本实施例提供的所述半导体结构可以采用如图1、图2A-图2N所示的半导体结构的制作方法形成，本实施例提供的半导体结构的示意图可参见图2N。如图2A-图2N所示，本实施提供的半导体结构，包括：
衬底20；
位线结构，位于所述衬底20表面，所述位线结构采用上任一项所述的半导体结构的制作方法形成。
本实施例提供的半导体结构及其制作方法，通过形成保护层，所述保护层覆盖且仅覆盖位于牺牲层的顶面的第一绝缘层，使得后续在去除第一沟槽底部的所述第一绝缘层时，能够避免损伤所述第一牺牲层顶面以及所述第一沟槽侧壁的所述第一绝缘层，使得将所述牺牲层中的图形向下转移之后，能够得到侧壁平坦、光滑、且形貌竖直的位线，提高了半导体结构中位线形貌的均匀性、一致性，有助于改善半导体结构的电性能。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种半导体结构的制作方法，包括：
    提供衬底，所述衬底上包括依次形成的多晶硅层、第一导电层、第一介质层、掩膜层和牺牲层；其中，所述牺牲层具有多个间隔分布的第一沟槽且所述多晶硅层与所述衬底内的有源区电连接；
    于所述牺牲层上形成第一绝缘层，所述第一绝缘层覆盖所述牺牲层的顶面、所述第一沟槽的底部和侧壁；
    形成保护层，所述保护层仅覆盖位于所述牺牲层顶面上方的所述第一绝缘层的表面；
    去除位于所述第一沟槽底部的所述第一绝缘层；
    去除所述保护层、部分所述第一绝缘层、所述牺牲层和部分所述掩膜层，形成第一图案层；
    以所述第一图案层为掩膜去除部分所述第一介质层、部分所述第一导电层、部分所述多晶硅层，以形成位线结构。
  2. 根据权利1所述的半导体结构的制作方法，包括：
    沉积碳材料于所述牺牲层顶面上方的所述第一绝缘层的表面，形成所述保护层。
  3. 根据权利要求2所述的半导体结构的制作方法，其中，所述形成保护层的步骤包括：
    使CH 4经过等离子体反应分解成碳层，并沉积于所述牺牲层顶面上方的所述第一绝缘层的表面。
  4. 根据权利要求1所述的半导体结构的制作方法，包括：
    形成所述第一绝缘层的方法为原子层沉积法。
  5. 根据权利要求4所述的半导体结构的制作方法，包括：
    所述第一绝缘层的材料为二氧化硅。
  6. 根据权利要求5所述的半导体结构的制作方法，包括：
    所述形成保护层的步骤之后原位进行所述去除位于所述第一沟槽底部的所述第一绝缘层的步骤。
  7. 根据权利要求1所述的半导体结构的制作方法，其中，所述去除位于所述第一沟槽底部的所述第一绝缘层包括：
    以所述保护层为掩膜，利用蚀刻工艺刻蚀位于所述第一沟槽底部的所述第一绝缘层。
  8. 根据权利要求1所述的半导体结构的制作方法，其中，所述去除所述保护层、部分所述第一绝缘层、所述牺牲层和部分所述掩膜层，形成第一图案层的步骤包括：
    利用刻蚀工艺去除所述保护层；
    利用平坦化工艺去除所述牺牲层顶面上方的所述第一绝缘层；
    利用刻蚀工艺去除所述牺牲层和部分所述掩模层。
  9. 根据权利要求1所述的半导体结构的制作方法，其中，所述衬底上还包括：
    金属阻挡层，所述金属阻挡层位于所述多晶硅层和所述第一导电层之间。
  10. 根据权利要求1所述的半导体结构的制作方法，其中，在所述形成位线结构的步骤之后还包括：
    形成位线隔离层，所述位线隔离层至少覆盖所述位线结构的侧壁。
  11. 根据权利要求10所述的半导体结构的制作方法，其中，所述形成位线隔离层的步骤包括：
    形成第一隔离层，所述第一隔离层至少覆盖所述位线结构的侧壁；
    形成第二隔离层，所述第二隔离层覆盖所述第一隔离层的表面；
    形成第三隔离层，所述第三隔离层覆盖所述第二隔离层的表面；
    其中，所述第一隔离层、所述第二隔离层和所述第三隔离层构成所述位线隔离层。
  12. 根据权利要求11所述的半导体结构的制作方法，包括：
    形成所述第一隔离层的材料的致密度大于形成所述第二隔离层的材料的致密度且形成所述第一隔离层的材料的介电常数大于形成所述第二隔离层的材料的介电常数。
  13. 根据权利要求12所述的半导体结构的制作方法，包括：
    形成所述第一隔离层的材料与形成所述第三隔离层的材料相同
  14. 根据权利要求13所述的半导体结构的制作方法，包括：
    形成所述第一隔离层的材料为氮化硅，形成所述第二隔离层的材料为氧化硅。
  15. 一种半导体结构，包括：
    衬底；
    位线结构，位于所述衬底表面，所述位线结构采用如权利要求1-14中任一项所述的半导体结构的制作方法形成。
PCT/CN2021/101943 2021-03-08 2021-06-24 半导体结构及其制作方法 WO2022188295A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/465,744 US11984398B2 (en) 2021-03-08 2021-09-02 Semiconductor structure and manufacturing method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110250796.6 2021-03-08
CN202110250796.6A CN113035873B (zh) 2021-03-08 2021-03-08 半导体结构及其制作方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/465,744 Continuation US11984398B2 (en) 2021-03-08 2021-09-02 Semiconductor structure and manufacturing method thereof

Publications (1)

Publication Number Publication Date
WO2022188295A1 true WO2022188295A1 (zh) 2022-09-15

Family

ID=76466826

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/101943 WO2022188295A1 (zh) 2021-03-08 2021-06-24 半导体结构及其制作方法

Country Status (2)

Country Link
CN (1) CN113035873B (zh)
WO (1) WO2022188295A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117529103A (zh) * 2024-01-03 2024-02-06 长鑫新桥存储技术有限公司 半导体结构及其形成方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113675146B (zh) * 2021-08-11 2023-05-19 长鑫存储技术有限公司 半导体结构及其形成方法和存储器
CN113964088B (zh) * 2021-09-29 2024-05-17 长鑫存储技术有限公司 半导体结构的形成方法及半导体结构
CN116847649A (zh) * 2022-03-22 2023-10-03 长鑫存储技术有限公司 半导体结构及其制备方法、半导体器件
CN118073272A (zh) * 2022-11-11 2024-05-24 长鑫存储技术有限公司 存储器、半导体结构及其制备方法
US20240172414A1 (en) * 2022-11-18 2024-05-23 Nanya Technology Corporation Semiconductor structure and manufacturing method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110151632A1 (en) * 2009-12-21 2011-06-23 Hynix Semiconductor Inc. Method for forming semiconductor device
US20160203983A1 (en) * 2015-01-14 2016-07-14 Eun-Jung Kim Methods of manufacturing semiconductor devices
CN109950311A (zh) * 2017-12-20 2019-06-28 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN112447602A (zh) * 2019-08-30 2021-03-05 长鑫存储技术有限公司 半导体结构及其形成方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100704470B1 (ko) * 2004-07-29 2007-04-10 주식회사 하이닉스반도체 비결정성 탄소막을 희생 하드마스크로 이용하는반도체소자 제조 방법
KR20200085512A (ko) * 2019-01-07 2020-07-15 삼성전자주식회사 패턴 형성 방법 및 이를 이용한 반도체 장치의 제조 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110151632A1 (en) * 2009-12-21 2011-06-23 Hynix Semiconductor Inc. Method for forming semiconductor device
US20160203983A1 (en) * 2015-01-14 2016-07-14 Eun-Jung Kim Methods of manufacturing semiconductor devices
CN109950311A (zh) * 2017-12-20 2019-06-28 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN112447602A (zh) * 2019-08-30 2021-03-05 长鑫存储技术有限公司 半导体结构及其形成方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117529103A (zh) * 2024-01-03 2024-02-06 长鑫新桥存储技术有限公司 半导体结构及其形成方法
CN117529103B (zh) * 2024-01-03 2024-05-10 长鑫新桥存储技术有限公司 半导体结构及其形成方法

Also Published As

Publication number Publication date
CN113035873B (zh) 2022-04-12
CN113035873A (zh) 2021-06-25

Similar Documents

Publication Publication Date Title
WO2022188295A1 (zh) 半导体结构及其制作方法
KR100880310B1 (ko) 반도체 소자의 제조방법
KR101884002B1 (ko) 콘택 구조물 형성 방법
KR20200007609A (ko) 에어갭을 구비한 반도체장치 및 그 제조 방법
WO2021109504A1 (zh) 半导体存储器及其形成方法
US20140042548A1 (en) Dram structure with buried word lines and fabrication thereof, and ic structure and fabrication thereof
TWI763221B (zh) 具有埋藏字元線的半導體元件及其製備方法
TWI718859B (zh) 動態隨機存取記憶體裝置及其製造方法
CN110970351A (zh) 半导体存储器电容接点结构及制备方法
CN110061001B (zh) 半导体元件及其制作方法
WO2022028164A1 (zh) 半导体结构及其制作方法
CN109427651B (zh) 半导体结构及其形成方法
TW202018860A (zh) 半導體結構及其製造方法
WO2022142180A1 (zh) 半导体器件的制造方法及半导体器件
US11984398B2 (en) Semiconductor structure and manufacturing method thereof
WO2022088850A1 (zh) 半导体结构及半导体结构的制作方法
WO2024011767A1 (zh) 半导体结构及其形成方法
KR20130037519A (ko) 캐패시터 및 그 제조 방법
US11825644B2 (en) Semiconductor memory device
CN114068546B (zh) 半导体结构及其制作方法
WO2022142293A1 (zh) 半导体结构及半导体结构的制作方法
WO2021204289A1 (zh) 半导体结构及其形成方法
CN110277389B (zh) 具有导电线的半导体结构以及停止层的制作方法
CN117976619A (zh) 互联层中空气间隙的形成方法
CN114267674A (zh) 半导体结构及其形成方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21929765

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21929765

Country of ref document: EP

Kind code of ref document: A1