WO2024011767A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2024011767A1
WO2024011767A1 PCT/CN2022/124005 CN2022124005W WO2024011767A1 WO 2024011767 A1 WO2024011767 A1 WO 2024011767A1 CN 2022124005 W CN2022124005 W CN 2022124005W WO 2024011767 A1 WO2024011767 A1 WO 2024011767A1
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Prior art keywords
contact
forming
trench
layer
contact structure
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PCT/CN2022/124005
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English (en)
French (fr)
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金成镇
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长鑫存储技术有限公司
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Publication of WO2024011767A1 publication Critical patent/WO2024011767A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor structure and a method of forming the same.
  • the size of the semiconductor structure is further reduced, and the size of the gate structure inside the semiconductor structure is also further reduced.
  • the shrinkage of the gate structure causes the size and distance of the conductive contact structures located on opposite sides of the gate structure to continue to shrink, which not only causes parasitic interference between the conductive contact structures on opposite sides of the gate structure.
  • the capacitance is getting larger and larger, and it is easy to cause leakage between the conductive contact structures on opposite sides of the gate structure.
  • the parasitic capacitance effect between adjacent conductive elements can be reduced by forming an air gap structure, on the one hand, the position of the air gap structure is uncontrollable; on the other hand, the air gap structure is usually formed using a specific deposition process. This leads to randomness in whether the air gap structure is formed.
  • different spacings between conductive elements will lead to different sizes and positions of the air gap structures formed, which is not conducive to the standardized production of semiconductor devices.
  • the semiconductor structure and its formation method provided by some embodiments of the present disclosure are used to reduce the parasitic capacitance effect between the conductive contact structures on both sides of the gate structure, while improving the controllability of the position and size of the air gap structure, thereby improving the semiconductor structure. electrical properties of the structure.
  • the present disclosure provides a method for forming a semiconductor structure, including the following steps:
  • the substrate includes a substrate and a gate structure located above the substrate.
  • a first contact structure and a second contact structure are respectively provided on both sides of the gate structure, and a gate structure located on the first contact structure. a first trench between the second contact structure;
  • the sacrificial layer is removed to form a first air gap structure in the first trench.
  • specific steps of forming the substrate include:
  • the substrate Provide the substrate, and define a channel region in the substrate, and source regions and drain regions distributed on opposite sides of the channel region;
  • a first contact structure that penetrates the dielectric layer and is electrically connected to the source region and a second contact structure that is electrically connected to the drain region are formed, and the first contact structure is exposed to the A gap between a portion of the top surface of the dielectric layer and a portion of the second contact structure exposed to the top surface of the dielectric layer serves as the first trench.
  • the specific steps of forming a first contact structure that penetrates the dielectric layer and is electrically connected to the source region and a second contact structure that is electrically connected to the drain region include:
  • first contact structure and the second contact structure including a second contact pillar and a second contact layer located on the top surface of the second contact pillar are formed at the same time, and the width of the first contact layer is greater than that of the second contact layer.
  • the width of a contact pillar, the width of the second contact layer is greater than the width of the second contact pillar.
  • the specific steps of forming a sacrificial layer within the first trench and above the first contact structure and the second contact structure include:
  • the sacrificial layer filling the first trench and covering the surface of the isolation layer is formed.
  • the specific steps of forming a sacrificial layer within the first trench and above the first contact structure and the second contact structure include:
  • the isolation layer includes located above the first trench, And a recess connected to the first trench, the width of the recess is greater than the width of the area in the first trench that is not covered by the isolation layer;
  • top surface of the structure is flush with the top surface of the second contact structure, or the top surface of the remaining sacrificial layer is flush with the top surface of the remaining isolation layer above the first contact structure and the second contact structure.
  • the top surface is flush.
  • the specific steps of forming an insulating covering layer over the sacrificial layer include:
  • the insulating covering layer is formed to continuously cover the sacrificial layer and the isolation layer and extend over the first contact structure and the second contact structure.
  • the first contact structure and the second contact structure are arranged on opposite sides of the gate structure along a first direction, and the first direction is parallel to the top of the substrate.
  • the specific steps of forming the first air gap structure in the first trench include:
  • the second direction is parallel to the top surface of the substrate direction, and the first direction intersects the second direction.
  • the specific steps of forming a sacrificial layer in the first trench and above the first contact structure and the second contact structure include:
  • the sacrificial layer is formed to continuously cover the top surface of the first contact structure, the top surface of the second contact structure, and the inner wall of the first trench.
  • the specific steps of forming an insulating covering layer over the sacrificial layer include:
  • An insulating coating layer is formed covering the surface of the sacrificial layer and filling the first trench.
  • the first contact structure and the second contact structure are arranged on opposite sides of the gate structure along a first direction, and the first direction is parallel to the top of the substrate.
  • the specific steps of forming the first air gap structure in the first trench include:
  • a lateral etching process is used to remove the sacrificial layer along the first direction to form the first air gap structure.
  • the first air gap structure is continuously distributed above the first contact structure and the second contact structure. above the structure and within the first trench.
  • the substrate includes a plurality of gate structures spaced apart along the first direction, and each gate structure is provided with the gate structures on opposite sides along the first direction.
  • the first contact structure and the second contact structure for two adjacent gate structures, the first contact structure located on one side of the gate structure is different from the first contact structure located on the other side of the gate structure.
  • the sacrificial layer is removed, a first air gap structure is formed in the first trench, and a second air gap structure is formed in the second trench at the same time.
  • the width of the first trench along the first direction is smaller than the width of the second trench along the first direction
  • the width of the first air gap structure along the first direction is smaller than the width of the second trench along the first direction.
  • the width is smaller than the width of the second air gap structure along the first direction.
  • the filling capacity of the sacrificial layer is stronger than the filling capacity of the insulating cover layer.
  • the sacrificial layer is made of carbonaceous material or oxide material.
  • the present disclosure also provides a semiconductor structure formed by using the method for forming a semiconductor structure as described in any one of the above.
  • the semiconductor structure and its formation method provided by some embodiments of the present disclosure utilize the low dielectric constant of air to enhance the structure by forming a first air gap structure between the first contact structure and the second contact structure on opposite sides of the gate structure.
  • the electrical isolation effect between the first contact structure and the second contact structure thereby reduces the electrical isolation between the first contact structure and the second contact structure on opposite sides of the adjacent gate structure.
  • the capacitive parasitic effect reduces the probability of electrical breakdown between two adjacent conductive elements, and reduces the risk of electrical breakdown between the first contact structure and the second contact structure on opposite sides of the gate structure. The probability of electrical leakage occurring between the components is improved, thereby improving the electrical properties of the semiconductor structure.
  • some embodiments of the present disclosure fill a sacrificial layer between the first contact structure and the second contact structure on opposite sides of the gate structure and form an insulating covering at least above the sacrificial layer. After the layer is formed, the sacrificial layer is removed to form the first air gap structure.
  • the first air gap structure is formed between the first contact structure and the second contact structure, and the specific position and specific size of the first air gap structure can be defined through the sacrificial layer, which improves the controllability of the performance of the semiconductor structure.
  • the process is simple and does not require the use of complex filling processes or filling equipment, which greatly reduces the difficulty of manufacturing semiconductor structures.
  • FIG. 1 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure
  • 2A-2D are schematic cross-sectional views of main processes in the process of forming a semiconductor structure according to the first embodiment of the present disclosure
  • 3A-3D are schematic cross-sectional views of main processes in the process of forming a semiconductor structure according to the second embodiment of the present disclosure.
  • FIG. 1 is a flow chart of a method for forming a semiconductor structure in the specific embodiment of the present disclosure.
  • FIGS. 2A-2D are diagrams of the method for forming a semiconductor structure in the first embodiment of the present disclosure.
  • 3A-3D are main process cross-sectional schematic diagrams of the process of forming a semiconductor structure in the second embodiment of the present disclosure.
  • the method for forming the semiconductor structure includes the following steps:
  • Step S11 forming a substrate, which includes a substrate 20 and a gate structure 26 located above the substrate 20.
  • a first contact structure 25 and a second contact structure 23 are respectively provided on both sides of the gate structure 26.
  • a first trench 24 located between the first contact structure 25 and the second contact structure 23, as shown in Figures 2A and 3A;
  • Step S12 form a sacrificial layer 31 in the first trench 24 and above the first contact structure 25 and the second contact structure 23, as shown in Figure 2C and Figure 3B;
  • Step S13 form an insulating covering layer 32 on the sacrificial layer 31, as shown in Figure 2D and Figure 3C;
  • Step S14 remove the sacrificial layer 31 and form a first air gap structure 33 in the first trench 24 , as shown in FIG. 2D and FIG. 3D .
  • specific steps of forming the substrate include:
  • the substrate 20 Provide the substrate 20, and define a channel region in the substrate 20, as well as source regions and drain regions distributed on opposite sides of the channel region;
  • the first contact structure 25 and the second contact structure 23 that are electrically connected to the drain region are formed through the dielectric layer and are electrically connected to the source region respectively.
  • the first contact structure 25 is electrically connected to the drain region.
  • the gap between the portion of the contact structure 25 exposed to the top surface of the dielectric layer and the portion of the second contact structure 23 exposed to the top surface of the dielectric layer serves as the first trench 24, as shown in Figure 2A and Figure 3A shown.
  • the specific steps of forming a first contact structure 25 that penetrates the dielectric layer and is electrically connected to the source region and a second contact structure 23 that is electrically connected to the drain region are formed. include:
  • first contact structure 25 and the second contact structure 23 including a second contact pillar and a second contact layer located on the top surface of the second contact pillar are formed at the same time.
  • the width of the first contact layer is greater than the width of the first contact layer.
  • the width of the first contact pillar, and the width of the second contact layer are greater than the width of the second contact pillar.
  • the substrate 20 may be, but is not limited to, a silicon substrate.
  • the substrate 20 is a silicon substrate as an example for description.
  • the substrate 20 may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide or SOI.
  • the substrate 20 is used to support device structures thereon.
  • the substrate 20 includes a channel region, and the source region and the drain region distributed on opposite sides of the channel region along a first direction D1, where the first direction D1 is parallel to The direction of the top surface of the substrate 20 .
  • the gate structure includes a gate dielectric layer 261 covering the surface of the channel region, a gate contact layer 262 covering the surface of the gate dielectric layer 261, and a gate contact layer 262 covering the surface of the gate contact layer 262.
  • the material of the gate dielectric layer 261 may be, but is not limited to, an oxide material, such as silicon dioxide; the material of the gate contact layer 262 may be, but is not limited to, polysilicon; the material of the gate conductive layer 263 It can be but is not limited to metal tungsten.
  • a gate isolation layer 28 covering the gate structure 26 may also be formed.
  • the gate isolation layer 28 may have a single-layer structure or a multi-layer structure.
  • the gate isolation layer 28 includes a first sub-gate isolation layer covering the gate structure 26 , a second sub-gate isolation layer covering the first sub-gate isolation layer, and A third sub-gate isolation layer covering the second sub-gate isolation layer.
  • the material of the first sub-gate isolation layer and the third sub-gate isolation layer may both be a nitride material (such as silicon nitride), and the material of the second sub-gate isolation layer may be an oxide material. material (such as silica).
  • a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process may be used to form the dielectric layer on the surface of the substrate 20 to isolate the substrate 20 from subsequent formation on the dielectric layer.
  • conductive device structure may have a single-layer structure to simplify the manufacturing process of the semiconductor structure and reduce the manufacturing cost of the semiconductor structure.
  • the dielectric layer may be a multi-layer structure, which can better reduce the leakage between the conductive device structure above the substrate 20 and the substrate 20 and at the same time reduce the leakage of the semiconductor structure. Internal parasitic capacitance effects.
  • the dielectric layer includes a first dielectric layer 21 covering the top surface of the substrate 20 and a second dielectric layer 22 covering the top surface of the first dielectric layer 21 , and the first dielectric layer 21 covers the top surface of the substrate 20 .
  • the material of the dielectric layer 21 is different from the material of the second dielectric layer 22.
  • the material of the first dielectric layer 21 is an oxide material (such as silicon dioxide), and the material of the second dielectric layer 22 is nitrogen. compound materials (such as silicon nitride).
  • the top surface of the substrate 20 refers to the surface of the substrate 20 facing the dielectric layer
  • the top surface of the dielectric layer refers to the surface of the dielectric layer facing away from the substrate 20 surface.
  • the semiconductor structure formed in this specific embodiment may be, but is not limited to, DRAM.
  • a photolithography process may be used to etch the dielectric layer and portions downward in a direction perpendicular to the top surface of the substrate 20 (for example, the third direction D3 in FIGS. 2A and 3A ). of the substrate 20 to form the first contact hole that penetrates the dielectric layer along the third direction D3 and extends to the source region inside the substrate 20, and simultaneously forms the first contact hole along the third direction D3.
  • the third direction D3 penetrates the dielectric layer and extends to the second contact hole of the drain region inside the substrate 20 .
  • an atomic layer deposition process can be used to deposit conductive materials such as metal tungsten or TiN in the first contact hole, the second contact hole and the top surface of the dielectric layer to simultaneously form the first contact structure. 25 and the second contact structure 23 .
  • the first contact structure 25 includes the first contact post located in the first contact hole, and the first contact post directly electrically connected to the first contact post and located on the top surface of the dielectric layer.
  • Contact layer in order to increase the contact area between the first contact structure 25 and other conductive structures above it, the width of the first contact layer at least along the first direction D1 is larger than that along the first contact pillar. The width in the first direction D1.
  • the second contact structure 23 includes the second contact post located in the second contact hole, and the second contact post directly electrically connected to the second contact post and located on the top surface of the dielectric layer.
  • Contact layer in order to increase the contact area between the second contact structure 23 and other conductive structures above it, the width of the second contact layer at least along the first direction D1 is larger than that along the second contact pillar. The width in the first direction D1.
  • the specific steps of forming the sacrificial layer 31 within the first trench 24 and above the first contact structure 25 and the second contact structure 23 include:
  • Form an isolation layer 30 that continuously covers the inner wall of the first trench 24, the top surface of the first contact structure 25, and the top surface of the second contact structure 23, as shown in Figure 2B;
  • the sacrificial layer 31 is formed that fills the first trench 24 and covers the surface of the isolation layer 30 .
  • the specific steps of forming the sacrificial layer 31 within the first trench 24 and above the first contact structure 25 and the second contact structure 23 include:
  • An isolation layer 30 is formed that continuously covers the inner wall of the first trench 24 , the top surface of the first contact structure 25 , and the top surface of the second contact structure 23 .
  • the isolation layer 30 includes a A depression 29 above the trench 24 and connected to the first trench 24, the width of the depression 29 is greater than the width of the area of the first trench 24 not covered by the isolation layer 30;
  • the specific steps of forming the insulating covering layer 32 above the sacrificial layer 31 include:
  • the insulating covering layer 32 is formed to continuously cover the sacrificial layer 31 and the isolation layer 30 and extend above the first contact structure 25 and the second contact structure 23 .
  • the first contact structure 25 and the second contact structure 23 are arranged on opposite sides of the gate structure 26 along a first direction D1, and the first direction D1 is parallel In the direction of the top surface of the substrate 20; the specific steps of forming the first air gap structure 33 in the first trench 24 include:
  • the sacrificial layer 31 is removed along a second direction using a lateral etching process to form the first air gap structure 33 located in the first trench 24 .
  • the second direction is parallel to the substrate 20 The direction of the top surface, and the first direction D1 intersects the second direction.
  • first contact structure 25 and the second contact structure 23 After forming the first contact structure 25 and the second contact structure 23 , a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process may be used to first deposit nitride (such as silicon nitride), etc. Insulating dielectric material is provided on the inner wall of the first trench 24 (including the sidewalls of the first trench 24 and the bottom wall of the first trench 24), above the first contact structure 25 and on the The isolation layer 30 is formed above the second contact structure 23 .
  • nitride such as silicon nitride
  • the isolation layer 30 in order to increase the size of the subsequently formed first air gap structure 33 to further enhance the electrical isolation effect between the first contact structure 25 and the second contact structure 23, you can The position and thickness of the isolation layer 30 are adjusted by adjusting deposition parameters, or through a post-deposition etching process, or through a selective deposition process. On the one hand, the isolation layer 30 can protect the sidewalls of the first contact structure 25 and the second contact structure 23 and prevent subsequent deposition or etching processes from damaging the first contact structure 25 and the second contact structure 23 .
  • the contact structure 23 causes damage; on the other hand, by forming the isolation layer 30 covering the inner wall of the first trench 24, the size of the first trench 24 can be reduced (for example, the size of the first trench 24 along the width in the first direction D1) to prevent the insulating covering layer 32 from entering the formed first air gap structure 33 from the recess 29 with a larger width after the sacrificial layer 31 is subsequently removed, thereby This further improves the controllability of the formation of the first air gap structure 33 .
  • the position and size of the subsequently formed first air gap structure 33 can also be adjusted to meet different application requirements and improve the manufacturing flexibility of the semiconductor structure.
  • the formed isolation layer 30 includes the recess 29 located above the first trench 24 , and the recess 29 is connected to the first trench 24 , as shown in FIG. 2B shown.
  • the recess 29 is at least along the first direction D1. The width is greater than the width of the first trench 24 along the first direction D1 , where the first direction D1 is a direction parallel to the top surface of the substrate 20 .
  • the recess 29 has an inverted trapezoidal cross-section, and the width of the bottom surface of the recess 29 is equal to the width of the top surface of the first groove 24 , and the width of the top surface of the recess 29 is greater than the width of the top surface of the recess 29 .
  • the width of the bottom surface of the depression 29 is equal to the width of the top surface of the first groove 24 , and the width of the top surface of the recess 29 is greater than the width of the top surface of the recess 29 .
  • carbon, carbon-containing organic materials or oxide materials such as silicon dioxide
  • other materials with good fluidity are deposited or spin-coated into the first trench 24 , the recess 29 and the isolation layer. 30, forming the sacrificial layer 31 that fills the first trench 24 and the recess 29 and covers the top surface of the isolation layer 30, as shown in FIG. 2C. Since the sacrificial layer 31 needs to be formed in the first trench 24 with a smaller size in this embodiment, the material of the sacrificial layer 31 should have good fluidity or hole-filling ability (or filling ability).
  • Materials such as stronger carbon, carbon-containing organic materials or oxide materials (such as silicon dioxide) are used to ensure that the sacrificial layer 31 can fill the first trench 24 with a smaller size, thereby ensuring that all subsequently formed
  • the position of the first air gap structure 33 is described.
  • a planarization process such as chemical mechanical polishing can be used, and the isolation layer 30 and the sacrificial layer 31 above the first trench 24 and the first contact structure 25 can be removed by controlling polishing parameters such as polishing time. and part or all of the isolation layer 30 above the second contact structure 23 , so that the top surface of the remaining sacrificial layer 31 is in contact with the top surfaces of the first contact structure 25 and the second contact structure 23 Flush, or make the top surface of the remaining sacrificial layer 31 flush with the top surface of the remaining isolation layer 30 above the first contact structure 25 and the second contact structure 23, thereby ensuring the depression 29, and the sacrificial layer 31 in the recess 29 are completely removed, so as to avoid the subsequent removal of the sacrificial layer 31 in the first trench 24, the insulating covering layer 32 from having a larger width.
  • the recess 29 enters the formed first air gap structure 33 .
  • a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process may be used to deposit an insulating dielectric material such as nitride (such as silicon nitride) to form a layer that continuously covers the sacrificial layer 31 and the isolation layer 30 and extends to The insulating covering layer 32 above the first contact structure 25 and the second contact structure 23 .
  • an insulating dielectric material such as nitride (such as silicon nitride)
  • nitride such as silicon nitride
  • There should be a high etching selectivity ratio between the insulating covering layer 32 and the sacrificial layer 31 for example, the etching selectivity ratio between the insulating covering layer 32 and the sacrificial layer 31 is greater than 3), so as to facilitate The sacrificial layer 31 is subsequently removed through a selective etching process.
  • a lateral wet etching process can be used to remove the sacrificial layer 31 along the second direction to form the first air gap structure 33 located in the first trench 24, as shown in FIG. 2D.
  • the intersection described in this specific embodiment may be a vertical intersection (ie, an orthogonal intersection) or an oblique intersection.
  • the sacrificial layer 31 is first formed to define the position of the first air gap structure 33 to be formed subsequently, and then the sacrificial layer 31 is removed through an etching process to form the first air gap structure 33. Therefore, the first air gap structure 33 can be formed at a predetermined position, which ensures that the first air gap structure 33 can be formed and at the same time improves the controllability of the position of the first air gap structure 33 .
  • the first air gap structure 33 of this specific embodiment is located between the first contact structure 25 and the second contact structure 23, and the first air gap structure 33 does not expose the second contact structure 25.
  • a contact structure 25 and the second contact structure 23 can improve the electrical isolation effect between the first contact structure 25 and the second contact structure 23 and reduce the parasitic capacitance effect.
  • the first contact structure 25 and the second contact structure 23 are protected.
  • by adjusting the thickness and position of the isolation layer 30 the position and size of the first air gap structure 33 can also be adjusted, which greatly improves the flexibility of manufacturing the semiconductor structure.
  • the specific steps of forming the sacrificial layer 31 in the first trench 24 and above the first contact structure 25 and the second contact structure 23 include:
  • the sacrificial layer 31 is formed to continuously cover the top surface of the first contact structure 25 , the top surface of the second contact structure 23 , and the inner wall of the first trench 24 , as shown in FIG. 3B .
  • the specific steps of forming the insulating covering layer 32 above the sacrificial layer 31 include:
  • An insulating covering layer 32 is formed covering the surface of the sacrificial layer 31 and filling the first trench 24, as shown in FIG. 3C.
  • first contact structure 25 and the second contact structure 23 are arranged on opposite sides of the gate structure 26 along a first direction D1, and the first direction D1 is parallel to the gate structure 26.
  • the direction of the top surface of the substrate 20; the specific steps of forming the first air gap structure 33 in the first trench 24 include:
  • the sacrificial layer 31 is removed along the first direction D1 using a lateral etching process to form the first air gap structure 33.
  • the first air gap structure 33 is continuously distributed above the first contact structure 25. Above the second contact structure 23 and within the first trench 24, as shown in FIG. 3D.
  • a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process may be used to deposit an insulating layer such as an oxide (such as silicon dioxide).
  • the dielectric material is applied to the inner wall of the first trench 24 , the top surface of the first contact structure 25 and the top surface of the second contact structure 23 to form a continuous covering of the top surface of the first contact structure 25 and all the other surfaces.
  • the top surface of the second contact structure 23 and the sacrificial layer 31 on the inner wall of the first trench 24 are as shown in FIG. 3B .
  • an insulating dielectric material such as nitride (such as silicon nitride) is deposited on the surface of the sacrificial layer 31 and in the first trench 24 to form a layer that covers the surface of the sacrificial layer 31 and fills the first trench 24 .
  • the insulating covering layer 32 of the trench 24 is as shown in FIG. 3C.
  • There should be a high etching selectivity ratio between the insulating covering layer 32 and the sacrificial layer 31 for example, the etching selectivity ratio between the insulating covering layer 32 and the sacrificial layer 31 is greater than 3), so as to facilitate The sacrificial layer 31 is subsequently removed through a selective etching process.
  • a lateral wet etching process may be used to remove all of the sacrificial layer 31 along the first direction D1 to form the first air gap structure 33 extending along the first direction D1, and the first air gap structure 33 may be formed along the first direction D1.
  • An air gap structure 33 is continuously distributed above the first contact structure 25 , above the second contact structure 23 , and in the first trench 24 .
  • the insulating covering layer 32 covers the top surface of the dielectric layer along the second direction or is connected to other supporting structures along the second direction.
  • the sacrificial layer 31 is first formed to define the position of the first air gap structure 33 to be formed subsequently, and then the sacrificial layer 31 is removed through an etching process to form the first air gap structure 338. Therefore, the first air gap structure 33 can be formed at a predetermined position, which ensures that the first air gap structure 33 can be formed and at the same time improves the controllability of the position of the first air gap structure 33 .
  • the thickness and position of the sacrificial layer 31 by adjusting the thickness and position of the sacrificial layer 31, the size and position of the first air gap structure 33 can be adjusted, thereby improving the flexibility of the semiconductor structure manufacturing process to meet different applications. need.
  • the first air gap structure 33 in this embodiment is continuously distributed above the first contact structure 25, above the second contact structure 23, and in the first trench 24.
  • it can The size of the first air gap structure 33 between the first contact structure 25 and the second contact structure 23 on both sides of the gate structure 26 is increased, thereby further strengthening the first contact structure 25 and the second contact structure 23 .
  • the electrical isolation effect between the second contact structures 23 can also be enhanced; on the other hand, it can also enhance the first contact structure 25 and the second contact structure 23 and other conductive structures subsequently formed above the insulating covering layer 32 Electrical isolation effect between device structures.
  • the substrate 20 includes a plurality of gate structures 26 spaced apart along the first direction D1, and each gate structure 26 is arranged along opposite sides of the first direction D1.
  • the first contact structure 25 and the second contact structure 23 are respectively provided.
  • the first contact structure located on one side of one of the gate structures 26 There is a second trench 27 between 25 and the second contact structure 23 located on one side of the other gate structure 26, and the first direction D1 is a direction parallel to the top surface of the substrate 20;
  • the method of forming the semiconductor structure further includes:
  • a sacrificial layer 31 is formed within the first trench 24, within the second trench 27, and above each first contact structure 25 and above each second contact structure 23;
  • the sacrificial layer 31 is removed, a first air gap structure 33 is formed in the first trench 24 , and a second air gap structure 34 is formed in the second trench 27 at the same time.
  • the width of the first trench 24 along the first direction D1 is smaller than the width of the second trench 27 along the first direction D1
  • the first air gap structure 33 is The width of the first direction D1 is smaller than the width of the second air gap structure 34 along the first direction D1.
  • the semiconductor structure may include a plurality of transistor structures spaced apart along the first direction D1 , each of the transistor structures including the gate structure 26 , and The first contact structure 25 and the second contact structure 23 are distributed on opposite sides of the gate structure 26 along the first direction D1.
  • the first contact structure 25 in one of the transistor structures is adjacent to the second contact structure 23 in the other transistor structure, that is, for any Two adjacent gate structures 26, the first contact structure 25 located on one side of one gate structure 26 and the second contact structure located on one side of the other gate structure 26 23 adjacent.
  • the first contact structure 25 and the second contact structure inside one of the transistor structures can be While the first air gap structure 33 is formed between two adjacent transistor structures, the second air gap structure is also formed between two adjacent transistor structures, thereby reducing the gap between two adjacent transistor structures. parasitic capacitance effects and reduce leakage between two adjacent transistor structures.
  • the second air gap structure 34 is at least The width along the first direction D1 is greater than the width of the first air gap structure 33 along the first direction D1, which can better avoid signal crosstalk between two adjacent transistor structures.
  • the filling capacity of the sacrificial layer 31 is stronger than the filling capacity of the insulating covering layer 32 .
  • the material of the sacrificial layer 31 is a carbon-containing material or an oxide material. In other embodiments, the sacrificial layer 31 may also be made of carbon.
  • This specific embodiment also provides a semiconductor structure, which is formed by using the method for forming a semiconductor structure described in any one of the above.
  • the schematic diagram of the semiconductor structure formed in this specific embodiment can be seen in Figure 2D or Figure 3D.
  • the semiconductor structure described in this specific embodiment may be, but is not limited to, DRAM.
  • the semiconductor structure and its formation method provided by some embodiments of this specific embodiment utilize the low dielectric constant of air by forming a first air gap structure between the first contact structure and the second contact structure on opposite sides of the gate structure. to enhance the electrical isolation effect between the first contact structure and the second contact structure, thereby reducing the gap between the first contact structure and the second contact structure on opposite sides of the adjacent gate structure.
  • the capacitance parasitic effect between two adjacent conductive elements is reduced, and the probability of electrical breakdown between the two adjacent conductive elements is reduced, and the first contact structure and the second contact on opposite sides of the gate structure are reduced.
  • the probability of leakage between structures improves the electrical properties of semiconductor structures.
  • some embodiments of the present disclosure fill a sacrificial layer between the first contact structure and the second contact structure on opposite sides of the gate structure and form an insulating covering at least above the sacrificial layer. After the layer is formed, the sacrificial layer is removed to form the first air gap structure.
  • the first air gap structure is formed between the first contact structure and the second contact structure, and the specific position and specific size of the first air gap structure can be defined through the sacrificial layer, which improves the controllability of the performance of the semiconductor structure.
  • the process is simple and does not require the use of complex filling processes or filling equipment, which greatly reduces the difficulty of manufacturing semiconductor structures.

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Abstract

本公开涉及一种半导体结构及其形成方法。所述半导体结构的形成方法包括如下步骤：形成基底，所述基底包括衬底、以及位于所述衬底上方的栅极结构，所述栅极结构两侧分别设置有第一接触结构和第二接触结构、以及位于所述第一接触结构和所述第二接触结构之间的第一沟槽；在所述第一沟槽内、以及所述第一接触结构和所述第二接触结构上方形成牺牲层；在所述牺牲层上方形成绝缘覆盖层；去除所述牺牲层，在所述第一沟槽内形成第一气隙结构。本公开减少了位于栅极结构两侧的第一接触结构与第二接触结构之间的寄生电容效应，且提高了第一气隙结构形成的可控性。

Description

半导体结构及其形成方法
相关申请引用说明
本申请要求于2022年07月13日递交的中国专利申请号202210820735.3、申请名为“半导体结构及其形成方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本公开涉及半导体制造技术领域，尤其涉及一种半导体结构及其形成方法。
背景技术
随着集成电路技术的不断发展，半导体结构的尺寸进一步微缩，半导体结构内部的栅极结构的尺寸也随着进一步微缩。所述栅极结构的微缩导致位于所述栅极结构相对两侧的导电接触结构的尺寸、以及距离不断的缩小，这不仅会使得所述栅极结构相对两侧的导电接触结构之间的寄生电容越来越大，而且还容易造成所述栅极结构相对两侧的所述导电接触结构之间的漏电。虽然通过形成气隙结构可以降低相邻导电元件之间的寄生电容效应，但是，一方面，气隙结构的位置具有不可控性；另一方面，气隙结构通常是采用特定的沉积工艺形成，这就导致气隙结构是否形成具有随机性。另外，导电元件之间的间距不同，会导致形成的气隙结构的大小、位置等不同，不利于半导体器件的标准化生产。
因此，如何减小栅极结构两侧的导电接触结构之间的寄生电容效应，同时提高气隙结构位置和尺寸的可控性，从而改善半导体结构的电性能，是当前亟待解决的技术问题。
发明内容
本公开一些实施例提供的半导体结构及其形成方法，用于减小栅极结构两侧的导电接触结构之间的寄生电容效应，同时提高气隙结构位置和尺寸的可控性，从而改善半导体结构的电性能。
根据一些实施例，本公开提供了一种半导体结构的形成方法，包括如下步骤：
形成基底，所述基底包括衬底、以及位于所述衬底上方的栅极结构，所述栅极结构两侧分别设置有第一接触结构和第二接触结构、以及位于所述第一接触结构和所述第二接触结构之间的第一沟槽；
在所述第一沟槽内、以及所述第一接触结构和所述第二接触结构上方形成牺牲层；
在所述牺牲层上方形成绝缘覆盖层；
去除所述牺牲层，在所述第一沟槽内形成第一气隙结构。
在一些实施例中，形成基底的具体步骤包括：
提供所述衬底，并于所述衬底中定义沟道区、以及分布于所述沟道区相对两侧的源极区和漏极区；
于所述衬底的所述沟道区上方形成所述栅极结构；
形成覆盖所述衬底和所述栅极结构的介质层；
形成均贯穿所述介质层、并分别与所述源极区电接触连接的第一接触结构和与所述漏极区电接触连接的第二接触结构，所述第一接触结构暴露于所述介质层顶面的部分与所述第二接触结构暴露于所述介质层顶面的部分之间的间隙作为所述第一沟槽。
在一些实施例中，形成均贯穿所述介质层、并分别与所述源极区电接触连接的第一接触结构和与所述漏极区电接触连接的第二接触结构的具体步骤包括：
刻蚀所述介质层，形成贯穿所述介质层并暴露所述源极区的第一接触孔、并同时形成贯穿所述介质层并暴露所述漏极区的第二接触孔；
沉积导电材料于所述第一接触孔内、所述第二接触孔内和部分所述介质层的表面，形成包括第一接触柱和位于所述第一接触柱顶面的第一接触层的所述第一接触结构、并同时形成包括第二接触柱和位于所述第二接触柱顶面的第二接触层的所述第二接触结构，所述第一接触层的宽度大于所述第一接触柱的宽度，所述第二接触层的宽度大于所述第二接触柱的宽度。
在一些实施例中，在所述第一沟槽内、以及所述第一接触结构和所述第二接触结构上方形成牺牲层的具体步骤包括：
形成连续覆盖所述第一沟槽的内壁、所述第一接触结构的顶面、以及所述第二接触结构的顶面的隔离层；
形成填充满所述第一沟槽、且覆盖所述隔离层表面的所述牺牲层。
在一些实施例中，在所述第一沟槽内、以及所述第一接触结构和所述第二接触结构上方形成牺牲层的具体步骤包括：
形成连续覆盖所述第一沟槽的内壁、所述第一接触结构的顶面、以及所述第二接触结构的顶面的隔离层，所述隔离层包括位于所述第一沟槽上方、且与所述第一沟槽连通的凹陷，所述凹陷的宽度大于所述第一沟槽内未被所述隔离层覆盖的区域的宽度；
形成填充满所述第一沟槽和所述凹陷、并覆盖所述隔离层的顶面的所述牺牲层；
去除所述第一接触结构上方、所述第二接触结构上方和所述第一沟槽上方的所述隔离层和所述牺牲层，残留的所述牺牲层的顶面与所述第一接触结构的顶面和所述第二接触结 构的顶面平齐，或者，残留的所述牺牲层的顶面与所述第一接触结构和所述第二接触结构上方残留的所述隔离层的顶面平齐。
在一些实施例中，在所述牺牲层上方形成绝缘覆盖层的具体步骤包括：
形成连续覆盖所述牺牲层和所述隔离层、并延伸至第一接触结构和所述第二接触结构上方的所述绝缘覆盖层。
在一些实施例中，所述第一接触结构和所述第二接触结构沿第一方向排布于所述栅极结构的相对两侧，所述第一方向为平行于所述衬底的顶面的方向；在所述第一沟槽内形成第一气隙结构的具体步骤包括：
采用侧向刻蚀工艺沿第二方向去除所述牺牲层，形成位于所述第一沟槽内的所述第一气隙结构，所述第二方向为平行于所述衬底的顶面的方向，且所述第一方向与所述第二方向相交。
在一些实施例中于，在所述第一沟槽内、以及所述第一接触结构和所述第二接触结构上方形成牺牲层的具体步骤包括：
形成连续覆盖所述第一接触结构的顶面、所述第二接触结构的顶面、以及所述第一沟槽的内壁的所述牺牲层。
在一些实施例中，在所述牺牲层上方形成绝缘覆盖层的具体步骤包括：
形成覆盖于所述牺牲层表面、并填充满所述第一沟槽的绝缘覆盖层。
在一些实施例中，所述第一接触结构和所述第二接触结构沿第一方向排布于所述栅极结构的相对两侧，所述第一方向为平行于所述衬底的顶面的方向；在所述第一沟槽内形成第一气隙结构的具体步骤包括：
采用侧向刻蚀工艺沿所述第一方向去除所述牺牲层，形成所述第一气隙结构，所述第一气隙结构连续分布于所述第一接触结构上方、所述第二接触结构上方、以及所述第一沟槽内。
在一些实施例中，所述衬底上包括沿第一方向间隔排布的多个所述栅极结构，每个所述栅极结构沿所述第一方向的相对两侧分别设置有所述第一接触结构和所述第二接触结构，对于相邻的两个所述栅极结构，位于其中一个所述栅极结构一侧的所述第一接触结构与位于另一个所述栅极结构一侧的所述第二接触结构之间具有第二沟槽，所述第一方向为平行于所述衬底的顶面的方向；所述半导体结构的形成方法还包括：
在所述第一沟槽内、所述第二沟槽内、以及每个所述第一接触结构上方和每个所述第 二接触结构上方形成牺牲层；
在所述牺牲层上方形成绝缘覆盖层；
去除所述牺牲层，在所述第一沟槽内形成第一气隙结构、并同时在所述第二沟槽内形成第二气隙结构。
在一些实施例中，所述第一沟槽沿所述第一方向的宽度小于所述第二沟槽沿所述第一方向的宽度，所述第一气隙结构沿所述第一方向的宽度小于所述第二气隙结构沿所述第一方向的宽度。
在一些实施例中，所述牺牲层的填充能力强于所述绝缘覆盖层的填充能力。
在一些实施例中，所述牺牲层的材料为含碳材料或者氧化物材料。
根据另一些实施例，本公开还提供了一种半导体结构，采用如上任一项所述的半导体结构的形成方法形成。
本公开一些实施例提供的半导体结构及其形成方法，通过在栅极结构相对两侧的第一接触结构和第二接触结构之间形成第一气隙结构，利用空气的低介电常数来增强所述第一接触结构和所述第二接触结构之间的电性隔离效果，从而降低相邻所述栅极结构相对两侧的所述第一接触结构和所述第二接触结构之间的电容寄生效应，减少了相邻两个所述导电元件之间发生电性击穿的概率，并降低了所述栅极结构相对两侧的所述第一接触结构与所述第二接触结构之间发生漏电的概率，实现了对半导体结构电性能的改善。而且，本公开的一些实施例是在所述栅极结构相对两侧的所述第一接触结构和所述第二接触结构之间填充牺牲层、且形成至少位于所述牺牲层上方的绝缘覆盖层之后，再去除所述牺牲层来形成所述第一气隙结构，一方面，即便是半导体结构的尺寸不断微缩，也能确保在所述栅极结构相对两侧的所述第一接触结构和所述第二接触结构之间形成所述第一气隙结构，且能够通过所述牺牲层限定所述第一气隙结构的具体位置和具体尺寸，提高了所述半导体结构性能的可控性；另一方面，工艺简单，无需使用复杂的填充工艺或者填充设备，极大的降低了半导体结构的制造难度。
附图说明
附图1是本公开具体实施方式中半导体结构的形成方法流程图；
附图2A-2D是本公开具体实施方式第一实施例在形成半导体结构的过程中主要的工艺截面示意图；
附图3A-3D是本公开具体实施方式第二实施例在形成半导体结构的过程中主要的工艺 截面示意图。
具体实施方式
下面结合附图对本公开提供的半导体结构及其形成方法的具体实施方式做详细说明。
本具体实施方式提供了一种半导体结构的形成方法，附图1是本公开具体实施方式中半导体结构的形成方法流程图，附图2A-2D是本公开具体实施方式第一实施例在形成半导体结构的过程中主要的工艺截面示意图，附图3A-3D是本公开具体实施方式第二实施例在形成半导体结构的过程中主要的工艺截面示意图。如图1、图2A-图2D和图3A-图3D所示，所述半导体结构的形成方法，包括如下步骤：
步骤S11，形成基底，所述基底包括衬底20、以及位于所述衬底20上方的栅极结构26，所述栅结构26两侧分别设置有第一接触结构25和第二接触结构23、以及位于所述第一接触结构25和所述第二接触结构23之间的第一沟槽24，如图2A和图3A；
步骤S12，在所述第一沟槽24内、以及所述第一接触结构25和所述第二接触结构23上方形成牺牲层31，如图2C和图3B所示；
步骤S13，在所述牺牲层31上方形成绝缘覆盖层32，如图2D和图3C所示；
步骤S14，去除所述牺牲层31，在所述第一沟槽24内形成第一气隙结构33，如图2D和图3D所示。
在一些实施例中，形成基底的具体步骤包括：
提供所述衬底20，并于所述衬底20中定义沟道区、以及分布于所述沟道区相对两侧的源极区和漏极区；
于所述衬底20的所述沟道区上方形成所述栅极结构26；
形成覆盖所述衬底20和所述栅极结构26的介质层；
形成均贯穿所述介质层、并分别与所述源极区电接触连接的所述第一接触结构25和与所述漏极区电接触连接的所述第二接触结构23，所述第一接触结构25暴露于所述介质层顶面的部分与所述第二接触结构23暴露于所述介质层顶面的部分之间的间隙作为所述第一沟槽24，如图2A和图3A所示。
在一些实施例中，形成均贯穿所述介质层、并分别与所述源极区电接触连接的第一接触结构25和与所述漏极区电接触连接的第二接触结构23的具体步骤包括：
刻蚀所述介质层，形成贯穿所述介质层并暴露所述源极区的第一接触孔、并同时形成贯穿所述介质层并暴露所述漏极区的第二接触孔；
沉积导电材料于所述第一接触孔内、所述第二接触孔内和部分所述介质层的表面，形成包括第一接触柱和位于所述第一接触柱顶面的第一接触层的所述第一接触结构25、并同时形成包括第二接触柱和位于所述第二接触柱顶面的第二接触层的所述第二接触结构23，所述第一接触层的宽度大于所述第一接触柱的宽度，所述第二接触层的宽度大于所述第二接触柱的宽度。
具体来说，所述衬底20可以是但不限于硅衬底，本具体实施方式以所述衬底20为硅衬底为例进行说明。在其他实施例中，所述衬底20还可以为氮化镓、砷化镓、碳化镓、碳化硅或SOI等半导体衬底。所述衬底20用于支撑在其上的器件结构。所述衬底20包括沟道区、以及沿第一方向D1分布于所述沟道区相对两侧的所述源极区和所述漏极区，其中，所述第一方向D1为平行于所述衬底20的顶面的方向。所述栅极结构包括覆盖于所述沟道区表面的栅极介质层261、覆盖于所述栅极介质层261表面的栅极接触层262、以及覆盖于所述栅极接触层262表面的栅极导电层263。其中，所述栅极介质层261的材料可以是但不限于氧化物材料，例如二氧化硅；所述栅极接触层262的材料可以是但不限于多晶硅；所述栅极导电层263的材料可以是但不限于金属钨。在形成所述栅极结构26之后，还可以形成包覆所述栅极结构26的栅极隔离层28。所述栅极隔离层28可以为单层结构，也可以为多层结构。在一示例中，所述栅极隔离层28包括包覆所述栅极结构26的第一子栅极隔离层、覆盖所述第一子栅极隔离层的第二子栅极隔离层、以及覆盖所述第二子栅极隔离层的第三子栅极隔离层。其中，所述第一子栅极隔离层和所述第三子栅极隔离层的材料可以均为氮化物材料(例如氮化硅)，所述第二子栅极隔离层的材料可以为氧化物材料(例如二氧化硅)。
之后，可以采用化学气相沉积工艺、物理气相沉积工艺或者原子层沉积工艺形成所述介质层于所述衬底20的表面，以用于隔离所述衬底20与后续在所述介质层上方形成的导电器件结构。在一实施例中，所述介质层可以为单层结构，以简化所述半导体结构的制造工艺，降低所述半导体结构的制造成本。在另一实施例中，所述介质层可以为多层结构，在更好的降低所述衬底20上方的导电器件结构与所述衬底20之间的漏电的同时，减少所述半导体结构内部的寄生电容效应。举例来说，所述介质层包括覆盖于所述衬底20的顶面的第一介质层21、以及覆盖于所述第一介质层21顶面的第二介质层22，且所述第一介质层21的材料与所述第二介质层22的材料不同，例如，所述第一介质层21的材料为氧化物材料(例如二氧化硅)，所述第二介质层22的材料为氮化物材料(例如氮化硅)。在本具体 实施方式中，所述衬底20的顶面是指所述衬底20朝向所述介质层的表面，所述介质层的顶面是指所述介质层背离所述衬底20的表面。本具体实施方式中形成的半导体结构可以是但不限于DRAM。
在形成所述介质层之后，可以采用光刻工艺沿垂直于所述衬底20的顶面的方向(例如图2A和图3A中的第三方向D3)向下刻蚀所述介质层和部分的所述衬底20，以形成沿所述第三方向D3贯穿所述介质层并延伸至所述衬底20内部的所述源极区的所述第一接触孔、并同时形成沿所述第三方向D3贯穿所述介质层并延伸至所述衬底20内部的所述漏极区的所述第二接触孔。之后，可以采用原子层沉积工艺沉积金属钨或者TiN等导电材料于所述第一接触孔内、所述第二接触孔内和所述介质层的顶面，以同时形成所述第一接触结构25和所述第二接触结构23。所述第一接触结构25包括位于所述第一接触孔中的所述第一接触柱、以及与所述第一接触柱直接接触电连接且位于所述介质层的顶面的所述第一接触层，为了增大所述第一接触结构25与其上方的其他导电结构之间的接触面积，所述第一接触层至少沿所述第一方向D1的宽度大于所述第一接触柱沿所述第一方向D1的宽度。所述第二接触结构23包括位于所述第二接触孔中的所述第二接触柱、以及与所述第二接触柱直接接触电连接且位于所述介质层的顶面的所述第二接触层，为了增大所述第二接触结构23与其上方的其他导电结构之间的接触面积，所述第二接触层至少沿所述第一方向D1的宽度大于所述第二接触柱沿所述第一方向D1的宽度。
在一些实施例中，在所述第一沟槽24内、以及所述第一接触结构25和所述第二接触结构23上方形成牺牲层31的具体步骤包括：
形成连续覆盖所述第一沟槽24的内壁、所述第一接触结构25的顶面、以及所述第二接触结构23的顶面的隔离层30，如图2B所示；
形成填充满所述第一沟槽24、且覆盖所述隔离层30表面的所述牺牲层31。
在一些实施例中，在所述第一沟槽24内、以及所述第一接触结构25和所述第二接触结构23上方形成牺牲层31的具体步骤包括：
形成连续覆盖所述第一沟槽24的内壁、所述第一接触结构25的顶面、以及所述第二接触结构23的顶面的隔离层30，所述隔离层30包括位于所述第一沟槽24上方、且与所述第一沟槽24连通的凹陷29，所述凹陷29的宽度大于所述第一沟槽24未被所述隔离层30覆盖的区域的宽度；
形成填充满所述第一沟槽24和所述凹陷29、并覆盖所述隔离层30的顶面的所述牺牲 层31；
去除所述第一接触结构25上方、所述第二接触结构23上方和所述第一沟槽24上方的所述隔离层30和所述牺牲层31，残留的所述牺牲层31的顶面与所述第一接触结构25和所述第二接触结构23的顶面平齐，或者，残留的所述牺牲层31的顶面与所述第一接触结构25和所述第二接触结构23上方残留的所述隔离层30的顶面平齐。
在一些实施例中，在所述牺牲层31上方形成绝缘覆盖层32的具体步骤包括：
形成连续覆盖所述牺牲层31和所述隔离层30、并延伸至所述第一接触结构25和所述第二接触结构23上方的所述绝缘覆盖层32。
在一些实施例中，所述第一接触结构25和所述第二接触结构23沿第一方向D 1排布于所述栅极结构26的相对两侧，所述第一方向D 1为平行于所述衬底20的顶面的方向；在所述第一沟槽内24形成第一气隙结构33的具体步骤包括：
采用侧向刻蚀工艺沿第二方向去除所述牺牲层31，形成位于所述第一沟槽24内的所述第一气隙结构33，所述第二方向为平行于所述衬底20的顶面的方向，且所述第一方向D1与所述第二方向相交。
举例来说，在形成所述第一接触结构25和所述第二接触结构23之后，可以采用化学气相沉积工艺、物理气相沉积工艺或者原子层沉积工艺先沉积氮化物(例如氮化硅)等绝缘介质材料于所述第一沟槽24的内壁(包括所述第一沟槽24的侧壁和所述第一沟槽24的底壁)、所述第一接触结构25的上方和所述第二接触结构23的上方，形成所述隔离层30。在一实施例中，为了增大后续形成的所述第一气隙结构33的尺寸，从而进一步增强所述第一接触结构25与所述第二接触结构23之间的电性隔离效果，可以通过调整沉积参数、或者通过沉积后刻蚀工艺、或者通过选择性沉积工艺，调整所述隔离层30的位置和厚度。所述隔离层30一方面可以保护所述所述第一接触结构25和所述第二接触结构23的侧壁，避免后续沉积或者刻蚀工艺对所述第一接触结构25和所述第二接触结构23造成损伤；另一方面，通过形成覆盖所述第一沟槽24的内壁的所述隔离层30，可以缩小所述第一沟槽24的尺寸(例如所述第一沟槽24沿所述第一方向D1的宽度)，避免后续在去除所述牺牲层31之后、所述绝缘覆盖层32从宽度较大的所述凹陷29进入形成的所述第一气隙结构33内，从而进一步提高所述第一气隙结构33形成的可控性。另外，通过调整所述隔离层30的厚度，还能够调整后续形成的所述第一气隙结构33的位置和尺寸，以满足不同的应用需求，提高所述半导体结构的制造灵活性。由于所述隔离层30仅覆盖所述第一沟槽24的内壁、 并未填充满所述第一沟槽24，即所述隔离层30并未封闭所述第一沟槽24顶部的开口，且由于沉积工艺本身的限制，使得形成的所述隔离层30中包括位于所述第一沟槽24上方的所述凹陷29，所述凹陷29与所述第一沟槽24连通，如图2B所示。以所述第一接触结构25和所述第二接触结构23位于所述栅极结构26沿所述第一方向D1的相对两侧为例，所述凹陷29至少沿所述第一方向D1的宽度大于所述第一沟槽24沿所述第一方向D1的宽度，其中，所述第一方向D1为平行于所述衬底20的顶面的方向。在一实施例中，所述凹陷29的截面呈倒梯形，且所述凹陷29的底面的宽度与所述第一沟槽24顶面的宽度相等，且所述凹陷29顶面的宽度大于所述凹陷29底面的宽度。
接着，将碳、含碳有机材料或者氧化物材料(例如二氧化硅)等流动性较好的材料沉积或者旋涂于所述第一沟槽24内、所述凹陷29内和所述隔离层30的表面，形成填充满所述第一沟槽24和所述凹陷29、并覆盖所述隔离层30的顶面的所述牺牲层31，如图2C所示。由于本实施例中需要在尺寸较小的所述第一沟槽24内形成所述牺牲层31，因此，所述牺牲层31的材料应为流动性较好或者填孔能力(或者填充能力)较强的碳、含碳有机材料或者氧化物材料(例如二氧化硅)等材料，从而确保所述牺牲层31能够填充满尺寸较小的所述第一沟槽24，进而确保后续形成的所述第一气隙结构33的位置。
然后，可以采用化学机械研磨等平坦化工艺、通过控制研磨时间等研磨参数，去除所述第一沟槽24上方的所述隔离层30和所述牺牲层31、以及所述第一接触结构25和所述第二接触结构23上方的部分或者全部的所述隔离层30，使得残留的所述牺牲层31的顶面与所述第一接触结构25和所述第二接触结构23的顶面平齐，或者使得残留的所述牺牲层31的顶面与所述第一接触结构25和所述第二接触结构23上方残留的所述隔离层30的顶面平齐，从而确保所述凹陷29、以及所述凹陷29内的所述牺牲层31均被完全去除，从而避免后续在去除所述第一沟槽24内的所述牺牲层31之后、所述绝缘覆盖层32从宽度较大的所述凹陷29进入形成的所述第一气隙结构33内。
之后，可以采用化学气相沉积工艺、物理气相沉积工艺或者原子层沉积工艺沉积氮化物(例如氮化硅)等绝缘介质材料，形成连续覆盖所述牺牲层31和所述隔离层30、并延伸至所述第一接触结构25和所述第二接触结构23上方的所述绝缘覆盖层32。所述绝缘覆盖层32与所述牺牲层31之间应具有较高的刻蚀选择比(例如所述绝缘覆盖层32与所述牺牲层31之间的刻蚀选择比大于3)，以便于后续通过选择性刻蚀工艺去除所述牺牲层31。接着，可以采用侧向湿法刻蚀工艺沿第二方向去除所述牺牲层31，形成位于所述第一沟槽24 内的所述第一气隙结构33，如图2D所示。本具体实施方式中所述的相交可以是垂直相交(即正交)，也可以是倾斜相交。
本实施例通过先形成所述牺牲层31，限定后续将要形成的所述第一气隙结构33的位置，之后通过刻蚀工艺去除所述牺牲层31来形成所述第一气隙结构33，从而使得所述第一气隙结构33能够在预定的位置形成，在确保所述第一气隙结构33能够形成的同时，提高了对所述第一气隙结构33位置的可控性。另外，本具体实施方式的所述第一气隙结构33位于所述第一接触结构25和所述第二接触结构23之间、且所述第一气隙结构33未暴露所述所述第一接触结构25和所述第二接触结构23，从而在提高所述第一接触结构25和所述第二接触结构23之间的电性隔离效果、减小寄生电容效应的同时，也能对所述第一接触结构25和所述第二接触结构23进行了保护。而且，本实施例通过调整所述隔离层30的厚度和位置，还能实现对所述第一气隙结构33位置和尺寸的调整，极大的提高了所述半导体结构制造的灵活性。
在另一些实施例中，在所述第一沟槽24内、以及所述第一接触结构25和所述第二接触结构23上方形成牺牲层31的具体步骤包括：
形成连续覆盖所述第一接触结构25的顶面、所述第二接触结构23的顶面、以及所述第一沟槽24的内壁的所述牺牲层31，如图3B所示。
在一些实施例中，在所述牺牲层31上方形成绝缘覆盖层32的具体步骤包括：
形成覆盖于所述牺牲层31表面、并填充满所述第一沟槽24的绝缘覆盖层32，如图3C所示。
在一些实施例中，所述第一接触结构25和所述第二接触结构23沿第一方向D1排布于所述栅极结构26的相对两侧，所述第一方向D1为平行于所述衬底20的顶面的方向；在所述第一沟槽24内形成第一气隙结构33的具体步骤包括：
采用侧向刻蚀工艺沿所述第一方向D1去除所述牺牲层31，形成所述第一气隙结构33，所述第一气隙结构33连续分布于所述第一接触结构25上方、所述第二接触结构23上方、以及所述第一沟槽24内，如图3D所示。
举例来说，在形成所述第一接触结构25和所述第二接触结构23之后，可以采用化学气相沉积工艺、物理气相沉积工艺或者原子层沉积工艺沉积氧化物(例如二氧化硅)等绝缘介质材料于所述第一沟槽24的内壁、所述第一接触结构25的顶面和所述第二接触结构23的顶面，形成连续覆盖所述第一接触结构25的顶面、所述第二接触结构23的顶面、以 及所述第一沟槽24的内壁的所述牺牲层31，如图3B所示。之后，沉积氮化物(例如氮化硅)等绝缘介质材料于所述牺牲层31的表面和所述第一沟槽24内，形成覆盖于所述牺牲层31表面、并填充满所述第一沟槽24的所述绝缘覆盖层32，如图3C所示。所述绝缘覆盖层32与所述牺牲层31之间应具有较高的刻蚀选择比(例如所述绝缘覆盖层32与所述牺牲层31之间的刻蚀选择比大于3)，以便于后续通过选择性刻蚀工艺去除所述牺牲层31。接着，可以采用侧向湿法刻蚀工艺沿所述第一方向D1去除全部的所述牺牲层31，形成沿所述第一方向D1延伸的所述第一气隙结构33，且所述第一气隙结构33连续分布于所述第一接触结构25上方、所述第二接触结构23上方、以及所述第一沟槽24内。所述绝缘覆盖层32沿所述第二方向覆盖于所述介质层的顶面或者沿所述第二方向与其他支撑结构连接。
本实施例通过先形成所述牺牲层31，限定后续将要形成的所述第一气隙结构33的位置，之后通过刻蚀工艺去除所述牺牲层31来形成所述第一气隙结构338，从而使得所述第一气隙结构33能够在预定的位置形成，在确保所述第一气隙结构33能够形成的同时，提高了对所述第一气隙结构33位置的可控性。本实施例通过调整所述牺牲层31的厚度和位置，可以实现对所述第一气隙结构33尺寸和位置的调整，从而提高了所述半导体结构制程工艺的灵活性，以满足不同的应用需求。另外，本实施例中的所述第一气隙结构33连续分布于所述第一接触结构25上方、所述第二接触结构23上方、以及所述第一沟槽24内，一方面，能够增大位于所述栅极结构26两侧的所述第一接触结构25和所述第二接触结构23之间的第一气隙结构33尺寸，从而进一步增强所述第一接触结构25和所述第二接触结构23之间的电性隔离效果；另一方面，还能够增强所述第一接触结构25和所述第二接触结构23与后续在所述绝缘覆盖层32上方形成的其他导电器件结构之间的电性隔离效果。
在一些实施例中，所述衬底20上包括沿第一方向D1间隔排布的多个所述栅极结构26，每个所述栅极结构26沿所述第一方向D1的相对两侧分别设置有所述第一接触结构25和所述第二接触结构23，对于相邻的两个所述栅极结构26，位于其中一个所述栅极结构26一侧的所述第一接触结构25与位于另一个所述栅极结构26一侧的所述第二接触结构23之间具有第二沟槽27，所述第一方向D1为平行于所述衬底20的顶面的方向；所述半导体结构的形成方法还包括：
在所述第一沟槽24内、所述第二沟槽27内、以及每个所述第一接触结构25上方和每个所述第二接触结构23上方形成牺牲层31；
在所述牺牲层31上方形成绝缘覆盖层32；
去除所述牺牲层31，在所述第一沟槽24内形成第一气隙结构33、并同时在所述第二沟槽27内形成第二气隙结构34。
在一些实施例中，所述第一沟槽24沿所述第一方向D1的宽度小于所述第二沟槽27沿所述第一方向D1的宽度，所述第一气隙结构33沿所述第一方向D1的宽度小于所述第二气隙结构34沿所述第一方向D1的宽度。
具体来说，如图2A和图3A所示，所述半导体结构可以包括沿所述第一方向D1间隔排布的多个晶体管结构，每个所述晶体管结构包括所述栅极结构26、以及沿所述第一方向D1分布于所述栅极结构26相对两侧的所述第一接触结构25和所述第二接触结构23。对于任意相邻的两个所述晶体管结构，其中一个所述晶体管结构中的所述第一接触结构25与另一个所述晶体管结构中的所述第二接触结构23相邻，即：对于任意相邻的两个所述栅极结构26，位于其中一个所述栅极结构26一侧的所述第一接触结构25与位于另一个所述栅极结构26一侧的所述第二接触结构23相邻。相邻的两个所述晶体管结构之间具有所述第二沟槽27。为了进一步降低所述半导体结构内部的寄生电容效应，并减少所述半导体结构内部的漏电，本具体实施方式可以在一个所述晶体管结构内部的所述第一接触结构25与所述第二接触结构23之间形成所述第一气隙结构33的同时，也在相邻的两个所述晶体管结构之间形成所述第二气隙结构，从而能够减少相邻两个所述晶体管结构之间的寄生电容效应，并减少相邻两个所述晶体管结构之间的漏电。
本具体实施方式通过使得所述第二沟槽27至少沿所述第一方向D1的宽度大于所述第一沟槽24沿所述第一方向D1的宽度，所述第二气隙结构34至少沿所述第一方向D1的宽度大于所述第一气隙结构33沿所述第一方向D1的宽度，可以更好的避免相邻的两个所述晶体管结构之间的信号串扰。
为了使得所述牺牲层31能够形成于尺寸较小的所述第一沟槽24内，且避免在去除所述牺牲层31之后所述绝缘覆盖层32进入所述第一气隙结构33，在一些实施例中，所述牺牲层31的填充能力强于所述绝缘覆盖层32的填充能力。
在一些实施例中，所述牺牲层31的材料为含碳材料或者氧化物材料。在另一些实施例中，所述牺牲层31的材料还可以是碳。
本具体实施方式还提供了一种半导体结构，采用如上任一项所述的半导体结构的形成方法形成。本具体实施方式形成的半导体结构的示意图可以参见图2D或者图3D。本具体实施方式中所述的半导体结构可以是但不限于DRAM。
本具体实施方式一些实施例提供的半导体结构及其形成方法，通过在栅极结构相对两侧的第一接触结构和第二接触结构之间形成第一气隙结构，利用空气的低介电常数来增强所述第一接触结构和所述第二接触结构之间的电性隔离效果，从而降低相邻所述栅极结构相对两侧的所述第一接触结构和所述第二接触结构之间的电容寄生效应，减少了相邻两个所述导电元件之间发生电性击穿的概率，并降低了所述栅极结构相对两侧的所述第一接触结构与所述第二接触结构之间发生漏电的概率，实现了对半导体结构电性能的改善。而且，本公开的一些实施例是在所述栅极结构相对两侧的所述第一接触结构和所述第二接触结构之间填充牺牲层、且形成至少位于所述牺牲层上方的绝缘覆盖层之后，再去除所述牺牲层来形成所述第一气隙结构，一方面，即便是半导体结构的尺寸不断微缩，也能确保在所述栅极结构相对两侧的所述第一接触结构和所述第二接触结构之间形成所述第一气隙结构，且能够通过所述牺牲层限定所述第一气隙结构的具体位置和具体尺寸，提高了所述半导体结构性能的可控性；另一方面，工艺简单，无需使用复杂的填充工艺或者填充设备，极大的降低了半导体结构的制造难度。
以上所述仅是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本公开原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (15)

  1. 一种半导体结构的形成方法，包括如下步骤：
    形成基底，所述基底包括衬底、以及位于所述衬底上方的栅极结构，所述栅极结构两侧分别设置有第一接触结构和第二接触结构、以及位于所述第一接触结构和所述第二接触结构之间的第一沟槽；
    在所述第一沟槽内、以及所述第一接触结构和所述第二接触结构上方形成牺牲层；
    在所述牺牲层上方形成绝缘覆盖层；
    去除所述牺牲层，在所述第一沟槽内形成第一气隙结构。
  2. 根据权利要求1所述的半导体结构的形成方法，其中，形成基底的具体步骤包括：
    提供所述衬底，并于所述衬底中定义沟道区、以及分布于所述沟道区相对两侧的源极区和漏极区；
    于所述衬底的所述沟道区上方形成所述栅极结构；
    形成覆盖所述衬底和所述栅极结构的介质层；
    形成均贯穿所述介质层、并分别与所述源极区电接触连接的第一接触结构和与所述漏极区电接触连接的第二接触结构，所述第一接触结构暴露于所述介质层顶面的部分与所述第二接触结构暴露于所述介质层顶面的部分之间的间隙作为所述第一沟槽。
  3. 根据权利要求2所述的半导体结构的形成方法，其中，形成均贯穿所述介质层、并分别与所述源极区电接触连接的第一接触结构和与所述漏极区电接触连接的第二接触结构的具体步骤包括：
    刻蚀所述介质层，形成贯穿所述介质层并暴露所述源极区的第一接触孔、并同时形成贯穿所述介质层并暴露所述漏极区的第二接触孔；
    沉积导电材料于所述第一接触孔内、所述第二接触孔内和部分所述介质层的表面，形成包括第一接触柱和位于所述第一接触柱顶面的第一接触层的所述第一接触结构、并同时形成包括第二接触柱和位于所述第二接触柱顶面的第二接触层的所述第二接触结构，所述第一接触层的宽度大于所述第一接触柱的宽度，所述第二接触层的宽度大于所述第二接触柱的宽度。
  4. 根据权利要求2所述的半导体结构的形成方法，其中，在所述第一沟槽内、以及所述第一接触结构和所述第二接触结构上方形成牺牲层的具体步骤包括：
    形成连续覆盖所述第一沟槽的内壁、所述第一接触结构的顶面、以及所述第二接触结构的顶面的隔离层；
    形成填充满所述第一沟槽、且覆盖所述隔离层表面的所述牺牲层。
  5. 根据权利要求2所述的半导体结构的形成方法，其中，在所述第一沟槽内、以及所述第一接触结构和所述第二接触结构上方形成牺牲层的具体步骤包括：
    形成连续覆盖所述第一沟槽的内壁、所述第一接触结构的顶面、以及所述第二接触结构的顶面的隔离层，所述隔离层包括位于所述第一沟槽上方、且与所述第一沟槽连通的凹陷，所述凹陷的宽度大于所述第一沟槽内未被所述隔离层覆盖的区域的宽度；
    形成填充满所述第一沟槽和所述凹陷、并覆盖所述隔离层的顶面的所述牺牲层；
    去除所述第一接触结构上方、所述第二接触结构上方和所述第一沟槽上方的所述隔离层和所述牺牲层，残留的所述牺牲层的顶面与所述第一接触结构的顶面和所述第二接触结构的顶面平齐，或者，残留的所述牺牲层的顶面与所述第一接触结构和所述第二接触结构上方残留的所述隔离层的顶面平齐。
  6. 根据权利要求4或5所述的半导体结构的形成方法，其中，在所述牺牲层上方形成绝缘覆盖层的具体步骤包括：
    形成连续覆盖所述牺牲层和所述隔离层、并延伸至第一接触结构和所述第二接触结构上方的所述绝缘覆盖层。
  7. 根据权利要求6所述的半导体结构的形成方法，其中，所述第一接触结构和所述第二接触结构沿第一方向排布于所述栅极结构的相对两侧，所述第一方向为平行于所述衬底的顶面的方向；在所述第一沟槽内形成第一气隙结构的具体步骤包括：
    采用侧向刻蚀工艺沿第二方向去除所述牺牲层，形成位于所述第一沟槽内的所述第一气隙结构，所述第二方向为平行于所述衬底的顶面的方向，且所述第一方向与所述第二方向相交。
  8. 根据权利要求2所述的半导体结构的形成方法，其中，在所述第一沟槽内、以及所述第一接触结构和所述第二接触结构上方形成牺牲层的具体步骤包括：
    形成连续覆盖所述第一接触结构的顶面、所述第二接触结构的顶面、以及所述第一沟槽的内壁的所述牺牲层。
  9. 根据权利要求8所述的半导体结构的形成方法，其中，在所述牺牲层上方形成绝缘覆盖 层的具体步骤包括：
    形成覆盖于所述牺牲层表面、并填充满所述第一沟槽的绝缘覆盖层。
  10. 根据权利要求9所述的半导体结构的形成方法，其中，所述第一接触结构和所述第二接触结构沿第一方向排布于所述栅极结构的相对两侧，所述第一方向为平行于所述衬底的顶面的方向；在所述第一沟槽内形成第一气隙结构的具体步骤包括：
    采用侧向刻蚀工艺沿所述第一方向去除所述牺牲层，形成所述第一气隙结构，所述第一气隙结构连续分布于所述第一接触结构上方、所述第二接触结构上方、以及所述第一沟槽内。
  11. 根据权利要求1所述的半导体结构的形成方法，其中，所述衬底上包括沿第一方向间隔排布的多个所述栅极结构，每个所述栅极结构沿所述第一方向的相对两侧分别设置有所述第一接触结构和所述第二接触结构，对于相邻的两个所述栅极结构，位于其中一个所述栅极结构一侧的所述第一接触结构与位于另一个所述栅极结构一侧的所述第二接触结构之间具有第二沟槽，所述第一方向为平行于所述衬底的顶面的方向；所述半导体结构的形成方法还包括：
    在所述第一沟槽内、所述第二沟槽内、以及每个所述第一接触结构上方和每个所述第二接触结构上方形成牺牲层；
    在所述牺牲层上方形成绝缘覆盖层；
    去除所述牺牲层，在所述第一沟槽内形成第一气隙结构、并同时在所述第二沟槽内形成第二气隙结构。
  12. 根据权利要求11所述的半导体结构的形成方法，其中，所述第一沟槽沿所述第一方向的宽度小于所述第二沟槽沿所述第一方向的宽度，所述第一气隙结构沿所述第一方向的宽度小于所述第二气隙结构沿所述第一方向的宽度。
  13. 根据权利要求1所述的半导体结构的形成方法，其中，所述牺牲层的填充能力强于所述绝缘覆盖层的填充能力。
  14. 根据权利要求13所述的半导体结构的形成方法，其中，所述牺牲层的材料为含碳材料或者氧化物材料。
  15. 一种半导体结构，采用如权利要求1-14中任一项所述的半导体结构的形成方法形成。
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