WO2023134331A1 - 半导体结构的制备方法及半导体结构 - Google Patents

半导体结构的制备方法及半导体结构 Download PDF

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Publication number
WO2023134331A1
WO2023134331A1 PCT/CN2022/136886 CN2022136886W WO2023134331A1 WO 2023134331 A1 WO2023134331 A1 WO 2023134331A1 CN 2022136886 W CN2022136886 W CN 2022136886W WO 2023134331 A1 WO2023134331 A1 WO 2023134331A1
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Prior art keywords
bit line
conductive layer
initial
layer
contact structure
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PCT/CN2022/136886
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English (en)
French (fr)
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严勋
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长鑫存储技术有限公司
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Priority to US18/327,224 priority Critical patent/US20230328969A1/en
Publication of WO2023134331A1 publication Critical patent/WO2023134331A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines

Definitions

  • Embodiments of the present disclosure relate to but are not limited to a method for fabricating a semiconductor structure and the semiconductor structure.
  • Capacitive contact structure and bit line contact structure With the rapid development of integrated circuit technology, the density of devices in integrated circuits is getting higher and higher, and the feature size of semiconductor devices is continuously reduced. Capacitive contact structure and bit line contact structure.
  • the capacitor contact structure is connected to one of the source/drain in the semiconductor structure, so that the capacitor is electrically connected to the source/drain, and the bit line contact structure is connected to the other source/drain in the semiconductor structure, so that the bit line The line is electrically connected to the source/drain, so that the data information stored in the capacitor can be read through the bit line, or the data information can be written into the capacitor, so as to ensure the normal operation of the semiconductor device.
  • Embodiments of the present disclosure provide a method for fabricating a semiconductor structure and the semiconductor structure.
  • an embodiment of the present disclosure provides a method for preparing a semiconductor structure, including: providing a substrate, the substrate has a concave hole, and the surface of the substrate exposes the opening of the concave hole; forming a conductive layer, the conductive layer includes : the first conductive layer and the second conductive layer, the first conductive layer is located on the surface of the substrate, the second conductive layer is located in the concave hole, the top surface of the second conductive layer is lower than the top surface of the first conductive layer, and is located in the concave hole
  • the second conductive layer has a hole; the first initial bit line conductive layer is formed on the side of the first conductive layer away from the substrate, and the second initial bit line conductive layer is formed on the side of the second conductive layer away from the substrate, the first The top surface of the initial bit line conductive layer is higher than the top surface of the second initial bit line conductive layer; the first etching process is used to etch the first initial bit line conductive layer
  • Conductive layer of a bit line at the same time, carry out first etching process to part of the second initial conductive layer of bit line, the second initial conductive layer of bit line is not completely etched; Adopt second etching process to etch the first conductive layer etch to form the first conductive structure. In the direction perpendicular to the substrate, the width of the first conductive structure remains unchanged.
  • the second etching process is used to etch the remaining second initial bit line conductive layer to form the first Two bit line conductive layers, and the etching rate of the first etching process to the second initial bit line conductive layer is greater than the etching rate of the second etching process to the second initial bit line conductive layer; etching the second conductive layer , forming a bit line contact structure wrapping the hole, the width of the bit line contact structure gradually increases along the direction from the top surface of the bit line contact structure to the bottom surface of the bit line contact structure.
  • an embodiment of the present disclosure further provides a semiconductor structure, including: a substrate, the substrate has a concave hole, and the surface of the substrate exposes the opening of the concave hole; a bit line contact structure, the bit line contact structure is located In the concave hole, the bit line contact structure is wrapped with a cavity, and in the direction along the top surface of the bit line contact structure pointing to the bottom surface of the bit line contact structure, the width of the bit line contact structure gradually increases; the first conductive structure, the first conductive The structure is located on the surface of the substrate, and the width of the first conductive structure is constant in the direction perpendicular to the substrate; the first bit line conductive layer and the second bit line conductive layer, the first bit line conductive layer is located on the first conductive structure away from the substrate On the bottom side, the second bit line conductive layer is located on the side of the bit line contact structure away from the substrate, and the top surface of the first bit line conductive layer is higher than the top surface of the second bit
  • 1 to 3 are structural schematic diagrams corresponding to each step in a method for preparing a semiconductor structure
  • FIG. 4 is a schematic structural diagram corresponding to the step of forming a first initial conductive layer in a method for preparing a semiconductor structure according to an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram corresponding to the step of forming a second initial conductive layer in a method for preparing a semiconductor structure according to an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram corresponding to the steps of forming a first conductive layer and a second conductive layer in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 7 is a schematic structural diagram corresponding to the step of removing the first sacrificial layer 13 in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 8 is a schematic structural diagram corresponding to the step of forming a first initial bit line conductive layer and a second initial bit line conductive layer in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 9 is a schematic structural diagram corresponding to the step of patterning the second sacrificial layer in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure
  • FIG. 10 is a schematic structural diagram corresponding to the step of forming a bit line contact structure in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 11 is a schematic structural diagram corresponding to the steps of forming a first initial adhesion layer and a second initial adhesion layer in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 12 is a schematic structural diagram corresponding to the step of forming a bit line contact structure in another semiconductor structure manufacturing method provided by an embodiment of the present disclosure
  • FIG. 13 is a structural diagram corresponding to the step of forming a bit line protection layer and a capacitive contact structure in another semiconductor structure manufacturing method provided by an embodiment of the present disclosure.
  • FIGS. 1 to 3 are structural schematic diagrams corresponding to each step in a method for preparing a semiconductor structure. Referring to FIG. 1 , a bit line contact structure 110 is formed in the recessed hole 10 of the substrate 100.
  • the initial conductive layer in the recessed hole 10 Since the initial conductive layer (not shown) in the recessed hole 10 has a cavity 20, the initial conductive layer in the recessed hole 10 is When etching to form the bit line contact structure 110, the etching rate of the initial conductive layer facing the hole 20 is relatively high in the etching process, thereby forming the bit line contact structure 110 with a neck-shaped morphology, that is, the bit line contact structure 110 with the hole The sidewall of the bit line contact structure 110 opposite to 20 is thinner. Referring to FIG. 2, the bit line protection layer 130 is formed on both sides of the bit line contact structure 110.
  • bit line contact structure 110 Since the sidewall of the bit line contact structure 110 facing the hole 20 is relatively thin, during the process of forming the bit line protection layer 130, there are Process damage may occur to the bit line contact structure 110 , resulting in removal of the sidewall of the bit line contact structure 110 facing the void 20 , thereby forming a channel 30 in the bit line contact structure 110 .
  • capacitive contact structures 140 are formed on both sides of the bit line contact structure 110. Since a channel is formed in the bit line contact structure 110, when the conductive material is deposited to form the capacitive contact structure 140, the conductive material will also be located in the channel 30. , the capacitive contact structures 140 located on both sides of the bit line contact structure 110 will form an electrical connection through the channel 30 to cause a short circuit. In addition, the electrical connection between the bit line contact structure 110 and the capacitive contact structure 140 will result in a short circuit, thereby causing a short circuit phenomenon in the semiconductor structure.
  • An embodiment of the present disclosure provides a method for preparing a semiconductor structure, by setting the top surface of the first conductive layer higher than the top surface of the second conductive layer, and the top surface of the first initial bit line conductive layer is higher than the second initial bit line
  • the top surface of the conductive layer so that when the first initial bit line and the second initial bit line are etched by the first etching process, the first initial bit line conductive layer is etched first, and the second initial bit line conductive layer It has not been etched yet, so when the second etching process starts to etch the first conductive layer, the second etching process needs to continue to etch the second initial bit line conductive layer.
  • the second etching process is a process designed based on the first conductive layer, the etching rate of the second initial bit line conductive layer in the second etching process is relatively slow, so that in the formed second bit line conductive layer, The second bit line conductive layer points to the direction of the second conductive layer, and the width of the second bit line conductive layer gradually increases toward the second conductive layer.
  • the second conductive layer is subsequently etched, the morphology of the second conductive layer will be continued, so that the width of the bit line contact structure gradually increases along the direction from the top surface of the bit line contact structure to the bottom surface of the bit line contact structure.
  • the thickness of the sidewall of the bit line contact structure facing the hole gradually increases, so that after the capacitive contact structure is formed on both sides of the bit line contact structure, it will not penetrate the side wall of the bit line contact structure facing the hole. In turn, the possibility of a short circuit occurring in the semiconductor structure is reduced.
  • 4 to 7 are structural schematic diagrams corresponding to the step of forming a conductive layer in the method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present disclosure.
  • substrate 200 is provided, substrate 200 has concave hole 10, and the opening of substrate 200 surface exposes concave hole 10;
  • Form conductive layer 210, conductive layer 210 comprises: first conductive layer 211 and second conductive layer Layer 212, the first conductive layer 211 is located on the surface of the substrate 200, the second conductive layer 212 is located in the concave hole 10, the top surface of the second conductive layer 212 is lower than the top surface of the first conductive layer 211, and is located in the concave hole 10
  • the second conductive layer 212 has a cavity 20 .
  • the material of the substrate 200 is a semiconductor material. In some embodiments, the material of the substrate 200 is silicon. In some other embodiments, the substrate 200 may also be a germanium substrate, a silicon germanium substrate, a silicon carbide substrate or a silicon-on-insulator substrate.
  • the method for forming the concave hole 10 may include: patterning the substrate 200 to define the opening position of the concave hole 10; A concave hole 10 with a set depth is formed in 200. Since the concave hole 10 has a larger aspect ratio, when the second conductive layer 212 is subsequently formed in the concave hole 10 , the second conductive layer 212 will form a cavity 20 .
  • the method for forming the top surface of the second conductive layer 212 lower than the top surface of the first conductive layer 211 includes:
  • a first initial conductive layer 11 and a second initial conductive layer 12 are formed, the first initial conductive layer 11 covers the surface of the substrate 200 , and the second initial conductive layer 12 fills the concave hole 10 .
  • the first initial conductive layer 11 can be formed on the surface of the substrate 200 before the concave hole 10 is formed, and the first initial conductive layer 11 can be formed on the surface of the substrate 200 by a deposition process.
  • the first sacrificial layer 13 may be formed on the top surface of the first initial conductive layer 11 to perform patterning on the surface of the first initial conductive layer 11 .
  • the surface of the patterned first initial conductive layer 11 is etched until a part of the substrate 200 is exposed, and a concave hole 10 with a predetermined depth is formed in the substrate 200, and the remaining first initial conductive layer 11 can be used as the first a conductive layer 211 .
  • the material of the first sacrificial layer 13 can be silicon oxide, and in other embodiments, the material of the first sacrificial layer 13 can also be carbon material, SOC material, borosilicate glass, borophosphosilicate glass or Either of tetraethyl orthosilicate.
  • a second initial conductive layer 12 may be formed in the concave hole 10 by a deposition process, and the second initial conductive layer 12 is also located on the top surface of the first sacrificial layer 13 .
  • the deposition process may include any of chemical vapor deposition, physical vapor deposition, atomic layer deposition, or metalorganic chemical vapor deposition.
  • the material of the first initial conductive layer 11 and the material of the second initial conductive layer 12 may be the same, such as polysilicon material.
  • an initial etching process is performed on the top surface of the second initial conductive layer 12 to form the second conductive layer 212 , and the top surface of the second conductive layer 212 is lower than the top surface of the first conductive layer 211 .
  • the initial etching process is an etch-back process, and the second initial conductive layer 12 is etched using the etch-back process to remove the second initial conductive layer 12 higher than the top surface of the first sacrificial layer 13 .
  • layer 12 and the second initial conductive layer 12 partially in contact with the first conductive layer 211 to form the second conductive layer 212, the top surface of the second conductive layer 212 is lower than the top surface of the first conductive layer 211.
  • the initial etching process may be a dry etching process.
  • the top surface of the second conductive layer 212 is lower than the top surface of the first conductive layer 211, so that in the same process step, as shown in FIG. 8, the first initial bit line conductive layer 14 is formed on the top surface of the first conductive layer 211.
  • the top surface of the second initial bit line conductive layer 15 can be lower than the top surface of the first initial bit line conductive layer 14 .
  • the first initial bit line conductive layer 14 and the second initial bit line conductive layer 14 can be combined
  • the height difference of the second initial bit line conductive layer 15, and the height difference between the first conductive layer 211 and the second conductive layer 212 are converted into the etching rate difference when the second initial bit line conductive layer 15 is etched, so that
  • the second bit line conductive layer 222 formed by the second etching process has a trapezoidal shape with a narrow top and a wide bottom.
  • the shape of the bit line conductive layer 222 can be formed so that the bit line contact structure 232 also has a trapezoidal shape with a narrow top and a wide bottom.
  • the time for performing the initial etching process on the second initial conductive layer 12 is 8s ⁇ 16s. Control the etching process time in the range of 8s to 16s, so that the etching time will not be too long, so that the formed second conductive layer 212 will not be too low relative to the first conductive layer 211, so that the subsequently formed second conductive layer 212 will not be too low.
  • the initial bit line conductive layer 15 is not too low relative to the first initial bit line conductive layer 14 (refer to FIG. 8 ), that is, it can prevent the etching time of the second initial bit line conductive layer 15 from the second etching process from being too long.
  • the width of the bottom of the formed second bit line conductive layer 222 is too large (refer to FIG. 10 ). Therefore, when the second conductive layer 212 is etched along the topography of the second bit line conductive layer 222 to form the bit line contact structure 232, the width of the bottom of the bit line contact structure 232 will not be too large, that is, it can prevent the occurrence of The volume occupied by the bit line contact structure 232 in the concave hole 10 is too large, so that when the bit line protective layer 260 is subsequently formed on both sides of the bit line contact structure 232, the bit line protective layer 260 formed in the concave hole 10 is too thin , so that the bit line protection layer 260 may not achieve a good isolation effect (refer to FIG.
  • Controlling the etching process time within the range of 8s to 16s can also make the etching time not too short, that is, the distance from the top surface of the second initial bit line conductive layer 15 to the top surface of the first initial bit line conductive layer 14 formed later
  • the height difference is not too small, which can prevent the formation of the bit line contact structure 232 with a trapezoidal shape with a narrow top and a wide bottom due to the short etching time of the second initial bit line conductive layer 15 in the second etching process. The problem.
  • the height difference d1 from the top surface of the second conductive layer 212 to the top surface of the first conductive layer 211 is 8 nm ⁇ 16 nm. It should be considered that the volume occupied by the formed bit line contact structure 232 in the concave hole 10 should not be too large. A certain space is reserved, because if the bit line protection layer 260 is too thin, the problem of electric leakage may occur in the substrate 200 (refer to FIG. 13 ).
  • bit line contact structure 232 in the direction along the top surface of the bit line contact structure 232 pointing to the bottom surface of the bit line contact structure 232, it is necessary to form the shape that the width of the bit line contact structure 232 gradually increases, so that it can be compared with
  • the sidewall of the bit line contact structure 232 facing the cavity 20 is relatively thick, so that when the bit line protection layer 260 and the capacitor contact structure 270 are formed on both sides of the bit line contact structure 232 later, the bit line contact structure 270 directly facing the cavity 20 is not easy to occur.
  • the sidewall of the contact structure 232 is penetrated due to being too thin, which causes the capacitive contact structure 270 located on both sides of the bit line contact structure 232 to be electrically connected through the penetrated bit line contact structure 232 to cause a short circuit of the semiconductor structure.
  • setting the height difference d1 from the top surface of the second conductive layer 212 to the top surface of the first conductive layer 211 is 8nm-16nm, which can greatly reduce the possibility of short circuit in the semiconductor structure, and at the same time maintain the semiconductor structure. Better structure performance.
  • the time for performing the initial etching process on the second initial conductive layer 12 can be adjusted to adjust the height difference from the top surface of the second conductive layer 212 to the top surface of the first conductive layer 211 .
  • the height difference to be formed from the top surface of the second conductive layer 212 to the top surface of the first conductive layer 211 can also be determined in advance, combined with the etching rate of the initial etching process, to determine the initial etching process. time.
  • the rate of the initial etching process is 1nm/s
  • the height difference between the top surface of the second conductive layer 212 and the top surface of the first conductive layer 211 can be 8nm-16nm, and the control for the second initial etching process can be controlled.
  • the time for performing the initial etching process on the conductive layer 12 is 8s ⁇ 16s.
  • the first sacrificial layer 13 is removed, so that a first initial bit line conductive layer can be formed on the top surface of the first conductive layer 211 subsequently.
  • a first initial bit line conductive layer 14 is formed on the side of the first conductive layer 211 away from the substrate 200, and a second initial bit line conductive layer 15 is formed on the side of the second conductive layer 212 away from the substrate 200,
  • the top surface of the first initial bit line conductive layer 14 is higher than the top surface of the second initial bit line conductive layer 15 .
  • the first initial bit line conductive layer 14 in the same process step, can be deposited on the side of the first conductive layer 211 away from the substrate 200 by using a deposition process, and the first initial bit line conductive layer 14 can be deposited on the side of the second conductive layer 212 away from the substrate 200.
  • a second initial bit line conductive layer 15 is formed on one side.
  • the material for forming the first initial bit line conductive layer 14 may be the same as the material for forming the second initial bit line conductive layer 15, that is, the first initial bit line conductive layer 14 may be formed simultaneously in the same process step. And the second initial bit line conductive layer 15 .
  • the first initial bit line conductive layer 14 is formed on the basis of the first conductive layer 211 and the second conductive layer 212. and the second initial bit line conductive layer 15, so that the formed first initial bit line conductive layer 14 and the second initial bit line conductive layer 15 also have a shape similar to that of the first conductive layer 211 and the second conductive layer 212, That is, the top surface of the first initial bit line conductive layer 14 is also higher than the top surface of the second initial bit line conductive layer 15 .
  • the height difference between the first initial bit line conductive layer 14 and the second initial bit line conductive layer 15, and the height difference between the first conductive layer 211 and the second conductive layer 212 can be converted into The difference in etching rate between the two initial bit line conductive layers 15 when performing the etching process, as shown in FIG.
  • Layer 222 has a trapezoidal shape with a narrow top and a wide bottom. So that when the second conductive layer 212 is subsequently etched, the shape of the second bit line conductive layer 222 facing the second conductive layer 212 is used as a mold to form a bit line contact structure 232 that also has a trapezoidal shape with a narrow top and a wide bottom. appearance.
  • the material of the first initial bit line conductive layer 14 and the second initial bit line conductive layer 15 may be a metal material, which may include any one of tungsten, copper or aluminum.
  • the length of the first initial bit line conductive layer 14 is smaller than the length of the second initial bit line conductive layer 15 .
  • the length of the second initial bit line conductive layer 15 is set to be longer, and the second etching process is used subsequently to When the second initial bit line conductive layer 15 is etched, the etching time of the second initial bit line conductive layer 15 in the second etching process is longer, as shown in FIG. 10 , so that the formed second bit line conductive layer The 222 has a larger bottom width.
  • the overall width of the bit line contact structure 232 is larger, which can further increase the connection with the cavity 20.
  • the thickness of the sidewall of the bit line contact structure 232 facing to it further prevents the problem that the side wall of the bit line contact structure 232 facing the cavity 20 is penetrated in the subsequent process.
  • the method for forming the length of the first initial bit line conductive layer 14 to be shorter than the length of the second initial bit line conductive layer 15 may include: depositing initial bits on the top surfaces of the first conductive layer 211 and the second conductive layer 212 Line conductive layer, wherein the initial bit line conductive layer positioned on the top surface of the first conductive layer 211 is used as the first initial bit line conductive layer 14; a mask layer is formed on the top surface of the first initial bit line conductive layer 14; The same material as that of the initial bit line conductive layer is deposited on the top surface of the line conductive layer to form the second initial bit line conductive layer 15 ; the mask layer is removed.
  • it also includes: forming a second sacrificial layer 280 on the side of the first initial bit line conductive layer 14 and the second initial bit line conductive layer 15 away from the substrate 200, the second sacrificial layer 280 is used as a mask, It is used for etching the first initial bit line and the second initial bit line with preset shapes.
  • the second sacrificial layer 280 is patterned.
  • a bit line contact structure 232 is formed.
  • the first etching process first etches the first initial bit line conductive layer 14 .
  • the second initial bit line conductive layer 15 has not been completely etched due to the subsequent etching of the second initial bit line conductive layer 15. .
  • the first conductive layer 211 is etched by using the second etching process to form the first conductive structure 231. In the direction perpendicular to the substrate 200, the width of the first conductive structure 231 remains unchanged.
  • the second etching process is used Etching the remaining second initial bit line conductive layer 15 to form the second bit line conductive layer 222, and the etching rate of the second initial bit line conductive layer 15 by the first etching process is greater than that of the second etching process The etching rate for the second initial bit line conductive layer 15 .
  • the second etching process is an etching process based on the first conductive layer 211.
  • the material of the first conductive layer 211 is different from the material of the first initial bit line conductive layer 14, so that the second etching process
  • the etching selectivity of the first conductive layer 211 is greater than the etching selectivity of the first initial bit line conductive layer 14 in the second etching process.
  • the second etching process is used to etch the remaining second initial bit line conductive layer 15, the etching selection of the second initial bit line conductive layer 15 in the second etching process is relatively small, and the first etching can be realized.
  • the etching rate of the second initial bit line conductive layer 15 by the etching process is greater than the etching rate of the second initial bit line conductive layer 15 by the second etching process.
  • the etching rate of the second initial conductive layer 12 becomes smaller;
  • the second bit line conductive layer 222 formed by the second etching process may have a shape whose width gradually increases.
  • the first etching process is an etching process based on the first initial bit line conductive layer 14
  • the second etching process is an etching process based on the first conductive layer 211
  • the first etching process The etching rate of the first initial bit line conductive layer 14 by the process is equal to the etching rate of the first conductive layer 211 by the second etching process, so as to form the shape of the first conductive structure 231 with a constant width.
  • the width of the first conductive structure 231 is set to be constant, so that the first conductive structure There is a larger space between the first conductive structure 231 and the bit line contact structure 232, as shown in FIG. Create a larger space.
  • the subsequently formed bit line protection layer 260 can have a larger thickness, which can better isolate the bit line contact structure 232 from the capacitive contact structure 270; on the other hand, the formed capacitive contact structure 270 has a larger thickness.
  • the volume is beneficial to improve the electrical performance of the capacitive contact structure 270 .
  • the first etching process and the second etching process may be dry etching processes.
  • the first etching process may use a first etching gas, such as Cl 2 ;
  • the second etching process may use a second etching gas, such as HBr. Since the first etching gas first contacts the first initial bit line conductive layer 14 with a higher top surface, the first etching gas first etches the first initial bit line conductive layer 14, so that the first etching gas can be realized First, the first initial bit line conductive layer 14 is etched.
  • the etching selection of the second initial bit line conductive layer 15 by the second etching gas is relatively small, so that the etching rate of the second initial bit line conductive layer 15 by the first etching gas is greater than the etching rate of the second initial bit line conductive layer 15 by the second etching gas.
  • it also includes: forming a first initial adhesion layer 16 between the first conductive layer 211 and the first initial bit line conductive layer 14, forming a first initial adhesion layer 16 between the second conductive layer 212 and the second initial bit line A second initial adhesion layer 17 is formed between the wire conductive layers 15 .
  • the first initial adhesion layer 16 and the second initial adhesion layer 17 can increase the adhesion between the first conductive layer 211 and the first initial bit line conductive layer 14 and the adhesion between the second conductive layer 212 and the second initial bit line conductive layer 15.
  • the adhesion between them is conducive to improving the electrical connection performance between the first conductive layer 211 and the first initial bit line conductive layer 14 and the electrical connection between the second conductive layer 212 and the second initial bit line conductive layer 15 performance.
  • the materials of the first initial adhesion layer 16 and the second initial adhesion layer 17 may be the same, and the first initial adhesion layer 16 and the second initial adhesion layer 17 may be formed in the same process step, and the first initial adhesion layer The top surface of layer 16 is higher than the top surface of second initial adhesion layer 17 .
  • a deposition process may be used to form the first initial adhesion layer 16 and the second initial adhesion layer 17 .
  • the material of the first initial adhesion layer 16 and the second initial adhesion layer 17 may be at least one of titanium nitride or titanium.
  • a first adhesive layer 241 and a second adhesive layer 242 are formed.
  • the third etching process designed for the initial adhesion layer 16 etches the first initial adhesion layer 16 , the third etching process will also etch the remaining second initial bit line conductive layer 15 . Since the material of the first initial adhesion layer 16 is different from that of the first initial bit line conductive layer 14, the etching selection of the first initial bit line conductive layer 14 in the third etching process is relatively small, so that the third etching process The etching options for the second initial bit line conductive layer 15 are relatively small.
  • the etching rate of the second initial bit line conductive layer 15 by the third etching process is lower than the etching rate of the second initial bit line conductive layer 15 by the first etching process, so that the conductive layer 15 in the second initial bit line
  • the layer 15 points to the direction of the second conductive layer 212, and the width of the part of the second bit line conductive layer 222 formed by the third etching process increases gradually.
  • the first conductive layer 211 is etched by the second etching process. Since the second etching process also etches the remaining second initial bit line conductive layer 15, in the direction where the second initial bit line conductive layer 15 points to the second conductive layer 212, the second etching process forms The width of the second bit line conductive layer 222 also gradually increases, and when the second initial adhesion layer 17 is subsequently etched, the formed second adhesion layer 242 will continue the morphology of the second bit line conductive layer 222, that is, The second adhesive layer 242 points to the direction of the second conductive layer 212 , and the width of the second adhesive layer 242 gradually increases.
  • the shape of the second adhesive layer 242 can also be used as a mold to form the bit line contact structure 232 on the top surface of the bit line contact structure 232. In the direction of the bottom surface, the width of the bit line contact structure 232 gradually increases.
  • it also includes: forming a first initial insulating layer 18 on the top surface of the first initial bit line conductive layer 14, and forming a second initial insulating layer 18 on the top surface of the second initial bit line conductive layer 15. initial insulating layer 19 .
  • the first initial insulating layer 18 and the second initial insulating layer 19 may be made of the same material, and the first initial insulating layer 18 and the second initial insulating layer 19 may be formed in the same process step.
  • the first initial insulating layer 18 Since the top surface of the first initial bit line conductive layer 14 is higher than the top surface of the second initial bit line conductive layer 15, when the first initial insulating layer 18 and the second initial insulating layer 19 are formed in the same process step, the first initial insulating layer The top surface of layer 18 is higher than the top surface of second initial insulating layer 19 .
  • the material of the first initial insulating layer 18 and the second initial insulating layer 19 may include any one of silicon oxide or silicon nitride.
  • a first insulating layer 251 and a second insulating layer 252 are formed.
  • the fourth etching process can be used to etch the first initial insulating layer 18 until the first initial bit line conductive layer 14 is exposed, so as to form the first insulating layer 251;
  • the second initial insulating layer 19 is subjected to the fourth etching process, and the second initial insulating layer 19 is not completely etched. Since the top surface of the first initial insulating layer 18 is higher than the top surface of the second initial insulating layer 19, in the same process step, a fourth etching process is used to etch the first initial insulating layer 18 and the second initial insulating layer 19.
  • the fourth etching process first etches the first initial insulating layer 18, and when the fourth etching process has etched the first initial insulating layer 18, the second initial insulating layer 19 has not been etched yet .
  • the first initial bit line conductive layer 14 is etched using the first etching process, and at the same time, the remaining second initial insulating layer 19 is etched using the first etching process.
  • Etching to form the second insulating layer 252 the etching rate of the second initial insulating layer 19 by the fourth etching process is greater than the etching rate of the second initial insulating layer 19 by the first etching process.
  • the first etching process is an etching process designed based on the first initial bit line conductive layer 14, and the material of the first initial bit line conductive layer 14 is different from the material of the first initial insulating layer 18, the first etching process
  • the etching options for the second initial insulating layer 19 are relatively small.
  • the width of the second insulating layer 252 formed by the first etching process gradually increases.
  • the subsequent formation of the second bit line conductive layer 222, the second adhesive layer 242 and the bit line contact structure 232 all have a gradually increasing width in the direction in which the second insulating layer 252 points to the second bit line conductive layer 222 .
  • the second conductive layer 212 is etched to form a bit line contact structure 232 surrounding the cavity 20.
  • the bit line contact In the direction along the top surface of the bit line contact structure 232 pointing to the bottom surface of the bit line contact structure 232, the bit line contact The width of the structures 232 gradually increases.
  • the second etching process may continue to etch the second conductive layer 212 . Since the second initial bit line conductive layer 15 points to the direction of the second conductive layer 212, the width of the second bit line conductive layer 222 formed by the second etching process gradually increases, and the second etching process is in the direction of the second conductive layer 212.
  • the bit line contact structure 232 When the layer 212 is etched to form the bit line contact structure 232, the topography of the second bit line conductive layer 222 in contact with the second conductive layer 212 can be continued, so that the top surface of the bit line contact structure 232 points to the bit line contact In the direction of the bottom surface of the structure 232, the bit line contact structure 232 also has a shape whose width gradually increases. That is to say, along the direction along the top surface of the bit line contact structure 232 to the cavity 20 , the width of the bit line contact structure 232 gradually increases, so that the width of the bit line contact structure 232 opposite to the cavity 20 is larger. Referring to FIG.
  • the first conductive structure 231 and the first bit line conductive layer 221 constitute the first bit line 1
  • the bit line contact structure 232 and the second bit line conductive layer 222 constitute the second bit line 2
  • It also includes: forming a bit line protection layer 260 on the sidewall of the first bit line 1 and the side wall of the second bit line 2 .
  • the bit line protection layer 260 is used to protect the first bit line 1 and the second bit line 2.
  • the capacitive contact structure 270 is isolated from the bit line contact structure 232 to prevent the short circuit of the semiconductor structure caused by the electrical connection between the capacitive contact structure 270 and the bit line contact structure 232 .
  • the bit line protection layer 260 can be a multi-layer structure, for example, it can be a first bit line protection layer 261, a second bit line protection layer 262 and a third bit line protection layer 263 arranged in sequence, wherein, The material of the first bit line protection layer 261 can be the same as that of the third bit line protection layer 263 , such as silicon nitride, and the material of the second bit line protection layer 262 can be silicon oxide.
  • the bit line protection layer 260 is configured as a multi-layer structure, so that the bit line protection layer 260 has relatively strong hardness and can better protect the bit lines.
  • a deposition process may be used to form the bit line protection layer 260 on the sides of the first bit line 1 and the second bit line 2 .
  • the deposition process may be any one of chemical vapor deposition, physical vapor deposition, atomic layer deposition, or metal organic compound chemical vapor deposition.
  • the first adhesive layer 241 is formed between the first conductive structure 231 and the first bit line conductive layer 221, and the second adhesive layer is formed between the bit line contact structure 232 and the second bit line conductive layer 222.
  • the first insulating layer 251 is formed on the top surface of the first bit line conductive layer 221, and the second insulating layer 252 is formed on the top surface of the second bit line conductive layer 222
  • the bit line protective layer 260 is also located: on the first The side of the adhesive layer 241 , the side of the second adhesive layer 242 , the side of the first insulating layer 251 and the side of the second insulating layer 252 .
  • the bit line protection layer 260 after forming the bit line protection layer 260 on the sides of the first bit line 1 and the second bit line 2, it further includes: forming a capacitive contact structure between adjacent bit line protection layers 260 270.
  • the formed capacitive contact structure 270 is also located in part of the substrate 200 . The capacitive contact structure 270 is used to lead out the electrical signal of the source/drain in the substrate 200 and form an electrical connection with the capacitive structure (not shown).
  • the method for forming the capacitive contact structure 270 may include: patterning the substrate 200 between adjacent bit line protection layers 260, in some embodiments, adjacent bit line protection layers 260 may be The layer 260 is used as a mask to pattern the substrate 200, which facilitates the simplification of the process flow; the surface of the patterned substrate 200 is etched to form a groove with a predetermined depth in the substrate 200; The capacitive contact structure 270 is formed in the groove using a deposition process, and the capacitive contact structure 270 is also formed between adjacent bit line protection layers 260 .
  • the material of the capacitive contact structure 270 may be polysilicon.
  • the top surface of the first initial bit line conductive layer 14 is set higher than the top surface of the second initial bit line conductive layer 15, and the top surface of the first conductive layer 211 The surface is higher than the top surface of the second conductive layer 212 .
  • the height difference between the first initial bit line conductive layer 14 and the second initial bit line conductive layer 15, and the height difference between the first conductive layer 211 and the second conductive layer 212 are converted into the first etching
  • the etching rate difference between the first etching process and the second etching process when etching the second initial bit line conductive layer 15 is different.
  • bit line contact structure 232 In the direction in which the second bit line conductive layer 222 points to the second conductive layer 212, a portion of the second bit line conductive layer 222 facing the second conductive layer 212 will form a shape with a gradually increasing width, so that the subsequent second conductive layer 212 is etched to form the bit line contact structure 232, the bit line contact structure 232 will also continue the shape of the second conductive layer 212, so that the width of the bit line contact structure 232 facing the hole 20 is relatively large, so that the bit line After the capacitive contact structure 270 is formed on both sides of the contact structure 232 , it is not easy to penetrate through the sidewall of the bit line contact structure 232 corresponding to the cavity 20 , thereby improving the phenomenon of short circuit in the semiconductor structure.
  • An embodiment of the present disclosure also provides a semiconductor structure, which can be prepared by the method for preparing a semiconductor structure provided in the above embodiments.
  • the semiconductor structure provided by an embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.
  • the semiconductor structure includes: a substrate 200, the substrate 200 has a concave hole 10, the surface of the substrate 200 exposes the opening of the concave hole 10; a bit line contact structure 232, the bit line contact structure 232 is located in the concave hole 10, and the bit line The contact structure 232 is wrapped with the cavity 20, and along the direction from the top surface of the bit line contact structure 232 to the bottom surface of the bit line contact structure 232, the width of the bit line contact structure 232 gradually increases; the first conductive structure 231, the first conductive The structure 231 is located on the surface of the substrate 200, and in the direction perpendicular to the substrate 200, the width of the first conductive structure 231 is constant; the first bit line conductive layer 221 and the second bit line conductive layer 222, the first bit line conductive layer 221 Located on the side of the first conductive structure 231 away from the substrate 200, the second bit line conductive layer 222 is located on the side of the bit line contact structure 232 away from the substrate 200, the top surface of the first
  • the width of the bit line contact structure 232 is gradually increased, that is, in the direction along the top surface of the bit line contact structure 232 pointing to the cavity 20 In the direction of , the width of the bit line contact structure 232 gradually increases, so that the width of the bit line contact structure 232 opposite to the cavity 20 is larger.
  • the capacitive contact structure 270 is formed on both sides of the bit line contact structure 232, it will not penetrate through the side wall of the bit line contact structure 232 corresponding to the cavity 20, thereby preventing the formed capacitive contact structure 270 from contacting the bit line.
  • the problem of forming an electrical connection between the structures 232 through the penetrated bit line contact structure 232 reduces the possibility of a short circuit in the semiconductor structure.
  • the top width of the bit line contact structure 232 is 5 nm ⁇ 10 nm. Because part of the bit line contact structure 232 is located in the concave hole 10, it is connected to the source/drain in the substrate 200, and is used to extract the signal of the source/drain, and the side wall of the part of the bit line contact structure 232 located in the concave hole 10 There is also a bit line protection layer 260 for isolating the bit line contact structure 232 from other conductive structures in the substrate 200 . If the bit line protection layer 260 is too thin, the bit line protection layer 260 may not achieve a good isolation effect, which may cause leakage in the substrate 200 .
  • the width of the top of the bit line contact structure 232 is 5 nm ⁇ 10 nm, the width of the bit line contact structure 232 is not too large, so that the bit line protection layer 260 in the concave hole 10 has a relatively large thickness.
  • the width of the bit line contact structure 232 is not too small, so that the problem that the effect of wrapping the cavity 20 cannot be achieved due to the too small width of the bit line contact structure 232 can be prevented. .
  • the bottom width of the bit line contact structure 232 is 10 nm ⁇ 15 nm. Within this range, on the one hand, the bottom of the bit line contact structure 232 has a larger width, so that in the direction along the top surface of the bit line contact structure 232 to the bottom surface of the bit line contact structure 232, the width of the bit line contact structure 232 The gradually increasing range is larger, so that the bit line contact structure 232 facing the cavity 20 has a larger width, which can better wrap the cavity 20, that is, the side wall of the bit line contact structure 232 facing the cavity 20 has a Greater thickness.
  • the capacitive contact structure 270 is formed on both sides of the bit line contact structure 232, it is not easy to occur that the side wall of the bit line contact structure 232 facing the cavity 20 is too thin, resulting in a through hole in the process.
  • the problem of the sidewall of the bit line contact structure 232 corresponding to the cavity 20 can further improve the problem of a short circuit in the semiconductor structure.
  • the width of the bottom of the bit line contact structure 232 is not too large, so that the bit line protection layer 260 located in the concave hole 10 can have a larger thickness.
  • the bit line contact structure 232 has opposite side walls and a bottom wall connected to the side walls, the side wall of the bit line contact structure 232 and the bottom wall of the bit line contact structure 232 have a first angle, The first included angle is 60°-80°.
  • the size of the first angle is related to the width of the top surface and the width of the bottom surface of the bit line contact structure 232. Within this range, the width of the top surface of the bit line contact structure 232 will not be too small, so that the top surface of the bit line contact structure 232 The face width is not too small compared to the bottom face width.
  • the gradually increasing width of the bit line contact structure 232 will not be too large. is too large, so that the bit line protection layer 260 located in the concave hole 10 has a relatively large thickness, on the other hand, it can prevent the bit line contact structure 232 facing the hole 20 from being at a position with a small width, causing The problem that the bit line contact structure 232 cannot cover the cavity 20 well.
  • the width of the second bit line conductive layer 222 gradually increases along the direction from the top of the second bit line conductive layer 222 to the bottom of the second bit line conductive layer 222 .
  • the second bit line conductive layer 222 on the top surface of the bit line contact structure 232 needs to be etched first.
  • the width of the second bit line conductive layer 222 gradually increases, so that in the actual manufacturing process, the formed bit line contact structure 232
  • the shape of the second bit line conductive layer 222 can be continued, that is, along the direction from the top surface of the bit line contact structure 232 to the bottom surface of the bit line contact structure 232, a shape in which the width of the bit line contact structure 232 gradually increases is also formed. appearance.
  • the width of the first bit line conductive layer 221 is constant in a direction along the top of the first bit line conductive layer 221 toward the bottom of the first bit line conductive layer 221 .
  • the width of the first conductive structure 231 gradually increases, the width of the first conductive structure 231 is set to be constant, so that the first conductive structure There is a larger space between the first conductive structure 231 and the bit line contact structure 232 , which reserves a larger space for subsequent formation of the bit line protection layer 260 and the capacitor contact structure 270 between the first conductive structure 231 and the bit line contact structure 232 .
  • the subsequently formed bit line protection layer 260 can have a larger thickness, which can better isolate the bit line contact structure 232 from the capacitive contact structure 270; on the other hand, the formed capacitive contact structure 270 has a larger thickness.
  • the volume is beneficial to improve the electrical performance of the capacitive contact structure 270 .
  • it further includes: a first adhesive layer 241 and a first insulating layer 251, the first adhesive layer 241 is located between the first conductive structure 231 and the first bit line conductive layer 221, and the first insulating layer 251 is located between the first bit line conductive layer 221.
  • the first adhesive layer 241 and the second adhesive layer 242 can increase the adhesion between the first conductive structure 231 and the first bit line conductive layer 221 and the adhesion between the bit line contact structure 232 and the second bit line conductive layer 222.
  • Adhesion is beneficial to improve the electrical connection performance between the first conductive structure 231 and the first bit line conductive layer 221 and the electrical connection performance between the bit line contact structure 232 and the second bit line conductive layer 222 .
  • the second adhesive layer 242 needs to be etched first. As the width of the second adhesive layer 242 gradually increases toward the bottom of 242 , the formed bit line contact structure 232 will continue the shape of the second adhesive layer 242 , which makes the process of preparing the bit line contact structure 232 relatively simple.
  • the first insulating layer 251 and the second insulating layer 252 are used to protect the first bit line conductive layer 221 and the second bit line conductive layer 222;
  • the line conductive layer 222 is isolated from other conductive structures.
  • the first conductive structure 231 and the first bit line conductive layer 221 form the first bit line 1
  • the bit line contact structure 232 and the second bit line conductive layer 222 form the second bit line 2
  • the semiconductor structure further includes the first adhesive layer 241, the first insulating layer 251, the second adhesive layer 242, and the second insulating layer 252
  • the first adhesive layer 241 and the first insulating layer can also serve as a part of the first bit line 1
  • the second adhesive layer 242 and the second insulating layer 252 can also serve as a part of the second bit line 2 .
  • bit line protection layer 260 located on the sidewalls of the first bit line 1 and the second bit line 2 , and part of the bit line protection layer 260 is also located in the concave hole 10 .
  • the bit line protection layer 260 is used to protect the first bit line 1 and the second bit line 2.
  • the capacitive contact structure 270 is isolated from the bit line contact structure 232 to prevent the short circuit of the semiconductor structure caused by the electrical connection between the capacitive contact structure 270 and the bit line contact structure 232 .
  • bit line protection layer 260 Part of the bit line protection layer 260 is located in the concave hole 10 and is used to isolate the bit line contact structure 232 from other conductive structures in the substrate 200 to prevent electric leakage in the substrate 200 .
  • the bit line protection layer 260 can be a multi-layer structure, for example, it can be a first bit line protection layer 261, a second bit line protection layer 262 and a third bit line protection layer 263 arranged in sequence, wherein, the first bit line protection layer 260
  • the material of the bit line protection layer 261 can be the same as that of the third bit line protection layer 263 , such as silicon nitride, and the material of the second bit line protection layer 262 can be silicon oxide.
  • it further includes: a capacitive contact structure 270 located between adjacent bit line protection layers 260 .
  • the capacitive contact structure 270 is also located in part of the substrate 200 . The capacitive contact structure 270 is used to lead out the electrical signal of the source/drain in the substrate 200 and form an electrical connection with the capacitive structure (not shown).
  • the bit line contact structure 232 increases gradually along the direction from the top surface of the bit line contact structure 232 to the bottom surface of the bit line contact structure 232, that is, in the direction along the hole 20 to the bottom surface of the bit line contact structure 232, the bit line The width of the line contact structure 232 increases gradually, so that the width of the bit line contact structure 232 facing the cavity 20 is larger, which can better wrap the cavity 20 .
  • the capacitive contact structure 270 In the process of actually manufacturing the capacitive contact structure 270, it is not easy to penetrate the sidewall of the bit line contact structure 232 corresponding to the cavity 20, thereby preventing the formed capacitive contact structure 270 and the bit line contact structure 232 from passing through the bit line.
  • the problem of forming an electrical connection with the contact structure 232 is beneficial to reduce the probability of a short circuit in the semiconductor structure.
  • the width of the bit line contact structure 232 gradually increases by being arranged along the direction from the top surface of the bit line contact structure 232 to the bottom surface of the bit line contact structure 232, so that the width of the bit line contact structure 232 is directly opposite to the cavity 20.
  • the width of the bit line contact structure 232 is larger, so that the bit line contact structure 232 can better wrap the cavity 20 .
  • the problem of forming an electrical connection between the structures 232 through the penetrated bit line contact structure 232 reduces the possibility of a short circuit in the semiconductor structure.
  • the height difference between the first initial bit line conductive layer and the second initial bit line conductive layer, and the height difference between the first conductive layer and the second conductive layer are converted
  • part of the second bit line conductive layer facing the second conductive layer will A shape whose width gradually increases is formed, so that when the second conductive layer is subsequently etched, the shape of the second bit line conductive layer will be continued.
  • the side wall of the bit line contact structure facing the hole is thicker, so that after the capacitive contact structure is formed on both sides of the bit line contact structure, it will not penetrate through the side wall of the bit line contact structure corresponding to the hole, The possibility of short circuits in the semiconductor structure is thereby reduced.

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Abstract

本公开公布了一种半导体结构的制备方法及半导体结构，涉及半导体领域，半导体结构的制备方法包括：设置第二导电层顶面低于第一导电层的顶面；设置第一初始位线导电层的顶面高于第二初始位线导电层的顶面；采用第一刻蚀工艺对第一初始位线导电层进行刻蚀，同时对部分第二初始位线导电层进行第一刻蚀工艺；采用第二刻蚀工艺对第一导电层进行刻蚀，同时对剩余的第二初始位线导电层进行刻蚀，且第一刻蚀工艺对第二初始位线导电层的刻蚀速率大于第二刻蚀工艺对与第二初始位线导电层的刻蚀速率；形成包裹空洞的位线接触结构，在沿位线接触结构顶面指向位线接触结构底面的方向上，位线接触结构的宽度逐渐增大。

Description

半导体结构的制备方法及半导体结构
本公开基于申请号为202210051482.8、申请日为2022年01月17日、申请名称为“半导体结构的制备方法及半导体结构”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开实施例涉及但不限于一种半导体结构的制备方法及半导体结构。
背景技术
随着集成电路技术的快速发展，集成电路中器件的密集度越来越高，半导体器件的特征尺寸不断减小，在制作过程中，为了引出源/漏极信号，通常会在半导体结构中制备电容接触结构以及位线接触结构。
电容接触结构与半导体结构中源/漏极的其中一者连接，以使电容与源/漏极形成电连接，位线接触结构与半导体结构中源/漏极的另一者连接，以使位线与源/漏极形成电连接，从而可以通过位线读取存储在电容器中的数据信息，或者将数据信息写入到电容器中，保证半导体器件的正常运行。
然而，采用目前的工艺用于制备半导体结构时，可能存在半导体结构发生短路的问题。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种半导体结构的制备方法及半导体结构。
根据本公开的第一方面，本公开实施例提供了一种半导体结构的制备方法，包括：提供衬底，衬底具有凹孔，衬底表面露出凹孔的开口；形成导电层，导电层包括：第一导电层以及第二导电层，第一导电层位于衬底表面，第二导电层位于凹孔中，第二导电层顶面低于第一导电层的顶面，且位于凹孔中的第二导电层具有空洞；在第一导电层远离衬底的一侧形成第一初始位线导电层，在第二导电层远离衬底的一侧形成第二初始位线导电层，第一初始位线导电层的顶面高于第二初始位线导电层的顶面；采用第一刻蚀工艺对第一初始位线导电层进行刻蚀直至露出第一导电层时停止，以形成第一位线导电层，同时，对部分第二初始位线导电层进行第一刻蚀工艺，第二初始位线导电层未被完全刻蚀；采用第二刻蚀工艺对第一导电层进行刻蚀，形成第一导电结构，在垂直于衬底方向上，第一导电结构的宽度不变，同时，采用第二刻蚀工艺对剩余的第二初始位线导电层进行刻蚀，以形成第二位线导电层，且第一刻蚀工艺对第二初始位线导电层的刻蚀速率大于第二刻蚀工艺对与第二初始位线导电层的刻蚀速率；刻蚀第二导电层，形成包裹空洞的位线接触结构，在沿位线接触结构的顶面指向位线接触结构底面的方向上，位线接触结构的宽度逐渐增大。
根据本公开的第二方面，本公开实施例还提供了一种半导体结构，包括：衬底，衬底具有凹孔，衬底表面露出凹孔的开口；位线接触结构，位线接触结构位于凹孔中，位线接触结构包裹有空洞，且在沿位线接触结构的顶面指向位线接触结构底面的方向上，位线接触结构的宽度逐渐增大；第一导电结构，第一导电结构位于衬底表面，在垂直于衬底方向上，第一导电结构的宽度不变；第一位线导电层以及第二位线导电层，第一位线导电层位于第一导电结构远离衬底的一侧，第二位线导电层位于位线接触结构远离衬底的一侧，第一位线导电层的顶面高于第二位线导电层的顶面。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1至图3为一种半导体结构的制备方法中各步骤对应的结构示意图；
图4为本公开一实施例提供的一种半导体结构的制备方法中形成第一初始导电层的步骤对应的结构示意图；
图5为本公开一实施例提供的一种半导体结构的制备方法中形成第二初始导电层的步骤对应的结构示意图；
图6为本公开一实施例提供的一种半导体结构的制备方法中形成第一导电层以及第二导电层的步骤对应的结构示意图；
图7为本公开一实施例提供的一种半导体结构的制备方法中去除第一牺牲层13的步骤对应的结构示意图；
图8为本公开一实施例提供的一种半导体结构的制备方法中形成第一初始位线导电层以及第二初始位线导电层的步骤对应的结构示意图；
图9为本公开一实施例提供的一种半导体结构的制备方法中对第二牺牲层进行图形化处理的步骤对应的结构示意图；
图10为本公开一实施例提供的一种半导体结构的制备方法中形成位线接触结构的步骤对应的结构示意图；
图11为本公开一实施例提供的一种半导体结构的制备方法中形成第一初始黏附层以及第二初始黏附层的步骤对应的结构示意图；
图12为本公开一实施例提供的另一种半导体结构的制备方法中形成位线接触结构的步骤对应的结构示意图；
图13为本公开一实施例提供的另一种半导体结构的制备方法中形成位线保护层以及电容接触结构的步骤对应的结构示意图。
附图标记说明：
200、衬底；10、凹孔；11、第一初始导电层；12、第二初始导电层；13、第一牺牲层；14、第一初始位线导电层；15、第二初始位线导电层；16、第一初始黏附层；17、第二初始黏附层；18、第一初始绝缘层；19、第二初始绝缘层；20、空洞；210、导电层；211、第一导电层；212、第二导电层；221、第一位线导电层；222、第二位线导电层；231、第一导电结构；232、位线接触结构；241、第一黏附层；242、第二黏附层；251、第一绝缘层；252、第二绝缘层；1、第一位线；2、第二位线；260、位线保护层；261、第一位线保护层；262、第二位线保护层；263、第三位线保护层；270、电容接触结构；280、第二牺牲层。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中 的特征可以相互任意组合。
由背景技术可知，采用目前的工艺制备半导体结构时，可能存在半导体结构发生短路的问题。
分析发现，导致半导体结构可能发生短路的原因之一在于，在制备位线接触结构时，需要在衬底中先制备凹孔，再在凹孔中填充初始导电层，由于凹孔具有较大的深宽比，因此在形成初始导电层时，会在初始导电层中形成空洞。由于该空洞的存在，使得后续在位线接触结构两侧形成电容接触结构时，可能会发生位于位线接触结构两侧的电容接触结构形成电连接，而导致半导体结构发生短路的现象。
结合一种半导体结构的制备方法对上述问题的原因进行进一步分析，图1至图3为一种半导体结构的制备方法中各步骤对应的结构示意图。参考图1，在衬底100的凹孔10中形成位线接触结构110，由于凹孔10中的初始导电层(未图示)中具有空洞20，在对凹孔10中的初始导电层进行刻蚀以形成位线接触结构110时，使得刻蚀工艺对与空洞20正对的初始导电层处的刻蚀速率较大，从而形成具有颈状形貌的位线接触结构110，即与空洞20正对的位线接触结构110的侧壁较薄。参考图2，在位线接触结构110两侧形成位线保护层130，由于与空洞20正对的位线接触结构110的侧壁较薄，在形成位线保护层130的工艺过程中，有可能会对位线接触结构110产生工艺损伤，而导致与空洞20正对的位线接触结构110的侧壁被去除，从而在位线接触结构110中形成一条通道30。参考图3，在位线接触结构110两侧形成电容接触结构140，由于位线接触结构110中形成了一条通道，使得在沉积导电材料以形成电容接触结构140时，导电材料也将位于通道30处，位于位线接触结构110两侧的电容接触结构140将会通过通道30形成电连接而造成短接。此外，还会使得位线接触结构110与电容接触结构140形成电连接而造成短接，从而导致半导体结构产生短路的现象。
本公开实施例提供一种半导体结构的制备方法，通过设置第一导电层的顶面高于第二导电层的顶面，以及第一初始位线导电层的顶面高于第二初始位线导电层的顶面，使得采用第一刻蚀工艺对第一初始位线以及第二初始位线进行刻蚀时，第一初始位线导电层先被刻蚀完，第二初始位线导电层还未被刻蚀完，因此当采用第二刻蚀工艺开始对第一导电层进行刻蚀时，第二刻蚀工艺还需继续对第二初始位线导电层进行刻蚀。由于第二刻蚀工艺是基于第一导电层设计的工艺，因此第二刻蚀工艺对第二初始位线导电层的刻蚀速率较慢，从而形成的第二位线导电层中，在第二位线导电层指向第二导电层的方向上，部分朝向第二导电层的第二位线导电层的宽度逐渐增大。当后续对第二导电层进行刻蚀时，将延续第二导电层的形貌，使得在沿位线接触结构的顶面指向位线接触结构底面的方向上，位线接触结构的宽度逐渐增大，即与空洞正对的位线接触结构的侧壁厚度逐渐增大，从而后续在位线接触结构两侧形成电容接触结构后，不会贯穿与空洞正对的位线接触结构侧壁，进而减小半导体结构出现短路的可能性。
图4至图7为本公开一示例性实施例提供的半导体结构的制备方法中形成导电层的步骤对应的结构示意图。
参考图4以及图7，提供衬底200，衬底200具有凹孔10，衬底200表面露出凹孔10的开口；形成导电层210，导电层210包括：第一导电层211以及第二导电层212，第一导电层211位于衬底200表面，第二导电层212位于凹孔10中，第二导电层212顶面低于第一导电层211的顶面，且位于凹孔10中的第二导电层212具有空洞20。
在一些实施例中，衬底200的材料为半导体材料。在一些实施例中，衬底200的材料为硅。在另一些实施例中，衬底200也可以为锗基底、锗硅基底、碳化硅基底或者绝缘体 上的硅基底。
在一些实施例中，形成凹孔10的方法可以包括：对衬底200进行图形化处理，用于定义凹孔10的开口位置；对图形化的衬底200表面进行刻蚀，以在衬底200内形成设定深度的凹孔10。由于凹孔10具有较大的深宽比，后续在凹孔10中形成第二导电层212时，第二导电层212会形成空洞20。
在一些实施例中，形成第二导电层212的顶面低于第一导电层211的顶面的方法包括：
参考图4以及图5，形成第一初始导电层11以及第二初始导电层12，第一初始导电层11覆盖衬底200表面，第二初始导电层12填满凹孔10。具体地，参考图4，在一些实施例中，可以在形成凹孔10前，在衬底200表面形成第一初始导电层11，可以采用沉积工艺在衬底200表面形成第一初始导电层11。在一些实施例中，在形成凹孔10前，可以在第一初始导电层11顶面形成第一牺牲层13，以对第一初始导电层11表面进行图形化处理。接着对图形化的第一初始导电层11表面进行刻蚀，直至露出部分衬底200，并在衬底200内形成设定深度的凹孔10，且剩余的第一初始导电层11可以作为第一导电层211。在一些实施例中，第一牺牲层13的材料可以是氧化硅，在另一些实施例中，第一牺牲层13的材料也可以是碳材料、SOC材料、硼硅玻璃、硼磷硅玻璃或者正硅酸乙酯中的任一种。
参考图5，在一些实施例中，可以采用沉积工艺在凹孔10中形成第二初始导电层12，且第二初始导电层12还位于第一牺牲层13顶面。在一些实施例中，沉积工艺可以包括：化学气相沉积、物理气相沉积、原子层沉积、或者金属有机化合物化学气相沉淀中的任一者。在一些实施例中，第一初始导电层11的材料与第二初始导电层12的材料可以相同，例如可以是多晶硅材料。
参考图6，对第二初始导电层12顶面进行初始刻蚀工艺，以形成第二导电层212，且第二导电层212的顶面低于第一导电层211的顶面。具体地，在一些实施例中，初始刻蚀工艺为回刻蚀工艺，采用回刻蚀工艺对第二初始导电层12进行刻蚀，去除高于第一牺牲层13顶面的第二初始导电层12，以及部分与第一导电层211接触的第二初始导电层12，以形成第二导电层212，第二导电层212的顶面低于第一导电层211的顶面。在一些实施例中，初始刻蚀工艺可以是干法刻蚀工艺。第二导电层212的顶面低于第一导电层211的顶面，使得后续在同一工艺步骤中，参考图8所示，在第一导电层211顶面形成第一初始位线导电层14以及在第二导电层212顶面形成第二初始位线导电层15时，使得第二初始位线导电层15的顶面可以低于第一初始位线导电层14的顶面。使得后续再对第一初始位线导电层14、第二初始位线导电层15、第一导电层211、以及第二导电层212进行刻蚀时，可以将第一初始位线导电层14与第二初始位线导电层15的高度差，以及第一导电层211与第二导电层212的高度差转换为对第二初始位线导电层15进行刻蚀工艺时的刻蚀速率差，使得第二刻蚀工艺形成的第二位线导电层222，具有上窄下宽的梯形形貌，结合图9和图10所示，使得后续对第二导电层212进行刻蚀时，将延续第二位线导电层222的形貌，从而可以形成位线接触结构232也具有上窄下宽的梯形形貌。
在一些实施例中，对第二初始导电层12进行初始刻蚀工艺的时间为8s～16s。控制刻蚀工艺时间在8s～16s这个范围内，使得刻蚀时间不至于过长，使形成的第二导电层212相对于第一导电层211不至于过低，从而可以使得后续形成的第二初始位线导电层15相对于第一初始位线导电层14不至于过低(参考图8)，即可以防止第二刻蚀工艺对第二初始位线导电层15的刻蚀时间过长，从而使得形成的第二位线导电层222底部的宽度过大的问题(参考图10)。从而后续在沿着第二位线导电层222的形貌刻蚀第二导电层212 以形成位线接触结构232时，位线接触结构232底部的宽度不至于过大，即，可以防止发生由于位线接触结构232在凹孔10中所占的体积过大，而导致后续在位线接触结构232两侧形成位线保护层260时，形成于凹孔10中的位线保护层260过薄，使得位线保护层260可能达不到较好的隔离效果的问题(参考图13)，从而可以防止衬底200中产生漏电的问题。控制刻蚀工艺时间在8s～16s这个范围内还可以使得刻蚀时间不至于过短，即使得后续形成的第二初始位线导电层15顶面到第一初始位线导电层14顶面的高度差不至于过小，可以防止由于第二刻蚀工艺对第二初始位线导电层15的刻蚀时间过短而达不到形成的位线接触结构232具有上窄下宽的梯形形貌的问题。
在一些实施例中，参考图6所示，在垂直于衬底200方向上，第二导电层212顶面到第一导电层211顶面的高度差d1为8nm～16nm。需要考虑到形成的位线接触结构232在凹孔10中所占的体积不能过大，换句话说，需要在凹孔10中为后续在位线接触结构232两侧形成位线保护层260预留一定的空间，这是因为，若位线保护层260过薄，可能会使得衬底200发生漏电的问题(参考图13)。另一方面，则要考虑到在沿位线接触结构232的顶面指向位线接触结构232底面的方向上，需要形成位线接触结构232的宽度逐渐增大这一形貌，从而可以使得与空洞20正对的位线接触结构232的侧壁较厚，使得后续在位线接触结构232两侧形成位线保护层260以及电容接触结构270时，不容易发生与空洞20正对的位线接触结构232侧壁由于过薄而被贯穿，从而导致位于位线接触结构232两侧的电容接触结构270通过被贯穿的位线接触结构232产生电连接而导致半导体结构短路的问题。考虑到以上这两点，设置第二导电层212顶面到第一导电层211顶面的高度差d1为8nm～16nm，可以较大地减小半导体结构发生短路的可能性，同时还能保持半导体结构较好的性能。
值得注意的是，在一些实施例中，可以调节对第二初始导电层12进行初始刻蚀工艺的时间，以调节第二导电层212顶面到第一导电层211顶面的高度差。在另一些实施例中，也可以预先确定第二导电层212顶面到第一导电层211顶面的待形成高度差，再结合初始刻蚀工艺的刻蚀速率，以确定初始刻蚀工艺的时间。例如，在一些实施例中，初始刻蚀工艺的速率为1nm/s，则可以基于第二导电层212顶面到第一导电层211顶面的高度差为8nm～16nm，控制对第二初始导电层12进行初始刻蚀工艺的时间为8s～16s。
参考图7，去除第一牺牲层13，以使得后续可以在第一导电层211顶面形成第一初始位线导电层。
参考图8，在第一导电层211远离衬底200的一侧形成第一初始位线导电层14，在第二导电层212远离衬底200的一侧形成第二初始位线导电层15，第一初始位线导电层14的顶面高于第二初始位线导电层15的顶面。
在一些实施例中，可以在同一工艺步骤中，采用沉积工艺在第一导电层211远离衬底200的一侧沉积第一初始位线导电层14，在第二导电层212远离衬底200的一侧形成第二初始位线导电层15。在一些实施例中，形成第一初始位线导电层14的材料可以与形成第二初始位线导电层15的材料相同，即可以在同一工艺步骤中，同时形成第一初始位线导电层14以及第二初始位线导电层15。由于第二导电层212的顶面低于第一导电层211的顶面，在同一工艺步骤中，在第一导电层211以及第二导电层212的基础上形成第一初始位线导电层14以及第二初始位线导电层15时，使得形成的第一初始位线导电层14与第二初始位线导电层15也具有与第一导电层211以及第二导电层212相似的形貌，即第一初始位线导电层14的顶面也高于第二初始位线导电层15的顶面。在后续的刻蚀步骤中，可以将第一初始位线导电层14与第二初始位线导电层15的高度差，以及第一导电层211与第二导电层212的高度差转换为对第二初始位线导电层15进行刻蚀工艺时的刻蚀速率 差，参考图10所示，以使形成的第二位线导电层222中，朝向第二导电层212的部分第二位线导电层222具有上窄下宽的梯形形貌。使得后续对第二导电层212进行刻蚀时，以朝向第二导电层212的部分第二位线导电层222的形貌作为模子，形成位线接触结构232也具有上窄下宽的梯形形貌。
在一些实施例中，第一初始位线导电层14以及第二初始位线导电层15的材料可以是金属材料，可以包括：钨、铜或者铝中的任一种。
在一些实施例中，在垂直于衬底200方向上，第一初始位线导电层14的长度小于第二初始位线导电层15的长度。相较于第一初始位线导电层14的长度等于第二初始位线导电层15的长度而言，设置第二初始位线导电层15的长度更长，后续在采用第二刻蚀工艺对第二初始位线导电层15进行刻蚀时，使得第二刻蚀工艺对第二初始位线导电层15的刻蚀时间更长，参考图10所示，使得形成的第二位线导电层222的底部宽度更大。后续在沿着第二位线导电层222的形貌继续刻蚀第二导电层212以形成位线接触结构232时，使得位线接触结构232的整体宽度较大，可以进一步增大与空洞20正对的位线接触结构232的侧壁的厚度，进一步防止发生在后续工艺过程中，与空洞20正对的位线接触结构232侧壁被贯穿的问题。
在一些实施例中，形成第一初始位线导电层14的长度小于第二初始位线导电层15的长度的方法可以包括：在第一导电层211以及第二导电层212顶面沉积初始位线导电层，其中位于第一导电层211顶面的初始位线导电层作为第一初始位线导电层14；在第一初始位线导电层14顶面形成掩膜层；在露出的初始位线导电层顶面沉积与初始位线导电层相同的材料，以形成第二初始位线导电层15；去除掩膜层。
在一些实施例中，还包括：在第一初始位线导电层14以及第二初始位线导电层15远离衬底200的一侧形成第二牺牲层280，第二牺牲层280作为掩膜，用于刻蚀具有预设形状的第一初始位线以及第二初始位线。
参考图9，对第二牺牲层280进行图形化处理。
参考图9以及图10，形成位线接触结构232。采用第一刻蚀工艺对第一初始位线导电层14进行刻蚀直至露出第一导电层211时停止，以形成第一位线导电层221，同时，对部分第二初始位线导电层15进行第一刻蚀工艺，第二初始位线导电层15未被完全刻蚀。也就是说，在同一工艺步骤中，采用第一刻蚀工艺对第一初始位线导电层14以及第二初始位线导电层15进行刻蚀。由于第一初始位线导电层14的顶面高于第二初始位线导电层15的顶面，使得第一刻蚀工艺先对第一初始位线导电层14进行刻蚀。当采用第一刻蚀工艺刻蚀完第一初始位线导电层14时，由于第二初始位线导电层15后刻蚀，此时第二初始位线导电层15还未被完全刻蚀完。
采用第二刻蚀工艺对第一导电层211进行刻蚀，形成第一导电结构231，在垂直于衬底200方向上，第一导电结构231的宽度不变，同时，采用第二刻蚀工艺对剩余的第二初始位线导电层15进行刻蚀，以形成第二位线导电层222，且第一刻蚀工艺对第二初始位线导电层15的刻蚀速率大于第二刻蚀工艺对与第二初始位线导电层15的刻蚀速率。第二刻蚀工艺是基于第一导电层211设置刻蚀工艺，在一些实施例中，第一导电层211的材料与第一初始位线导电层14的材料不同，使得第二刻蚀工艺对第一导电层211的刻蚀选择比大于与第二刻蚀工艺对第一初始位线导电层14的刻蚀选择比。当采用第二刻蚀工艺对剩余的第二初始位线导电层15进行刻蚀时，使得第二刻蚀工艺对第二初始位线导电层15的刻蚀选择比较小，可以实现第一刻蚀工艺对第二初始位线导电层15的刻蚀速率大于第二刻蚀工艺对第二初始位线导电层15的刻蚀速率。也就是说，在沿第二初始导电层12顶 部指向第二初始导电层12底部方向上，对第二初始导电层12的刻蚀速率变小，在沿第二初始导电层12顶部指向第二初始导电层12底部方向上，可以使得由第二刻蚀工艺形成的第二位线导电层222具有宽度逐渐变大的形貌。
如图10所示，由于第一刻蚀工艺为基于第一初始位线导电层14设置的刻蚀工艺，第二刻蚀工艺为基于第一导电层211设置的刻蚀工艺，第一刻蚀工艺对第一初始位线导电层14的刻蚀速率等于第二刻蚀工艺对第一导电层211的刻蚀速率，以形成第一导电结构231的宽度不变的形貌。相较于在第一位线导电层221指向第一导电结构231的方向上，第一导电结构231的宽度逐渐增大而言，设置第一导电结构231的宽度不变，使得第一导电结构231与位线接触结构232之间具有更大的空间，结合图13所示，为后续在第一导电结构231与位线接触结构232之间形成位线保护层260以及电容接触结构270预留出较大的空间。一方面使得后续形成的位线保护层260可以具有较大的厚度，可以较好地将位线接触结构232与电容接触结构270隔离开，另一方面，使得形成的电容接触结构270具有较大的体积，有利于提高电容接触结构270的电性能。
在一些实施例中，第一刻蚀工艺以及第二刻蚀工艺可以为干法刻蚀工艺。具体地，在一些实施例中，第一刻蚀工艺可以采用第一刻蚀气体，例如可以为Cl 2；第二刻蚀工艺可以采用第二刻蚀气体，例如可以为HBr。由于第一刻蚀气体先接触到顶面较高的第一初始位线导电层14，使得第一刻蚀气体先对第一初始位线导电层14进行刻蚀，从而可以实现第一刻蚀气体先将第一初始位线导电层14刻蚀完，当采用第二刻蚀气体对第一导电层211进行刻蚀时，第二刻蚀气体对第二初始位线导电层15的刻蚀选择比较小，从而使得第一刻蚀气体对第二初始位线导电层15的刻蚀速率大于第二刻蚀气体对第二初始位线导电层15的刻蚀速率。采用刻蚀气体对第一初始位线导电层14、第一导电层211以及第二初始位线导电层15进行刻蚀，使得第一刻蚀工艺先将第一初始位线导电层14刻蚀完这一步骤较容易实现，且步骤简单，有利于规模化应用。
参考图11，在另一些实施例中，还包括：在第一导电层211与第一初始位线导电层14之间形成第一初始黏附层16，在第二导电层212与第二初始位线导电层15之间形成第二初始黏附层17。第一初始黏附层16以及第二初始黏附层17可以增加第一导电层211和第一初始位线导电层14之间的粘附性以及第二导电层212与第二初始位线导电层15之间的粘附性，有利于提高第一导电层211与第一初始位线导电层14之间的电连接性能以及第二导电层212与第二初始位线导电层15之间的电连接性能。在一些实施例中，第一初始黏附层16以及第二初始黏附层17的材料可以相同，可以在同一工艺步骤中形成第一初始黏附层16以及第二初始黏附层17，且第一初始黏附层16的顶面高于第二初始黏附层17的顶面。在一些实施例中，可以采用沉积工艺形成第一初始黏附层16以及第二初始黏附层17。在一些实施例中，第一初始黏附层16以及第二初始黏附层17的材料可以为氮化钛或者钛中的至少一种。
参考图11以及图12，形成第一黏附层241以及第二黏附层242。在一些实施例中，在形成第一初始黏附层16以及第二初始黏附层17后，在采用第二刻蚀工艺对第一导电层211进行刻蚀之前，还包括；采用第三刻蚀工艺对第一初始黏附层16进行刻蚀；同时，对第二初始位线导电层15进行第三刻蚀工艺，且第一刻蚀工艺对第二初始位线导电层15的刻蚀速率大于第三刻蚀工艺对第二初始位线导电层15的刻蚀速率。由于第一初始位线导电层14的顶面高于第二初始位线导电层15的顶面，当采用第一刻蚀工艺刻蚀完第一初始位线导电层14后，采用基于第一初始黏附层16设计的第三刻蚀工艺对第一初始黏附层16进行刻蚀时，第三刻蚀工艺还将对剩余的第二初始位线导电层15进行刻蚀。由于第一初始黏附层16的材料与第一初始位线导电层14的材料不同，第三刻蚀工艺对第一初始位 线导电层14的刻蚀选择比较小，从而使得第三刻蚀工艺对第二初始位线导电层15的刻蚀选择比较小。也就是说，第三刻蚀工艺对第二初始位线导电层15的刻蚀速率小于第一刻蚀工艺对第二初始位线导电层15的刻蚀速率，使得在第二初始位线导电层15指向第二导电层212的方向上，第三刻蚀工艺所形成的部分第二位线导电层222的宽度逐渐增加。
可以理解的是，当采用第三刻蚀工艺刻蚀完第一初始黏附层16后，采用第二刻蚀工艺对第一导电层211进行刻蚀。由于第二刻蚀工艺还对剩余的第二初始位线导电层15进行刻蚀，使得在第二初始位线导电层15指向第二导电层212的方向上，第二刻蚀工艺所形成的第二位线导电层222的宽度也逐渐增大，后续在对第二初始黏附层17进行刻蚀时，形成的第二黏附层242将延续第二位线导电层222的形貌，即在第二黏附层242指向第二导电层212的方向上，第二黏附层242的宽度逐渐增大。后续在对第二导电层212进行刻蚀以形成位线接触结构232时，也可以以第二黏附层242的形貌为模子，以形成在位线接触结构232顶面指向位线接触结构232底面的方向上，位线接触结构232的宽度逐渐增大的形貌。
继续参考图9以及图11，在一些实施例中，还包括：在第一初始位线导电层14顶面形成第一初始绝缘层18，在第二初始位线导电层15顶面形成第二初始绝缘层19。在一些实施例中，第一初始绝缘层18以及第二初始绝缘层19的材料可以相同，可以在同一工艺步骤中，形成第一初始绝缘层18以及第二初始绝缘层19。由于第一初始位线导电层14顶面高于第二初始位线导电层15顶面，使得在同一工艺步骤中形成第一初始绝缘层18以及第二初始绝缘层19时，第一初始绝缘层18的顶面高于第二初始绝缘层19的顶面。在一些实施例中，第一初始绝缘层18以及第二初始绝缘层19的材料可以包括：氧化硅或者氮化硅中的任一者。
参考图10以及图12，形成第一绝缘层251以及第二绝缘层252。
在一些实施例中，可以采用第四刻蚀工艺对第一初始绝缘层18进行刻蚀，直至露出第一初始位线导电层14时停止，以形成第一绝缘层251；同时，对部分第二初始绝缘层19进行第四刻蚀工艺，第二初始绝缘层19未被完全刻蚀。由于第一初始绝缘层18的顶面高于第二初始绝缘层19的顶面，在同一工艺步骤中，采用第四刻蚀工艺对第一初始绝缘层18以及第二初始绝缘层19进行刻蚀时，使得第四刻蚀工艺先对第一初始绝缘层18进行刻蚀，当第四刻蚀工艺刻蚀完第一初始绝缘层18时，第二初始绝缘层19还未被刻蚀完成。
当第一初始绝缘层18被刻蚀完时，采用第一刻蚀工艺对第一初始位线导电层14进行刻蚀，同时，采用第一刻蚀工艺对剩余的第二初始绝缘层19进行刻蚀，以形成第二绝缘层252，第四刻蚀工艺对第二初始绝缘层19的刻蚀速率大于第一刻蚀工艺对第二初始绝缘层19的刻蚀速率。由于第一刻蚀工艺是基于第一初始位线导电层14设计的刻蚀工艺，且第一初始位线导电层14的材料与第一初始绝缘层18的材料不同，使得第一刻蚀工艺对第二初始绝缘层19的刻蚀选择比较小。在第二绝缘层252指向第二位线导电层222的方向上，采用第一刻蚀工艺形成的第二绝缘层252的宽度逐渐增大。使得后续形成的第二位线导电层222、第二黏附层242以及位线接触结构232在第二绝缘层252指向第二位线导电层222的方向上，均具有宽度逐渐增大的形貌。
参考图10以及图12，刻蚀第二导电层212，形成包裹空洞20的位线接触结构232，在沿位线接触结构232的顶面指向位线接触结构232底面的方向上，位线接触结构232的宽度逐渐增大。在一些实施例中，当第二刻蚀工艺对第二初始位线导电层15刻蚀完成后，第二刻蚀工艺可以继续对第二导电层212进行刻蚀。由于在第二初始位线导电层15指向 第二导电层212的方向上，第二刻蚀工艺形成的第二位线导电层222的宽度逐渐增大，第二刻蚀工艺在对第二导电层212进行刻蚀以形成位线接触结构232时，可以延续与第二导电层212相接触的第二位线导电层222的形貌，使得在位线接触结构232的顶面指向位线接触结构232底面的方向上，位线接触结构232也具有宽度逐渐增大的形貌。也就是说，在沿位线接触结构232的顶面指向空洞20的方向上，位线接触结构232的宽度逐渐增大，从而使得与空洞20正对的位线接触结构232的宽度较大。参考图13所示，使得后续在位线接触结构232两侧形成电容接触结构270后，不会贯穿与空洞20对应的位线接触结构232侧壁，从而减小半导体结构出现短路的可能性。
参考图13，在一些实施例中，第一导电结构231与第一位线导电层221构成第一位线1，位线接触结构232与第二位线导电层222构成第二位线2。还包括：在第一位线1侧壁以及第二位线2侧壁形成位线保护层260。位线保护层260用于对第一位线1以及第二位线2起到保护作用，同时，后续在第一位线1以及第二位线2之间形成电容接触结构270时，还用于将电容接触结构270以及位线接触结构232隔离开，防止发生电容接触结构270与位线接触结构232发生电连接而造成半导体结构短路的现象。在一些实施例中，位线保护层260可以为多层结构，例如可以为依次排布的第一位线保护层261、第二位线保护层262以及第三位线保护层263，其中，第一位线保护层261的材料可以与第三位线保护层263的材料相同，例如可以是氮化硅，第二位线保护层262的材料可以是氧化硅。位线保护层260设置为多层结构，使得位线保护层260具有较强的硬度，可以较好地保护位线。在一些实施例中，可以采用沉积工艺在第一位线1以及第二位线2的侧面形成位线保护层260。沉积工艺可以为化学气相沉积、物理气相沉积、原子层沉积、或者金属有机化合物化学气相沉淀中的任一者。
在一些实施例中，在第一导电结构231以及第一位线导电层221之间形成第一黏附层241，在位线接触结构232以及第二位线导电层222之间形成第二黏附层242，且在第一位线导电层221顶面形成第一绝缘层251，以及在第二位线导电层222顶面形成第二绝缘层252时，位线保护层260还位于：在第一黏附层241侧面、第二黏附层242侧面、第一绝缘层251侧面以及第二绝缘层252侧面。
继续参考图13，在一些实施例中，在第一位线1以及第二位线2侧面形成位线保护层260后，还包括：在相邻的位线保护层260之间形成电容接触结构270。在一些实施例中，形成的电容接触结构270还位于部分衬底200中。电容接触结构270用于将衬底200中源/漏极的电信号引出，并与电容结构(未图示)形成电连接。在一些实施例中，形成电容接触结构270的方法可以包括：对相邻的位线保护层260之间的衬底200进行图形化处理，在一些实施例中，可以将相邻的位线保护层260作为掩膜，以对衬底200进行图形化处理，如此，有利于简化工艺流程；对图形化的衬底200表面进行刻蚀，以在衬底200内形成设定深度的凹槽；采用沉积工艺在凹槽中形成电容接触结构270，且还在相邻的位线保护层260之间形成电容接触结构270。在一些实施例中，电容接触结构270的材料可以为多晶硅。
上述公开实施例提供的半导体结构的制备方法的技术方案中，设置第一初始位线导电层14的顶面高于第二初始位线导电层15的顶面，且第一导电层211的顶面高于第二导电层212的顶面。后续在进行刻蚀时，将第一初始位线导电层14与第二初始位线导电层15的高度差，以及第一导电层211与第二导电层212的高度差转换为第一刻蚀工艺以及第二刻蚀工艺对第二初始位线导电层15进行刻蚀时的刻蚀速率差。在第二位线导电层222指向第二导电层212的方向上，部分朝向第二导电层212的第二位线导电层222会形成宽度逐渐增大的形貌，使得后续对第二导电层212进行刻蚀以形成位线接触结构232时，位线 接触结构232也将延续第二导电层212的形貌，使得与空洞20正对的位线接触结构232宽度较大，从而在位线接触结构232两侧形成电容接触结构270后，不容易贯穿与空洞20对应的位线接触结构232侧壁，从而改善半导体结构出现短路的现象。
本公开实施例还提供一种半导体结构，该半导体结构可由上述实施例提供的半导体结构的制备方法制备而成，以下将结合附图对本公开一实施例提供的半导体结构进行详细说明。
参考图13，半导体结构包括：衬底200，衬底200具有凹孔10，衬底200表面露出凹孔10的开口；位线接触结构232，位线接触结构232位于凹孔10中，位线接触结构232包裹有空洞20，且在沿位线接触结构232的顶面指向位线接触结构232底面的方向上，位线接触结构232的宽度逐渐增大；第一导电结构231，第一导电结构231位于衬底200表面，在垂直于衬底200方向上，第一导电结构231的宽度不变；第一位线导电层221以及第二位线导电层222，第一位线导电层221位于第一导电结构231远离衬底200的一侧，第二位线导电层222位于位线接触结构232远离衬底200的一侧，第一位线导电层221的顶面高于第二位线导电层222的顶面。
在沿位线接触结构232的顶面指向位线接触结构232底面的方向上，设置位线接触结构232的宽度逐渐增大，也就是说，在沿位线接触结构232的顶面指向空洞20的方向上，位线接触结构232的宽度逐渐增大，从而使得与空洞20正对的位线接触结构232的宽度较大。在实际工艺过程中，当在位线接触结构232两侧形成电容接触结构270后，不会贯穿与空洞20对应的位线接触结构232侧壁，从而防止形成的电容接触结构270与位线接触结构232之间通过被贯穿的位线接触结构232形成电连接的问题，减小半导体结构出现短路的可能性。
在一些实施例中，位线接触结构232的顶部宽度为5nm～10nm。由于部分位线接触结构232位于凹孔10中，与衬底200中的源/漏极连接，用于引出源/漏极的信号，且位于凹孔10中的部分位线接触结构232侧壁还具有位线保护层260，以用于隔离位线接触结构232与衬底200中的其它导电结构。若位线保护层260过薄，使得位线保护层260可能达不到较好的隔离效果，从而有可能导致衬底200中发生漏电的现象。因此需要在凹孔10中为形成位线保护层260预留一定的空间。当位线接触结构232的顶部宽度为5nm～10nm时，使得位线接触结构232的宽度不至于过大，使得位于凹孔10中的位线保护层260具有较大的厚度。另一方面，在这个范围内，使得位线接触结构232的宽度也不至于过小，从而可以防止发生由于位线接触结构232的宽度过小，而达不到包裹住空洞20的效果的问题。
在一些实施例中，位线接触结构232的底部宽度为10nm～15nm。在这个范围内，一方面使得位线接触结构232底部具有较大的宽度，从而使得在沿位线接触结构232的顶面指向位线接触结构232底面的方向上，位线接触结构232的宽度逐渐增大的幅度较大，使得与空洞20正对的位线接触结构232具有较大的宽度，可以较好地包裹住空洞20，即与空洞20正对的位线接触结构232侧壁具有较大的厚度。在实际工艺过程中，当在位线接触结构232两侧形成电容接触结构270后，不容易发生由于与空洞20正对的位线接触结构232侧壁过薄，而导致在工艺过程中，贯穿与空洞20对应的位线接触结构232侧壁的问题，进而改善半导体结构出现短路的问题。另一方面，在这个范围内使得位线接触结构232底部的宽度不至于过大，从而使得位于凹孔10中的位线保护层260可以具有较大的厚度。
在一些实施例中，位线接触结构232具有相对的侧壁以及与侧壁相连的底壁，位线接 触结构232的侧壁与位线接触结构232的底壁之间具有第一夹角，第一夹角为60°～80°。第一夹角的大小与位线接触结构232的顶面宽度以及底面宽度相关，在这个范围内，使得位线接触结构232的顶面宽度不至于过小，从而使得位线接触结构232的顶面宽度相较于底面宽度而言不至于过小。换句话说，在沿位线接触结构232的顶面指向位线接触结构232底面的方向上，位线接触结构232的宽度逐渐增大的幅度不至于过大，一方面使得底部的宽度不至于太大，从而使得位于凹孔10中的位线保护层260具有较大的厚度，另一方面，可以防止由于与空洞20正对的位线接触结构232正好处于宽度较小的位置，而导致位线接触结构232不能较好地包裹住空洞20的问题。
在一些实施例中，在沿第二位线导电层222的顶部指向第二位线导电层222的底部方向上，第二位线导电层222的宽度逐渐增大。在实际制备位线接触结构232的过程中，需要先对位于位线接触结构232顶面的第二位线导电层222进行刻蚀。在第二位线导电层222的顶部指向第二位线导电层222的底部方向上，第二位线导电层222的宽度逐渐增大，使得在实际制备工艺中，形成的位线接触结构232可以延续第二位线导电层222的形貌，即，在沿位线接触结构232的顶面指向位线接触结构232底面的方向上，也形成位线接触结构232的宽度逐渐增大的形貌。
在一些实施例中，在沿第一位线导电层221的顶部指向第一位线导电层221的底部的方向上，第一位线导电层221的宽度不变。相较于在第一位线导电层221指向第一导电结构231的方向上，第一导电结构231的宽度逐渐增大而言，设置第一导电结构231的宽度不变，使得第一导电结构231与位线接触结构232之间具有更大的空间，为后续在第一导电结构231与位线接触结构232之间形成位线保护层260以及电容接触结构270预留出较大的空间。一方面使得后续形成的位线保护层260可以具有较大的厚度，可以较好地将位线接触结构232与电容接触结构270隔离开，另一方面，使得形成的电容接触结构270具有较大的体积，有利于提高电容接触结构270的电性能。
在一些实施例中，还包括：第一黏附层241以及第一绝缘层251，第一黏附层241位于第一导电结构231与第一位线导电层221之间，第一绝缘层251位于第一位线导电层221顶面；第二黏附层242以及第二绝缘层252，第二黏附层242位于位线接触结构232与第二位线导电层222之间，第二绝缘层252位于第二位线导电层222顶面，且在沿第二黏附层242顶部指向第二黏附层242底部方向上，第二黏附层242的宽度逐渐增大。第一黏附层241以及第二黏附层242可以增加第一导电结构231和第一位线导电层221之间的粘附性以及位线接触结构232与第二位线导电层222之间的粘附性，有利于提高第一导电结构231与第一位线导电层221之间的电连接性能以及位线接触结构232与第二位线导电层222之间的电连接性能。在实际制备工艺中，在形成位线接触结构232之前，需要先对第二黏附层242进行刻蚀，当第二黏附层242的形貌为在沿第二黏附层242顶部指向第二黏附层242底部方向上，第二黏附层242的宽度逐渐增大时，形成的位线接触结构232将延续第二黏附层242的形貌，使得制备位线接触结构232的工艺较为简单。
第一绝缘层251以及第二绝缘层252一方面用于保护第一位线导电层221以及第二位线导电层222，另一方面，用于将第一位线导电层221以及第二位线导电层222与其它导电结构隔离开来。
在一些实施例中，第一导电结构231与第一位线导电层221构成第一位线1，位线接触结构232与第二位线导电层222构成第二位线2。可以理解的是，在另一些实施例中，半导体结构还包括第一黏附层241、第一绝缘层251、第二黏附层242以及第二绝缘层252时，第一黏附层241以及第一绝缘层251也可以作为第一位线1的一部分，第二黏附层242以及第二绝缘层252也可以作为第二位线2的一部分。
在一些实施例中，还包括：位线保护层260，位线保护层260位于第一位线1和第二位线2侧壁，且部分位线保护层260还位于凹孔10中。位线保护层260用于对第一位线1以及第二位线2起到保护作用，同时，后续在第一位线1以及第二位线2之间形成电容接触结构270时，还用于将电容接触结构270以及位线接触结构232隔离开，防止发生电容接触结构270与位线接触结构232发生电连接而造成半导体结构短路的现象。部分位线保护层260位于凹孔10中，用于隔离位线接触结构232与衬底200中的其它导电结构，防止衬底200中发生漏电的问题。在一些实施例中，位线保护层260可以为多层结构，例如可以为依次排布的第一位线保护层261第二位线保护层262以及第三位线保护层263，其中，第一位线保护层261的材料可以与第三位线保护层263的材料相同，例如可以是氮化硅，第二位线保护层262的材料可以是氧化硅。
在一些实施例中，还包括：电容接触结构270，电容接触结构270位于相邻的位线保护层260之间。在一些实施例中，电容接触结构270还位于部分衬底200中。电容接触结构270用于将衬底200中源/漏极的电信号引出，并与电容结构(未图示)形成电连接。由于在沿位线接触结构232的顶面指向位线接触结构232底面的方向上，位线接触结构232的宽度逐渐增大，即在沿空洞20指向位线接触结构232底面的方向上，位线接触结构232的宽度逐渐增大，使得与空洞20正对的位线接触结构232的宽度较大，可以较好地包裹住空洞20。在实际制备电容接触结构270的工艺过程中，不容易贯穿与空洞20对应的位线接触结构232侧壁，从而防止形成的电容接触结构270与位线接触结构232之间通过被贯穿的位线接触结构232形成电连接的问题，有利于减小半导体结构出现短路的概率。
上述实施例提供的半导体结构中，通过设置在沿位线接触结构232的顶面指向位线接触结构232底面的方向上，位线接触结构232的宽度逐渐增大，从而使得与空洞20正对的位线接触结构232的宽度较大，可以使位线接触结构232较好的包裹住空洞20。在实际工艺过程中，当在位线接触结构232两侧形成电容接触结构270后，不容易贯穿与空洞20对应的位线接触结构232侧壁，从而防止形成的电容接触结构270与位线接触结构232之间通过被贯穿的位线接触结构232形成电连接的问题，减小半导体结构出现短路的可能性。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以 在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例提供的半导体结构的制备方法的技术方案中，将第一初始位线导电层与第二初始位线导电层的高度差，以及第一导电层与第二导电层的高度差转换为对第二初始位线导电层进行刻蚀工艺时的刻蚀速率差，在第二位线导电层指向第二导电层的方向上，部分朝向第二导电层的第二位线导电层会形成宽度逐渐增大的形貌，使得后续对第二导电层进行刻蚀时，将延续第二位线导电层的形貌。形成位线接触结构后，使得与空洞正对的位线接触结构侧壁较厚，从而在位线接触结构两侧形成电容接触结构后，不会贯穿与空洞对应的位线接触结构侧壁，从而减小半导体结构出现短路的可能性。

Claims (18)

  1. 一种半导体结构的制备方法，所述制备方法包括：
    提供衬底，所述衬底具有凹孔，所述衬底表面露出所述凹孔的开口；
    形成导电层，所述导电层包括：第一导电层以及第二导电层，所述第一导电层位于所述衬底表面，所述第二导电层位于所述凹孔中，所述第二导电层顶面低于所述第一导电层的顶面，且位于所述凹孔中的所述第二导电层具有空洞；
    在所述第一导电层远离所述衬底的一侧形成第一初始位线导电层，在所述第二导电层远离所述衬底的一侧形成第二初始位线导电层，所述第一初始位线导电层的顶面高于所述第二初始位线导电层的顶面；
    采用第一刻蚀工艺对所述第一初始位线导电层进行刻蚀直至露出所述第一导电层时停止，以形成第一位线导电层，同时，对部分所述第二初始位线导电层进行所述第一刻蚀工艺，所述第二初始位线导电层未被完全刻蚀；
    采用第二刻蚀工艺对所述第一导电层进行刻蚀，形成第一导电结构，在垂直于所述衬底方向上，所述第一导电结构的宽度不变，同时，采用所述第二刻蚀工艺对剩余的所述第二初始位线导电层进行刻蚀，以形成第二位线导电层，且所述第一刻蚀工艺对所述第二初始位线导电层的刻蚀速率大于所述第二刻蚀工艺对与所述第二初始位线导电层的刻蚀速率；
    刻蚀所述第二导电层，形成包裹所述空洞的位线接触结构，在沿所述位线接触结构的顶面指向所述位线接触结构底面的方向上，所述位线接触结构的宽度逐渐增大。
  2. 根据权利要求1所述的半导体结构的制备方法，其中，所述制备方法还包括：在所述第一导电层与所述第一初始位线导电层之间形成第一初始黏附层，在所述第二导电层与所述第二初始位线导电层之间形成第二初始黏附层；在采用第二刻蚀工艺对所述第一导电层进行刻蚀之前，还包括；采用第三刻蚀工艺对所述第一初始黏附层进行刻蚀，同时，对所述第二初始位线导电层进行所述第三刻蚀工艺，且所述第一刻蚀工艺对所述第二初始位线导电层的刻蚀速率大于所述第三刻蚀工艺对所述第二初始位线导电层的刻蚀速率。
  3. 根据权利要求1所述的半导体结构的制备方法，其中，在垂直于所述衬底方向上，所述第一初始位线导电层的长度小于所述第二初始位线导电层的长度。
  4. 根据权利要求1所述的半导体结构的制备方法，其中，所述制备方法还包括：
    在所述第一初始位线导电层顶面形成第一初始绝缘层，在所述第二初始位线导电层顶面形成第二初始绝缘层；
    采用第四刻蚀工艺对所述第一初始绝缘层进行刻蚀，直至露出所述第一初始位线导电层时停止，以形成第一绝缘层；同时，对部分所述第二初始绝缘层进行所述第四刻蚀工艺，所述第二初始绝缘层未被完全刻蚀；
    采用第一刻蚀工艺对所述第一初始位线导电层进行刻蚀，同时，采用所述第一刻蚀工艺对剩余的所述第二初始绝缘层进行刻蚀，以形成第二绝缘层，所述第四刻蚀工艺对所述第二初始绝缘层的刻蚀速率大于所述第一刻蚀工艺对所述第二初始绝缘层的刻蚀速率。
  5. 根据权利要求1所述的半导体结构的制备方法，其中，所述形成所述第二导电层的顶面低于所述第一导电层的顶面的方法包括：
    形成第一初始导电层以及第二初始导电层，所述第一初始导电层覆盖所述衬底表面，所述第二初始导电层填满所述凹孔；
    对所述第二初始导电层顶面进行初始刻蚀工艺，以形成所述第二导电层，且所述第二导电层的顶面低于所述第一导电层的顶面。
  6. 根据权利要求5所述的半导体结构的制备方法，其中，对所述第二初始导电层进行所述初始刻蚀工艺的时间为8s～16s。
  7. 根据权利要求1或6所述的半导体结构的制备方法，其中，在垂直于所述衬底方向上，所述第二导电层顶面到所述第一导电层顶面的高度差为8nm～16nm。
  8. 根据权利要求1所述的半导体结构的制备方法，其中，所述第一刻蚀工艺以及所述第二刻蚀工艺为干法刻蚀工艺。
  9. 一种半导体结构，所述半导体结构包括：
    衬底，所述衬底具有凹孔，所述衬底表面露出所述凹孔的开口；
    位线接触结构，所述位线接触结构位于所述凹孔中，所述位线接触结构包裹有空洞，且在沿所述位线接触结构的顶面指向位线接触结构底面的方向上，所述位线接触结构的宽度逐渐增大；
    第一导电结构，所述第一导电结构位于所述衬底表面，在垂直于所述衬底方向上，所述第一导电结构的宽度不变；
    第一位线导电层以及第二位线导电层，所述第一位线导电层位于所述第一导电结构远离所述衬底的一侧，所述第二位线导电层位于所述位线接触结构远离所述衬底的一侧，所述第一位线导电层的顶面高于所述第二位线导电层的顶面。
  10. 根据权利要求9所述的半导体结构，其中，所述位线接触结构的顶部宽度为5nm～10nm。
  11. 根据权利要求9或10所述的半导体结构，其中，所述位线接触结构的底部宽度为10nm～15nm。
  12. 根据权利要求9所述的半导体结构，其中，所述位线接触结构具有相对的侧壁以及与所述侧壁相连的底壁，所述位线接触结构的侧壁与所述位线接触结构的底壁之间具有第一夹角，所述第一夹角为60°～80°。
  13. 根据权利要求9所述的半导体结构，其中，在沿所述第二位线导电层的顶部指向所述第二位线导电层的底部方向上，所述第二位线导电层的宽度逐渐增大。
  14. 根据权利要求13所述的半导体结构，其中，在沿所述第一位线导电层的顶部指向所述第一位线导电层的底部的方向上，所述第一位线导电层的宽度不变。
  15. 根据权利要求9所述的半导体结构，其中，所述半导体结构还包括：
    第一黏附层以及第一绝缘层，所述第一黏附层位于所述第一导电结构与所述第一位线导电层之间，所述第一绝缘层位于所述第一位线导电层顶面；
    第二黏附层以及第二绝缘层，所述第二黏附层位于所述位线接触结构与所述第二位线导电层之间，所述第二绝缘层位于所述第二位线导电层顶面，且在沿所述第二黏附层顶部指向所述第二黏附层底部方向上，所述第二黏附层的宽度逐渐增大。
  16. 根据权利要求9所述的半导体结构，其中，所述第一导电结构与所述第一位线导 电层构成第一位线，所述位线接触结构与所述第二位线导电层构成第二位线。
  17. 根据权利要求16所述的半导体结构，其中，所述半导体结构还包括：位线保护层，所述位线保护层位于所述第一位线和所述第二位线侧壁，且部分所述位线保护层还位于所述凹孔中。
  18. 根据权利要求17所述的半导体结构，其中，所述半导体结构还包括：电容接触结构，所述电容接触结构位于相邻的所述位线保护层之间。
PCT/CN2022/136886 2022-01-17 2022-12-06 半导体结构的制备方法及半导体结构 WO2023134331A1 (zh)

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US20160163637A1 (en) * 2014-12-04 2016-06-09 Hyeonok JUNG Semiconductor device and method for manufacturing the same
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