WO2022179022A1 - 半导体结构的形成方法及半导体结构 - Google Patents

半导体结构的形成方法及半导体结构 Download PDF

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Publication number
WO2022179022A1
WO2022179022A1 PCT/CN2021/103038 CN2021103038W WO2022179022A1 WO 2022179022 A1 WO2022179022 A1 WO 2022179022A1 CN 2021103038 W CN2021103038 W CN 2021103038W WO 2022179022 A1 WO2022179022 A1 WO 2022179022A1
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dielectric layer
forming
barrier
layer
trench
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PCT/CN2021/103038
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English (en)
French (fr)
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任兴润
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长鑫存储技术有限公司
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Priority to US17/445,675 priority Critical patent/US20220270921A1/en
Publication of WO2022179022A1 publication Critical patent/WO2022179022A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure

Definitions

  • the present application relates to the technical field of semiconductor manufacturing, and in particular, to a method for forming a semiconductor structure and a semiconductor structure.
  • the size of the circuit gradually becomes smaller, the depth required for the conductive contact structure inside the semiconductor device also gradually increases, and the current density in the conductive structure such as the plugging wire increases, and the traditional plugging Wire structures are undergoing a huge test.
  • the conductive materials most commonly used to form the plugged wire are metal Cu and metal Al, and correspondingly, the materials of the wire barrier layer are usually Ta, Ru and Ti.
  • a dielectric layer is usually etched by a dry etching process to form a through hole, then a barrier layer is deposited in the through hole, and finally a metal wire is deposited in the through hole.
  • silicon oxide is usually used as the dielectric layer, but due to the problem of the compactness of the silicon oxide material, during the process of forming the through hole through the etching process, the corners of the through hole will be damaged.
  • the damage at the corners will be further aggravated.
  • the plug wire is subjected to the scouring of the current for a long time, and leakage is likely to occur at the corner of the plug wire, which leads to the diffusion of metal ions, which affects the service life of the device, and even causes the device to fail in severe cases.
  • generally denser materials have larger dielectric constants (for example, silicon nitride is very dense, but the dielectric constant of silicon nitride is much larger than that of silicon oxide). If only the dielectric layer is replaced with Materials with higher density will lead to large parasitic capacitances between wire structures, which will seriously affect the performance of semiconductor devices.
  • the present application provides a method for forming a semiconductor structure and a semiconductor structure, which are used to solve the problem of poor stability of a plug wire in the prior art, so as to improve the reliability of a semiconductor device.
  • the present application provides a method for forming a semiconductor structure, comprising the following steps:
  • first barrier structures distributed at intervals on the substrate, with first trench structures exposing the substrate between adjacent first barrier structures;
  • the dielectric layer has a second trench structure, and the second trench structure exposes part of the first barrier structure; wherein, the first barrier structure is formed
  • the density of the material is greater than the density of the material forming the dielectric layer
  • a conductive layer is formed, and the conductive layer fills the second trench structure.
  • the step of forming a plurality of spaced first barrier structures on the substrate includes:
  • a dielectric layer is formed on the first barrier layer, the dielectric layer has a third trench structure, and the projection of the third trench structure on the substrate is at the same level as the first trench structure The projections on the substrate are coincident;
  • the dielectric layer is removed.
  • the specific step of forming a dielectric layer on the first barrier layer includes:
  • the mask layer and part of the initial dielectric layer are removed, and the initial dielectric layer covering the sidewalls of the fourth trench structure remains.
  • the forming of an initial dielectric layer, the initial dielectric layer covering at least the bottom and sidewalls of the fourth trench structure includes:
  • the initial dielectric layer is formed by atomic layer deposition.
  • the dielectric constant of the material forming the first barrier structure is greater than the dielectric constant of the material forming the dielectric layer.
  • the material for forming the first barrier structure is silicon nitride, and the material for forming the dielectric layer is silicon oxide.
  • the method further includes:
  • a second barrier layer is formed, and the second barrier layer covers the upper surface of the dielectric layer, the bottom of the second trench structure and the sidewall of the second trench structure.
  • a material forming the second barrier layer includes titanium nitride.
  • the dielectric layer covers the upper surface of the first blocking structure.
  • the present application also provides a semiconductor structure, including:
  • first barrier structure the first barrier structures are distributed on the substrate at intervals, and there are first trench structures exposing the substrate between adjacent first barrier structures;
  • the dielectric layer at least partially fills the first trench structure, the dielectric layer has a second trench structure, and the second trench structure exposes a part of the first barrier structure; wherein the formation of the The density of the material of the first barrier structure is greater than the density of the material forming the dielectric layer;
  • a conductive layer, the conductive layer fills the second trench structure.
  • the dielectric constant of the material forming the first barrier structure is greater than the dielectric constant of the material forming the dielectric layer.
  • the material for forming the first barrier structure is silicon nitride
  • the material for forming the dielectric layer is silicon oxide
  • a second barrier layer is located between the dielectric layer and the conductive layer, and the second barrier layer covers the upper surface of the dielectric layer, the bottom of the second trench structure and all the sidewalls of the second trench structure.
  • the material for forming the second barrier layer is titanium nitride.
  • the dielectric layer covers the upper surface of the first blocking structure.
  • a first barrier structure is embedded in a dielectric layer, and the density of the material for forming the first barrier structure is greater than that of the material for forming the dielectric layer, and can be etched in the dielectric layer.
  • the layers prevent damage to the corners of the vias during the formation of the plugged wires.
  • the embedded first barrier structure can prevent the plug wire from diffusing into the dielectric layer, thereby increasing the stability of the conductive layer, thereby improving the reliability of the entire device structure.
  • the first blocking structure is embedded in the dielectric layer, under the condition of greatly improving the stability of the plug wire structure, only a small amount of parasitic capacitance is added, which ensures the electrical performance of the semiconductor device.
  • FIG. 1 is a flowchart of a method for forming a semiconductor structure in a specific embodiment of the present application
  • 2A-2J are schematic cross-sectional views of main processes in the process of forming the semiconductor structure in the specific embodiment of the present application.
  • FIG. 1 is a flowchart of the method for forming a semiconductor structure in the specific embodiment of the present application
  • FIGS. 2A-2J are the process of forming the semiconductor structure in the specific embodiment of the present application. Schematic diagram of the main process cross-section.
  • the semiconductor structure described in this specific embodiment may be, but is not limited to, a dynamic random access memory (Dynamic Random Access Memory, DRAM).
  • DRAM Dynamic Random Access Memory
  • step S11 the substrate 20 is provided.
  • the substrate 20 may be, but not limited to, a silicon substrate or a polysilicon substrate.
  • the substrate 20 is a silicon substrate as an example for description, and the substrate 20 is used to support device structure on it.
  • the substrate 20 may be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI.
  • the substrate 20 may be a single-layer substrate or a multi-layer substrate formed by stacking a plurality of semiconductor layers, and those skilled in the art can choose according to actual needs.
  • the substrate 20 may also be provided with structures such as active regions, transistors, shallow trench isolation structures, word lines, and the like.
  • Step S12 forming a plurality of first barrier structures 211 distributed at intervals on the substrate 20 , and there are first trench structures 212 exposing the substrate 20 between adjacent first barrier structures 211 , as shown in FIG. 2F is shown.
  • the specific steps of forming a plurality of first barrier structures 211 distributed at intervals on the substrate 20 include:
  • first barrier layer 21 on the substrate 20, the first barrier layer 21 covering the substrate 20, as shown in FIG. 2A;
  • a dielectric layer 231 is formed on the first barrier layer 21, the dielectric layer 231 has a third trench structure 30, and the projection of the third trench structure 30 on the substrate 20 is the same as that of the The projections of the first trench structure 212 on the substrate 20 overlap, as shown in FIG. 2E ;
  • the first barrier layer 21 is etched using the dielectric layer 231 as a mask, as shown in FIG. 2F ;
  • the dielectric layer 231 is removed.
  • a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process may be used to deposit a first barrier layer 21 on the surface of the substrate 20, and the first barrier layer 21 covers the liner the surface of the bottom 20 .
  • a dielectric is formed on the surface of the first barrier layer 21 .
  • Layer 231, the dielectric layer 231 has a third trench structure 30, as shown in FIG. 2E.
  • the projection of the third trench structure 30 in the direction perpendicular to the substrate 20 coincides with the projection of the first trench structure 212 to be finally formed in the direction perpendicular to the substrate 20 .
  • the first barrier layer 21 is patterned by means of etching or the like.
  • a plurality of first trench structures 212 are formed in the first barrier layer 21 along a direction perpendicular to the substrate 20 penetrating the first barrier layer 21 , and the plurality of first trench structures 212 will be used for the remaining
  • the first barrier layer 21 is divided into a plurality of mutually independent first barrier structures 211 .
  • the multiple mentioned in this specific embodiment refers to two or more.
  • the plurality of first barrier structures 211 distributed at intervals refer to physical isolation between any two of the first barrier structures 211 (that is, there is a first trench between any two of the first barrier structures 211 that are connected at random) structure 212), that is, any two of the first blocking structures 211 are not connected to each other.
  • the dielectric layer 231 has a plurality of the third trench structures 30 with different widths (for example, the third trench structure 30 in FIG. 2E includes first sub-trenches with different widths)
  • the structure 222 and the second sub-trench structure 223) are taken as an example for description, and those skilled in the art can also set all the third trench structures 30 in the dielectric layer to have the same width according to actual needs.
  • the width of the third trench structure 30 refers to the inner diameter of the third trench structure 30 .
  • the specific steps of forming the dielectric layer 231 on the first barrier layer 21 include:
  • the initial mask layer 22 is patterned to form a mask layer 31, and the mask layer 31 has a fourth trench structure 221, as shown in FIG. 2B;
  • the initial dielectric layer 23 at least covers the bottom and sidewalls of the fourth trench structure 221, as shown in FIG. 2C;
  • the mask layer 31 and part of the initial dielectric layer 23 are removed, and the initial dielectric layer 23 covering the sidewall of the fourth trench structure 221 is retained as the dielectric layer 231, as shown in FIG. 2E .
  • the forming an initial dielectric layer 23, the initial dielectric layer 23 covering at least the bottom and sidewalls of the fourth trench structure 221 includes:
  • the initial dielectric layer 23 is formed by atomic layer deposition. Compared with other deposition processes, the atomic layer deposition process can well control the uniformity of the deposited film. The use of the atomic layer deposition method to form the initial dielectric layer 23 can ensure that the thickness of the initial dielectric layer 23 is the same at each position, thereby The stability of the subsequently formed semiconductor structure is ensured.
  • the initial mask layer 22 is deposited on the surface of the first barrier layer 21, so that the initial mask layer 22 completely covers the entire surface of the substrate 20.
  • the first barrier layer 21 is described, as shown in FIG. 2A .
  • the material of the initial mask layer 22 may be an organic mask material, such as SOC, or a hard mask material, such as polysilicon.
  • the initial mask layer 22 may be formed on the surface of the first barrier layer 21 by a chemical vapor deposition process or an atomic layer deposition process.
  • the initial mask layer 22 is patterned, that is, the initial mask layer 22 is etched by using a dry etching process or a wet etching process.
  • a fourth trench structure 221 penetrating the initial mask layer 22 in a direction perpendicular to the substrate 20 is formed to form a mask layer 31 , as shown in FIG. 2B .
  • an atomic layer deposition process is used to deposit a silicon oxide material, etc., to form an inner wall (including the bottom and sidewalls of the fourth trench structure 221 ) covering the fourth trench structure 221 and the top surface of the mask layer 31 ( That is, the initial dielectric layer 23 of the mask layer 31 facing away from the surface of the substrate 20 ), as shown in FIG. 2C .
  • the uniformity of the initial dielectric layer 23 formed by the atomic layer deposition process is good, which ensures the uniformity of the morphology of the first barrier structure 211 formed subsequently.
  • the material of the mask layer 31 and the material of the initial dielectric layer 23 should have a high etching selectivity ratio, for example, the mask layer
  • the etching selectivity ratio between the layer 31 and the initial dielectric layer 23 is greater than 3 (eg, the etching selectivity ratio is 5).
  • the initial dielectric layer 23 covering the top surface of the mask layer 31 and the bottom of the fourth trench structure 221 is removed by means such as etching, and only the side covering the fourth trench structure 221 is left.
  • the initial dielectric layer 23 of the wall is used as the initial dielectric layer 23 covering the sidewall of the fourth trench structure 221 as the dielectric layer 231 , as shown in FIG. 2D .
  • the trench structure 30 includes a first sub-trench structure 222 and a second sub-trench structure 223 .
  • the width of the first sub-trench structure 222 and the width of the second sub-trench structure 223 may be the same or different.
  • the first sub-trench structure 222 is formed after the dielectric layer 231 is formed, and the first sub-trench structure 222 is formed at the position where the remaining mask layer 31 is removed.
  • the second sub-trench structure 223 is also formed after the dielectric layer 231 is formed, and the second sub-trench structure 223 is formed at the position of the fourth trench structure 221 . In the structure shown in FIG. 2E , along a direction parallel to the surface of the substrate 20 , the first sub-trench structures 222 and the second sub-trench structures 223 are alternately arranged.
  • the first barrier layer 21 is etched along the first sub-trench structure 222 and the second sub-trench structure 223 by a dry etching process, and a plurality of barrier layers are formed in the first barrier layer 21
  • the first trench structure 212 of the first barrier layer 21 penetrates in a direction perpendicular to the substrate 20 , and the remaining first barrier layer 21 serves as the first barrier structure 211 , as shown in FIG. 2F .
  • step S13 an initial dielectric layer 24 is formed, and the initial dielectric layer 24 fills the first trench structure 212 .
  • Step S14 removing part of the initial dielectric layer 24 to form a dielectric layer 242, the dielectric layer 242 has a second trench structure 241, and the second trench structure 241 exposes a part of the first barrier structure 211; Wherein, the density of the material forming the first barrier structure 211 is greater than the density of the material forming the dielectric layer 242 , as shown in FIG. 2H .
  • a chemical vapor deposition process is used to deposit materials such as silicon oxide to form a filling
  • the initial dielectric layer 24 that fills all the first trench structures 212 and completely covers all the top surfaces of the first barrier structures 211 (that is, the surface of the first barrier structures 211 facing away from the substrate 20 ), such as shown in Figure 2G.
  • a dry etching process is used to etch a portion of the initial dielectric layer 24 to form a second trench structure 241 penetrating the initial dielectric layer 24 in a direction perpendicular to the substrate 20 .
  • the trench structure 241 separates the initial dielectric layer 24 into a plurality of dielectric layers 242, as shown in FIG. 2H.
  • the density of the material forming the first barrier structure 211 is defined to be greater than the density of the material forming the dielectric layer 242 , so that the first barrier structure 211 can be better than the dielectric layer 242 It blocks the diffusion of conductive particles in the subsequently formed conductive layer 26, prevents the conductive particles in the conductive layer 26 from diffusing from the corners of the second trench structure 241, and reduces the generation of leakage current.
  • step S15 a conductive layer 26 is formed, and the conductive layer 26 fills the second trench structure 241 , as shown in FIG. 2I .
  • the method further includes:
  • a second barrier layer 25 is formed, and the second barrier layer 25 covers the upper surface of the dielectric layer 242 , the bottom of the second trench structure 241 and the sidewall of the second trench structure 241 .
  • the method for forming the semiconductor structure further includes:
  • the material for forming the second barrier layer 25 includes titanium nitride.
  • the titanium nitride material has a high density, which can better prevent the conductive layer 26 from penetrating into the dielectric layer 242, and the titanium nitride material has a certain conductivity, which can ensure the electrical conductivity of the plug wire.
  • a barrier material such as titanium nitride is deposited on the second trench structure by an atomic layer deposition process or a chemical vapor deposition process.
  • the top surface of the dielectric layer 242 ie, the surface of the dielectric layer 242 facing away from the substrate 20
  • the first barrier structure exposed through the sidewall of the second trench structure 241 211's surface.
  • the second trench structure 241 is filled by a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process or an electroplating process to form the conductive layer 26, as shown in FIG. 2I .
  • the method for forming the semiconductor structure includes:
  • the dielectric layer 242 covers the upper surface of the first blocking structure 211 .
  • the height of the dielectric layer 242 is greater than the height of the first barrier structure 211, so as to avoid increasing the parasitic capacitance inside the semiconductor structure and ensure that the semiconductor The performance stability of the structure.
  • the relative proportional relationship between the height of the dielectric layer 242 and the height of the first blocking structure 211 can be selected by those skilled in the art according to actual needs, for example, according to the specific material of the first blocking structure 211 , etc. .
  • the height of the dielectric layer 242 is more than twice the height of the first blocking structure 211 .
  • first blocking structures 211 there are more than three first blocking structures 211 between two adjacent second trench structures 241 .
  • each of the second trench structures 241 are exposed to the sidewalls of the two first barrier structures 211 .
  • those skilled in the art can modify the pattern in the mask layer 31 so that there are only two of the first trench structures 241 between adjacent two of the second trench structures 241 .
  • Blocking structure 211 For example, as shown in FIG. 2J , in two adjacent second trench structures 241 , the sidewalls of each of the second trench structures 241 expose two of the first barrier structures 211 . No additional first barrier structures 211 are disposed between the two first barrier structures 211 exposed through the adjacent two second trench structures 241 , so that the manufacturing process can be simplified.
  • the width of the first barrier structure 211 is smaller than or equal to the width of the second barrier layer 25 .
  • the width of the first barrier structure 211 is smaller than or equal to the width of the second barrier layer 25 , the parasitic capacitance of the semiconductor structure can be not increased, and the adjacent second trench can be ensured
  • the interval width between the groove structures 241 does not affect the feature size of the conductive layer 26 .
  • the method for forming the semiconductor structure further includes:
  • the dielectric constant of the material forming the first barrier structure 211 is greater than the dielectric constant of the material forming the dielectric layer 242 .
  • the material for forming the first barrier structure 211 is silicon nitride, and the material for forming the dielectric layer 242 is silicon oxide.
  • the present embodiment also provides a semiconductor structure.
  • the semiconductor structure provided by this specific embodiment can be formed by using the formation method of the semiconductor structure shown in FIG. 1 and FIG. 2A- FIG. 2J .
  • the schematic diagrams of the semiconductor structure provided by this specific embodiment can be seen in FIG. 2I and FIG. 2J .
  • the semiconductor structure provided by this specific embodiment includes:
  • first barrier structure 211 a first barrier structure 211 , the first barrier structures 211 are distributed on the substrate 20 at intervals, and there are first trench structures 212 exposing the substrate 20 between adjacent first barrier structures 211 ;
  • the conductive layer 26 is filled with the second trench structure 241 .
  • the dielectric constant of the material forming the first barrier structure 211 is greater than the dielectric constant of the material forming the dielectric layer 242 .
  • the material for forming the first barrier structure 211 is silicon nitride, and the material for forming the dielectric layer 242 is silicon oxide.
  • the semiconductor structure further includes:
  • the second barrier layer 25, the second barrier layer 25 is located between the dielectric layer 242 and the conductive layer 26, and the second barrier layer 25 covers the upper surface of the dielectric layer 242, the second barrier layer 25 The bottom of the trench structure 241 and the sidewall of the second trench structure 241 .
  • the material for forming the second barrier layer 25 is titanium nitride.
  • the dielectric layer 242 covers the upper surface of the first blocking structure 211 .
  • the height of the dielectric layer 242 is greater than the height of the first barrier structure 211, so as to avoid increasing the parasitic capacitance inside the semiconductor structure and ensure that the semiconductor The performance stability of the structure.
  • the relative proportional relationship between the height of the dielectric layer 242 and the height of the first blocking structure 211 can be selected by those skilled in the art according to actual needs, for example, according to the specific material of the first blocking structure 211 , etc. .
  • the height of the dielectric layer 242 is more than twice the height of the first blocking structure 211 .
  • first blocking structures 211 there are more than three first blocking structures 211 between two adjacent second trench structures 241 .
  • each of the second trench structures 241 expose two of the first barrier structures 211 , and are exposed through two adjacent second trench structures 241 .
  • those skilled in the art can modify the pattern in the mask layer 31 so that there are only two of the first barrier structures between the adjacent second trench structures 241 211.
  • the sidewalls of each of the second trench structures 241 expose two of the first barrier structures 211 , and are exposed through two adjacent second trench structures 241 .
  • No other first blocking structure 211 is disposed between the two first blocking structures 211, so that the manufacturing process can be simplified.
  • the width of the first barrier structure 211 is smaller than or equal to the width of the second barrier layer 25 .
  • the width of the first barrier structure 211 is smaller than or equal to the width of the second barrier layer 25 , the parasitic capacitance of the semiconductor structure can be not increased, and the adjacent second trench can be ensured The interval width between the groove structures 241 .
  • the material of the first blocking structure 211 is one or a combination of two of SIN and SICN.
  • the material of the first blocking structure 211 is SIN.
  • the material of the first barrier structure 211 may be the same as the material of the second barrier layer 25 , or may be different from the material of the second barrier layer 25 .
  • the material of the first barrier structure 211 is different from the material of the second barrier layer 25 .
  • the material of the first barrier structure 211 is SIN; the material of the second barrier layer 25 is TiN.
  • the material of the conductive layer 26 is a metal material, such as Cu or Al.
  • the first barrier structure is embedded in the dielectric layer, and the density of the material for forming the first barrier structure is greater than that of the material for forming the dielectric layer.
  • the embedded first barrier structure can prevent the plug wire from diffusing into the dielectric layer, thereby increasing the stability of the conductive layer, thereby improving the reliability of the entire device structure.
  • the first blocking structure is embedded in the dielectric layer, under the condition of greatly improving the stability of the plug wire structure, only a small amount of parasitic capacitance is added, which ensures the electrical performance of the semiconductor device.

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Abstract

本申请涉及半导体制造技术领域，尤其涉及一种半导体结构的形成方法及半导体结构。所述半导体结构的形成方法包括如下步骤：提供衬底；于所述衬底上形成多个间隔分布的第一阻挡结构，相邻所述第一阻挡结构之间具有暴露所述衬底的第一沟槽结构；形成初始介质层，所述初始介电层填充满所述第一沟槽结构；去除部分所述初始介质层，以形成介质层，所述介质层具有第二沟槽结构，所述第二沟槽结构暴露部分所述第一阻挡结构；其中，形成所述第一阻挡结构的材料的致密度大于形成所述介质层的材料的致密度；形成导电层，所述导电层填充满所述第二沟槽结构。本申请增加了栓塞导电结构的稳定性，提高了整个器件结构的可靠性。

Description

半导体结构的形成方法及半导体结构
相关申请引用说明
本申请要求于2021年2月23日递交的中国专利申请号202110200555.0、申请名为“半导体结构的形成方法及半导体结构”的优先权，其全部内容以引用的形式附录于此。
技术领域
本申请涉及半导体制造技术领域，尤其涉及一种半导体结构的形成方法及半导体结构。
背景技术
随着半导体器件的集成度越来越高，电路尺寸相应逐渐变小，半导体器件内部的导电接触结构所需达到的深度也逐渐增加，栓塞导线等导电结构中的电流密度增大，传统的栓塞导线结构正承受着巨大的考验。
在典型的栓塞导线的制造工艺中，最常用于形成栓塞导线的导电材料有金属Cu和金属Al，相应的，导线阻挡层的材料通常有Ta、Ru和Ti。在传统的导线制造工艺中，通常会通过干法刻蚀工艺蚀刻介质层以形成通孔，随后于所述通孔内沉积阻挡层，最后在所述通孔内沉积金属导线。但是，在现有工艺中，通常会使用氧化硅作为介质层，但是由于氧化硅材料致密性的问题，在通过刻蚀工艺形成通孔的过程中，会使通孔的角落处产生损伤。后续通过湿法刻蚀工艺对刻蚀后的结构进行清洗时，会进一步加重角落处的损伤。而且，在半导体器件的使用过程中，栓塞导线长期承受着电流的冲刷，在栓塞导线的角落部分容易发生漏电从而导致金属离子的扩散，影响器件的使用寿命，严重时甚至导致器件的失效。另外，一般致密度较高的材料都具有较大的介电常数(如氮化硅的致密性很好，但是，氮化硅的介电常数远大于氧化硅)，如果仅仅将介质层换成致密度较高的材料，会导致导线结构之间存在很大寄生电容，从而严重影响半导体器件的性能。
随着手机等电子产品在人们的日常生活中应用越来越广泛，电子产品内部的内存芯片或者逻辑芯片所承担的运算强度呈几何倍数增长。因此，如何提高栓塞导线的性能稳定性，从而提升半导体器件的可靠性，是当前亟待解决的技术问题。
发明内容
本申请提供一种半导体结构的形成方法及半导体结构，用于解决现有技术中的栓塞导线稳定性较差的问题，以提高半导体器件的可靠性。
为了解决上述问题，本申请提供了一种半导体结构的形成方法，包括如下步骤：
提供衬底；
于所述衬底上形成多个间隔分布的第一阻挡结构，相邻所述第一阻挡结构之间具有暴露所述衬底的第一沟槽结构；
形成初始介质层，所述初始介质层填充满所述第一沟槽结构；
去除部分所述初始介质层，以形成介质层，所述介质层具有第二沟槽结构，所述第二沟槽结构暴露部分所述第一阻挡结构；其中，形成所述第一阻挡结构的材料的致密度大于形成所述介质层的材料的致密度；
形成导电层，所述导电层填充满所述第二沟槽结构。
可选的，于所述衬底上形成多个间隔分布的第一阻挡结构的步骤包括：
于所述衬底上形成第一阻挡层，所述第一阻挡层覆盖所述衬底；
于所述第一阻挡层上形成介电层，所述介电层具有第三沟槽结构，且所述第三沟槽结构在所述衬底上的投影与所述第一沟槽结构在所述衬底上的投影重合；
以所述介电层为掩模版刻蚀所述第一阻挡层；
去除所述介电层。
可选的，于所述第一阻挡层上形成介电层的具体步骤包括：
于所述第一阻挡层上形成初始掩膜层，所述初始掩膜层覆盖所述第一阻挡层；
图形化所述初始掩膜层，形成掩膜层，所述掩膜层具有第四沟槽结构；
形成初始介电层，所述初始介电层至少覆盖所述第四沟槽结构的底部及侧壁；
去除所述掩膜层和部分所述初始介电层，保留覆盖所述第四沟槽结构侧壁的所述初始介电层。
可选的，所述形成初始介电层，所述初始介电层至少覆盖所述第四沟槽结 构的底部及侧壁包括：
采用原子层沉积法形成所述初始介电层。
可选的，包括：
形成所述第一阻挡结构的材料的介电常数大于形成所述介质层的材料的介电常数。
可选的，包括：
形成所述第一阻挡结构的材料为氮化硅，形成所述介质层的材料为氧化硅。
可选的，在形成所述介质层的步骤之后、且形成导电层的步骤之前还包括：
形成第二阻挡层，所述第二阻挡层覆盖所述介质层的上表面、所述第二沟槽结构的底部和所述第二沟槽结构的侧壁。
可选的，包括：
形成所述第二阻挡层的材料包括氮化钛。
可选的，包括：
所述介质层覆盖所述第一阻挡结构的上表面。
为了解决上述问题，本申请还提供了一种半导体结构，包括：
衬底；
第一阻挡结构，所述第一阻挡结构间隔分布于所述衬底上，且相邻所述第一阻挡结构之间具有暴露所述衬底的第一沟槽结构；
介质层，所述介质层至少填充满部分所述第一沟槽结构，所述介质层具有第二沟槽结构且所述第二沟槽结构暴露部分所述第一阻挡结构；其中，形成所述第一阻挡结构的材料的致密度大于形成所述介质层的材料的致密度；
导电层，所述导电层填充满所述第二沟槽结构。
可选的，形成所述第一阻挡结构的材料的介电常数大于形成所述介质层的材料的介电常数。
可选的，形成所述第一阻挡结构的材料为氮化硅，形成所述介质层的材料为氧化硅。
可选的，还包括：
第二阻挡层，所述第二阻挡层位于所述介质层和所述导电层之间且所述第 二阻挡层覆盖所述介质层的上表面、所述第二沟槽结构的底部和所述第二沟槽结构的侧壁。
可选的，形成所述第二阻挡层的材料为氮化钛。
可选的，所述介质层覆盖所述第一阻挡结构的上表面。
本申请提供的半导体结构的形成方法及半导体结构，在介质层中内嵌第一阻挡结构，且形成第一阻挡结构的材料的致密度大于形成介质层的材料的致密度，可以在刻蚀介质层形成栓塞导线的过程中防止通孔的角落处产生损伤。另外，通过内嵌式第一阻挡结构可以防止栓塞导线向介质层中扩散，从而增加所述导电层的稳定性，进而提高整个器件结构的可靠性。而且，在介质层中内嵌第一阻挡结构，在大幅度提高栓塞导线结构稳定性的情况下，只增加了少量的寄生电容，保证了半导体器件的电性能。
附图说明
附图1是本申请具体实施方式中半导体结构的形成方法流程图；
附图2A-2J是本申请具体实施方式在形成半导体结构的过程中主要的工艺截面示意图。
具体实施方式
下面结合附图对本申请提供的半导体结构的形成方法及半导体结构的具体实施方式做详细说明。
本具体实施方式提供了一种半导体结构的形成方法，附图1是本申请具体实施方式中半导体结构的形成方法流程图，附图2A-2J是本申请具体实施方式在形成半导体结构的过程中主要的工艺截面示意图。本具体实施方式所述的半导体结构可以是但不限于动态随机存储器(Dynamic Random Access Memory，DRAM)。如图1、图2A-图2J所示，本具体实施方式提供的半导体结构的形成方法，包括如下步骤：
步骤S11，提供衬底20。
具体来说，所述衬底20可以是但不限于硅衬底或者多晶硅衬底，本具体实施方式中以所述衬底20为硅衬底为例进行说明，所述衬底20用于支撑在其上的器件结构。在其他示例中，所述衬底20可以为氮化镓、砷化镓、碳化镓、碳化硅或SOI等半导体衬底。所述衬底20可以为单层衬底，也可以为由多个 半导体层叠置构成的多层衬底，本领域技术人员可以根据实际需要进行选择。所述衬底20内部还可以设置有有源区、晶体管、浅沟槽隔离结构、字线等结构。
步骤S12，于所述衬底20上形成多个间隔分布的第一阻挡结构211，相邻所述第一阻挡结构211之间具有暴露所述衬底20的第一沟槽结构212，如图2F所示。
可选的，于所述衬底20上形成多个间隔分布的第一阻挡结构211的具体步骤包括：
于所述衬底20上形成第一阻挡层21，所述第一阻挡层21覆盖所述衬底20，如图2A所示；
于所述第一阻挡层21上形成介电层231，所述介电层231具有第三沟槽结构30，且所述第三沟槽结构30在所述衬底20上的投影与所述第一沟槽结构212在所述衬底20上的投影重合，如图2E所示；
以所述介电层231为掩模版刻蚀所述第一阻挡层21，如图2F所示；
去除所述介电层231。
具体来说，在形成所述衬底20之后，可以采用化学气相沉积工艺、物理气相沉积工艺或者原子层沉积工艺于所述衬底20表面沉积第一阻挡层21，第一阻挡层21覆盖衬底20的表面。之后，根据所需形成的所述第一阻挡结构211的形状以及相邻所述第一阻挡结构211之间的第一沟槽结构212的形状，于所述第一阻挡层21表面形成介电层231，所述介电层231中具有第三沟槽结构30，如图2E所示。所述第三沟槽结构30在垂直于所述衬底20方向上投影与最终所要形成的所述第一沟槽结构212在垂直于所述衬底20方向上的投影重合。在形成具有所述第三沟槽结构30的所述介电层231之后，以所述介电层231为掩模版，采用刻蚀等方式对所述第一阻挡层21进行图案化处理，在所述第一阻挡层21中形成多个沿垂直于所述衬底20的方向贯穿所述第一阻挡层21的第一沟槽结构212，多个所述第一沟槽结构212将剩余的所述第一阻挡层21分割为多个相互独立的所述第一阻挡结构211。本具体实施方式中所述的多个是指两个及两个以上。多个间隔分布的所述第一阻挡结构211是指，任意两个所述第一阻挡结构211之间物理隔离(即任意相连的两个所述第一阻挡结构 211之间具有第一沟槽结构212)，即任意两个所述第一阻挡结构211互不连接。
本具体实施方式是以所述介电层231中具有多个宽度不同的所述第三沟槽结构30(例如图2E中所述的第三沟槽结构30包括宽度不同的第一子沟槽结构222和第二子沟槽结构223)为例进行说明，本领域技术人员也可以根据实际需要设置所述介电层中的所有所述第三沟槽结构30的的宽度均相同。在本具体实施方式中，所述第三沟槽结构30的宽度是指所述第三沟槽结构30的内径。
可选的，于所述第一阻挡层21上形成介电层231的具体步骤包括：
于所述第一阻挡层21上形成初始掩膜层22，所述初始掩膜层22覆盖所述第一阻挡层21，如图2A所示；
图形化所述初始掩膜层22，形成掩膜层31，所述掩膜层31具有第四沟槽结构221，如图2B所示；
形成初始介电层23，所述初始介电层23至少覆盖所述第四沟槽结构221的底部及侧壁，如图2C所示；
去除所述掩膜层31和部分所述初始介电层23，保留覆盖所述第四沟槽结构221侧壁的所述初始介电层23，作为所述介质层231，如图2E所示。
可选的，所述形成初始介电层23，所述初始介电层23至少覆盖所述第四沟槽结构221的底部及侧壁包括：
采用原子层沉积法形成所述初始介电层23。原子层沉积工艺相较于其他沉积工艺，可以很好的控制沉积的薄膜的均匀性，采用原子层沉积法形成初始介电层23，可以保证初始介电层23在各个位置的厚度相同，从而保证后续形成的半导体结构的稳定性。
举例来说，在所述衬底20表面形成所述第一阻挡层21之后，于所述第一阻挡层21表面沉积所述初始掩膜层22，使得所述初始掩膜层22完全覆盖所述第一阻挡层21，如图2A所示。所述初始掩膜层22的材料可以是有机掩膜材料，例如SOC；也可以是硬掩膜材料，例如多晶硅。所述初始掩膜层22可以通过化学气相沉积工艺或者原子层沉积工艺形成于所述第一阻挡层21表面。之后，对所述初始掩膜层22进行图案化，即采用干法刻蚀工艺或者湿法刻蚀工艺刻蚀对所述初始掩膜层22进行刻蚀，在所述初始掩膜层22中形成沿垂直 于所述衬底20的方向贯穿所述初始掩膜层22的第四沟槽结构221，形成掩膜层31，如图2B所示。
接着，采用原子层沉积工艺沉积氧化硅材料等，形成覆盖所述第四沟槽结构221内壁(包括所述第四沟槽结构221的底部和侧壁)和所述掩膜层31顶面(即所述掩膜层31背离所述衬底20的表面)的所述初始介电层23，如图2C所示。采用原子层沉积工艺形成的所述初始介电层23的均匀性较好，确保了后续形成的所述第一阻挡结构211的形貌均匀性。为了便于后续对所述掩膜层31进行选择性去除，所述掩膜层31的材料与所述初始介电层23的材料之间应该具有较高的刻蚀选择比，例如所述掩膜层31与所述初始介电层23之间的刻蚀选择比大于3(例如刻蚀选择比为5)。然后，采用刻蚀等方式去除覆盖于所述掩膜层31顶面和所述第四沟槽结构221底部的所述初始介电层23，仅保留覆盖于所述第四沟槽结构221侧壁的所述初始介电层23，并以覆盖于所述第四沟槽结构221侧壁的所述初始介电层23作为所述介电层231，如图2D所示。之后，采用湿法刻蚀方式清洗或者方向性较强的干法刻蚀工艺去除所有的所述掩膜层31，形成如图2E所示的所述第三沟槽结构30，所述第三沟槽结构30包括第一子沟槽结构222和第二子沟槽结构223。所述第一子沟槽结构222与所述第二子沟槽结构223的宽度可以相同，也可以不同。其中，所述第一子沟槽结构222是在形成所述介电层231之后形成，且所述第一子沟槽结构222是在去除残留的所述掩膜层31的位置形成。所述第二子沟槽结构223也是在形成所述介电层231之后形成，且所述第二子沟槽结构223是于所述第四沟槽结构221的位置形成。在图2E所示的结构中，沿平行于所述衬底20的表面的方向上，所述第一子沟槽结构222与所述第二子沟槽结构223交替排列。
接着，采用干法刻蚀工艺沿所述第一子沟槽结构222和所述第二子沟槽结构223刻蚀所述第一阻挡层21，在所述第一阻挡层21中形成多个沿垂直于所述衬底20的方向贯穿所述第一阻挡层21的第一沟槽结构212，残留的所述第一阻挡层21作为所述第一阻挡结构211，如图2F所示。
步骤S13，形成初始介质层24，所述初始介质层24填充满所述第一沟槽结构212。
步骤S14，去除部分所述初始介质层24，以形成介质层242，所述介质层 242中具有第二沟槽结构241，所述第二沟槽结构241暴露部分所述第一阻挡结构211；其中，形成所述第一阻挡结构211的材料的致密度大于形成所述介质层242的材料的致密度，如图2H所示。
具体来说，在形成所述第一阻挡结构211和位于相邻所述第一阻挡结构211之间的所述第一沟槽结构212之后，采用化学气相沉积工艺沉积氧化硅等材料，形成填充满所有所述第一沟槽结构212并完全覆盖所有所述第一阻挡结构211顶面(即所述第一阻挡结构211背离所述衬底20的表面)的所述初始介质层24，如图2G所示。之后，采用干法刻蚀工艺刻蚀部分所述初始介质层24，以形成沿垂直于所述衬底20的方向贯穿所述初始介质层24的第二沟槽结构241，所述第二沟槽结构241将所述初始介质层24分隔为多个介质层242，如图2H所示。
本具体实施方式通过限定形成所述第一阻挡结构211的材料的致密度大于形成所述介质层242的材料的致密度，使得所述第一阻挡结构211相对于所述介质层242能够更好的阻挡后续形成的导电层26中导电粒子的扩散，避免了所述导电层26中的导电粒子自所述第二沟槽结构241的角落处的扩散，减少了漏电流的产生。
步骤S15，形成导电层26，所述导电层26填充满所述第二沟槽结构241，如图2I所示。
可选的，在形成所述介质层242的步骤之后、且形成导电层26的步骤之前还包括：
形成第二阻挡层25，所述第二阻挡层25覆盖所述介质层242的上表面、所述第二沟槽结构241的底部和所述第二沟槽结构241的侧壁。
可选的，所述半导体结构的形成方法，还包括：
形成所述第二阻挡层25的材料包括氮化钛。氮化钛材料具有较大的致密度，可以较好的阻挡导电层26渗透到介质层242中，并且氮化钛材料具有一定的导电性，可以保证栓塞导线的导电能力。
具体来说，在刻蚀部分所述初始介质层24形成所述第二沟槽结构241之后，采用原子层沉积工艺或者化学气相沉积工艺沉积氮化钛等阻挡材料于所述第二沟槽结构241的内壁、所述介质层242的顶面(即所述介质层242背离所 述衬底20的表面)、以及通过所述第二沟槽结构241的侧壁暴露的所述第一阻挡结构211的表面。然后，通过物理气相沉积工艺、化学气相沉积工艺、原子层沉积工艺或者电镀工艺将所述第二沟槽结构241填满，形成所述导电层26，如图2I所示。
可选的，所述半导体结构的形成方法包括：
所述介质层242覆盖所述第一阻挡结构211的上表面。
具体来说，在沿垂直于所述衬底20的方向上，所述介质层242的高度大于所述第一阻挡结构211的高度，从而避免增大半导体结构内部的寄生电容，确保所述半导体结构的性能稳定性。其中，所述介质层242的高度与所述第一阻挡结构211的高度之间的相对比例关系，本领域技术人员可以根据实际需要进行选择，例如根据所述第一阻挡结构211的具体材料等。可选的，所述介质层242的高度为所述第一阻挡结构211的高度的2倍以上。
可选的，相邻的两个所述第二沟槽结构241之间具有三个以上的所述第一阻挡结构211。
具体来说，如图2H所示，每个所述第二沟槽结构241的侧壁暴露有两个所述第一阻挡结构211的侧壁。在通过相邻的两个所述第二沟槽结构241暴露的两个所述第一阻挡结构211之间还具有至少一个被所述介质层242覆盖的所述第一阻挡结构211，从而可以更好地避免相邻所述导电层26之间的漏电。
在其他具体实施方式中，本领域技术人员可以通过修改所述掩膜层31中的图案，使得相邻的两个所述第二沟槽结构241之间具有且仅具有两个所述第一阻挡结构211。举例来说，如图2J所示，在相邻的两个所述第二沟槽结构241中，每个所述第二沟槽结构241的侧壁暴露两个所述第一阻挡结构211。在通过相邻的两个所述第二沟槽结构241暴露的两个所述第一阻挡结构211之间不设置另外的所述第一阻挡结构211，从而可以简化制程工艺。
可选的，在沿所述第二沟槽结构241的径向方向上，所述第一阻挡结构211的宽度小于或者等于所述第二阻挡层25的宽度。
具体来说，通过将所述第一阻挡结构211的宽度设置为小于或者等于所述第二阻挡层25的宽度，可以在不增加半导体结构的寄生电容的同时，确保相邻所述第二沟槽结构241之间的间隔宽度，从而不对所述导电层26的特征尺 寸造成影响。
为了减小寄生电容的影响，可选的，所述半导体结构的形成方法还包括：
形成所述第一阻挡结构211的材料的介电常数大于形成所述介质层242的材料的介电常数。
可选的，形成所述第一阻挡结构211的材料为氮化硅，形成所述介质层242的材料为氧化硅。
不仅如此，本具体实施方式还提供了一种半导体结构。本具体实施方式提供的半导体结构可以采用如图1、图2A-图2J所示的半导体结构的形成方法形成。本具体实施方式提供的半导体结构的示意图可参见图2I和图2J。如图2I和图2J所示，本具体实施方式提供的半导体结构，包括：
衬底20；
第一阻挡结构211，所述第一阻挡结构211间隔分布于所述衬底20上，且相邻所述第一阻挡结构211之间具有暴露所述衬底20的第一沟槽结构212；
介质层242，所述介质层242至少填充满部分所述第一沟槽结构212，所述介质层242具有第二沟槽结构241且所述第二沟槽结构241暴露部分所述第一阻挡结构211；其中，形成所述第一阻挡结构211的材料的致密度大于形成所述介质层242的材料的致密度；
导电层26，所述导电层26填充满所述第二沟槽结构241。
可选的，形成所述第一阻挡结构211的材料的介电常数大于形成所述介质层242的材料的介电常数。
可选的，形成所述第一阻挡结构211的材料为氮化硅，形成所述介质层242的材料为氧化硅。
可选的，所述半导体结构还包括：
第二阻挡层25，所述第二阻挡层25位于所述介质层242和所述导电层26之间且所述第二阻挡层25覆盖于所述介质层242的上表面、所述第二沟槽结构241的底部和所述第二沟槽结构241的侧壁。
可选的，形成所述第二阻挡层25的材料为氮化钛。
可选的，所述介质层242覆盖所述第一阻挡结构211的上表面。
具体来说，在沿垂直于所述衬底20的方向上，所述介质层242的高度大 于所述第一阻挡结构211的高度，从而避免增大半导体结构内部的寄生电容，确保所述半导体结构的性能稳定性。其中，所述介质层242的高度与所述第一阻挡结构211的高度之间的相对比例关系，本领域技术人员可以根据实际需要进行选择，例如根据所述第一阻挡结构211的具体材料等。可选的，所述介质层242的高度为所述第一阻挡结构211的高度的2倍以上。
可选的，相邻的两个所述第二沟槽结构241之间具有三个以上的所述第一阻挡结构211。
具体来说，如图2I所示，每个所述第二沟槽结构241的侧壁暴露两个所述第一阻挡结构211，在通过相邻的两个所述第二沟槽结构241暴露的两个所述第一阻挡结构211之间还具有至少一个被所述介质层242覆盖的所述第一阻挡结构211，从而可以更好地避免相邻所述导电层26之间的漏电。
在其他具体实施方式中，本领域技术人员可以通过修改所述掩膜层31中的图案，使得相邻的所述第二沟槽结构241之间具有且仅具有两个所述第一阻挡结构211。举例来说，如图2J所示，每个所述第二沟槽结构241的侧壁暴露两个所述第一阻挡结构211，在通过相邻的两个所述第二沟槽结构241暴露的两个所述第一阻挡结构211之间不设置另外的所述第一阻挡结构211，从而可以简化制程工艺。
可选的，在沿所述第二沟槽结构241的径向方向上，所述第一阻挡结构211的宽度小于或者等于所述第二阻挡层25的宽度。
具体来说，通过将所述第一阻挡结构211的宽度设置为小于或者等于所述第二阻挡层25的宽度，可以在不增加半导体结构的寄生电容的同时，确保相邻所述第二沟槽结构241之间的间隔宽度。
可选的，所述第一阻挡结构211的材料为SIN、SICN中的一种或者两种的组合。本实施例中，所述第一阻挡结构211的材料为SIN。
具体来说，所述第一阻挡结构211的材料可以与所述第二阻挡层25的材料相同，也可以与所述第二阻挡层25的材料不同。在本具体实施方式中，为了进一步提高所述导电层26的稳定性，更好的避免漏电，所述第一阻挡结构211的材料与所述第二阻挡层25的材料不同。例如，所述第一阻挡结构211的材料为SIN；所述第二阻挡层25的材料为TiN。所述导电层26的材料为金 属材料，例如Cu或者Al。
本具体实施方式提供的半导体结构的形成方法及半导体结构，在介质层中内嵌第一阻挡结构，且形成第一阻挡结构的材料的致密度大于形成介质层的材料的致密度，可以在刻蚀介质层形成栓塞导线的过程中防止通孔的角落处产生损伤。另外，通过内嵌式第一阻挡结构可以防止栓塞导线向介质层中扩散，从而增加所述导电层的稳定性，进而提高整个器件结构的可靠性。而且，在介质层中内嵌第一阻挡结构，在大幅度提高栓塞导线结构稳定性的情况下，只增加了少量的寄生电容，保证了半导体器件的电性能。
以上所述仅是本申请的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (15)

  1. 一种半导体结构的形成方法，包括如下步骤：
    提供衬底；
    于所述衬底上形成多个间隔分布的第一阻挡结构，相邻所述第一阻挡结构之间具有暴露所述衬底的第一沟槽结构；
    形成初始介质层，所述初始介质层填充满所述第一沟槽结构；
    去除部分所述初始介质层，以形成介质层，所述介质层具有第二沟槽结构，所述第二沟槽结构暴露部分所述第一阻挡结构；其中，形成所述第一阻挡结构的材料的致密度大于形成所述介质层的材料的致密度；
    形成导电层，所述导电层填充满所述第二沟槽结构。
  2. 根据权利要求1所述的半导体结构的形成方法，其中，于所述衬底上形成多个间隔分布的第一阻挡结构的步骤包括：
    于所述衬底上形成第一阻挡层，所述第一阻挡层覆盖所述衬底；
    于所述第一阻挡层上形成介电层，所述介电层具有第三沟槽结构，且所述第三沟槽结构在所述衬底上的投影与所述第一沟槽结构在所述衬底上的投影重合；
    以所述介电层为掩模版刻蚀所述第一阻挡层；
    去除所述介电层。
  3. 根据权利要求2所述的半导体结构的形成方法，其中，于所述第一阻挡层上形成介电层的具体步骤包括：
    于所述第一阻挡层上形成初始掩膜层，所述初始掩膜层覆盖所述第一阻挡层；
    图形化所述初始掩膜层，形成掩膜层，所述掩膜层具有第四沟槽结构；
    形成初始介电层，所述初始介电层至少覆盖所述第四沟槽结构的底部及侧壁；
    去除所述掩膜层和部分所述初始介电层，保留覆盖所述第四沟槽结构侧壁的所述初始介电层。
  4. 根据权利要求3所述的半导体结构的形成方法，其中，所述形成初始介电 层，所述初始介电层至少覆盖所述第四沟槽结构的底部及侧壁包括：
    采用原子层沉积法形成所述初始介电层。
  5. 根据权利要求1所述的半导体结构的形成方法，包括：
    形成所述第一阻挡结构的材料的介电常数大于形成所述介质层的材料的介电常数。
  6. 根据权利要求5所述的半导体结构的形成方法，包括：
    形成所述第一阻挡结构的材料为氮化硅，形成所述介质层的材料为氧化硅。
  7. 根据权利要求1所述的半导体结构的形成方法，其中，在形成所述介质层的步骤之后、且形成导电层的步骤之前还包括：
    形成第二阻挡层，所述第二阻挡层覆盖所述介质层的上表面、所述第二沟槽结构的底部和所述第二沟槽结构的侧壁。
  8. 根据权利要求7所述的半导体结构的形成方法，包括：
    形成所述第二阻挡层的材料包括氮化钛。
  9. 根据权利要求1所述半导体结构的形成方法，包括：
    所述介质层覆盖所述第一阻挡结构的上表面。
  10. 一种半导体结构，包括：
    衬底；
    第一阻挡结构，所述第一阻挡结构间隔分布于所述衬底上，且相邻所述第一阻挡结构之间具有暴露所述衬底的第一沟槽结构；
    介质层，所述介质层至少填充满部分所述第一沟槽结构，所述介质层具有第二沟槽结构且所述第二沟槽结构暴露部分所述第一阻挡结构；其中，形成所述第一阻挡结构的材料的致密度大于形成所述介质层的材料的致密度；
    导电层，所述导电层填充满所述第二沟槽结构。
  11. 根据权利要求10所述的半导体结构，其中，形成所述第一阻挡结构的材料的介电常数大于形成所述介质层的材料的介电常数。
  12. 根据权利要求11所述的半导体结构，其中，形成所述第一阻挡结构的材料为氮化硅，形成所述介质层的材料为氧化硅。
  13. 根据权利要求11所述的半导体结构，还包括：
    第二阻挡层，所述第二阻挡层位于所述介质层和所述导电层之间且所述第二阻挡层覆盖所述介质层的上表面、所述第二沟槽结构的底部和所述第二沟槽结构的侧壁。
  14. 根据权利要求13所述的半导体结构，其中，形成所述第二阻挡层的材料为氮化钛。
  15. 根据权利要求10所述的半导体结构，其中，所述介质层覆盖所述第一阻挡结构的上表面。
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