TWI553780B - 接觸結構以及採用該接觸結構的半導體記憶元件 - Google Patents

接觸結構以及採用該接觸結構的半導體記憶元件 Download PDF

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TWI553780B
TWI553780B TW102113657A TW102113657A TWI553780B TW I553780 B TWI553780 B TW I553780B TW 102113657 A TW102113657 A TW 102113657A TW 102113657 A TW102113657 A TW 102113657A TW I553780 B TWI553780 B TW I553780B
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semiconductor memory
dielectric layer
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俞建安
吳奇煌
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南亞科技股份有限公司
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    • H01—ELECTRIC ELEMENTS
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Description

接觸結構以及採用該接觸結構的半導體記憶元件
本發明係有關於一種接觸結構以及採用該接觸結構的半導體元件，特別是有關於一種置於高密度記憶體陣列中的接觸結構，用以拾接記憶體陣列區域內的位址線(address lines)。
為了獲得更高密度的動態隨機存取記憶體(DRAM)晶片，半導體工業面臨的挑戰是如何將記憶胞單元進一步的微縮。過去幾個世代，DRAM製造業者已發展出各種記憶胞佈局，目的在減少其所佔晶片面積。最近的設計是將位址線埋入在矽基材中，再將電晶體及電容製作於上面，構成垂直堆疊，藉以提高晶片密度。
目前的DRAM製程中，仍須要額外的製程步驟，將第一層金屬接觸連接至靠近陣列邊緣的週邊區內的位址線，例如，位元線。對於非常高密度的記憶體陣列，且各個記憶胞大小約為4F2來說(F為製程最小尺寸)，幾乎已無空間在高密度的記憶體陣列區域內對位元線進行拾接，尤其是在陣列中央，因此，影響到電路佈局的應用，並且使得晶片尺寸無法進一步縮小。由此可知，該技術領域仍需要改良的接觸結構，使其可以被佈置在高密度記憶體陣列內，用以拾接位址線。
本發明的主要目的即在於提供一種改良的接觸結構，以解決上述先前技藝的不足與缺點。
為達上述目的，本發明披露一種半導體記憶元件，包含有一 基材，其上包含一記憶陣列區域以及一週邊電路區域；一第一介電層，覆蓋該記憶陣列區域以及該週邊電路區域；一第二介電層，位於該第一介電層上，覆蓋該記憶陣列區域以及該週邊電路區域；至少一電容結構，位於該記憶陣列區域內，且該電容結構包含一電極材料層，埋設在該第二介電層中；以及一接觸結構，包含該電極材料層以及一導電接觸材料層，該導電接觸材料層位在該電極材料層上並直接接觸該電極材料層。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉較佳實施方式，並配合所附圖式，作詳細說明如下。然而如下之較佳實施方式與圖式僅供參考與說明用，並非用來對本發明加以限制者。
10‧‧‧基材
12‧‧‧第一介電層
14‧‧‧第二介電層
16‧‧‧硬遮罩層
20‧‧‧插塞
20a‧‧‧插塞
20b‧‧‧插塞
22‧‧‧開孔
22a‧‧‧開孔
22b‧‧‧開孔
24‧‧‧電極材料層
26‧‧‧犧牲層
32‧‧‧第三介電層
32a‧‧‧開口
32b‧‧‧開口
40‧‧‧接觸材料層
40a‧‧‧接觸結構
40b‧‧‧接觸結構
102‧‧‧記憶陣列區域
104‧‧‧週邊電路區域
第1圖至第5圖為依據本發明實施例所繪示的與堆疊電容製程相容的接觸結構製作方法的剖面示意圖。
在下文中，將參照附圖說明本發明實施細節，該些附圖中之內容構成說明書一部份，並以可實行該實施例之特例描述方式繪示。下文實施例已揭露足夠的細節俾使該領域之一般技藝人士得以具以實施。當然，本發明中亦可採行其他的實施例，或是在不悖離文中所述實施例的前提下作出任何結構性、邏輯性、及電性上的改變。因此，下文之細節描述將不欲被視為是一種限定，反之，其中所包含的實施例將由隨附的申請專利範圍來加以界定。
文中所提及的「晶圓」或「基材」等名稱可以是在表面上已有材料層或積體電路元件層的半導體基底，其中，基材可以被理解為包括半導體晶圓。基材也可以指在製作過程中的半導體基底或晶圓，其上形成有不同材料層。舉例而言，晶圓或基材可以包括摻雜或未摻雜半導 體、在絕緣材或半導體底材上形成的磊晶半導體、及其它已知的半導體結構。
本發明主要披露一種置於高密度記憶體陣列中的接觸結構，用以拾接記憶體陣列區域內的位址線，然而，熟習該項技藝者應能理解所披露的接觸結構也可以被應用在記憶體陣列外的週邊電路區域。例如，所披露的接觸結構還可能被應用在位元線拾接接觸、週邊電路元件、字元線編結(word line stitch)、或特殊的分層數位線的應用。此外，熟習該項技藝者應理解一個記憶胞通常由一個電容及一個電晶體所構成。
本發明係特別適合被應用在動態隨機存取記憶體胞結構中，其中具有堆疊式記憶胞佈局以及埋入式位元線或字元線，另外，亦適合被應用在結合該等動態隨機存取記憶體胞結構的積體電路，其中各個動態隨機存取記憶體胞所佔面積大小為4F2(F指製程最小尺寸)。
第1圖至第5圖例示一種與目前堆疊電容製程相容的接觸結構製作方法。如第1圖所示，先提供一基材10，其中，為簡化說明，已製作在基材10中的電晶體或絕緣結構將不顯示。在基材10表面上形成有一第一介電層12，在第一介電層12中有複數個插塞20、20a及20b。舉例來說，插塞20及20a係製作於記憶體陣列區域102內，而插塞20b(僅例示其中一個)係製作於週邊電路區域104內，其中週邊電路區域104靠近記憶體陣列區域102。根據本發明實施例，插塞20、20a及20b可以是鎢插塞。根據本發明實施例，插塞20係用以耦合一電容，更明確的說，是耦合記憶胞的下電極。插塞20a及20b則作為相對應接觸結構的基座，用來拾接，例如，位元線或編結字元線。根據本發明實施例，插塞20可以電連結至一垂直通道電晶體的汲極或源極(圖未示)。
仍然參閱第1圖，在形成插塞20、20a及20b之後，接著在第一介電層12上沈積一第二介電層14，例如，硼磷矽玻璃(BPSG)等，覆蓋在第一介電層12以及插塞20、20a及20b上。然後，在第二介電層14 上沈積一硬遮罩層16，例如，氮化矽層。第二介電層14及硬遮罩層16的厚度總和大致上決定了在記憶陣列區域102內記憶胞的電容高度。接著，以微影及蝕刻製程在硬遮罩層16及第二介電層14內蝕刻出開孔22、22a及22b，其分別顯露出插塞20、20a及20b。
如第2圖所示，在基材10上先沈積均厚的電極材料層24，例如，氮化鈦層或類似材料，使電極材料層24共形的覆蓋硬遮罩層16上表面以及開孔22、22a及22b的表面。值得注意的是，電極材料層24並不會填滿開孔22、22a及22b。然後，在電極材料層24表面形成一犧牲層26，例如，光阻材料，並填滿開孔22、22a及22b。再以化學機械研磨(CMP)製程移除開孔22、22a及22b外的犧牲層26及電極材料層24，其中以硬遮罩層16作為研磨停止層。在完成CMP製程後，硬遮罩層16的上表面約略與犧牲層26的上表面齊平。
如第3圖所示，接著以低溫化學氣相沈積製程在基材10上沈積一第三介電層32，例如，二氧化矽或氮化矽。根據本發明實施例，上述低溫化學氣相沈積製程可以包括原子層沈積法。第三介電層32覆蓋硬遮罩層16上表面以及犧牲層26的上表面。然後，以微影及蝕刻製程在記憶陣列區域102內形成開口32a，在週邊電路區域104內形成開口32b，其中開口32a顯露出位於開孔22a中的犧牲層26，開口32b顯露出位於開孔22b中的犧牲層26。接下來，以圖案化的第三介電層32作為硬遮罩，進行乾蝕刻製程，將顯露出來的犧牲層26從開孔22a及22b完全去除，如此顯露出開孔22a及22b的電極材料層24。
如第4圖所示，接著在基材10上沈積一接觸材料層40。由於開孔22a及22b的尺寸通常非常小，因此較佳是採用原子層沈積法來沈積接觸材料層40，以確保開孔22a及22b可以被完全填滿，而無孔洞或間隙形成。根據本發明實施例，接觸材料層40可以是鈦、氮化鈦或其他材料所構成。
如第5圖所示，沈積接觸材料層40之後，繼續進行CMP製程，去除開孔22a及22b外多出的接觸材料層40。較佳者，可以將第三介電層32在此步驟中一併移除，顯露出開孔22的犧牲層26以及硬遮罩層16的上表面，如此在記憶陣列區域102內形成接觸結構40a，而在週邊電路區域104內形成接觸結構40b。接續上述接觸結構製作方法，還可以另外進行記憶陣列區域102內電容其餘部分的製作，例如，先將開孔22內的犧牲層26移除以顯露出電極材料層24，其可以作為電容的下電極。然後，可以在下電極上形成電容介電層(圖未示)，再於電容介電層上形成上電極(圖未示)。
本發明的優點在於接觸結構製程係與電容製作步驟整合，如此一來，第一層金屬到位元線的接觸即可被佈置在記憶陣列的中央，用以拾接位元線或位址線，因此，無需再將位元線延伸至週邊線路區域，這使得晶片面積可以進一步縮小。此外，在週邊電路區域內的接觸結構也可以與電容製作步驟整合在一起，如此，傳統設置在陣列邊緣的拾接接觸即可省略以節省成本。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
10‧‧‧基材
12‧‧‧第一介電層
14‧‧‧第二介電層
16‧‧‧硬遮罩層
20‧‧‧插塞
20a‧‧‧插塞
20b‧‧‧插塞
24‧‧‧電極材料層
26‧‧‧犧牲層
40‧‧‧接觸材料層
40a‧‧‧接觸結構
40b‧‧‧接觸結構
102‧‧‧記憶陣列區域
104‧‧‧週邊電路區域

Claims (12)

  1. 一種半導體記憶元件，包含有：一基材，其上包含一記憶陣列區域以及一週邊電路區域；一第一介電層，覆蓋該記憶陣列區域以及該週邊電路區域；一第二介電層，位於該第一介電層上，覆蓋該記憶陣列區域以及該週邊電路區域；第一插塞以及一第二插塞，僅埋設在該第一介電層中；至少一電容結構，位於該記憶陣列區域內，且該電容結構包含一電極材料層，埋設在該第二介電層中；以及一接觸結構，包含該電極材料層以及一導電接觸材料層，該導電接觸材料層位在該電極材料層上並直接接觸該電極材料層，其中該接觸結構係埋設在該第二介電層中，其中該電容結構與該接觸結構具有相同的高度。
  2. 如申請專利範圍第1項所述之一種半導體記憶元件，其中該第一插塞係電連接至該電容結構的下電極。
  3. 如申請專利範圍第1項所述之一種半導體記憶元件，其中該第二插塞係電連接至該接觸結構。
  4. 如申請專利範圍第1項所述之一種半導體記憶元件，其中該電容結構係埋設在該第二介電層的一第一開孔中。
  5. 如申請專利範圍第4項所述之一種半導體記憶元件，其中該接觸結構係埋設在該第二介電層的第二開孔中。
  6. 如申請專利範圍第5項所述之一種半導體記憶元件，其中該電極材料層覆蓋在該第一、第二開孔的表面上。
  7. 如申請專利範圍第1項所述之一種半導體記憶元件，其中該第一、第二插塞為鎢插塞。
  8. 如申請專利範圍第1項所述之一種半導體記憶元件，其中該接觸結構係位於該記憶陣列區域內。
  9. 如申請專利範圍第1項所述之一種半導體記憶元件，其中該接觸結構係位於該週邊電路區域內。
  10. 如申請專利範圍第1項所述之一種半導體記憶元件，其中該電極材料層包含氮化鈦。
  11. 如申請專利範圍第1項所述之一種半導體記憶元件，其中該接觸結構包含鈦或氮化鈦。
  12. 如申請專利範圍第5項所述之一種半導體記憶元件，其中該接觸材料層完全填滿該第二開孔。
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