WO2021056984A1 - 电接触结构、接触垫版图及结构、掩模板组合及制造方法 - Google Patents

电接触结构、接触垫版图及结构、掩模板组合及制造方法 Download PDF

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Publication number
WO2021056984A1
WO2021056984A1 PCT/CN2020/079580 CN2020079580W WO2021056984A1 WO 2021056984 A1 WO2021056984 A1 WO 2021056984A1 CN 2020079580 W CN2020079580 W CN 2020079580W WO 2021056984 A1 WO2021056984 A1 WO 2021056984A1
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Prior art keywords
contact
area
contact pad
edge
main
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PCT/CN2020/079580
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English (en)
French (fr)
Inventor
童宇诚
詹益旺
黄永泰
方晓培
吴少一
曾依蕾
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福建省晋华集成电路有限公司
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Priority claimed from CN201910926990.4A external-priority patent/CN111640747A/zh
Priority claimed from CN201910926986.8A external-priority patent/CN111640733A/zh
Application filed by 福建省晋华集成电路有限公司 filed Critical 福建省晋华集成电路有限公司
Publication of WO2021056984A1 publication Critical patent/WO2021056984A1/zh
Priority to US17/320,244 priority Critical patent/US20210272961A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures

Definitions

  • the present invention relates to the field of semiconductor technology, in particular to an electrical contact structure and a manufacturing method thereof, a contact pad layout, a contact pad structure, a mask plate combination, a semiconductor device and a manufacturing method thereof.
  • integrated circuits Due to the difference in circuit pattern spacing, integrated circuits are generally divided into device dense area (Dense), device sparse area (ISO) and device isolated area.
  • the device dense area is the area with higher device density (that is, the device is denser), and the device sparse area It is an area where the device density is low (that is, the device is relatively sparse), and the device isolated area is an area where the relatively sparse area and the dense area are separately arranged.
  • the density of circuit patterns and/or device heights also continue to increase, subject to the resolution limit of the optical exposure too1 and the density difference between dense and sparse devices.
  • the influence of the effect ie the density/sparse effect of the circuit pattern
  • the difficulty in performing the photolithography process and/or the etching process will also increase a lot (for example, the process margin is reduced), which in turn leads to the deterioration of the manufactured semiconductor device Performance is affected.
  • each memory cell in the array memory area can be composed of a metal oxide semiconductor (MOS) transistor and a capacitor structure in series.
  • MOS metal oxide semiconductor
  • the capacitor is located in the storage area of the array, the capacitor is stacked above the bit line and is electrically coupled to the storage node contact portion corresponding to the capacitor, and the storage node contact portion is electrically coupled to the active area below it.
  • the purpose of the present invention is to provide an electrical contact structure and its manufacturing method, contact pad layout, contact pad structure, mask combination, semiconductor device and its manufacturing method, to solve the existing dynamic random access memory and other semiconductor devices.
  • the optical proximity effect and the dense/sparse effect of the circuit patterns lead to inconsistent electrical structures connected to the contact plugs inside the core area and abnormal electrical structures connected to the contact plugs at the boundary of the core area.
  • the present invention provides an electrical contact structure of a semiconductor device, the electrical contact structure comprising:
  • a plurality of contact plugs are formed above the core element in the core area of the semiconductor device, and the bottom of each contact plug is in contact with the active area of the corresponding core element,
  • the tops of at least two contact plugs formed at the boundary of the core area are connected together, and all the contact plugs connected together at the tops include the outermost contact plug at the boundary.
  • the present invention also provides a semiconductor device, including:
  • a semiconductor substrate having a core region, and a plurality of core elements are formed in the core region;
  • the electrical contact structure of the semiconductor device of the present invention is formed in the interlayer dielectric layer, and the bottom of each contact plug of the electrical contact structure is active with the corresponding core element. Area contact, and the tops of at least two contact plugs formed at the boundary of the core area in the electrical contact structure are connected together, and all the contact plugs connected at the top include the most at the boundary. Contact plug on the outside.
  • the present invention also provides a method for manufacturing an electrical contact structure of a semiconductor device, including:
  • the semiconductor substrate having a core region, and a plurality of core elements are formed in the core region;
  • An interlayer dielectric layer is formed on the semiconductor substrate, and a plurality of contact holes are formed in the interlayer dielectric layer. Each of the contact holes penetrates the interlayer dielectric layer and exposes the active components of the corresponding core element. Area;
  • a contact plug is formed in the contact hole, and the bottom of each contact plug is in contact with the active area of the corresponding core element, and the top of at least two contact plugs formed at the boundary of the core area Are connected together, and all the contact plugs connected together at the top include the outermost contact plug at the boundary.
  • the present invention also provides a method for manufacturing a semiconductor device, including: using the method for manufacturing an electrical contact structure of a semiconductor device according to the present invention, forming a corresponding core on a semiconductor substrate with a core area Electrical contact structure for electrical contact of components.
  • the electrical structure at the boundary and the combined contact structure can have a larger contact area, so the contact resistance is reduced, which is beneficial to improve the electrical performance of the device.
  • the increase in the size of the electrical structure at the boundary can buffer the density difference of the circuit pattern between the core area and the peripheral area, thereby forming all electrical structures in the core area in the lithography process and /Or the optical proximity effect can be improved in the etching process, the sparse/dense load effect can be improved in the etching process, the sparse/dense load effect can be improved in the etching process, the sparse/dense load effect can
  • the present invention also provides a contact pad layout of a semiconductor device, and the contact pad layout includes:
  • the main layout area is provided with a plurality of main contact pad patterns, each of the main contact pad patterns is similar in shape and size, and all the main contact pad patterns are staggered and arranged in a checkerboard shape.
  • the pad patterns have a fourth distance between each other;
  • the first edge layout area is distributed on the outer side of one side of the main layout area, the first edge layout area is provided with at least one first edge contact pad pattern, and the area of each first edge contact pad pattern is larger than For each area of the main contact pad pattern, there is a first edge distance between the first edge layout area and the main layout area;
  • the first edge contact pad pattern is different from the main contact pad pattern, and the first edge pitch is different from the fourth pitch.
  • the present invention also provides a contact pad structure formed by using the contact pad layout of the semiconductor device of the present invention, including:
  • a plurality of main contact pads are arranged alternately in a checkerboard shape, each of the main contact pads is similar in shape and size, and the main contact pads have a fourth distance between each other;
  • At least one first edge contact pad is distributed on the outer side of one side of all the main contact pad arrangement areas, and the top surface area of each first edge contact pad is larger than the top surface area of each main contact pad. There is a first edge distance between the first edge contact pad close to the main contact pad and the nearest main contact pad;
  • the size of the first edge contact pad is different from the size of the main contact pad, and the first edge distance is different from the fourth distance.
  • the present invention also provides a semiconductor device, including:
  • a semiconductor substrate having a core region, and a plurality of core elements are formed in the core region;
  • the contact pad structure of the semiconductor device according to the present invention is formed in the interlayer dielectric layer
  • a plurality of contact plugs are formed in the interlayer dielectric layer, and each contact plug is aligned with the corresponding contact pad in the contact pad structure, so as to electrically connect the corresponding contact pad and the active area of the core element. connection.
  • the present invention also provides a mask combination for manufacturing the contact pad structure of the semiconductor device of the present invention, including:
  • the first mask plate has a plurality of parallel first lines, the first interval between two adjacent first lines is a first interval, and the line width of at least one first line on the outermost side of the first mask plate is larger than that of other first lines A line, the line width of at least one first spacer on the outermost side of the first mask is larger than the line width of other first spacers;
  • the second mask has a plurality of second stripes that are parallel and intersect with each of the first lines, a second spacer area is formed between two adjacent second lines, and at least one second line on the outermost side of the second mask is second
  • the line width of the line is larger than the other second lines, and the line width of the at least one second spacer on the outermost side of the second mask is larger than the line width of the other second spacers;
  • the overlapping area of the first line and the second line is The area where the contact pad is formed; when the first mask and the second mask are heterogeneous masks and the second mask and the first mask are aligned and overlapped, the first line and the second space
  • the overlapping area of the zone is the area where the contact pad is formed.
  • the first edge contact pad pattern can be used to form the corresponding virtual contact at the boundary of the core area or in the boundary area between the core area and the peripheral area.
  • the electrical structure can improve the dense/sparse effect of the circuit pattern between the core area and the peripheral area, improve the consistency of the electrical structure connected to the main contact pad inside the core area, and avoid the main contact pad at the boundary of the core area.
  • the problem of abnormal electrical structure improves the performance of the final formed semiconductor device.
  • FIGS. 1A to 1D are schematic cross-sectional structural diagrams in a method of manufacturing an electrical contact structure of a semiconductor device according to an embodiment of the present invention
  • FIGS. 2A to 2D are schematic diagrams of cross-sectional structures in a method of manufacturing an electrical contact structure of a semiconductor device according to another embodiment of the present invention.
  • FIG. 3 is a schematic top view of a structure in a method of manufacturing a semiconductor device according to an embodiment of the present invention
  • FIG. 4-12 are schematic diagrams of the cross-sectional structure along the line aa' in FIG. 3 in the method of manufacturing a semiconductor device according to an embodiment of the present invention
  • FIG. 13 is a schematic structural diagram of a layout of a contact pad according to an embodiment of the present invention.
  • FIG. 14 is a schematic structural diagram of a contact pad layout according to another embodiment of the present invention.
  • FIG. 15 is a schematic structural diagram of a contact pad layout according to another embodiment of the present invention.
  • 16A is a schematic structural diagram of a contact pad structure according to an embodiment of the present invention.
  • 16B is a schematic structural diagram of a contact pad structure according to another embodiment of the present invention.
  • 17A is a schematic diagram of the structure of the first mask in the mask assembly according to an embodiment of the present invention.
  • 17B is a schematic structural diagram of a second mask in the mask assembly according to an embodiment of the present invention.
  • 18 is a schematic diagram of the structure of the two masks superimposed when the first mask and the second mask in the mask combination of an embodiment of the present invention are both positive masks;
  • 19 is a schematic diagram of the structure of two masks superimposed when the first mask is a positive mask and the second mask is a negative mask in the mask combination of an embodiment of the present invention
  • 20A to 20D are schematic diagrams of the structure in the process of transferring the pattern in the first mask or the second mask to the layer to be etched in an embodiment of the present invention
  • 21A to 21D are schematic diagrams of the structure in the process of transferring the pattern in the first mask or the second mask to the layer to be etched in another embodiment of the present invention.
  • FIG. 22 is a schematic top view of the structure of the semiconductor device manufacturing method according to an embodiment of the present invention.
  • FIGS. 23-25 are schematic diagrams of the cross-sectional structure along the line aa' in FIG. 21A in the method of manufacturing a semiconductor device according to an embodiment of the present invention.
  • I-core area I-1-central area; I-2-boundary; II-peripheral area; III-junction area; BL-bit line; WL-word line; AA1, AA2-active area; S/D1 , S/D2-source region or drain region; G1-gate structure; W1-first width; W2-second width;
  • FIG. 1D is a schematic cross-sectional view showing an electrical contact structure of a semiconductor device according to an embodiment of the invention.
  • the electrical contact structure of the semiconductor device provided by an embodiment of the present invention includes a plurality of contact plugs 106a, 106b, wherein the contact plugs 106a, 106b are formed in the core element ( (Not shown) above, and the bottom of each of the contact plugs 106a, 106b is in contact with the active area 101 of the corresponding core element.
  • the core area I includes the boundary (or called the boundary area, the junction area, the interface area) I-2 and the central area I-1 located within the boundary I-2, which is formed at the boundary of the core area I.
  • the tops of at least two contact plugs 106b of -2 are connected together.
  • the core area I is the device dense area
  • the surrounding peripheral area II is the device sparse area.
  • Each contact plug 106a, 106b, 106c may include a barrier metal layer (not shown) and a metal layer (not shown), and the barrier metal layer may include, for example, Ti, Ta, Mo, Ti x N y , Ta x N y , TixZry, Ti x Zr y N z , Nb x N y , Zr x N y , W x N y , V x N y , Hf x N y , Mo x N y , Ru x N y and/or Ti x Si y N z .
  • the metal layer may include, for example, tungsten, copper, and/or aluminum.
  • All the contact plugs 106b connected to the tops of I-2 at the boundary of the core area I constitute an inverted U-shaped electrical contact structure or a comb-shaped electrical contact structure, that is, the tops of I-2 at the boundary of the core area I are connected together. All contact plugs 106b at the boundary I-2 form a combined contact structure with a larger top cross-sectional area.
  • the semiconductor device is a dynamic random access memory (dynamic random access memory, DRAM)
  • the core area is the storage array area of the DRAM memory
  • the core element is a storage transistor
  • the structure is a storage node contact part, and a capacitor structure (that is, storage node) is connected to it. That is, each contact plug 106a in the central area I-1 of the core area I is connected to a capacitor structure (as shown in 705a in FIG. 12), and a combined contact structure in I-2 at the boundary of the core area I is connected to A capacitor structure (as shown in 705b in FIG.
  • the capacitor structure at the boundary of I-2 has a first width W1
  • the core area I is within the boundary of I-2 (that is, the central area I-
  • the capacitor structure of 1) has a second width W2. Due to the existence of a combined contact structure with a larger top cross-sectional area formed at the boundary of the core region I I-2, it can be the formation of the capacitor structure at the boundary of I-2
  • the process provides sufficient process margin to help increase the first width W1 of the capacitor structure at the boundary of I-2, so that the first width W1 is greater than the second width W2, and, on the one hand, to avoid this
  • the capacitive structure formed by I-2 at the boundary collapses; on the other hand, the capacitive structure at I-2 at the boundary and the combined contact structure underneath can have a larger contact area.
  • the size of the capacitor structure at the boundary I-2 is increased, which can buffer the density difference of the circuit pattern between the core area I and the peripheral area II, thereby performing optical
  • the engraving process and/or etching process can improve the optical proximity effect, reduce the sparse/dense load effect, and ensure the capacitance above the contact plug 106a in the area within I-2 at the boundary of the core area I (ie the central area I-1)
  • the consistency of the structure prevents abnormalities in the capacitor structure above the contact plugs at some locations in the core area I or the problem of the capacitor structure above the contact plugs at the boundary I-2 from collapsing.
  • the first width W1 is greater than 1.5 times the second width W2.
  • the semiconductor device includes a plurality of word lines WL and a plurality of bit lines BL, each of the word lines WL intersects a plurality of the active areas AA1 in the core area I,
  • the word line WL may be a buried word line
  • the bit line BL is formed above the core element of the core area I and is perpendicular to the word line WL
  • the top part is formed by all contact plugs connected together
  • a structure (for example, an inverted U-shaped electrical contact structure or a comb-shaped electrical contact structure) straddles at least one of the word lines WL and is aligned with (ie, parallel) to the bit line BL, for example, an inverted U-shaped electrical contact structure or a comb is formed
  • a line in an active area AA1 that crosses the outermost boundary of the core area I (that is, the side of I-2 closest to the peripheral area II at the boundary, which is the outermost of I-2 at the boundary) Line WL.
  • the semiconductor device is a DRAM as an example, the technical solution of the present invention is not limited to this.
  • the semiconductor device can also be any suitable electrical device, such as a memory of other architectures.
  • the capacitor structure can be replaced with a corresponding electrical structure, such as a resistor.
  • FIGS. 1A to 1D are schematic cross-sectional views of the device in the method of manufacturing the electrical contact structure of the semiconductor device according to the present embodiment. 1A to 1D, this embodiment also provides a method for manufacturing an electrical contact structure of a semiconductor device, including the following steps:
  • a semiconductor substrate 100 which includes a core region I and a peripheral region II.
  • the semiconductor substrate 100 can be selected from a silicon substrate, a silicon-on-insulator (SOI), a germanium substrate, and a germanium-on-insulator substrate (GOI), silicon germanium substrate, etc.
  • a plurality of shallow trench isolation structures are formed in the semiconductor substrate 100.
  • the shallow trench isolation structures are formed by etching the semiconductor substrate 100 to form trenches, and then filling the trenches with insulating materials.
  • the material of the shallow trench isolation structure may include silicon oxide, silicon nitride, or silicon oxynitride.
  • the shallow trench isolation structure defines the boundary between the core area I and the peripheral area II on a two-dimensional plane (that is, defines the boundary of the core area I at I-2), and also defines the boundary in the core area I
  • the interlayer dielectric layer 102 is covered on the semiconductor substrate 100, and the interlayer dielectric layer 102 can be configured to have a single-layer structure or a multi-layer structure.
  • the interlayer dielectric layer 102 may include at least one of silicon nitride, silicon oxynitride, and low-k dielectric materials.
  • the dielectric constant k of the low-k dielectric material is smaller than that of silicon oxide, and it can be used as an intermetal dielectric layer (IMD), such as high-density plasma (HDP) oxide, orthosilicate four Ethyl vinegar (TEOS), plasma-enhanced TEOS (PE-TEOS), undoped silicate glass (USG), silicate phosphorous glass (PSG), silicate greenhouse glass (BSG), silicate phosphorous glass (BPSG), fluorinated silicate glass (FSG), spin-on glass (SOG), etc.
  • IMD intermetal dielectric layer
  • an etch stop layer (not shown) may be formed between the semiconductor substrate 100 and the interlayer dielectric layer 102, and the etch stop layer may include SiN, SiON, SiC, SiCN, BN (nitride barrier) or any combination thereof.
  • the etch stop layer and the interlayer dielectric layer 102 may be formed using plasma enhanced CVD (PECVD), high density plasma CVD (HDP-CVD), atmospheric pressure CVD (APCVD) and/or spin coating process.
  • PECVD plasma enhanced CVD
  • HDP-CVD high density plasma CVD
  • APCVD atmospheric pressure CVD
  • a first mask pattern 103 is formed on the interlayer dielectric layer 102.
  • the first mask pattern 103 defines the position of each contact plug.
  • use The first mask pattern 103 is used as an etching mask to etch the interlayer dielectric layer 102 anisotropically to form contact holes 102a, 102b, and 102c penetrating the interlayer dielectric layer 102 and exposing the corresponding active region 101 below ,
  • the contact holes 102a, 102b, and 102c are independent of each other.
  • Each contact hole 102a is located in the central area I-1 of the core area I and exposes the active area 101 of the corresponding core element in the central area I-1.
  • the contact holes 102b are located at the boundary I-2 of the core area I and expose the active area 101 of the corresponding core element at the boundary I-2, and each contact hole 102c is located in the peripheral area II and exposes the corresponding peripheral element.
  • Source area 101 is located in the central area I-1 of the core area I and exposes
  • an ashing process or a wet cleaning process may be performed to remove the first mask pattern 103 and fill the sacrificial layer 104 in each of the contact holes 102a-102c.
  • the sacrificial layer 104 may be formed of a spin-on hard mask layer (SOH) or an amorphous carbon layer (ACL), which may enable the sacrificial layer 104 to fill the contact holes 102a-102c with a high aspect ratio.
  • a second mask pattern 105 can be formed on the interlayer dielectric layer 102 and the sacrificial layer 104 by a second photolithography process.
  • the second mask pattern 105 defines the boundary I- 2 Corresponding grooves 102d connected to the top of at least two contact holes 102b.
  • the interlayer dielectric layer at I-2 at the boundary is etched to form a trench 102d connecting the tops of at least two contact holes 102b at the boundary.
  • the trench 102d is at least The outermost contact hole of I-2 at the boundary is exposed (for example, the trench 102d exposes at least one of the contact holes of the outermost row of I-2 at the boundary).
  • oxygen, ozone or ultraviolet ashing process or wet cleaning process can be used to remove the sacrificial layer 104 and the second mask pattern 105 in the contact holes 102a-102c, 102d to re-expose each contact hole 102a ⁇ 102c and groove 102d.
  • a barrier metal layer (not shown) may be formed in the contact holes 102a-102c and the trench 102d.
  • the barrier metal layer may cover the inner walls of the contact holes and trenches and the interlayer dielectric layer with a uniform thickness. The top surface of 102.
  • the barrier metal layer can reduce or prevent the metal materials provided in the contact holes and trenches from diffusing into the interlayer dielectric layer 102.
  • the barrier metal layer may be formed of Ta, TaN, TaSiN, Ti, Ti N, TiSiN, W, WN, or any combination thereof, and may use chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition.
  • the metal layer may be formed of refractory metal(s) (for example, cobalt, iron, nickel, tungsten, and/or molybdenum).
  • the metal layer may be formed using a deposition process with good step coverage properties, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) (for example, sputtering).
  • the deposited metal layer also covers the surface of the interlayer dielectric layer 102 around the contact hole.
  • CMP chemical mechanical polishing
  • the top surface of the interlayer dielectric layer 102 forms the contact plugs 106a, 106c and the combined contact structure 106b in the interlayer dielectric layer 102.
  • the method shown in FIGS. 1A to 1D can reduce the number of deposition processes under the same number of photolithography, so that all the contact plugs 106 connected together at the top are integrally formed.
  • another embodiment of the present invention provides an electrical contact structure of a semiconductor device, including a plurality of contact plugs 106, wherein, formed at the boundary of the core region I of the semiconductor device (or called the boundary region , Junction area, interface area) 1-2 tops of at least two contact plugs 106 are connected together by a contact pad 109b with a larger area.
  • the core area I is the device dense area
  • the surrounding peripheral area II is the device sparse area.
  • the top of the contact plug 106 in the area within I-2 at the boundary of the core area I (referred to as the central area I-1) is provided with an independent contact pad 109a, and each contact pad 109a is in one-to-one correspondence with the corresponding contact.
  • the top of the plug 106 makes electrical contact.
  • All the contact plugs 106 connected together at the top of I-2 at the boundary of the core area I through the corresponding contact pads 109b constitute an inverted U-shaped electrical contact structure or a comb-shaped electrical contact structure, that is, I- at the boundary of the core area I
  • All the contact plugs 106 connected to the top of 2 form a combined contact structure with a larger top cross-sectional area at the boundary I-2.
  • the semiconductor device is a dynamic random access memory (dynamic random access memory, DRAM)
  • the core area is the storage array area of the DRAM memory
  • the core element is a storage transistor.
  • the electrical contact structure is a storage node contact portion, and a capacitor structure is connected to it. That is, each contact plug in the central area I-1 of the core area I is connected to a capacitor structure (as shown in 705a in Figure 12), and a combined contact structure in I-2 is connected to the boundary of the core area I.
  • the capacitor structure (as shown in 705b in FIG.
  • the capacitor structure at the boundary of I-2 has a first width W1
  • the boundary of the core area I is at I-2 (that is, the central area I-1)
  • the capacitor structure within has a second width W2. Due to the existence of the combined contact structure with a larger top cross-sectional area formed at the boundary of the core region I I-2, it can provide enough for the formation process of the capacitor structure at the boundary.
  • the process margin is beneficial to increase the first width W1 of the capacitor structure at the boundary I-2, so that the first width W1 is greater than the second width W2, and further, on the one hand, to avoid the formation of the boundary
  • the capacitor structure collapses; on the other hand, it enables a larger contact area between the capacitor structure at the boundary and the combined contact structure underneath.
  • a reduction in contact resistance is beneficial to improve the electrical performance of the device; more importantly Yes, the increased size of the capacitor structure at the boundary can buffer the density difference of the circuit pattern between the core area I and the peripheral area II, thereby improving the optical proximity effect when performing photolithography and/or etching processes , Reduce the sparse/dense load effect, ensure the consistency of the capacitor structure above the contact plug 106a in the area within I-2 at the boundary of the core area I (ie the central area I-1), and prevent some locations in the core area I from appearing
  • the capacitor structure above the contact plug is abnormal or the capacitor structure above the contact plug of I-2 at the boundary has a problem of collapse.
  • the first width W1 is greater than 1.5 times the second width W2.
  • FIGS. 2A to 2D are schematic cross-sectional views of a device in a method of manufacturing an electrical contact structure of a semiconductor device according to another embodiment of the present invention. 2A to 2D, this embodiment also provides a method for manufacturing an electrical contact structure of a semiconductor device, including the following steps:
  • a semiconductor substrate 100 which includes a core area I and a peripheral area II.
  • a plurality of shallow trench isolation structures (not shown) are formed in the semiconductor substrate 100.
  • the shallow trench isolation structures define the boundary between the core region I and the peripheral region II on a two-dimensional plane (that is, define the core At the boundary of the area I-2), the active area 101 corresponding to each core element in the core area I and the active area 101 corresponding to the peripheral elements in the peripheral area II are also defined.
  • first interlayer dielectric layer 102 on the semiconductor substrate 100.
  • an etching stop layer (not shown) may be formed between the semiconductor substrate 100 and the first interlayer dielectric layer 102; through the first photolithography process, a first mask is formed on the first interlayer dielectric layer 102 The first mask pattern 103 defines the position of each contact plug.
  • the first interlayer dielectric layer 102 is anisotropically etched to form a through hole
  • the first interlayer dielectric layer 102 exposes the contact holes 102a, 102b, and 102c of the corresponding active area 101 below, and each contact hole 102a is located in the central area I-1 of the core area I and exposes the central area I -1 in the active region 101 of the corresponding core element, each contact hole 102b is located at the boundary of the core region I at I-2 and exposes the active region 101 of the corresponding core element in the boundary at I-2, each contact The hole 102c is located in the peripheral area II and exposes the active area 101 of the corresponding peripheral element.
  • an ashing process or a wet cleaning process can be performed to remove the first mask pattern 103 and fill with a barrier metal layer (not shown) made of TiN or the like.
  • a metal layer (not shown) made of tungsten and other materials is placed in each contact hole 102a-102c, and a chemical mechanical polishing (CMP) process is further used to chemically mechanically polish the top surface of the deposited metal layer until the first interlayer is exposed.
  • CMP chemical mechanical polishing
  • a second interlayer dielectric layer 107 and a second mask pattern 108 can be formed on the first interlayer dielectric layer 102 and the contact plug 106, and the second mask pattern 108 passes through a second photolithography process.
  • the process is formed to define a trench for connecting the tops of at least two contact plugs 106 corresponding to I-2 at the boundary.
  • the second interlayer dielectric layer 107 is etched to form a trench exposing the top of the corresponding contact plug 106, and the corresponding trench 108b at the boundary of I-2 will be at least The tops of the two contact plugs 106 and the space between them are exposed, and the trenches 108a within I-2 at the boundary of the core area I (ie the central area I-1) expose the tops of the corresponding contact plugs 106, The trench 108c in the peripheral area II exposes the top of the corresponding contact plug 106. The groove 108b exposes at least the top of the outermost contact plug 106 at the boundary of I-2.
  • each contact hole trench 108a-108c is filled with a metal layer to form mutually independent contact pads 109a, 109b, and 109c.
  • the contact pads 109a are formed on the top of the contact plugs 106 in the central area I-1 of the core area I, and are in electrical contact with the tops of the corresponding contact plugs 106 in a one-to-one correspondence, and the contact pads 109b are formed in the core area.
  • the plug 106 constitutes an inverted U-shaped electrical contact structure or a comb-shaped electrical contact structure.
  • the method shown in Figures 2A to 2D can be produced by dividing each contact plug (including the top-connected contact plug and the independent contact plug) into two equal heights under the same number of photolithography. Therefore, the aspect ratio of the contact hole or trench corresponding to the etching process and the filling process corresponding to each section height can be reduced, and the performance of the formed electrical contact structure can be ensured.
  • an embodiment of the present invention also provides a semiconductor device, including a semiconductor substrate 100, the semiconductor substrate 100 has a core area I, the core area I formed a plurality of core elements;
  • the interlayer dielectric layer 102 covers the semiconductor substrate 100; and, as in the electrical contact structure of the semiconductor device according to the embodiments of the present invention, the electrical contact structure is formed in the interlayer dielectric layer 102, The bottom of each contact plug of the electrical contact structure is in contact with the active area 101 of the corresponding core element, and at least two contacts of I-2 are formed at the boundary of the core area in the electrical contact structure The tops of the plugs are connected together.
  • the semiconductor device further includes a capacitor structure formed on the interlayer dielectric layer 107 and the bottom is in contact with the electrical contact structure, the boundary of the I-2 capacitor structure (such as 12) has a first width W1, and the capacitor structure within I-2 at the boundary of the core area I (ie, the central area I-1) (as shown in 705a in FIG. 12) has The second width W2, the first width W1 is greater than the second width W2.
  • the technical solution of the present invention is not limited to the above-mentioned formation method of the electrical contact structure, and the method that can be used to form an independent contact plug and a top-connected contact plug can be applied to the present invention.
  • the technical solution of the invention for example, in another example of the present invention, after the structure of FIG. 1A is formed and the mask pattern 103 is removed, the sacrificial layer is no longer filled, but the material of the contact plug (including the barrier metal layer and the Metal layer) to form independent contact plugs, and then the mask pattern 105 in FIG.
  • the interlayer dielectric layer 102 is formed on the interlayer dielectric layer 102 and the independent contact plugs, and the interlayer dielectric layer 102 is further etched to form exposed At least two trenches 102d on the top sidewall of the contact plug 102b at the boundary 1-2, and then the trench 102d is filled with conductive material to form a contact pad (not shown), which connects the trench 102d The tops of the exposed contact plugs 102b are connected together.
  • FIGS. 3 to 12 is a schematic top view of the device structure in the method of manufacturing a semiconductor device according to an embodiment of the present invention
  • FIGS. 4-12 are devices along the line aa' in FIG. 3 in the method of manufacturing a semiconductor device according to an embodiment of the present invention Schematic diagram of structural section.
  • FIGS. 3 and 4 provide a semiconductor substrate 300 with multiple core elements (ie, memory transistors).
  • the specific process includes:
  • a semiconductor substrate 300a which includes a core area I and a peripheral area II.
  • the core area I is a storage area
  • the core element to be formed on the core area I includes a selection element, and then a data storage element is connected above the core element.
  • the selection element is, for example, a MOS transistor or a diode
  • the data storage element is, for example, a capacitor.
  • Variable resistors, etc., a selection element and the corresponding data storage element form a memory cell.
  • a peripheral circuit TR (for example, NMOS transistor and PMOS transistor, diode, or resistor) may be formed in the peripheral area II to control the memory cell.
  • a plurality of shallow trench isolation structures 301 are formed in the semiconductor substrate 300a.
  • the shallow trench isolation structures 301 define the boundary between the core region I and the peripheral region II on a two-dimensional plane (that is, define the boundary of the core region I).
  • the active area AA1 corresponding to each core element in the core area I and the active area AA2 corresponding to the peripheral elements in the peripheral area II are also defined.
  • the distribution of the active areas AA1 on the two-dimensional plane is in a stripe shape and all extend along the first direction, and the active areas AA1 may be arranged in a staggered arrangement on the surface of the semiconductor substrate 300a.
  • a buried word line WL is formed in the semiconductor substrate 300a.
  • the buried word line WL is generally buried at a predetermined depth in the semiconductor substrate 300a, extending in the second direction (ie the row direction) and passing through the shallow trench isolation structure. 301 and the active area AA1.
  • the second direction intersects but is not perpendicular to the first direction of the active area AA1.
  • the buried word line WL is used as the gate to control the switching of the memory cell. It includes but is not limited to doped semiconductor materials (such as doped silicon), metal materials (such as tungsten, aluminum, titanium, or tantalum), and conductive materials.
  • Metal compounds such as titanium nitride, tantalum nitride, or tungsten nitride), or semiconductor compounds (such as silicon nitride), etc.
  • the sidewalls and bottom of the buried word line WL are surrounded by a gate dielectric layer (not shown), and the top of the buried word line WL is buried in the gate cap layer 302. Since the buried word line WL is not the focus of the present invention, the related manufacturing process can refer to the known technical solutions in the art, which will not be described in detail here.
  • the gate dielectric layer may include silicon oxide or other suitable dielectric materials
  • the buried word line WL may include aluminum, tungsten, copper, titanium aluminum alloy, polysilicon or other suitable conductive materials
  • the gate cap layer 302 may Including silicon nitride, silicon oxynitride, silicon carbide nitride or other suitable insulating materials.
  • the active area AA1 on both sides of the buried word line WL can be doped with a second type of dopants, such as P-type or N-type dopants, to form source and drain regions (defined as S/ D1), one of the AA1 on both sides of the buried word line WL is located at the position corresponding to the predetermined bit line contact structure at the center of AA1, and the other is located at the predetermined storage node contact structure position at the end of the active area AA1.
  • the word lines WL and S/D1 may constitute or define a plurality of MOS memory transistors formed on the core region I of the semiconductor device.
  • the source and drain regions corresponding to the peripheral transistors can also be formed in the peripheral area II at the same time.
  • an etch stop layer 303 can be further formed on the semiconductor substrate 300a.
  • the etch stop layer 303 covers the S/D1 and S/D2.
  • silicon nitride (SiN) and/or silicon oxide (SiO 2 ) are included.
  • bit line contact plugs (not shown) and a bit line BL located above the bit line contact plugs are formed on the S/D1 serving as the drain region of the core region I.
  • the bit line The contact plug can be formed by the following method: firstly etch the S/D1 between two adjacent WLs formed in one active area AA1 to form a groove, and then form a metal silicide in the groove.
  • the bit lines BL are parallel to each other and extend along the third direction (ie, the column direction) perpendicular to the buried word line WL, and cross the active area AA1 and the buried word line WL at the same time.
  • Each bit line BL includes, for example, a semiconductor layer (such as polysilicon, not shown), a barrier layer (such as Ti or TiN, not shown), and a metal layer (such as tungsten, aluminum, or copper, etc.) stacked in sequence. Not shown) and a mask layer (for example, containing silicon oxide, silicon nitride or silicon carbonitride, not shown).
  • At least one gate structure G1 is formed, which includes, for example, a gate dielectric layer (not shown) and a gate layer (not shown) stacked in sequence.
  • the gate layer of the gate structure G1 and the semiconductor layer or metal layer of the bit line BL are formed together.
  • different processes or the same process can be used to form the sidewall spacers 304 respectively surrounding each bit line BL and the gate structure G1.
  • the manufacturing process of the sidewall spacer of the gate structure G1 may be performed first, so that the sidewall 304 of the gate structure G1 includes silicon oxide or silicon oxynitride (SiON), and then the manufacturing process of the sidewall spacer of the bit line BL is performed.
  • the sidewall spacer of the bit line BL may include silicon nitride.
  • an etching back manufacturing process may be performed again, so that the overall height of the gate structure G1 is lower than the bit line BL.
  • the method of manufacturing the electrical contact structure of the semiconductor device shown in FIGS. 1A to 1D or FIGS. 2A to 2D of the present invention can be used to form the storage node contact structure, and the electrical contact structure of the semiconductor device shown in FIGS. 1A to 1D is used below.
  • the manufacturing method of the contact structure to form the storage node contact structure Take the manufacturing method of the contact structure to form the storage node contact structure as an example, the specific process is as follows:
  • an interlayer dielectric layer 400 is formed on the semiconductor substrate 300a, the material of which includes, for example, Silicon oxide, silicon nitride or low-K dielectric, etc.
  • the interlayer dielectric layer 400 is completely covered on the semiconductor substrate 300a through a deposition process, and the interlayer dielectric layer 400 is made to fill the space between the bit lines BL, and the bit line BL and the gate structure G1 and its The sidewall spacers 304 are buried in, and then the interlayer dielectric layer 400 is planarized by a process such as chemical mechanical polishing to form the interlayer dielectric layer 400 having a flat top surface as a whole.
  • the top surface of the planarized interlayer dielectric layer 400 is at least not lower than the top surface of each bit line BL.
  • a first mask pattern (not shown) is formed on the interlayer dielectric layer 400 through a photolithography process, and the first mask pattern defines the position of each storage node contact structure, and then, Using the first mask pattern as an etching mask, the interlayer dielectric layer 400 is anisotropically etched to form S/D1 and S/D2 that penetrate the interlayer dielectric layer 400 and expose the corresponding source regions below.
  • each contact hole 401a is located in the central area I-1 of the core area I and exposes the corresponding core element in the central area I-1 as a source Area S/D1
  • each contact hole 401b is located at the boundary of the core area I-2 and exposes the S/D1 of the corresponding core element at the boundary I-2 serving as the source area
  • each contact hole 401d, 401e is located in the peripheral area II and exposes the source/drain area S/D2 or the gate structure G1 of the corresponding peripheral element.
  • the sacrificial layer 501 may be formed of a spin-on hard mask (SOH) layer or an amorphous carbon layer (ACL), which may enable the sacrificial layer 501 to fill the contact holes 401a, 401b, and 401d with high aspect ratios, 401e.
  • SOH spin-on hard mask
  • ACL amorphous carbon layer
  • a second mask pattern (not shown) can be formed on the interlayer dielectric layer 400 and the sacrificial layer 501, and the second mask pattern defines the boundary corresponding to I-2 At least two contact holes 401b are connected to the top of the trench 401c.
  • the interlayer dielectric layer 400 at the boundary I-2 is etched to form at least two contact holes 401b (including the column closest to the peripheral region II) corresponding to the boundary I-2 At least one of the contact holes) is connected to the top of the trench 401c.
  • the trench 401c crosses at least the outermost word line WL at the boundary of I-2.
  • the sacrificial layer 501 and the second mask pattern in the contact holes 401a, 401b, 401d, and 401e can be removed using an ashing process of oxygen, ozone, or ultraviolet rays or a wet cleaning process to expose each Contact holes 401a, 401b and 401d, 401e and trenches 401c.
  • a barrier metal layer (not shown) may be formed in the contact holes 401a, 401b and 401d, 401e and the trench 401c.
  • the barrier metal layer may cover the contact holes 401a, 401b and 401a with a uniform thickness.
  • the barrier metal layer can reduce or prevent the metal material provided in the contact holes 401a, 401b and 401d, 401e and the trench 401c from diffusing into the interlayer dielectric layer 400.
  • the barrier metal layer may be formed of Ta, TaN, TaSiN, Ti, Ti N, TiSiN, W, WN, or any combination thereof, and may use chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition. It is formed by processes such as deposition (PVD) (for example, sputtering). Then, a metal layer is filled in the respective contact holes 401a, 401b and 401d, 401e and the trench 401c to form contact plugs 501a, 501d, 501e and a combined contact structure 501b.
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • PVD physical vapor deposition
  • the metal layer may be formed of refractory metal(s) (for example, cobalt, iron, nickel, tungsten, and/or molybdenum).
  • the metal layer may be formed using a deposition process with good step coverage properties, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) (for example, sputtering).
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • PVD physical vapor deposition
  • the formed metal layer also covers the surface of the interlayer dielectric layer 400 around the contact hole and the trench. After that, the top surface of the deposited metal layer can be chemically and mechanically polished by a chemical mechanical polishing (CMP) process until the top surface of the deposited metal layer is exposed.
  • CMP chemical mechanical polishing
  • the top surface of the interlayer dielectric layer 400 is formed to form contact plugs 501a, 501d, 501e and a combined contact structure 501b in the interlayer dielectric layer 400.
  • the contact plug 501a serves as a storage node contact structure in the central area I-1 of the core area I, and is used to connect with the capacitor structure formed above the central area I-1 later.
  • the combined contact structure 501b is connected by at least two top contact plugs in I-2 at the boundary of the core region I (including the outermost contact plug at the boundary that is in electrical contact with the outermost source region of I-2 at the boundary ) Is formed as the storage node contact structure in I-2 at the boundary of the core area I, and is used to connect with the capacitor structure formed above the boundary I-2, and the top structure of the combined contact structure 501b (that is, the top is connected together
  • the top connection structure formed by all the contact plugs) is located above the bit line BL and crosses at least one word line WL, and the combined contact structure 501b is aligned and parallel to the bit line BL.
  • the combined contact structure 501b is, for example, an inverted U-shaped electrical contact structure or a comb-shaped electrical contact structure, which can cross at least one word line WL in the outermost active area AA1 at the boundary of I-2.
  • the contact plug 501d is used as the contact structure of the gate structure G1 of the peripheral region II to lead the gate structure G1 outward
  • the contact plug 501e is used as the contact structure of the source region or the drain region S/D2 of the peripheral region II. To lead the source region or drain region S/D2 of the peripheral region II to the outside.
  • a bottom support layer 600 and a second layer can be sequentially formed on the surface of the interlayer dielectric layer 400, the contact plugs 501a, 501d, 501e, and the combined contact structure 501b by chemical vapor deposition, spin coating, etc.
  • the bottom support layer 600 is used to support the bottom electrode layer subsequently formed on the one hand, and also to isolate the semiconductor liner on the other hand.
  • the formation process of the bottom support layer 600 may also be a thermal oxidation process.
  • the material of the bottom support layer 600, the middle support layer 601 and the top support layer 602 includes but is not limited to silicon nitride, and the material of the first sacrificial layer 611 and the second sacrificial layer 612 includes but is not limited to silicon oxide.
  • the thickness of the first sacrificial layer 611 defines the height of the intermediate support layer 601 to be formed later. Therefore, the thickness of the first sacrificial layer 611 can be adjusted according to the height position of the intermediate support layer 601 to be formed. In the case where the thickness of the first sacrificial layer 611 and the intermediate support layer 601 is determined, the thickness of the second sacrificial layer 612 defines the height of the top support layer 602 to be formed subsequently.
  • the second sacrificial layer The thickness of 612 can be adjusted according to the height position of the top support layer 602 to be formed.
  • two or more intermediate support layers 601 may be stacked between the bottom support layer 600 and the top support layer 602, and between adjacent intermediate support layers There is a sacrificial layer for isolation.
  • a plurality of capacitor holes 700a and 700b are formed in the sacrificial layer on the core area I and the support layer, and the capacitor holes 700a are formed in the central area I-1 of the core area I and The surface of the contact plug 501a in the central area I-1 is exposed for forming the capacitor structure in the central area I-1.
  • the capacitor hole 700b is formed at the boundary I-2 of the core region I and exposes the surface of the combined contact structure 501b at the boundary I-2, and is used to form the capacitor structure in the boundary I-2.
  • the capacitor holes 700a and 700b are arranged in an array, and the capacitor hole 700b has a first width W1, and the capacitor hole 700a has a second width W2.
  • W1 is not less than 1.5*W2.
  • a mask layer (not shown) is formed on the top support layer 602, the mask layer is patterned to expose the areas where the capacitor holes 700a and 700b are scheduled to be formed, and then a patterned mask is used.
  • the mold layer is a mask, and the top support layer 602, the second sacrificial layer 612, the middle support layer 601, the first sacrificial layer 611, and the bottom support layer 600 are etched in sequence to remove the peripheral area II and the core area
  • the supporting layer and the sacrificial layer are formed on the edge area of I, and a plurality of capacitor holes 700a and 700b are formed in the core area I, and then the patterned mask layer is removed.
  • the capacitor holes 700a and 700b sequentially penetrate the top support layer 602, the second sacrificial layer 612, the middle support layer 601, the first sacrificial layer 611, and the bottom support layer 600 to expose the corresponding contacts of the core region I
  • all the capacitor holes are arranged in a hexagonal close-packed arrangement.
  • the capacitor hole may be an inverted trapezoidal hole, a rectangular hole, etc., and the sidewalls thereof may have irregular shapes, such as curved sidewalls, etc., which are not specifically limited herein.
  • the bottom support layer 600 is also reserved on the peripheral region II to protect the device surface of the peripheral region II during the subsequent capacitor formation process.
  • the width of the capacitor hole 700b at the boundary of I-2 is relatively large. Large, avoid abnormal deformation or collapse of the capacitor hole 700b at the boundary, and at the same time make the capacitor structure formed at the boundary and the combined contact structure have a larger contact area, thereby reducing the contact resistance, and improving the device’s performance Electrical performance.
  • the width of the capacitor hole 700b at the boundary I-2 is larger, the difference in the density of the circuit patterns in the peripheral area II and the core area I can be buffered, so that the capacitor hole can be lithographically and/or etched.
  • a bottom electrode layer 701 is formed to cover the sidewalls and bottom walls of the capacitor holes 700a and 700b.
  • the part of the bottom electrode layer 701 located in the capacitor holes 700a, 700b has a shape consistent with the topography of the capacitor holes 700a, 700b, so that the bottom electrode located in the capacitor holes 700a, 700b
  • the layer 701 constitutes a cylindrical structure.
  • the lower electrode layer 701 can be formed on the basis of a deposition process combined with a planarization process. For example, first, a patterned protective layer (not shown) such as photoresist can be used to protect the peripheral region II and expose it.
  • the top surface of the top support layer 602 in the core area I and the surfaces of the capacitor holes 700a, 700b are removed; then, a physical vapor deposition or chemical vapor deposition process is used to form an electrode material layer on the patterned protective layer and the core area I On the exposed surface of the, the electrode material layer covers the bottom and sidewalls of the capacitor holes 700a and 700b, and the top surface of the top support layer 602 covering the core area I and the top surface of the patterned protective layer of the peripheral area II; Perform a planarization process (for example, a chemical mechanical polishing process CMP) to remove the part of the electrode material layer above the top support layer 602, so that the remaining electrode material layer is only formed in the capacitor holes 700a, 700b to A lower electrode layer 701 having a plurality of cylindrical structures is formed, and then the patterned protective layer is removed.
  • a planarization process for example, a chemical mechanical polishing process CMP
  • the contact plugs 501a, 501b are exposed through the capacitor holes 700a, 700b, respectively, so that the bottom of the cylindrical structure of the lower electrode layer 701 formed can contact the contact plugs. 501a and 501b are in electrical contact.
  • the lower electrode layer 701 may be a polysilicon electrode or a metal electrode.
  • a metal electrode a stacked structure of titanium nitride (TiN) and Ti can also be used.
  • the lower electrode layer 701 is a polysilicon electrode, it may be formed of a zero-doped and/or doped polysilicon material.
  • each of the sacrificial layers is removed and each of the supporting layers is retained. All the supporting layers form a lateral supporting layer to connect the multiple cylindrical structures of the lower electrode layer 701 laterally.
  • the outer wall of each cylindrical structure supports the lower electrode layer 701 on the side wall of each cylindrical structure.
  • the top support layer 602 is located at the outer periphery of the top of the plurality of cylindrical structures of the lower electrode layer 701
  • the middle support layer 601 is located at the middle part of the plurality of cylindrical structures of the lower electrode layer 701
  • the support layer 600 is located at the periphery of the bottom of the plurality of cylindrical structures of the lower electrode layer 701.
  • the specific process includes: forming a first opening (not shown) in the top support layer 602 and exposing the second sacrificial layer 612; the second sacrificial layer 612 can be etched and removed by a wet etching process Forming a second opening in the intermediate support layer 601 to expose the first sacrificial layer 611; using a wet etching process to etch and remove the first sacrificial layer 611; wherein, only one of the first openings It overlaps with one of the capacitor holes 700a or 700b, or one of the first openings overlaps with a plurality of the capacitor holes 700a and/or 700b at the same time; and one of the second openings overlaps with only one of the capacitor holes 700a or 700b.
  • 700b overlaps, or one of the second openings overlaps a plurality of the capacitor holes 700a and/or 700b at the same time.
  • the second opening may be completely aligned with the first opening.
  • the capacitor dielectric layer 702 may be a high-K dielectric layer such as metal oxide.
  • the capacitor dielectric layer 702 has a multilayer structure, for example, a two-layer structure of hafnium oxide-zirconia.
  • the upper electrode layer 703 may be a single-layer structure or a multilayer structure.
  • the upper electrode layer 703 is a single-layer structure, for example, a polysilicon electrode or a metal electrode
  • when the upper electrode layer 703 is a metal electrode In this case, for example, titanium nitride (TiN) can be used.
  • TiN titanium nitride
  • the upper electrode layer 703 can form a capacitor with the capacitive dielectric layer 702 and the lower electrode layer 701 corresponding to the inside of the cylindrical structure and the outside of the cylindrical structure.
  • the capacitor dielectric layer 702 and the upper electrode layer 703 all have uneven sidewall structures corresponding to the middle support layer 601 and the top support layer 602 outside the cylindrical structure of the lower electrode layer 701, As a result, the part of the upper electrode layer 703 on the edge area of the core area I (that is, the boundary area of the capacitor hole array) corresponds to the middle support layer 601 and the top support layer 602 to be far away from the lower electrode layer 701 Protruding in the direction of, making the boundary of the capacitor array in the core area I uneven.
  • the capacitor dielectric layer 702 and the upper electrode layer 703 also extend sequentially to cover the surface of the bottom support layer 600 remaining on the peripheral region II.
  • a chemical vapor deposition process may be used to form an upper electrode filling layer 704 on the surface of the upper electrode layer 703, and the upper electrode filling layer 704 fills the gap between the upper electrode layers 703.
  • the upper electrode filling layer 704 fills up the gap between the adjacent cylindrical structures and covers the structure formed above.
  • the material of the upper electrode filling layer 704 includes undoped or boron-doped polysilicon.
  • the size of the capacitor hole 700b is large, it is beneficial to material filling, thereby improving the performance of the capacitor structure formed at the boundary I-2.
  • an embodiment of the present invention provides a contact pad layout of a semiconductor device.
  • the contact pad layout includes a main layout area 10 and a first edge layout area 11.
  • the main layout area 10 is provided with a plurality of main contact pad patterns 131, each of the main contact pad patterns 131 is similar in shape and size, and all the main contact pad patterns 131 are staggered and arranged in a checkerboard shape, adjacent to each other.
  • Two rows of the main contact pad patterns 131 have a fourth distance D4 between each other, and two adjacent columns of the main contact pad patterns 131 have a fifth distance D5 between each other.
  • D4 may be equal to D5, or D4 may not be equal to D5.
  • the first edge layout area 11 is distributed on the outer side of one side of the main layout area 10.
  • the first edge layout area 11 is provided with a plurality of rows arranged in two rows along the extension direction of the one side of the main layout area 10.
  • the first edge contact pad pattern that is, in this embodiment, the first edge layout area 11 is provided with a row of first edge contact pad patterns 111 and a row of first edge contact pad patterns 112, and two rows of first edge contact pad patterns There is a sixth distance D6 between 111 and 112.
  • a row of first edge contact pad patterns 112 is relatively close to the main layout area 10, and the shape and size of each first edge contact pad pattern 112 in the row may be the same or not completely the same.
  • a row of first edge contact pad patterns 111 is relatively far away from the main layout area 10, and the shape and size of each first edge contact pad pattern 111 in the row may be the same or not.
  • Each of the first edge contact pad patterns 111 and 112 is aligned with the corresponding main contact pad pattern 131 in the main layout area 10 (for example, arranged in column alignment), and the one closest to the main layout area 10
  • the distance between a row of first edge contact pad patterns 112 and its nearest row of main contact pad patterns 131 is the first edge distance D1 (that is, between the first edge layout area 11 and the main layout area 10 The first edge distance D1).
  • each of the first edge contact pad patterns 111, 112 is greater than the area of each of the main contact pad patterns 131, and the first edge contact pad patterns 111, 112 are different from the main contact pad pattern 131 (For example, the area of each first edge contact pad pattern 111, 112 is greater than the area of the main contact pad pattern 131), the first edge distance D1 is different from the fourth distance D4, and the sixth distance D6 is different For the fourth distance D4 and the first edge distance D1, for example, D6 is greater than D1, and D1 is greater than D4.
  • the contact pad layout of this embodiment further includes a second edge layout area 12, and the second edge layout area 12 is distributed adjacent to the one side of the main layout area 10.
  • a plurality of second edge contact pad patterns 121 and/or 122 are provided in the second edge layout area 12, and each of the second edge contact pad patterns 121, 122 is different from the main contact pad pattern 131, and the area of each of the second edge contact pad patterns 121, 122 is larger than the area of each of the main contact pad patterns 131.
  • each of the second edge contact pad patterns 121, 122 in the second edge layout area 12 corresponds to the corresponding main contact pad pattern 131 and the first edge contact pad patterns 111, 112 in the main layout area 10.
  • the quasi-arrangement, for example, all the second edge contact pad patterns 121, 122 in the second edge layout area 12 are further arranged in two rows along the extension direction of the adjacent side, and the row close to the main layout area 10 is the first There are two edge contact pad patterns 121.
  • the column far away from the main layout area 10 is the second edge contact pad pattern 122.
  • the second edge contact pad patterns 121 and 122 in each column may not be completely the same.
  • the shape of the second edge contact pad pattern 122 in a column away from the main layout area 10 includes a long strip, a U-shape that is tilted to the left, and a shape that is tilted to the right. At least two of an inverted U shape, an L shape that is laid down to the left, an L shape that is laid down to the right, and a comb shape having at least two comb teeth.
  • FIG. 14 another embodiment of the present invention provides a contact pad layout of a semiconductor device.
  • the contact pad layout includes a main layout area 10, a first edge layout area 11 and a second edge layout area 12.
  • the main layout area 10 is provided with a plurality of main contact pad patterns 131, each of the main contact pad patterns 131 is similar in shape and size, and all the main contact pad patterns 131 are staggered and arranged in a checkerboard shape, adjacent to each other.
  • Two rows of the main contact pad patterns 131 have a fourth distance D4 between each other, and two adjacent columns of the main contact pad patterns 131 have a fifth distance D5 between each other.
  • D4 may be equal to D5, or D4 may not be equal to D5.
  • the first edge layout area 11 is distributed on the outer side of one side of the main layout area 10, and a strip with a jagged edge is provided in the first edge layout area 11 as the first edge contact pad pattern 111.
  • the saw-toothed edge faces the main layout area 10, and each saw tooth 111a in the saw-toothed edge is aligned with the corresponding main contact pad pattern 131 in the main layout area 10 (for example, each saw tooth 111a and the corresponding main contact pad patterns 131 are arranged in a column alignment), and the distance between the serration 111a and the aligned nearest main contact pad pattern 131 is the first edge distance D1.
  • first edge contact pad patterns 111 only one row of first edge contact pad patterns 111 is provided in the first edge layout area 11, and the row of first edge contact pad patterns 111 are connected as a whole.
  • the shape and size of each saw tooth may be the same or not completely the same, and the pitch of the saw tooth 111a is not completely the same.
  • the area of each of the saw teeth may be smaller than, equal to or greater than the area of each of the main contact pad patterns 131, and the first edge distance D1 is different from the fourth distance D4.
  • the second edge layout area 12 is distributed outside the adjacent side of the one side of the main layout area 10, and a plurality of second edge contact pad patterns 121 and/or 122 are provided in the second edge layout area 12, And each of the second edge contact pad patterns 121, 122 is different from the main contact pad pattern 131, and the area of each of the second edge contact pad patterns 121, 122 is larger than that of each of the main contact pad patterns 131 Area.
  • the corresponding second edge contact pad patterns 121, 122 in the second edge layout area 12 are aligned with the corresponding main contact pad patterns 131 in the main layout area 10, and the remaining second edges
  • the contact pad patterns 121 and 122 are aligned with the first edge contact pad pattern 111.
  • the corresponding second edge contact pad patterns 121 and 122 in the second edge layout area 12 further extend along the adjacent edge. The direction is arranged in two rows. The column close to the main layout area 10 is the second edge contact pad pattern 121, and the column far away from the main layout area 10 is the second edge contact pad pattern 122.
  • the second edge contact pad patterns 121, 122 may not be exactly the same.
  • the distance between the row of the second edge contact pad patterns 121 nearest to the main layout area 10 and the row of main contact pad patterns 131 nearest to the main layout area 10 is the second edge distance D2, and the two rows of the second There is a third distance D3 between the edge contact pad patterns 121 and 122, and the third distance D3 is greater than the second edge distance D2 and also greater than the fifth distance D5.
  • the second edge contact pad pattern 121 is a horizontally long strip structure, and its length extends along the row direction of the main layout area 10
  • the second edge contact pad pattern 122 is a vertical strip structure, and The length extends along the column direction of the main layout area 10.
  • FIG. 15 another embodiment of the present invention provides a contact pad layout of a semiconductor device.
  • the contact pad layout includes a main layout area 10, a first edge layout area 11 and a second edge layout area 12.
  • the structure of the main layout area 10 in this embodiment may be the same as the structure of the layout area 10 in the embodiment shown in FIG. 13 or FIG. 14, and will not be repeated here.
  • the first edge layout area 11 is distributed on the outer side of one side of the main layout area 10, the first edge layout area 11 is provided with two rows of structures, and a row close to the main layout area 10 is provided with a plurality of first edge contact pad patterns 112.
  • a row far away from the main layout area 10 is provided with a strip with a serrated edge as the first edge contact pad pattern 111.
  • the serrated edge faces the main layout area 10, so Each serration 111a in the serrated edge and the corresponding first edge contact pad pattern 112 are aligned and arranged with the corresponding main contact pad pattern 131 in the main layout area 10 (for example, each serration 111a, the first edge contact pad pattern 112)
  • the patterns 112 and the corresponding main contact pad patterns 131 are arranged in column alignment), and the distance between the first edge contact pad pattern 112 and the aligned nearest main contact pad pattern 131 is a first edge distance D1 ( That is, the row spacing between a row of first edge contact pad patterns 112 and its nearest row of main contact pad patterns 131 is the first edge distance D1), a row of first edge contact pad patterns 112 and a row of first edges with jagged edges
  • the row spacing between the contact pad patterns 111 is a sixth spacing D6.
  • the first edge contact pad pattern 111 is connected as a whole, and the shape and size of each saw tooth 111a may be the same or not completely the same, and the pitch of the saw tooth 111a may not be completely the same or the same.
  • the area of each saw tooth 111a may be less than, equal to or greater than the area of each of the main contact pad patterns 131, the first edge distance D1 is different from the fourth distance D4, and the sixth distance D6 is different from The first edge distance D1.
  • the second edge layout area 12 is distributed outside the adjacent side of the one side of the main layout area 10, and a plurality of second edge contact pad patterns 121 and/or 122 are provided in the second edge layout area 12, And each of the second edge contact pad patterns 121, 122 is different from the main contact pad pattern 131, and the area of each of the second edge contact pad patterns 121, 122 is larger than that of each of the main contact pad patterns 131 Area.
  • the corresponding second edge contact pad patterns 121, 122 in the second edge layout area 12 are aligned with the corresponding main contact pad patterns 131 in the main layout area 10, and the remaining second edges The contact pad patterns 121 and 122 are aligned with the first edge contact pad pattern 111.
  • the corresponding second edge contact pad patterns 121 and 122 in the second edge layout area 12 are further along the direction of the adjacent side. Arranged in two columns, the column close to the main layout area 10 is the second edge contact pad pattern 121, and the column far away from the main layout area 10 is the second edge contact pad pattern 122, and the second edge contact pad patterns 121, 122 in each column It may not be exactly the same.
  • the distance between the row of the second edge contact pad patterns 121 nearest to the main layout area 10 and the row of main contact pad patterns 131 nearest to the main layout area 10 is the second edge distance D2, and the two rows of the second
  • There is a third distance D3 between the edge contact pad patterns 121 and 122 (here, the smallest distance between the two rows of the second edge contact pad patterns 121 and 122 is the third distance D3), and the third distance D3 is greater than the second edge distance D2 and also greater than the fifth distance D5.
  • the second edge contact pad pattern 121 is a horizontally long strip structure, and its length extends along the row direction of the main layout area 10.
  • the shape of the second edge contact pad pattern 122 includes a long strip, At least two of the U shape that is laid down to the left, the U shape that is laid down to the right, the L shape that is laid down to the left, the L shape that is laid down to the right, and the comb shape that has at least two comb teeth.
  • the main layout area corresponds to the effective area of the core area of the semiconductor device or the entire area of the core area of the semiconductor device, and each main contact pad pattern is used to make the semiconductor device.
  • the main contact pad in the core region, the first edge layout region and the second edge layout region respectively correspond to the boundary of the corresponding side of the core region or respectively correspond to the core region of the semiconductor device and the peripheral region of the semiconductor device on the corresponding side
  • the boundary area between the first edge contact pad pattern and the second edge contact pad pattern are all used to make virtual contact pads at the boundary of the corresponding side of the core area of the semiconductor device or in the boundary area.
  • the area of each of the first edge contact pad patterns in the first edge layout area is greater than the area of each of the main contact pad patterns
  • the area of each second edge contact pad pattern in the second edge layout area is greater than The area of each of the main contact pad patterns. Therefore, when the main contact pads of the core area are formed based on the contact pad layout of the various embodiments of the present invention, the first edge contact pad pattern and the second edge contact pad pattern can be used to form the main contact pad.
  • the corresponding virtual contact pad, and the top surface area of the formed virtual contact pad is larger than the top surface area of the formed main contact pad, thus, the size of the electrical structure subsequently connected to the virtual contact pad can be increased.
  • the electrical structure When the electrical structure is connected to the virtual contact pad, it can improve the density/sparse effect of the circuit pattern between the core area and the peripheral area, thereby improving the consistency of the electrical structure connected to the main contact pad inside the core area, and at the same time avoiding the core area
  • the problem of abnormal electrical structure connected to the main contact pad at the boundary improves the performance of the final formed semiconductor device.
  • an embodiment of the present invention also provides a contact pad structure formed by using the contact pad layout of the semiconductor device shown in any one of FIGS. 13-15.
  • the contact pad structure includes a plurality of main contact pads 131a and at least one first edge contact pad 111b.
  • Each main contact pad 131a is made based on the corresponding main contact pad pattern 131 in the main layout area 10, and is located in the core area I of the semiconductor device and is staggered in a checkerboard pattern. The shape and size are similar, and the main contact pads 131a have a fourth distance D4 between each other.
  • Each main contact pad 131a is used to connect an effective electrical structure such as a capacitor structure (705a in FIG. 24).
  • Each first edge contact pad 111b is made based on the first edge contact pad pattern 111 or based on the first edge contact pad patterns 111 and 112, and is distributed on the outside of one side of all the main contact pad arrangement areas, and each of the first edge contact pads
  • the top surface area of an edge contact pad 111b is greater than the top surface area of each of the main contact pads (further, the cross-sectional area of each first edge contact pad 111b is greater than the cross-sectional area of each of the main contact pads Area), there is a first edge distance D1 between the first edge contact pad 111b (made based on the first edge contact pad pattern 111) next to the main contact pad 131a and the main contact pad 131a.
  • each of the first edge contact pads 111b is distributed at the boundary of the core region I, and electrically connects at least the two outermost source and drain regions S/D1 at the boundary of the core region I (for example, FIG. As shown in 24, each first edge contact pad 511b straddles the word line at the boundary of the core region I and the two source and drain regions S/D1 on both sides thereof).
  • the first edge contact pad 111b may be used as a virtual contact pad.
  • each first edge contact pad 111b is larger than the top surface area of each main contact pad 131a
  • the size of the electrical structure subsequently connected to the first edge contact pad 111b can be made
  • the size of the electrical structure connected to the main contact pad 131a is increased (the size of the capacitor structure 705b as shown in FIG. 24 is larger than that of the capacitor structure 705a) to reduce the gap between the first edge contact pad 111b and the electrical structure connected to it. Enhance the reliability of the device, and more importantly, when the corresponding electrical structure is connected to the main contact pad 131a and the first edge contact pad 111b, respectively, the electrical structure connected to the first edge contact pad 111b can be used.
  • the size is relatively increased to improve the density/sparse effect of the circuit pattern between the core area I and the peripheral area II, thereby improving the consistency between the electrical structures connected to all the main contact pads 131a inside the core area I, and also The problem of abnormal electrical structure connected to the main contact pad 101a at the boundary of the core region I (ie each main contact pad 101a next to each first edge contact pad 111b) can be avoided, and the performance of the final formed semiconductor device is improved.
  • FIGS. 13-15 and 16B Another embodiment of the present invention also provides a contact pad structure formed by using the contact pad layout of the semiconductor device shown in any one of FIGS. 13-15.
  • the contact The pad structure includes a plurality of main contact pads 131a and at least one first edge contact pad 111b.
  • Each main contact pad 131a is made based on the corresponding main contact pad pattern 131 in the main layout area 10, and is located in the core area I of the semiconductor device and is staggered in a checkerboard pattern.
  • the shape and size are similar, and the main contact pads 131a have a fourth distance D4 between each other.
  • Each main contact pad 131a is used to connect an effective electrical structure such as a capacitor structure (705a in FIG. 24).
  • Each first edge contact pad 111b is made based on the first edge contact pad pattern 111 or based on the first edge contact pad patterns 111 and 112, and is distributed on the outside of one side of all the main contact pad arrangement areas, and each of the first edge contact pads
  • the top surface area of an edge contact pad 111b is greater than the top surface area of each of the main contact pads (further, the cross-sectional area of each first edge contact pad 111b is greater than the cross-sectional area of each of the main contact pads Area), there is a first edge distance D1 between the first edge contact pad 111b (made based on the first edge contact pad pattern 111) next to the main contact pad 131a and the main contact pad 131a.
  • each of the first edge contact pads 111b is distributed on the boundary area III between the core area I and the peripheral area II, and is electrically connected to at least one source/drain area S/D1 at the boundary of the core area I Together (for example, as shown in FIG. 25, each first edge contact pad 511b extends from the boundary region III to the outermost source and drain region S/D1 at the boundary of the core region I, connecting the shallow trench isolation structure STI411a of the boundary region III with The source and drain regions S/D1 next to the shallow trench isolation structure STI411a are connected together).
  • the first edge contact pad 111b can be used as a virtual contact pad. Since the top surface area of each first edge contact pad 111b is larger than the top surface area of each main contact pad 131a, the size of the electrical structure subsequently connected to the first edge contact pad 111b can be made The size of the electrical structure connected to the main contact pad 131a is increased (the size of the capacitor structure 705b as shown in FIG.
  • the size of the electrical structure connected to the first edge contact pad 111b can be relatively increased to improve the density/sparse effect of the circuit pattern between the core area I and the peripheral area II, thereby increasing the core
  • the consistency between the electrical structures connected to all the main contact pads 131a inside the area I can also avoid the main contact pads 131a at the boundary of the core area I (that is, the main contact pads next to the first edge contact pads 111b).
  • the problem of abnormal electrical structure connected to it improves the performance of the final semiconductor device.
  • each of the first edge contact pads 111b may also be located on the boundary area III as a whole.
  • the area occupied by the first edge contact pad 111b and the electrical structure connected to it on the core area I can be reduced as much as possible, which is beneficial to improve the core area.
  • the effective area utilization rate of the region is further conducive to improving the device density; on the other hand, the size of the first edge contact pad 111b and the electrical structure connected to it can be increased as much as possible, so that all the main components in the core region I are improved.
  • the contact pad 131a has a better effect in terms of consistency between the electrical structures connected to the contact pad 131a.
  • the number of the first edge contact pads 111b is multiple, and the first edge contact pads 111b are arranged along the main
  • the extension direction of the one side of the contact pad 131a arrangement area (that is, the area within the boundary of the core area I, which may be referred to as the central area or the inner area of the core area I) is arranged in two rows, and each of the first edges contacts
  • the pads 111b are aligned and arranged with the corresponding main contact pads 131a, and the row of first edge contact pads 111b closest to the arrangement area of the main contact pads 131a (that is, the first edge contact pads formed based on the first edge contact pad pattern 112)
  • the distance between 111b and the nearest row of main contact pads 131a is the first edge distance D1.
  • the first edge contact pad 111b includes a strip with a jagged edge (not shown) Shown), which corresponds to the first edge contact pad pattern 111 in FIG. 14 or FIG. 15.
  • the serrated edge faces the arrangement area of the main contact pad 131a, and the elongated serrated edge Each saw tooth in the edge is aligned and arranged with the corresponding main contact pad 131a, and the distance between the elongated saw tooth and the aligned nearest main contact pad 131a is the first edge distance D1.
  • the contact pad structure of each embodiment of the present invention may also include a plurality of second edge contact pads (not shown), and the second edge contact pads are based on the second edge
  • the second edge contact pad patterns 121, 122 in the layout area 12 are fabricated and formed, and the second edge contact pads are distributed outside the adjacent sides of the one side of all the main contact pad arrangement areas, and each of the second edge contacts
  • the top surface area of the pad is greater than the top surface area of each of the main contact pads (further, the cross-sectional area of each second edge contact pad is greater than the cross-sectional area of each main contact pad), next to There is a second edge distance D2 between the second edge contact pad (that is, the second edge contact pad formed based on the second edge contact pad pattern 121) of the main contact pad and the main contact pad.
  • the shape of the edge contact pad is different from the shape of the first edge contact pad, and the second edge distance D2 is different from the fourth distance D4.
  • each of the second edge contact pads is aligned with the corresponding main contact pad.
  • all the second edge contact pads are arranged in two rows along the extension direction of the adjacent side, and are aligned with all the second edge contact pads.
  • the distance between the nearest row of second edge contact pads and the nearest row of main contact pads in the main contact pad arrangement area is the second edge distance D2, and the distance between the two rows of second edge contact pads There is a third distance D3, and the third distance D3 is greater than the second edge distance D2.
  • the cross-sectional shape (or top surface shape) of the second edge contact pad in a column far from the main contact pad arrangement area includes a long strip shape and a leftward shape. At least two of a U shape that is laid down, a U shape that is laid down to the right, an L shape that is laid down to the left, an L shape that is laid down to the right, and a comb shape that has at least two comb teeth.
  • the main contact pad 131a, the first edge contact pad 111b, and the second edge contact pad may be in contact with the peripheral region II.
  • the pad 135 is formed at the same time, the main contact pad 131a is connected to the corresponding active area AA1 (that is, the corresponding source or drain area S/D1) in the core area I through the corresponding contact plug 133a, the first edge contact pad 111b and The second edge contact pad is connected to the corresponding active area AA1 (that is, the corresponding source or drain area S/D1) at the boundary of the core area I through the corresponding contact plug 133b or is isolated from the shallow trench in the boundary area III
  • the structure 100a is connected, and the contact pad 135 is connected to the corresponding source or drain region S/D2 in the peripheral region II through the contact plug 133c.
  • each contact pad is formed by the same filling process; each contact pad and its contact plug can be made separately and separately, or can be formed by the same metal filling process, where each contact pad and its contact
  • the interlayer dielectric layer 132 can be deposited and etched to form contact holes, filled with metal and planarized to form contact plugs 133a, 133b, 133c, and then the interlayer dielectric layer 134 is deposited and etched
  • the trenches, metal filling, and planarization are formed to form the main contact pad 131a, the first edge contact pad 111b, the second edge contact pad, and the contact pad 135.
  • a thicker interlayer dielectric layer can be deposited at one time (for example, its thickness is equal to the sum of the thickness of the interlayer dielectric layer 132 and the interlayer dielectric layer 134), and then each contact pad and its contact are formed through the corresponding etching process, etc.
  • the channels connected by the contact plugs are filled with metal and planarized to form the contact plugs 133a, 133b, 133c, the main contact pad 131a, the first edge contact pad 111b, the second edge contact pad, and the contact Pad 135.
  • the main contact pad 131a and its contact plug 133a are integrally formed, the first edge contact pad 111b and its contact plug 133b are integrally formed, and the second edge contact pad and its contact plug are integrally formed.
  • 133b is integrally formed, and the contact pad 135 and its contact plug 133c are integrally formed.
  • an embodiment of the present invention also provides a semiconductor device, including: a semiconductor substrate 100, an interlayer dielectric layer, and the semiconductor device according to the present invention The contact pad structure.
  • the semiconductor substrate has a core area I, a peripheral area II, and a boundary area III between the core area I and the peripheral area II.
  • a plurality of core elements are formed in the core area I, and each core element is formed in a corresponding
  • a shallow trench isolation structure (STI) 100b is formed on the active area AA1 and between adjacent active areas AA1.
  • Each core element may be a MOS transistor with a buried gate formed in the corresponding active area AA1.
  • the interlayer dielectric layer has an interlayer dielectric layer 132 and an interlayer dielectric layer 134 sequentially covering the semiconductor substrate 100.
  • a shallow trench isolation structure (STI) 100a for isolating the core region I and the peripheral region II is formed in the junction region III.
  • the contact pad structure is formed in the interlayer dielectric layer 134 and includes at least a main contact pad 131a and a first edge contact 111b, and may further include a second edge contact pad.
  • the semiconductor device further includes a contact plug connected to each contact pad and an electrical structure (for example, a capacitor or a resistor, etc.) connected to each contact pad.
  • Each contact plug 133a, 133b, 133c is formed in the interlayer dielectric layer 132, and each contact plug 133a is aligned with the bottom of the corresponding main contact pad 131a and the active area AA1 of the corresponding core element (that is, the corresponding source Area or drain area S/D1) is arranged to electrically connect the corresponding main contact pad 131a and the active area AA1 of the core element, and the top of each contact plug 133b is aligned with the corresponding first edge contact pad 111b or The bottom of the two edge contact pads, the bottom of each contact plug 133b is aligned with the active area AA1 at the boundary of the core area I (that is, the corresponding source or drain area S/D1) or the STI 100a in the boundary area III. Connect the corresponding first edge contact pad 111b or second edge contact pad to the active area AA1 at the boundary of the core area I or the STI 100a at the boundary area III.
  • the present invention also provides a mask assembly for manufacturing the contact pad structure of the semiconductor device of the present invention, including: a first mask 20 and a second mask 30.
  • the first mask 20 has a plurality of parallel first lines 201, a first spacer 202 is formed between two adjacent first lines 201, and at least one first line 201 on the outermost side of the first mask 20
  • the line width of at least the other first lines 201 is larger, and the line width of at least one first spacer 202 on the outermost side of at least the first mask 20 is larger than the line width of other first spacers 202.
  • the two outermost first lines 201 of the first mask 20 (that is, the outermost first first line 201a and the second first line 201b) have line widths greater than those of the other first lines 201.
  • the line width of a line 201a is greater than the line width of the first line 201b
  • the line width D6 of the first spacer 202 between the first lines 201a and 201b (that is, the outermost first spacer 202 of the first mask 20) Is larger than the line width of other first spacers 202
  • the line width D1 of the first spacer 202 between the first line 201b and another adjacent first line 201 is different from that of the other first spacers 202 (that is, except
  • the first spacer 202 between the first lines 201a and 201b has a line width D4.
  • the second mask 30 has a plurality of second stripes 311 that are parallel and perpendicular to each of the first lines 201.
  • a second spacer 312 is formed between two adjacent second lines 311, and the second mask 30 is the most The line width of at least one outer second line 311 is larger than other second lines 311, and the line width of at least one second spacer 312 on the outermost side of the second mask plate 30 is larger than the line width of other second spacers 312, for example ,
  • the two outermost second lines of the second mask 30 (that is, the outermost first second line 311a and the second second line 311b) have a line width larger than the other second lines 311, and the second line
  • the line width of 311a is greater than the line width of the second line 311b
  • the line width of the second spacer 312 between the second lines 311a and 311b (that is, the outermost second spacer 312 of the second mask 30) is larger than the other The line width of the second spacer 312, and the line width of the
  • each The overlapping area of a line 201 and each second line 311 is the area where the contact pad is formed. Therefore, the overlapping area of the first line 201a and each second line 311 except for the second lines 311a and 311b defines the area in FIG. 13
  • the overlapping area of each first edge contact pad pattern 111 in the first edge layout area 11, the first line 201b and each second line 311 except for the second lines 311a and 311b defines the first edge layout area in FIG.
  • Each of the first edge contact pad patterns 112 in 11; the overlapping area of the second line 311a and each first line 201 except the first lines 201a and 201b defines each of the second edge layout regions 12 in FIG. 13
  • the two edge contact pad patterns 122, the overlapping area of the second line 311b and each first line 201 except the first lines 201a and 201b define each second edge contact pad pattern in the second edge layout area 12 in FIG. 13 121.
  • the overlapping area of each first line 201 except the first lines 201a and 201b and each second line 311 except the second lines 311a and 311b defines the main layout area 10 in FIG. 13 and the main contacts therein.
  • the pad pattern 111, the first spacer 202 between the first line 201b and the adjacent first line 201 inside it defines the first edge distance D1 between the first edge layout area 11 and the main layout area 10, and the first line
  • the line width of the first spacer 202 between 201b and its outer adjacent first line 201a defines the sixth distance D6 between the two rows of first edge contact pad patterns 111 and 112 in the first edge layout area 11.
  • the remaining first spacer area 202 defines the fourth interval D4 between the two rows of main contact pad patterns
  • the second spacer area 312 between the second line 311b and the inner adjacent second line 311 defines the second edge layout
  • the line width of the second spacer area 312 between the second line 311b and the second line 311a adjacent to the outside defines the line width in the second edge layout area 12
  • the third distance D3 between the two rows of second edge contact pad patterns 121 and 122, and the remaining second spacer regions 312 define the fifth distance D5 between the two rows of main contact pad patterns.
  • first mask 20 and the second mask 30 are same-sex masks means that the pattern development properties of the two masks are the same, and both retain the parts corresponding to the lines or the parts corresponding to the spacers.
  • the first mask 20 and the second mask 30 are respectively used for photoetching, and the corresponding parts of the first spacer and the second spacer will be retained as the lower film layer.
  • the etched mask structure when the two masks are both positive masks, the first mask 20 and the second mask 30 are respectively used for photoetching, and the corresponding parts of the first line and the second line will be retained accordingly.
  • Mask structure for etching the underlying film layer when the two masks are both negative masks, the first mask 20 and the second mask 30 are respectively used for photoetching, and the corresponding parts of the first spacer and the second spacer will be retained accordingly.
  • each of the first lines 201 and the overlapping area of each second spacer area 312 is the area where the contact pad is formed. Therefore, the overlapping area of the first line 201a and each second spacer area 312 defines each first edge in the first edge layout area 11 in FIG.
  • the edge contact pad pattern 111, the overlapping area of the first line 201b and each second spacer area 312 defines each first edge contact pad pattern 112 in the first edge layout area 11 in FIG.
  • each first line 201 exposed on the outside defines each second edge contact pad pattern 122 in the second edge layout area 12 in FIG. 15, and the second interval between the second line 311a and the second line 311b
  • the portions of each first line 201 exposed by the area 312 define each second edge contact pad pattern 121 in the second edge layout area 12 in FIG. 15, and each first line 201 exposed by the remaining second spacer areas 312
  • the part defines each main contact pad pattern 131 in the main layout area 10 in FIG.
  • the second line 311 except for the second line 311b and the second line 311a defines two main contact pad patterns in the main layout area 10 in FIG.
  • the fifth distance D5 between the column main contact pad patterns 131, the first line 201 except the first line 21b and the first line 201a defines the space between the two rows of main contact pad patterns 131 in the main layout area 10 in FIG. 15
  • the first mask 20 and the second mask 30 are heterogeneous masks, meaning that the pattern development properties of the two masks are opposite, one retains the part corresponding to the line, and the other retains the corresponding interval. part.
  • the corresponding part of the first spacer area will be retained as the lower film layer after photolithography using the first mask 20
  • the corresponding part of the second line will be retained as the mask structure for the etching of the lower film layer
  • the first mask plate 20 is a positive mask
  • the second mask 30 is a negative mask
  • the first mask 20 is used for photolithography
  • the corresponding part of the first line will be retained as the mask structure for the etching of the lower film layer
  • the second mask 30 is used for photolithography.
  • the corresponding part of the second spacer area is retained as a mask structure for the etching of the underlying film layer.
  • the second edge layout can be defined
  • the shape of the second edge contact pad pattern in the outermost column of the area is not exactly the same and includes a long strip, a U shape that is tilted to the left, a U shape that is tilted to the right, an L shape that is tilted to the left, and a shape that is tilted to the right.
  • the second mask 30 and the first mask 20 are aligned and overlapped, except for the first second line 311a on the outermost side of the second mask 30
  • the ends of all other second lines 311 do not exceed the outermost first first line 201a of the first mask plate 20.
  • the second mask 30 when the first mask 20 and the second mask 30 are heterogeneous masks and the second mask 30 and the first mask 20 are aligned and overlapped, the second mask
  • the outermost first second line 311 of 30 exposes at least one end 203 of the first line 201.
  • the first mask 20 and the second mask 30 may be capable of combining the first line and the first spacer, the second line and the second line through a single photolithography process, respectively.
  • the pattern of the spacer is transferred to the mask plate used to form the layer of the contact pad structure, and it can also be used in some auxiliary layers (for example, the layer used to form the contact pad structure) through a process of double patterning or multiple patterning, respectively.
  • the hard mask layer is formed in the first line and the first spacer pattern, the second line and the second spacer pattern, and the auxiliary layer with the first line and the first spacer pattern is In the first mask 20, the auxiliary layer having the patterns of the second lines and the second spacers is the first mask 30.
  • auxiliary layer for example, a hard mask layer on a layer used to form a contact pad structure
  • auxiliary layer for example, a hard mask layer on a layer used to form a contact pad structure
  • auxiliary layer can be regarded as a mask combination formed after the first mask 20 and the second mask 30 are aligned and overlapped.
  • the specific steps of forming the first mask 20 or the second mask 30 through a double patterning process include:
  • a semiconductor substrate 800 is provided.
  • an etch stop layer 801 such as silicon oxide, etc.
  • an interlayer dielectric layer 802 a layer for forming contact pads
  • the mask layer 803 for example, silicon nitride, etc.
  • the first auxiliary layer 804 for example, an organic dielectric layer, etc.
  • the bottom anti-reflection layer 805 and the photoresist layer 806, the photoresist layer 806 can be patterned by a single photolithography process , To form the corresponding pattern;
  • the bottom anti-reflective layer 805 and the first auxiliary layer 804 are etched to the top surface of the hard mask layer 803 to perform the patterned photolithography
  • the pattern in the adhesive layer 806 is transferred to the first auxiliary layer 804, the remaining bottom anti-reflection layer 805 and the first auxiliary layer 804 form multiple cores, and then the patterned photoresist layer 806 is removed;
  • the sidewalls 807a are formed on the sidewalls of the core (ie the bottom anti-reflection layer 805 and the first auxiliary layer 804), and then each core core (ie the bottom anti-reflection layer 805 and the first auxiliary layer 804) is removed.
  • the plate layer composed of 807a and its spacing is the first mask 20 or the second mask 30.
  • the side wall 807a is the first spacer 202 in the first mask 20
  • the interval between adjacent side walls 807 a is the first line 201 in the first mask 20.
  • first mask 20 and the second mask 30 are both formed by the method shown in FIGS. 20A to 20D, grooves extending in the first direction (ie corresponding to The first line 201 in the first mask 20) and the groove extending in a second direction perpendicular to the first direction (that is, corresponding to the second line 311 in the second mask 30), the grooves in the two directions meet The place is the position used to form the contact pad.
  • the specific steps of forming the first mask 20 or the second mask 30 through a double patterning process include:
  • a semiconductor substrate 800 is provided.
  • an etch stop layer 801 such as silicon oxide, etc.
  • an interlayer dielectric layer 802 a layer for forming contact pads
  • the mask layer 803 for example, silicon nitride, etc.
  • the first auxiliary layer 804 for example, an organic dielectric layer, etc.
  • the bottom anti-reflection layer 805 and the photoresist layer 806, the photoresist layer 806 can be patterned by a single photolithography process , To form the corresponding pattern;
  • the bottom anti-reflective layer 805 and the first auxiliary layer 804 are etched to the top surface of the hard mask layer 803 to perform the patterned photolithography
  • the pattern in the adhesive layer 806 is transferred to the first auxiliary layer 804, the remaining bottom anti-reflection layer 805 and the first auxiliary layer 804 form multiple cores, and then the patterned photoresist layer 806 is removed;
  • the remaining second auxiliary layer 807, the third auxiliary layer 809, the bottom anti-reflection layer 805, the first auxiliary layer 804 and the opening 808 constitute the plate layer structure that is the first mask 20 or the second mask 30.
  • the opening 808 is the first line 201 in the first mask 20
  • the second auxiliary layer 807 and the third auxiliary layer 809 on each side of the opening 808 form a stacked structure or bottom anti-reflection
  • the stacked structure formed by the layer 805 and the first auxiliary layer 804 is the first spacer 202 in the first mask 20.
  • the same method can be used to fabricate the second mask 30 on the first mask 20 that has been formed, or fabricate the first mask 20 on the second mask 30 that has been formed, so as to form an alignment overlap.
  • a semiconductor substrate 410 with multiple core elements is provided.
  • the specific process includes: First, a semiconductor substrate 410a is provided, which includes a core area I, a peripheral area II, and a boundary area. III.
  • the core area I is a storage area
  • the core element to be formed on the core area I includes a selection element, and then a data storage element is connected above the core element.
  • the selection element is, for example, a MOS transistor or a diode
  • the data storage element is, for example, a capacitor.
  • Variable resistors, etc., a selection element and the corresponding data storage element form a memory cell.
  • Peripheral circuits may be formed in the peripheral area II to control the memory cells.
  • a plurality of shallow trench isolation structures 411b are formed in the semiconductor substrate 410a of the core region I, shallow trench isolation structures 411a are formed in the semiconductor substrate 410a of the junction region III, and the shallow trench isolation structures 411a define a two-dimensional plane At the boundary between the core area I and the peripheral area II, the shallow trench isolation structure 411b defines the active area AA1 corresponding to each core element in the core area I.
  • the distribution of the active area AA1 on the two-dimensional plane is strip-shaped and all extend along the first direction, and the active area AA1 may be arranged in a staggered arrangement on the surface of the semiconductor substrate 410a.
  • the buried word line WL is formed in the semiconductor substrate 410a.
  • the buried word line WL is generally buried at a predetermined depth in the semiconductor substrate 410a, extending in the second direction (ie the row direction) and passing through the shallow trench isolation.
  • the second direction intersects but is not perpendicular to the first direction of the active area AA1.
  • the buried word line WL is used as a gate to control the switching of the memory cell.
  • the sidewall and bottom of the buried word line WL are surrounded by a gate dielectric layer (not shown), and the top of the buried word line WL is covered by the gate.
  • the cap layer 412 is buried inside. Since the buried word line WL is not the focus of the present invention, the related manufacturing process can refer to the known technical solutions in the art, which will not be described in detail here.
  • the gate dielectric layer may include silicon oxide or other suitable dielectric materials
  • the buried word line WL may include aluminum, tungsten, copper, titanium aluminum alloy, polysilicon or other suitable conductive materials
  • the gate cap layer 412 may Including silicon nitride, silicon oxynitride, silicon carbide nitride or other suitable insulating materials.
  • the active area AA1 on both sides of the buried word line WL can be doped with a second type of dopants, such as P-type or N-type dopants, to form source and drain regions (defined as S/ D1), one of the AA1 on both sides of the buried word line WL is located at the position corresponding to the predetermined bit line contact structure at the center of AA1, and the other is located at the predetermined storage node contact structure position at the end of the active area AA1.
  • the word lines WL and S/D1 may constitute or define a plurality of MOS memory transistors formed on the core region I of the semiconductor device.
  • the source and drain regions corresponding to the peripheral transistors can also be formed in the peripheral area II at the same time.
  • an etch stop layer 413 can be further formed on the semiconductor substrate 410a, the etch stop layer 413 covers the S/D1 and S/D2, and its material For example, silicon nitride (SiN) and/or silicon oxide (SiO 2 ) are included.
  • bit line contact plugs (not shown) and a bit line BL located above the bit line contact plugs are formed on the S/D1 serving as the drain region of the core region I, and the bit line
  • the contact plug can be formed by the following method: firstly etch the S/D1 between two adjacent WLs formed in one active area AA1 to form a groove, and then form a metal silicide in the groove.
  • the bit lines BL are parallel to each other and extend along the third direction (ie, the column direction) perpendicular to the buried word line WL, and cross the active area AA1 and the buried word line WL at the same time.
  • Each bit line BL includes, for example, a semiconductor layer (such as polysilicon, not shown), a barrier layer (such as Ti or TiN, not shown), and a metal layer (such as tungsten, aluminum, or copper, etc.) stacked in sequence. Not shown) and a mask layer (for example, containing silicon oxide, silicon nitride or silicon carbonitride, not shown).
  • a gate structure G1 is formed, which includes, for example, a gate dielectric layer (not shown) and a gate layer (not shown) stacked in sequence. .
  • the gate layer of the gate structure G1 and the semiconductor layer or metal layer of the bit line BL are formed together.
  • the manufacturing process of the sidewall spacer of the gate structure G1 may be performed first, so that the sidewall spacer 414 of the gate structure G1 includes silicon oxide or silicon oxynitride (SiON), and then the manufacturing process of the sidewall spacer 415 of the bit line BL is performed , And the sidewall spacer of the bit line BL may include silicon nitride.
  • an etching back manufacturing process may be performed again, so that the overall height of the gate structure G1 is lower than the bit line BL.
  • the contact pad layout shown in FIGS. 13 to 15 or the mask plate combination shown in FIGS. 17A to 19 of the present invention can be used to form the storage node contact structure.
  • the specific process is as follows:
  • an interlayer dielectric layer 500 is formed on the semiconductor substrate 410, the material of which is Examples include silicon oxide, silicon nitride, or low-K dielectrics.
  • the interlayer dielectric layer 500 is completely covered on the semiconductor substrate 410 through a deposition process, and the interlayer dielectric layer 500 is made to fill the space between the bit lines BL and connect the bit lines BL to the gate structure G1 and its The sidewall spacers 414 are buried inside, and then the interlayer dielectric layer 500 is planarized by a process such as chemical mechanical polishing to form the interlayer dielectric layer 500 having a flat top surface as a whole.
  • the top surface of the planarized interlayer dielectric layer 500 is at least not lower than the top surface of each bit line BL.
  • the first mask 20 and the second mask 20 shown in FIG. 18 or FIG. 19 are formed on the interlayer dielectric layer 500.
  • the mask 30 is aligned with the overlapped mask combination pattern (not shown).
  • the mask combination pattern is any one of the contact pad layouts shown in FIGS.
  • the interlayer dielectric layer 500 is anisotropically etched to form a contact hole that penetrates the interlayer dielectric layer 500 and exposes the corresponding S/D1 used as the source area below and The source region S/D2 or the contact hole (not shown) of the gate G1 in the peripheral region II is exposed.
  • the contact holes corresponding to the first edge contact pad pattern and the second edge contact pad pattern in the contact pad layout can be formed at the boundary of the core area I (at this time, the top of the contact hole is connected together and at least crosses the core
  • the outermost word line (WL) at the boundary of area I may also be formed at least partially on STI 411a of boundary area III; contact holes corresponding to the main contact pad pattern in the contact pad layout are formed in core area I.
  • an ashing process or wet cleaning or other suitable processes can be performed to remove the film layer above the interlayer dielectric layer 500, and fill each contact hole in sequence A barrier metal layer (not shown) and a conductive metal layer (not shown).
  • the barrier metal layer can cover the inner wall of the contact hole and the top surface of the interlayer dielectric layer 500 with a uniform thickness.
  • the barrier metal layer can reduce or prevent The metal material provided in the contact hole diffuses into the interlayer dielectric layer 500, which can be formed by Ta, TaN, TaSiN, Ti, Ti N, TiSiN, W, WN or any combination thereof.
  • the conductive metal layer can be made of (one or more) refractory metal (for example, cobalt, iron, nickel, tungsten) And/or molybdenum) is formed.
  • the conductive metal layer may be formed using a deposition process with good step coverage properties, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) (for example, sputtering).
  • the formed conductive metal layer also covers the surface of the interlayer dielectric layer 500 around the contact hole.
  • the top surface of the interlayer dielectric layer 500 forms a main contact pad 511a, peripheral contact pads 511d and 511e, and a first edge contact pad (or a second edge contact pad) 511b in the interlayer dielectric layer 500.
  • the main contact pad 511a serves as the storage node contact structure in the core area I, and is used to connect with the capacitor structure formed above the core area I later.
  • the first edge contact pad (or the second edge contact pad) 511b is formed by at least two top-connected contact plugs in the boundary of the core area I (as shown in FIG.
  • the contact plug is formed by connecting the top of the contact plug at the boundary of the core area I (as shown in FIG. 25), or is formed by a larger-sized contact structure in the boundary area III (not shown), as the core
  • the virtual storage node contact structure at the boundary of the area I or in the junction area III is used to connect with the capacitor structure formed at the boundary of the core area I or above the junction area III.
  • the first edge contact pad (or the second edge contact The pad 511b is aligned parallel to the bit line BL.
  • the cross-sectional structure of the first edge contact pad (or the second edge contact pad) 511b is, for example, an inverted U-shaped electrical contact structure or a comb-shaped electrical contact structure.
  • the peripheral contact pad 511d is used as the contact structure of the gate structure G1 of the peripheral region II to draw the gate structure G1 outward
  • the peripheral contact pad 511e is used as the contact structure of the source region or the drain region S/D2 of the peripheral region II.
  • the main contact pad 511a, the peripheral contact pads 511d and 511e, and the first edge contact pad (or the second edge contact pad) 511b may each be an integrally formed structure, or may be composed of a pad and a contact plug connected thereunder.
  • a capacitor structure 705a is connected to each main contact pad 511a of the core area I, and a capacitor structure 705b is connected to the first edge contact pad or the second edge contact pad 511b at the boundary of the core area I and/or the boundary area III.
  • Each capacitor includes The lower electrode layer 701, the capacitor dielectric layer 702 and the upper electrode layer 703.
  • the capacitors have a bottom support layer 600, a middle support layer 601 and a top support layer 602 that are laterally supported and stacked in intervals.
  • the bottom support layer 600 is used for The bottom electrode layer formed later is supported at the bottom, and on the other hand, it is also used to isolate the internal components of the semiconductor substrate 400 from the upper capacitors and other components.
  • the formation process of the bottom support layer 600 may also be a thermal oxidation process.
  • the materials of the bottom support layer 600, the middle support layer 601 and the top support layer 602 include but are not limited to silicon nitride.
  • two or more intermediate support layers 601 may be stacked between the bottom support layer 600 and the top support layer 602.
  • the capacitor structure 705b has a first width W1
  • the capacitor structure 705a has a second width W2.
  • all capacitor structures can be arranged in a hexagonal close-packed arrangement.
  • the lower electrode layer 701 has a cylindrical structure, and may be a polysilicon electrode or a metal electrode.
  • a metal electrode a stacked structure of titanium nitride (TiN) and Ti can also be used.
  • TiN titanium nitride
  • the lower electrode layer 701 is a polysilicon electrode, it may be formed of a zero-doped and/or doped polysilicon material.
  • the capacitor dielectric layer 702 covers the inner surface and the outer surface of the cylindrical structure of the lower electrode layer 701 to make full use of the two opposite surfaces of the lower electrode layer 701 to form a capacitor with a larger electrode surface area.
  • the capacitor dielectric layer 702 may be a high-K dielectric layer such as metal oxide.
  • the capacitor dielectric layer 702 has a multilayer structure, for example, a two-layer structure of hafnium oxide-zirconia.
  • the upper electrode layer 703 may be a single-layer structure or a multilayer structure.
  • the upper electrode layer 703 is a single-layer structure, for example, a polysilicon electrode or a metal electrode, when the upper electrode layer 703 is a metal electrode In this case, for example, titanium nitride (TiN) can be used.
  • TiN titanium nitride
  • the upper electrode layer 703 can form a capacitor with the capacitor dielectric layer 702 and the lower electrode layer 701 corresponding to the inside of the cylindrical structure and the outside of the cylindrical structure.
  • the capacitor dielectric layer 702 and the upper electrode layer 703 all have uneven sidewall structures corresponding to the middle support layer 601 and the top support layer 602 outside the cylindrical structure of the lower electrode layer 701, As a result, the part of the upper electrode layer 703 on the edge area of the core area I (that is, the boundary area of the capacitor hole array) corresponds to the middle support layer 601 and the top support layer 602 to be far away from the lower electrode layer 701 Protruding in the direction of, making the boundary of the capacitor array in the core area I uneven.
  • the capacitor dielectric layer 702 and the upper electrode layer 703 also extend sequentially to cover the surface of the bottom support layer 600 remaining on the peripheral region II.
  • a chemical vapor deposition process may be used to form an upper electrode filling layer 704 on the surface of the upper electrode layer 703.
  • the upper electrode filling layer 704 fills the space between the upper electrode layers 703. That is, the upper electrode filling layer 704 fills the gap between adjacent cylindrical structures and covers the structure formed above.
  • the material of the upper electrode filling layer 704 includes undoped or boron-doped polysilicon. This completes the fabrication of the capacitor array.
  • the capacitor structure 705b and the corresponding first edge contact pad or the second edge contact pad 511b have a larger contact area, thereby reducing the contact resistance. It is small, which is beneficial to improve the electrical performance of the device.
  • the width of the capacitor hole corresponding to the capacitor structure 705b is relatively large, the difference in the density of the circuit patterns in the peripheral area II and the core area I can be buffered, so that the optical lithography process and/or etching process of the capacitor hole can be improved.
  • the proximity effect reduces the sparse/dense loading effect of the circuit patterns in the peripheral area II and the core area I, protects the capacitor holes in the core area I, and ensures that the capacitor holes within the boundary of the core area and the capacitor holes filled in the core area
  • the consistency of the capacitor prevents the occurrence of abnormalities in the capacitor hole above the main contact pad in the core area, which may cause the subsequent failure of the capacitor structure.

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Abstract

一种电接触结构、接触垫版图及结构、掩模板组合及制造方法，通过使得形成在所述核心区（I）的边界处（I-2）的至少两个接触插塞（106b）的顶部相联在一起，在核心区（I）的边界处（I-2）形成顶部横截面积较大的组合接触结构，由此，为后续在核心区（I）的边界处（I-2）的接触结构上方形成电学结构的工艺提供足够的工艺余量，使得该边界处（I-2）的所述电学结构的尺寸增大，降低接触阻抗，且通过该边界处（I-2）尺寸增大的所述电学结构缓冲核心区（I）和周边区（II）之间的电路图案的密度差异，改善光学邻近效应，保证核心区（I）边界以内的接触插塞（106a、106b）上方的电学结构的一致性，并防止所述边界处（I-2）的接触插塞（106b）上方的电学结构出现坍塌，提高器件性能。

Description

电接触结构、接触垫版图及结构、掩模板组合及制造方法 技术领域
本发明涉及半导体技术领域，特别涉及一种电接触结构及其制造方法、接触垫版图、接触垫结构、掩模板组合、半导体器件及其制造方法。
背景技术
已使用各种技术，在半导体衬底或晶片的有限面积中集成更多电路图案。由于电路图案间距的不同，集成电路一般分为器件密集区(Dense)、器件稀疏区(ISO)及器件孤立区，器件密集区是器件密度较高(即器件比较密集)的区域，器件稀疏区是器件密度较低(即器件比较稀疏)的区域，器件孤立区是相对稀疏区和密集区单独设置的区域。随着半导体器件的临界尺寸不断减小，电路图案的密度和/或器件高度也不断增加，受到曝光机台(optical exposure too1)的分辨率极限以及器件密集区和器件稀疏区之间的密度差异效应(即电路图案的密集/稀疏效应)的影响，在执行光刻工艺和/或蚀刻工艺时的困难也会增大很多(例如，工艺余量减小)，进而导致制造出来的半导体器件的性能受到影响。
例如，在动态随机存取存储(dynamic random access memory，以下简称为DRAM)装置的情况中，数目庞大的存储单元(memory cell)聚集形成一阵列存储区，而阵列存储区的旁边存在有周边区，周边区内包含有其他晶体管元件以及接触结构等，阵列存储区作为DRAM的器件密集区，用来存储数据，周边区作为DRAM的器件稀疏区，用于提供阵列存储区所需的输入输出信号等。其中，阵列存储区中的每一存储单元可由一金属氧化半导体(metal oxide semiconductor，MOS)晶体管与一电容(capacitor)结构串联组成。其中，电容位于阵列存储区内，所述电容堆叠在位线上方并电耦接至所述电容器对应的存储节点接触部，所述存储节点接触部电耦接至其下的有源区。随着半导体技术的不断发展，器件的临界尺寸不断减小，DRAM装置的存储单元之间的间隙变得更窄，当通过自对准接触(Self Aligned Contact，SAC)工艺形成存储节点接触部时，受到曝光机台(optical exposure too1)的分辨率极限以及器件密集 区和器件稀疏区之间的密度差异效应的影响，阵列存储区内部形成的接触孔不一致，器件密集区边界的接触孔产生异常，进而导致上方形成的电容器与接触孔中的接触插塞接触面积减小、接触阻抗的增加，有可能造成一些存储位因接触插塞的断路或短路问题而失效，以及，阵列存储区边界处的电容器坍塌的问题，这些问题影响和限制了DRAM性能的提高。
发明内容
本发明的目的在于提供一种电接触结构及其制造方法、接触垫版图、接触垫结构、掩模板组合、半导体器件及其制造方法，以解决现有的动态随机存取存储器等半导体器件中因光学邻近效应以及电路图案的密集/稀疏效应而导致核心区内部的接触插塞上接的电学结构不一致以及核心区边界的接触插塞上接的电学结构异常的问题。
为解决上述技术问题，本发明提供一种半导体器件的电接触结构，所述电接触结构包括：
多个接触插塞，形成于所述半导体器件的核心区的核心元件的上方，且各个所述接触插塞的底部与相应的核心元件的有源区接触，
其中，形成在所述核心区的边界处的至少两个接触插塞的顶部相联在一起，且所述顶部相联在一起的所有接触插塞中包括边界处最外侧的接触插塞。
基于同一发明构思，本发明还提供一种半导体器件，包括：
半导体衬底，所述半导体衬底具有核心区，所述核心区中形成有多个核心元件；
层间介质层，覆盖在所述半导体衬底上；以及，
如本发明所述的半导体器件的电接触结构，所述电接触结构形成于所述层间介质层中，所述电接触结构的各个所述接触插塞的底部与相应的核心元件的有源区接触，且所述电接触结构中形成在所述核心区的边界处的至少两个接触插塞的顶部相联在一起，且所述顶部相联的所有的接触插塞中包括边界处最外侧的接触插塞。
基于同一发明构思，本发明还提供一种半导体器件的电接触结构的制造 方法，包括：
提供半导体衬底，所述半导体衬底具有核心区，所述核心区中形成有多个核心元件；
在所述半导体衬底上形成层间介质层，并在所述层间介质层中形成多个接触孔，各个所述接触孔贯穿所述层间介质层并暴露出相应的核心元件的有源区；
在所述接触孔中形成接触插塞，且各个所述接触插塞的底部与相应的核心元件的有源区接触，且形成在所述核心区的边界处的至少两个接触插塞的顶部相联在一起，所述顶部相联在一起的所有接触插塞中包括边界处最外侧的接触插塞。
基于同一发明构思，本发明还提供一种半导体器件的制造方法，包括：采用本发明所述的半导体器件的电接触结构的制造方法，在一具有核心区的半导体衬底上形成与相应的核心元件电接触的电接触结构。
与现有技术相比，本发明的技术方案，具有以下有益效果：
通过使得形成在所述核心区的边界处的至少两个接触插塞的顶部相联在一起，来在核心区的边界处形成顶部横截面积较大的组合接触结构，由此，一方面，可以为后续在核心区的边界处的组合接触结构上方形成电学结构(例如DRAM的电容器的下极板)的工艺提供足够的工艺余量，有利于该边界处的所述电学结构的尺寸增大，避免该边界处的电学结构出现异常或坍塌；另一方面，该边界处的电学结构和所述组合接触结构能具有较大的接触面积，因此接触阻抗减小，有利于提高器件的电学性能；更重要的是，该边界处的所述电学结构的尺寸增大，能够缓冲核心区和周边区之间的电路图案的密度差异，从而在形成核心区中的所有电学结构的光刻工艺和/或蚀刻工艺中能够改善光学邻近效应，减小稀疏/密集负载效应，保证核心区边界处以内的接触插塞上方的电学结构的一致性，提高器件性能。
本发明还提供一种半导体器件的接触垫版图，所述接触垫版图包括：
主版图区，所述主版图区中设有多个主接触垫图案，各个所述主接触垫图案的形状和尺寸相似，且所有的主接触垫图案呈棋盘状交错排布，所述主 接触垫图案彼此之间具有第四间距；
第一边缘版图区，分布在所述主版图区的一边外侧，所述第一边缘版图区中设有至少一个第一边缘接触垫图案，且每个所述第一边缘接触垫图案的面积大于每个所述主接触垫图案的面积，所述第一边缘版图区与所述主版图区之间具有第一边缘间距；
其中，所述第一边缘接触垫图案不同于所述主接触垫图案，所述第一边缘间距不同于所述第四间距。
基于同一发明构思，本发明还提供一种利用本发明所述的半导体器件的接触垫版图形成的接触垫结构，包括：
多个主接触垫，呈棋盘状交错排布，各个所述主接触垫的形状和尺寸相似，且所述主接触垫彼此之间具有第四间距；
至少一个第一边缘接触垫，分布在所有的主接触垫排布区域的一边外侧，且每个所述第一边缘接触垫的顶面面积大于每个所述主接触垫的顶面面积，最靠近所述主接触垫的所述第一边缘接触垫与最近邻的所述主接触垫之间具有第一边缘间距；
其中，所述第一边缘接触垫的尺寸不同于所述主接触垫的尺寸，所述第一边缘间距不同于所述第四间距。
基于同一发明构思，本发明还提供一种半导体器件，包括：
半导体衬底，所述半导体衬底具有核心区，所述核心区中形成有多个核心元件；
层间介质层，覆盖在所述半导体衬底上；
如本发明所述的半导体器件的接触垫结构，形成在所述层间介质层中；
多个接触插塞，形成在所述层间介质层中，各个接触插塞对准所述接触垫结构中的相应接触垫设置，以将相应的接触垫和所述核心元件的有源区电连接。
基于同一发明构思，本发明还提供一种用于制作本发明所述的半导体器件的接触垫结构的掩模板组合，包括：
第一掩模板，具有多条平行的第一线条，相邻的两条第一线条之间为第 一间隔区，且第一掩模板最外侧的至少一条第一线条的线宽大于其他的第一线条，第一掩模板最外侧的至少一个第一间隔区的线宽大于其他的第一间隔区的线宽；
第二掩模板，具有多条平行且与每条第一线条相交的第二条纹，相邻的两条第二线条之间为第二间隔区，且第二掩模板最外侧的至少一条第二线条的线宽大于其他的第二线条，第二掩模板最外侧的至少一个第二间隔区的线宽大于其他的第二间隔区的线宽；
其中，当所述第一掩模板和所述第二掩模板为同性掩模板且所述第二掩模板和所述第一掩模板对准重叠时，第一线条和第二线条的重叠区域为形成接触垫的区域；当所述第一掩模板和所述第二掩模板为异性掩模板且所述第二掩模板和所述第一掩模板对准重叠时，第一线条和第二间隔区的重叠区域为形成接触垫的区域。
与现有技术相比，本发明的技术方案还具有以下有益效果：
通过在主接触垫图案所在的主版图区的一侧设置第一边缘版图区，且第一边缘版图区中每个所述第一边缘接触垫图案的面积大于每个所述主接触垫图案的面积，由此基于该接触垫版图而形成核心区的主接触垫时，可以利用第一边缘接触垫图案形成在核心区边界处或核心区与周边区之间的交界区中形成相应的虚拟接触垫，且使得虚拟接触垫的顶面面积大于主接触垫的顶面面积，由此，能够增大后续在虚拟接触垫上上接的电学结构的尺寸，且在主接触垫和虚拟接触垫上上接电学结构时能够改善核心区与周边区之间的电路图案的密集/稀疏效应，提高核心区内部的主接触垫上接的电学结构的一致性，同时还能避免核心区边界处的主接触垫上接的电学结构异常的问题，提高了最终形成的半导体器件的性能。
附图说明
图1A～1D是本发明一实施例的半导体器件的电接触结构的制造方法中的剖面结构示意图；
图2A～2D是本发明另一实施例的半导体器件的电接触结构的制造方法中 的剖面结构示意图；
图3是本发明一实施例的半导体器件的制造方法中的俯视结构示意图；
图4～12是本发明一实施例的半导体器件的制造方法中的沿图3中的aa’线的剖面结构示意图；
图13是本发明一实施例的接触垫版图的结构示意图；
图14是本发明另一实施例的接触垫版图的结构示意图；
图15是本发明又一实施例的接触垫版图的结构示意图；
图16A是本发明一实施例的接触垫结构的结构示意图；
图16B是本发明另一实施例的接触垫结构的结构示意图；
图17A是本发明一实施例的掩模板组合中的第一掩模板的结构示意图；
图17B是本发明一实施例的掩模板组合中的第二掩模板的结构示意图；
图18是本发明一实施例的掩模板组合中的第一掩模板和第二掩模板均为正性掩模板时，两张掩模板叠加的结构示意图；
图19是本发明一实施例的掩模板组合中的第一掩模板为正性掩模板、第二掩模板为负性掩模板时，两张掩模板叠加的结构示意图；
图20A～图20D是本发明一实施例中将第一掩模板或第二掩模板中的图案转移到待刻蚀层的过程中的结构示意图；
图21A～图21D是本发明另一实施例中将第一掩模板或第二掩模板中的图案转移到待刻蚀层的过程中的结构示意图；
图22是本发明一实施例的半导体器件的制造方法中的俯视结构示意图；
图23～图25分别是本发明一实施例的半导体器件的制造方法中的沿图21A中的aa’线的剖面结构示意图。
其中，附图标记说明如下：
I-核心区；I-1-中央区；I-2-边界处；II-周边区；III-交界区；BL-位线；WL-字线；AA1、AA2-有源区；S/D1、S/D2-源区或漏区；G1-栅极结构；W1-第一宽度；W2-第二宽度；
100-半导体衬底；101-有源区；102-层间介质层；102a、102b、102c-接触孔；102d-沟槽；103-第一掩模图案；104-牺牲层；105-第二掩模图案；106、 106a、106c-接触插塞；106b-组合接触结构；107-第二层间介质层；108-第二掩模图案；108a、108b、108c-沟槽；109a、109b、109c-接触垫；300-半导体衬底；300a-半导体基底；301-浅沟槽隔离结构；302-栅极盖层；303-刻蚀停止层；304-侧墙；400-层间介质层；401a、401b、401d、401e-接触孔；401c-沟槽；501-牺牲层；501a、501d、501e-接触插塞；501b-组合接触结构；600-底层支撑层；601-中间支撑层；602-顶层支撑层；611-第一牺牲层；612-第二牺牲层；700a、700b-电容孔；701-下电极层；702-电容介质层；703-上电极层；704-上电极填充层；705a、705b-电容结构；
D1-第一边缘间距；D2-第二边缘间距；D3-第三间距；D4-第四间距；D5-第五间距；D6-第六间距；
10-主版图区；11-第一边缘版图区；12-第二边缘版图区；100-半导体衬底；100a、100b-浅沟槽隔离结构；111、112-第一边缘接触垫图案；111a-锯齿；111b-第一边缘接触垫；121、122-第二边缘接触垫图案；131-主接触垫图案；131a-主接触垫；132-层间介质层；133a、133b、133c-接触插塞；134-层间介质层；135-接触垫；201、201a、201b-第一线条；202-第一间隔区；203-末端；311、311a、311b-第二线条；312-第二间隔区；313-末端；410-半导体衬底；410a-半导体基底；411a、411b-浅沟槽隔离结构；412-栅极盖层；413-刻蚀停止层；414、415-侧墙；500-层间介质层；511a-主接触垫；511b-第一边缘接触垫或第二边缘接触垫；511d、511e-周边接触垫；800-半导体衬底；801-刻蚀停止层；802-层间介质层；803-硬掩膜层；804-第一辅助层；805-底部抗反射层；806-光刻胶层；807-第二辅助层；807a-侧墙；808-开口；809-第三辅助层。
具体实施方式
以下结合附图和具体实施例对本发明提出的技术方案作进一步详细说明。根据下面说明，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
图1D是示出本发明一实施例的半导体器件的电接触结构的剖面示意图。 请参考图1D，本发明一实施例提供的半导体器件的电接触结构包括多个接触插塞106a、106b，其中，接触插塞106a、106b形成于所述半导体器件的核心区I的核心元件(未图示)的上方，且各个所述接触插塞106a、106b的底部与相应的核心元件的有源区101接触。其中，核心区I包括边界处(或称为边界区、交界区、界面区)I-2以及位于边界处I-2以内的中央区I-1，形成在所述核心区I的边界处I-2的至少两个接触插塞106b的顶部相联在一起。核心区I为器件密集区，其周围的周边区II为器件稀疏区。
每个接触插塞106a、106b、106c可以包括阻挡金属层(未图示)和金属层(未图示)，阻挡金属层可以包括例如Ti、Ta、Mo、Ti xN y、Ta xN y、TixZry、Ti xZr yN z、Nb xN y、Zr xN y、W xN y、V xN y、Hf xN y、Mo xN y、Ru xN y和/或Ti xSi yN z。金属层可以包括例如钨、铜和/或铝。
核心区I的边界处I-2的顶部相联一起的所有接触插塞106b构成倒U形电接触结构或者梳状电接触结构，即核心区I的边界处I-2的顶部相联一起的所有接触插塞106b，在边界处I-2构成一个顶部横截面积较大的组合接触结构。
请结合图1D和图12，本实施例中，半导体器件为动态随机存取存储器(dynamic random access memory，DRAM)，核心区为DRAM存储器的存储阵列区，核心元件为存储晶体管，所述电接触结构为存储节点接触部，上接电容结构(即存储节点，storage node)。即核心区I的中央区I-1中的每个接触插塞106a上接一个电容结构(如图12中705a所示)，核心区I的边界处I-2中的一个组合接触结构上接一个电容结构(如图12中705b所示)，且所述边界处I-2的电容结构具有第一宽度W1，所述核心区I的所述边界处I-2以内(即中央区I-1)的电容结构具有第二宽度W2，由于核心区I的边界处I-2形成的顶部横截面积较大的组合接触结构的存在，因此，可以为边界处I-2的电容结构的形成工艺提供足够的工艺余量，以有利于增大该边界处I-2的电容结构的第一宽度W1，使得所述第一宽度W1大于所述第二宽度W2，进而，一方面，避免该边界处I-2形成的电容结构坍塌；另一方面，使得该边界处I-2的电容结构与其下的所述组合接触结构之间能具有较大的接触面积，一减小接触阻 抗，有利于提高器件的电学性能；更重要的是，该边界处I-2的所述电容结构的尺寸增大，能够缓冲核心区I和周边区II之间的电路图案的密度差异，从而在执行光刻工艺和/或蚀刻工艺时能够改善光学邻近效应，减小稀疏/密集负载效应，保证核心区I边界处I-2以内的区域(即中央区I-1)的接触插塞106a上方的电容结构的一致性，防止出现核心区I内一些位置的接触插塞上方的电容结构出现异常或边界处I-2的接触插塞上方的电容结构出现坍塌的问题。可选地，所述第一宽度W1大于1.5倍的所述第二宽度W2。
请参考图3和图12，所述半导体器件包括多条字线WL和多条位线BL，每条所述字线WL与所述核心区I中的多个所述有源区AA1相交，所述字线WL可以是埋入式字线，所述位线BL形成在核心区I的核心元件的上方并与所述字线WL垂直，所述顶部相联一起的所有接触插塞构成的结构(例如倒U形电接触结构或者梳状电接触结构)跨过至少一条所述字线WL并与所述位线BL对准(即平行)，例如形成的倒U形电接触结构或者梳状电接触结构跨过核心区I最外侧边界(即边界处I-2最靠近周边区II的一侧，也就是边界处I-2的最外侧)上的一个有源区AA1中的一条字线WL。需要说明的是，本实施例中，虽然举例所述半导体器件为DRAM，但是本发明的技术方案并不仅仅限定于此，半导体器件还以是任意合适的电学器件，例如其他架构的存储器，此时，所述电容结构可以替代为相应的电学结构，例如电阻器等。
图1A～图1D是示出根据本实施例的半导体器件的电接触结构的制造方法中的器件剖面示意图。请参考图1A～图1D，本实施例还提供一种半导体器件的电接触结构的制造方法，包括以下步骤：
首先，请参照图1A，提供一个半导体衬底100，其包含核心区I和周边区II，半导体衬底100可以选自硅基板、绝缘体上硅基板(SOI)、锗基板、绝缘体上锗基板(GOI)、硅锗基板等。半导体衬底100中形成有多个浅沟槽隔离结构(未图示)，该浅沟槽隔离结构通过刻蚀半导体衬底100以形成沟槽，然后再向沟槽中填入绝缘材料的方式来形成，该浅沟槽隔离结构的材质可包含氧化硅、氮化硅、或是氮氧化硅等。该浅沟槽隔离结构在二维平面上界定出了核心区I和周边区II的分界处(即界定出了核心区I的边界处I-2)，同时还 界定出了核心区I中的各个核心元件所对应的有源区101以及周边区II中的外围元件所对应的有源区101。
接着，请继续参照图1A，在半导体衬底100上覆盖层间介质层102，层间介质层102可以被设置成具有单层结构或多层结构。层间介质层102可以包括氮化硅、氮氧化硅和低k介电材料中的至少一种。其中，低k介电材料的介电常数k小于氧化硅的介电常数，并且它可以用作金属间介电层(IMD)，例如为高密度等离子体(HDP)氧化物、原硅酸四乙醋(TEOS)、等离子体增强型TEOS(PE-TEOS)、未掺杂硅酸盐玻璃(USG)、硅酸磷玻璃(PSG)、硅酸棚玻璃(BSG)、硅酸棚磷玻璃(BPSG)、氟化硅酸盐玻璃(FSG)、旋涂式玻璃(SOG)等。另外，可以在半导体衬底100和层间介质层102之间形成蚀刻停止层(未图示)，蚀刻停止层可以包括SiN、SiON、SiC、SiCN、BN(氮化棚)或其任何组合。可以使用等离子体增强型CVD(PECVD)、高密度等离子体CVD(HDP-CVD)、大气压CVD(APCVD)和/或旋涂工艺形成蚀刻停止层和层间介质层102。
然后，请继续参照图1A，通过第一次光刻工艺，在层间介质层102上形成第一掩模图案103，该第一掩模图案103定义出各个接触插塞的位置，然后，使用第一掩模图案103作为蚀刻掩模，各向异性地蚀刻层间介质层102，以形成贯穿所述层间介质层102且暴露出下方相应的有源区101的接触孔102a、102b和102c，接触孔102a、102b和102c均相互独立，每个接触孔102a位于在核心区I的中央区I-1中并暴露出中央区I-1中的相应核心元件的有源区101，每个接触孔102b位于核心区I的边界处I-2且暴露出边界处I-2中的相应核心元件的有源区101，每个接触孔102c位于周边区II中并暴露出相应外围元件的有源区101。
然后，请参考图1B，在形成接触孔102a～102c之后，可以执行灰化工艺或湿式清洗工艺，以去除第一掩模图案103，并填充牺牲层104于各个接触孔102a～102c中。所述牺牲层104可以由旋涂硬掩模层(SOH)或非晶碳层(ACL)形成，这样可以使得能够用牺牲层104填充具有高的高宽比的接触孔102a～102c。
接着，请继续参考图1B，可以通过第二次光刻工艺在层间介质层102和牺牲层104上形成第二掩模图案105，第二掩模图案105定义出用于将边界处I-2相应的至少两个接触孔102b的顶部相连的沟槽102d。以第二掩模图案105为掩模，刻蚀边界处I-2处的层间介质层，以形成将边界处相应的至少两个接触孔102b的顶部相连的沟槽102d，沟槽102d至少暴露出边界处I-2最外侧的一个接触孔(例如沟槽102d至少暴露出边界处I-2最外侧的一列接触孔中的一个)。
请参考图1C，可以使用氧、臭氧或紫外线的灰化工艺或者通过湿式清洗工艺去除接触孔102a～102c、102d中的牺牲层104以及第二掩模图案105，以重新暴露出各个接触孔102a～102c和沟槽102d。
请参考图1D，可以在接触孔102a～102c和沟槽102d中形成阻挡金属层(未图示)，例如，阻挡金属层可以以均匀的厚度覆盖接触孔和沟槽的内壁与层间介质层102的顶表面。阻挡金属层能够减少或防止设置在接触孔和沟槽中的金属材料扩散到层间介质层102中。例如，所述阻挡金属层可以由Ta、TaN、TaSiN、Ti、Ti N、TiSiN、W、WN或它们的任何组合形成，可以使用化学气相沉积(CVD)、原子层沉积(ALD)或物理气相沉积(PVD)(例如，溅射)等工艺形成。然后，在各个接触孔102a～102c和沟槽102d中填充金属层，以形成接触插塞106a、106c和组合接触结构106b。其中，金属层可以由(一种或多种)难熔金属(例如，钴、铁、镍、钨和/或钼)形成。另外，可以使用具有良好阶梯覆盖性质的沉积工艺形成金属层，例如，使用化学气相沉积(CVD)、原子层沉积(ALD)或物理气相沉积(PVD)(例如，溅射)形成。沉积形成的金属层还覆盖在接触孔周围的层间介质层102的表面上，之后，可以采用化学机械抛光(CMP)工艺对沉积的金属层的顶面进行化学机械抛光，直至暴露出出层间介质层102的顶面，以形成位于层间介质层102中的接触插塞106a、106c和组合接触结构106b。
图1A～图1D所示的方法，能够在相同的光刻次数下，减少沉积工艺的次数，使得顶部相联一起的所有接触插塞106一体成型。
请参考图2D，本发明另一实施例提供一种半导体器件的电接触结构，包 括多个接触插塞106，其中，形成于所述半导体器件的核心区I的边界处(或称为边界区、交界区、界面区)I-2的至少两个接触插塞106的顶部通过一面积较大的接触垫109b相联在一起。核心区I为器件密集区，其周围的周边区II为器件稀疏区。核心区I的边界处I-2以内的区域(称为中央区I-1)中的接触插塞106的顶部设有独立的接触垫109a，且各个接触垫109a一一对应地与相应的接触插塞106的顶部电接触。
核心区I的边界处I-2的通过相应的接触垫109b而顶部相联一起的所有接触插塞106构成倒U形电接触结构或者梳状电接触结构，即核心区I的边界处I-2的顶部相联一起的所有接触插塞106，在边界处I-2构成一个顶部横截面积较大的组合接触结构。
请结合图2D和图12，本发明另一实施例中，半导体器件为动态随机存取存储器(dynamic random access memory，DRAM)，核心区为DRAM存储器的存储阵列区，核心元件为存储晶体管，所述电接触结构为存储节点接触部，上接电容结构。即核心区I的中央区I-1中的每个接触插塞上接一个电容结构(如图12中705a所示)，核心区I的边界处I-2中的一个组合接触结构上接一个电容结构(如图12中705b所示)，且所述边界处I-2的电容结构具有第一宽度W1，所述核心区I的所述边界处I-2(即中央区I-1)以内的电容结构具有第二宽度W2，由于核心区I的边界处I-2形成的顶部横截面积较大的组合接触结构的存在，因此，可以为边界处的电容结构的形成工艺提供足够的工艺余量，以有利于增大该边界处I-2的电容结构的第一宽度W1，使得所述第一宽度W1大于所述第二宽度W2，进而，一方面，避免该边界处形成的电容结构坍塌；另一方面，使得该边界处的电容结构与其下的所述组合接触结构之间能具有较大的接触面积，一减小接触阻抗，有利于提高器件的电学性能；更重要的是，该边界处的所述电容结构的尺寸增大，能够缓冲核心区I和周边区II之间的电路图案的密度差异，从而在执行光刻工艺和/或蚀刻工艺时能够改善光学邻近效应，减小稀疏/密集负载效应，保证核心区I边界处I-2以内的区域(即中央区I-1)的接触插塞106a上方的电容结构的一致性，防止出现核心区I内一些位置的接触插塞上方的电容结构出现异常或边界处I-2的 接触插塞上方的电容结构出现坍塌的问题。可选地，所述第一宽度W1大于1.5倍的所述第二宽度W2。
图2A～图2D是示出本发明另一实施例的半导体器件的电接触结构的制造方法中的器件剖面示意图。请参考图2A～图2D，本实施例还提供一种半导体器件的电接触结构的制造方法，包括以下步骤：
首先，请参照图2A，提供一个半导体衬底100，其包含核心区I和周边区II。半导体衬底100中形成有多个浅沟槽隔离结构(未图示)，该浅沟槽隔离结构在二维平面上界定出了核心区I和周边区II的分界处(即界定出了核心区I的边界处I-2)，同时还界定出了核心区I中的各个核心元件所对应的有源区101以及周边区II中的外围元件所对应的有源区101。
接着，请继续参照图2A，在半导体衬底100上覆盖第一层间介质层102。另外，可以在半导体衬底100和第一层间介质层102之间形成蚀刻停止层(未图示)；通过第一次光刻工艺，在第一层间介质层102上形成第一掩模图案103，该第一掩模图案103定义出各个接触插塞的位置，然后，使用第一掩模图案103作为蚀刻掩模，各向异性地蚀刻第一层间介质层102，以形成贯穿所述第一层间介质层102且暴露出下方相应的有源区101的接触孔102a、102b和102c，每个接触孔102a位于在核心区I的中央区I-1中并暴露出中央区I-1中的相应核心元件的有源区101，每个接触孔102b位于核心区I的边界处I-2且暴露出边界处I-2中的相应核心元件的有源区101，每个接触孔102c位于周边区II中并暴露出相应外围元件的有源区101。
然后，请参考图2B，在形成接触孔102a～102c之后，可以执行灰化工艺或湿式清洗工艺，以去除第一掩模图案103，并填充TiN等材质的阻挡金属层(未图示)和钨等材质的金属层(未图示)于各个接触孔102a～102c中，并进一步采用化学机械抛光(CMP)工艺对沉积的金属层的顶面进行化学机械抛光，直至暴露出第一层间介质层102的顶面，以形成位于层间介质层102中的接触插塞106，核心区I中的各个所述接触插塞106的底部与相应的核心元件的有源区101接触。周边区II中的各个所述接触插塞106的底部与相应的外围元件的有源区101接触。
接着，请参考图2C，可以在第一层间介质层102和接触插塞106上形成第二层间介质层107和第二掩模图案108，第二掩模图案108通过第二次光刻工艺形成，定义出用于将边界处I-2相应的至少两个接触插塞106的顶部相连的沟槽。以第二掩模图案108为掩模，刻蚀第二层间介质层107，以形成暴露出相应的接触插塞106的顶部的沟槽，其中边界处I-2相应的沟槽108b将至少两个接触插塞106及其之间的间隔的顶部暴露出来，核心区I的边界处I-2以内(即中央区I-1)的沟槽108a暴露出相应的接触插塞106的顶部，周边区II中的沟槽108c暴露出相应的接触插塞106的顶部。沟槽108b至少暴露出边界处I-2最外侧的一个接触插塞106的顶部。
请参考图2D，可以使用氧、臭氧或紫外线的灰化工艺或者通过湿式清洗工艺去除第二掩模图案105，并在沟槽108a～108c中依次形成阻挡金属层(未图示)和金属层(未图示)。阻挡金属层能够减少或防止设置在接触孔和沟槽中的金属材料扩散到层间介质层102中。然后，在各个接触孔沟槽108a～108c填充金属层，以形成相互独立的接触垫109a、109b、109c。接触垫109a形成在所述核心区I的中央区I-1的接触插塞106的顶部，并一一对应地与相应的接触插塞106的顶部电接触，接触垫109b形成在所述核心区I的边界处I-2的接触插塞106的顶部，并一一对应地与相应的接触插塞106的顶部电接触，以使得边界处I-2中所述顶部相联一起的所有接触插塞106构成倒U形电接触结构或者梳状电接触结构。
图2A～图2D所示的方法，能够在相同的光刻次数下，将每个接触插塞(包括顶部相联在一起的接触插塞和独立的接触插塞)均分两段高度来制作，由此可以降低每段高度对应的刻蚀工艺和填充工艺所对应的接触孔或沟槽的深宽比，保证形成的电接触结构的性能。
请参考图1D和图2D，本发明一实施例还提供一种半导体器件，包括半导体衬底100，所述半导体衬底100具有核心区I，所述核心区I中形成有多个核心元件；层间介质层102，覆盖在所述半导体衬底100上；以及，如本发明各实施例所述的半导体器件的电接触结构，所述电接触结构形成于所述层间介质层102中，所述电接触结构的各个所述接触插塞的底部与相应的核心 元件的有源区101接触，且所述电接触结构中形成在所述核心区的边界处I-2的至少两个接触插塞的顶部相联在一起。
请结合图2D和图12,所述半导体器件还包括电容结构，形成于所述层间介质层107上且底部与所述电接触结构相接触，所述边界处I-2的电容结构(如图12中的705b所示)具有第一宽度W1，所述核心区I的所述边界处I-2以内(即中央区I-1)的电容结构(如图12中的705a所示)具有第二宽度W2，所述第一宽度W1大于所述第二宽度W2。
需要说明的是，本发明的技术方案并不仅仅限定于上述的电接触结构的形成方法，能够用于形成独立的接触插塞和顶部相联在一起的接触插塞的方法均可以适用于本发明的技术方案，例如在本发明的又一示例中，在形成图1A的结构并去除掩膜图案103之后，不再填充牺牲层，而是直接填充接触插塞的材料(包括阻挡金属层和金属层)，来形成独立的接触插塞，然后在层间介质层102和独立的接触插塞上形成图1B中的掩膜图案105，并进一步刻蚀层间介质层102，以形成暴露出边界处I-2处的至少两个接触插塞102b的顶部侧壁的沟槽102d，之后在沟槽102d中填充导电材料，以形成接触垫(未图示)，该接触垫将沟槽102d暴露出的接触插塞102b的顶部相联在一起。
在下文中，将参照图3至图12来详细描述本发明一实施例的半导体器件及其制造方法。其中图3是本发明一实施例的半导体器件的制造方法中的器件结构俯视示意图；图4～图12是本发明一实施例的半导体器件的制造方法中沿图3中的aa’线的器件结构剖面示意图。
首先，请参考图3和图4，提供具有多个核心元件(即存储晶体管)的半导体衬底300，具体过程包括：
首先，请参考图3和图4，提供一个半导体基底300a，其包含核心区I和周边区II。本实施例中，核心区I为存储区，核心区I上待形成的核心元件包括选择元件，后续在核心元件上方接数据存储元件，选择元件例如是MOS晶体管或二极管，数据存储元件例如是电容器、可变电阻器等，一个选择元件和相应的数据存储元件组成存储单元。周边区II中可形成外围电路TR(例如，NMOS晶体管和PMOS晶体管、二极管或电阻器)来控制存储单元。半 导体基底300a中形成有多个浅沟槽隔离结构301，该浅沟槽隔离结构301在二维平面上界定出了核心区I和周边区II的分界处(即界定出了核心区I的边界处I-2)，同时还界定出了核心区I中的各个核心元件所对应的有源区AA1以及周边区II中的外围元件所对应的有源区AA2。其中有源区AA1在二维平面上的分布呈现条形且均沿第一方向延伸，且有源区AA1在半导体基底300a的面上可呈现错位的排列设置。
然后，在半导体基底300a中形成埋入式字线WL，埋入式字线WL一般埋设在半导体基底300a中一预定深度位置，沿第二方向(即行方向)延伸并穿过浅沟槽隔离结构301以及有源区AA1，在此，第二方向与有源区AA1的第一方向相交但不垂直。埋入式字线WL作为栅极来控制存储单元的开关，其包含但不限定为掺杂性的半导体材料(如掺杂硅)、金属材(如钨、铝、钛、或钽)、导电性金属化合物(如氮化钛、氮化钽、或氮化钨)、或是半导体化合物(如氮化硅)等。通常埋入式字线WL的侧壁和底部被栅介质层(未图示)包围，埋入式字线WL的顶部被栅极盖层302掩埋在内。由于埋入式字线WL并非本发明的重点，其相关制作工艺可以参考本领域的已知技术方案，在此不再详述。此外，栅介质层可包括氧化硅或其他适合的介电材料，埋入式字线WL可包括铝、钨、铜、钛铝合金、多晶硅或其他适合的导电材料，而栅极盖层302可包括氮化硅、氮氧化硅、氮碳化硅或其他适合的绝缘材料。
再者，在埋入式字线WL两旁的有源区AA1中可掺入第二类型的掺质，如P类型或N类型的掺质，来形成源区和漏区(统一定义为S/D1)，埋入式字线WL两旁的AA1中的一者位于AA1中心处对应预定的位线接触结构的位置，另一者位于有源区AA1末端预定的存储节点接触结构的位置。字线WL和S/D1可以构成或限定形成在半导体器件的核心区I上的多个MOS存储晶体管。此外，在形成S/D1的同时，也可以一并在周边区II中形成外围晶体管对应的源区和漏区(统一定义为S/D2)。在形成所述S/D1和S/D2之后，还可进一步形成刻蚀停止层303在所述半导体基底300a上，所述刻蚀停止层303覆盖所述S/D1和S/D2，其材料例如包括氮化硅(SiN)和/或氧化硅(SiO 2)等。
然后，在核心区I的用作漏区的S/D1上形成多个位线接触插塞(bit line contact，未图示)以及位于所述位线接触插塞上方的位线BL，位线接触插塞可以通过如下方法形成：先刻蚀一个有源区AA1中形成的相邻两条WL之间的S/D1来形成凹槽，之后在凹槽中形成金属硅化物。多条位线BL相互平行且沿着垂直于埋入式字线WL的第三方向(即列方向)延伸，并同时横跨该有源区AA1与埋入式字线WL。各位线BL例如包含依序堆叠的一半导体层(例如多晶硅，未图示)、一阻障层(例如包括Ti或TiN等，未图示)、一金属层(例如钨、铝或铜等，未图示)与一掩模层(例如包含氧化硅、氮化硅或碳氮化硅，未图示)。
此外，在半导体基底300a的周边区II上，则形成有至少一栅极结构G1，其例如包含依序堆叠的一栅极介电层(未图示)和一栅极层(未图示)。在一具体示例中，栅极结构G1的栅极层与位线BL的半导体层或金属层是一并形成的。进一步地，可采用不同工艺或同道工艺形成分别环绕各位线BL与栅极结构G1的侧墙304。举例来说，可先进行栅极结构G1的侧墙的制作工艺，使栅极结构G1的侧墙304包含氧化硅或氮氧化硅(SiON)，再进行位线BL的侧墙的制作工艺，而使位线BL的侧墙可包含氮化硅。此外，在栅极结构G1的侧墙的制作工艺中，可再进行一回蚀刻(etching back)制作工艺，使栅极结构G1的整体高度低于各位线BL。
然后，可以采用本发明的图1A～1D或图2A～图2D所示的半导体器件的电接触结构的制作方法来形成存储节点接触结构，下面以采用图1A～1D所示的半导体器件的电接触结构的制作方法来形成存储节点接触结构为例，具体过程如下：
首先，请参考图5，在提供具有位线BL、核心元件的源区和漏区S/D1的半导体衬底300a之后，在半导体衬底300a上形成一层间介质层400，其材质例如包括氧化硅、氮化硅或低K介质等。具体地，先通过沉积工艺全面地在半导体衬底300a上覆盖层间介质层400，并使得层间介质层400填满各位线BL之间的空间并将各位线BL与栅极结构G1及其侧墙304掩埋在内，然后通过化学机械研磨等工艺对层间介质层400进行平坦化，形成整体上具有 平坦的顶表面的层间介质层400。其中，平坦化后的层间介质层400的顶表面至少不低于各位线BL的顶表面。
接着，请继续参照图5，通过光刻工艺，在层间介质层400上形成第一掩模图案(未图示)，该第一掩模图案定义出各个存储节点接触结构的位置，然后，使用第一掩模图案作为蚀刻掩模，各向异性地蚀刻层间介质层400，以形成贯穿所述层间介质层400且暴露出下方相应的用作源区的S/D1、S/D2或栅极结构G1的接触孔401a、401b和401d、401e，每个接触孔401a位于在核心区I的中央区I-1中并暴露出中央区I-1中的相应核心元件的用作源区的S/D1，每个接触孔401b位于核心区I的边界处I-2且暴露出边界处I-2中的相应核心元件的用作源区的S/D1，每个接触孔401d、401e位于周边区II中并暴露出相应外围元件的源区/漏区S/D2或栅极结构G1。
然后，请参考图6，在形成接触孔401a、401b和401d、401e之后，可以执行灰化工艺或湿式清洗工艺，以去除第一掩模图案，并填充牺牲层501于各个接触孔401a、401b和401d、401e中。所述牺牲层501可以由旋涂硬掩模(SOH)层或非晶碳层(ACL)形成，这样可以使得能够用牺牲层501填充具有高的高宽比的接触孔401a、401b和401d、401e。
接着，请继续参考图5和6，可以在层间介质层400和牺牲层501上形成第二掩模图案(未图示)，第二掩模图案定义出用于将边界处I-2相应的至少两个接触孔401b的顶部相连的沟槽401c。以第二掩模图案为掩模，刻蚀边界处I-2处的层间介质层400，以形成将边界处I-2相应的至少两个接触孔401b(包括最靠近周边区II的一列接触孔中的至少一个)的顶部相连的沟槽401c。沟槽401c至少跨过边界处I-2最外侧的一条字线WL。
然后，请参考图7，可以使用氧、臭氧或紫外线的灰化工艺或者通过湿式清洗工艺去除接触孔401a、401b和401d、401e中的牺牲层501以及第二掩模图案，以重新暴露出各个接触孔401a、401b和401d、401e和沟槽401c。
接着，请参考图8，可以在接触孔401a、401b和401d、401e和沟槽401c中形成阻挡金属层(未图示)，例如，阻挡金属层可以以均匀的厚度覆盖接触孔401a、401b和401d、401e和沟槽401c的内壁与层间介质层400的顶表 面。阻挡金属层能够减少或防止设置在接触孔401a、401b和401d、401e和沟槽401c中的金属材料扩散到层间介质层400中。例如，所述阻挡金属层可以由Ta、TaN、TaSiN、Ti、Ti N、TiSiN、W、WN或它们的任何组合形成，可以使用化学气相沉积(CVD)、原子层沉积(ALD)或物理气相沉积(PVD)(例如，溅射)等工艺形成。然后，在各个接触孔401a、401b和401d、401e和沟槽401c中填充金属层，以形成接触插塞501a、501d、501e和组合接触结构501b。其中，金属层可以由(一种或多种)难熔金属(例如，钴、铁、镍、钨和/或钼)形成。另外，可以使用具有良好阶梯覆盖性质的沉积工艺形成金属层，例如，使用化学气相沉积(CVD)、原子层沉积(ALD)或物理气相沉积(PVD)(例如，溅射)形成。形成的金属层还覆盖在接触孔和沟槽周围的层间介质层400的表面上，之后，可以采用化学机械抛光(CMP)工艺对沉积的金属层的顶面进行化学机械抛光，直至暴露出层间介质层400的顶面，以形成位于层间介质层400中的接触插塞501a、501d、501e和组合接触结构501b。接触插塞501a作为核心区I的中央区I-1中的存储节点接触结构，用于与后续在中央区I-1上方形成的电容结构连接。组合接触结构501b由核心区I的边界处I-2中的至少两个顶部相连的接触插塞(包括与边界处I-2的最外侧的源区电接触的边界处最外侧的接触插塞)形成，作为核心区I的边界处I-2中的存储节点接触结构，用于与后续在边界处I-2上方形成的电容结构连接，组合接触结构501b的顶部结构(即顶部相联一起的所有接触插塞形成的顶部连接结构)位于位线BL上方并横跨过至少一条字线WL，组合接触结构501b与位线BL对准平行。组合接触结构501b例如为倒U形电接触结构或者梳状电接触结构，其最少可以跨过边界处I-2最外侧的一个有源区AA1中的一条所述字线WL。接触插塞501d作为周边区II的栅极结构G1的接触结构，用于将栅极结构G1向外引出，接触插塞501e作为周边区II的源区或漏区S/D2的接触结构，用于将周边区II的源区或漏区S/D2向外引出。
之后，可以采用本领域常规的电容结构的制作方法在核心区I上制作相应的电容结构，请参考图9～12，具体过程如下：
首先，请参考图9，可以通过化学气相沉积、旋涂等工艺在所述层间介质 层400和接触插塞501a、501d、501e及组合接触结构501b的表面上依次形成底层支撑层600、第一牺牲层611、中间支撑层601、第二牺牲层612以及顶层支撑层602，其中底层支撑层600一方面用于对后续形成的下电极层进行底部支撑，另一方面还用于隔离半导体衬底300的内部元件与上方的电容器等元件。底层支撑层600的形成工艺还可以是热氧化工艺。所述底层支撑层600、中间支撑层601和顶层支撑层602的材质包含但不限于氮化硅，第一牺牲层611、第二牺牲层612的材质包含但不限于氧化硅。所述第一牺牲层611的厚度界定出后续所形成的中间支撑层601的高度，因此，所述第一牺牲层611的厚度可根据所需形成的中间支撑层601的高度位置进行调整。在所述第一牺牲层611与中间支撑层601的厚度确定的情况下，所述第二牺牲层612的厚度界定出后续所形成的顶层支撑层602的高度，因此，所述第二牺牲层612的厚度可根据所需形成的顶层支撑层602的高度位置进行调整。在本发明的其他实施例中，为了对下电极层进行更好的支撑，底层支撑层600和顶层支撑层602之间还可以层叠两层以上的中间支撑层601，相邻中间支撑层之间有牺牲层进行隔离。
接着，请参考图10所示，形成多个电容孔700a和700b在所述核心区I上的牺牲层与所述支撑层内，电容孔700a形成在核心区I的中央区I-1中且暴露出所述中央区I-1中接触插塞501a的表面，用于形成中央区I-1中的电容结构。电容孔700b形成在核心区I的边界处I-2且暴露出所述边界处I-2的组合接触结构501b的表面，用于形成边界处I-2中的电容结构。电容孔700a和700b呈阵列排布，且电容孔700b具有第一宽度W1，电容孔700a具有第二宽度W2，可选地，W1不小于1.5*W2。具体的，在所述顶层支撑层602上形成一掩模层(未图示)，对所述掩模层进行图形化，暴露出预定形成电容孔700a和700b的区域，然后以图形化的掩模层为掩模，依次对所述顶层支撑层602、第二牺牲层612、中间支撑层601、第一牺牲层611以及底层支撑层600进行刻蚀，以去除所述周边区II及核心区I边缘区域上的所述支撑层及牺牲层，并在核心区I中形成多个电容孔700a和700b，然后去除所述图形化的掩模层。所述电容孔700a和700b依次贯穿所述顶层支撑层602、第二牺牲层612、中 间支撑层601、第一牺牲层611以及底层支撑层600，以暴露出所述核心区I的相应的接触插塞501a和组合接触结构501b的表面，可选的，所有的电容孔呈六方密堆积排布。此外，电容孔可以是倒梯形孔、矩形孔等，其侧壁可以是不规则形貌，如具有曲线侧壁等，在此不做具体限制。此外，本实施例中，周边区II上还保留有所述底层支撑层600，以用于在后续电容器形成工艺中保护周边区II的器件表面。
可以理解的是，由于组合接触结构501b的面积较大，因此可以为边界处I-2的电容孔700b的制作提供足够的工艺余量，且使得边界处I-2的电容孔700b的宽度较大，避免该边界处的电容孔700b发生异常变形或坍塌，同时使得后续在该边界处形成的电容结构和所述组合接触结构具有较大的接触面积，进而降低接触阻抗，有利于提高器件的电学性能。此外，因为边界处I-2的电容孔700b的宽度较大，能够缓冲周边区II和核心区I中的电路图案的密度差异，从而在执行电容孔的光刻工艺和/或蚀刻工艺时能够改善光学邻近效应，减小稀疏/密集负载效应，保证核心区边界以内的电容孔的一致性，防止出现核心区内一些位置的接触插塞上方的电容孔出现异常而引起后续形成的电容结构失效的问题。
请参考图11所示，形成一下电极层701覆盖于所述电容孔700a、700b的侧壁和底壁上。所述下电极层701位于所述电容孔700a、700b中的部分，其形貌与所述电容孔700a、700b的形貌一致，从而使得位于所述电容孔700a、700b中的所述下电极层701构成一筒状结构。具体的，所述下电极层701可在沉积工艺的基础上结合平坦化工艺形成，例如，首先，可以采用光刻胶等图形化保护层(未图示)将周边区II保护起来，并暴露出核心区I中的顶层支撑层602的顶表面以及电容孔700a、700b的表面；接着，采用物理气相沉积或化学气相沉积等工艺形成一电极材料层于所述图形化保护层以及核心区I的暴露表面上，所述电极材料层覆盖所述电容孔700a、700b的底部和侧壁，以及覆盖所述核心区I的顶层支撑层602和周边区II的图形化保护层顶表面；接着，执行平坦化工艺(例如，化学机械研磨工艺CMP)，去除电极材料层中位于所述顶层支撑层602上方的部分，从而使剩余的电极材料层仅形成在所 述电容孔700a、700b中，以构成具有多个筒状结构的下电极层701，之后去除所述图形化保护层。此外，在本实施例中，所述接触插塞501a、501b分别通过所述电容孔700a、700b暴露出来，从而使得所形成的下电极层701的筒状结构的底部能够与所述接触插塞501a、501b电性接触。进一步的，所述下电极层701可以是多晶硅电极或金属电极。当下电极层701为金属电极时，还可以采用氮化钛(TiN)和Ti层叠结构。当下电极层701为多晶硅电极时，可以采用零掺杂和/或掺杂的多晶硅材料形成。
请继续参考图11所示，去除各个所述的牺牲层并保留各个所述的支撑层，所有的所述支撑层组成横向支撑层，以横向连接所述下电极层701的多个筒状结构的外壁，以在各个所述筒状结构的侧壁上对下电极层701进行支撑。具体的，所述顶层支撑层602位于所述下电极层701的多个筒状结构的顶部外围，所述中间支撑层601位于所述下电极层701的多个筒状结构的中间部位，底层支撑层600位于所述下电极层701的多个筒状结构的底部外围。其中，具体过程包括：形成第一开口(未图示)于所述顶层支撑层602并暴露出所述第二牺牲层612；可以采用湿法刻蚀工艺刻蚀去除所述第二牺牲层612；形成第二开口于所述中间支撑层601中以暴露出所述第一牺牲层611；采用湿法刻蚀工艺刻蚀去除所述第一牺牲层611；其中，一个所述第一开口仅与一个所述电容孔700a或700b交叠，或者一个所述第一开口同时与多个所述电容孔700a和/或700b交叠；一个所述第二开口仅与一个所述电容孔700a或700b交叠，或者一个所述第二开口同时与多个所述电容孔700a和/或700b交叠。此外，所述第二开口可以与所述第一开口完全对齐。
请参考图12所示，采用化学气相沉积工艺或原子层沉积工艺等形成一电容介质层702于所述下电极层701的内外表面以及各个所述支撑层暴露出的表面；接着，形成一上电极层703于所述电容介质层702的内表面和外表面。其中，所述电容介质层702覆盖所述下电极层701的筒状结构的内表面和外表面，以充分利用下电极层701的两个相对表面，构成具有较大电极表面积的电容器。优选的，所述电容介质层702可以为金属氧化物等高K介质层。进一步的，所述电容介质层702为多层结构，例如为氧化铪-氧化锆的两层结 构。所述上电极层703可以为单层结构也可以为多层结构，当所述上电极层703为单层结构时，例如为多晶硅电极，也可以为金属电极，当上电极层703为金属电极时，例如可以采用氮化钛(TiN)形成。所述上电极层703在对应所述筒状结构的内部和所述筒状结构的外部均能够与所述电容介质层702以及所述下电极层701构成电容器。此外，在核心区I边缘区域(即电容孔阵列的边界区域)上，由于横向支撑层(即中间支撑层601、顶层支撑层602)的存在，所述电容介质层702和所述上电极层703均具有凹凸不平形貌的侧壁结构，所述凹凸不平形貌的侧壁结构对应于在所述下电极层701的筒状结构筒外部的所述中间支撑层601、顶层支撑层602，由此使得所述上电极层703在所述核心区I边缘区域(即电容孔阵列的边界区域)上的部分，对应所述中间支撑层601、顶层支撑层602以远离所述下电极层701的方向凸出，使核心区I中的电容器阵列边界不平整。此外，本实施例中，所述电容介质层702和所述上电极层703还依次延伸覆盖在所述周边区II上保留的底层支撑层600的表面上。
请参考图12所示，可以先采用化学气相沉积工艺在所述上电极层703表面形成一上电极填充层704，所述上电极填充层704填满所述上电极层703之间的间隙，也就是说，所述上电极填充层704填充满相邻的筒状结构之间的间隙并覆盖上述形成的结构。优选的，所述上电极填充层704的材质包括未掺杂或者硼掺杂的多晶硅。由此完成了电容器阵列的制作，即在中央区I-1形成了电容结构705a，在边界处I-2形成电容结构705b。
由于电容孔700b的宽度大于电容孔700a的宽度，因此在边界处I-2的所述电容结构705b的宽度(即W1)大于中央区I-1的电容结构705a的宽度(即W2)，例如W1＝W2*1.5。且由于电容孔700b的尺寸较大，有利于材料填充，进而改善了在边界处I-2形成的所述电容结构的性能。
接着，请参考图13，本发明一实施例提供一种半导体器件的接触垫版图，所述接触垫版图包括主版图区10和第一边缘版图区11。其中，所述主版图区10中设有多个主接触垫图案131，各个所述主接触垫图案131的形状和尺寸相似，且所有的主接触垫图案131呈棋盘状交错排布，相邻两行所述主接触 垫图案131彼此之间具有第四间距D4，相邻两列主接触垫图案131彼此之间具有第五间距D5，D4可以等于D5，D4也可以不等于D5。第一边缘版图区11分布在所述主版图区10的一边外侧，所述第一边缘版图区11中设有多个沿所述主版图区10的所述一边的延伸方向排列为两行的第一边缘接触垫图案，即本实施例中，所述第一边缘版图区11中设有一行第一边缘接触垫图案111和一行第一边缘接触垫图案112,两行第一边缘接触垫图案111、112之间具有第六间距D6。一行第一边缘接触垫图案112相对靠近所述主版图区10且该行中的各个第一边缘接触垫图案112的形状和尺寸可以均相同，也可以不完全相同，一行第一边缘接触垫图案111相对远离所述主版图区10，且该行中的各个第一边缘接触垫图案111的形状和尺寸可以均相同，也可以不完全相同。各个所述第一边缘接触垫图案111、112与所述主版图区10中相应的主接触垫图案131对准排布(例如按列对准排布)，最靠近所述主版图区10的一行第一边缘接触垫图案112与其最近邻的一行主接触垫图案131之间的间距为所述第一边缘间距D1(即所述第一边缘版图区11与所述主版图区10之间具有第一边缘间距D1)。每个所述第一边缘接触垫图案111、112的面积均大于每个所述主接触垫图案131的面积，所述第一边缘接触垫图案111、112均不同于所述主接触垫图案131(例如各个第一边缘接触垫图案111、112的面积均大于所述主接触垫图案131的面积)，所述第一边缘间距D1不同于所述第四间距D4，所述第六间距D6不同于所述第四间距D4和第一边缘间距D1，例如D6大于D1，D1大于D4。
可选地，请继续参考图13，本实施例的所述接触垫版图还包括第二边缘版图区12，所述第二边缘版图区12分布在所述主版图区10的所述一边的邻边外侧，所述第二边缘版图区12中设有多个第二边缘接触垫图案121和/或122，且每个所述第二边缘接触垫图案121、122不同于所述主接触垫图案131，且每个所述第二边缘接触垫图案121、122的面积大于每个所述主接触垫图案131的面积。所述第二边缘版图区12和所述主版图区10之间具有第二边缘间距D2，所述第二边缘间距D2不同于所述第四间距D4，也不同于第五间距D5，还可以不同于所述第一边缘间距D1。此外，所述第二边缘版图区12中 的各个所述第二边缘接触垫图案121、122与所述主版图区10中相应的主接触垫图案131以及第一边缘接触垫图案111、112对准排布，例如所述第二边缘版图区12中的所有所述第二边缘接触垫图案121、122进一步沿所述邻边的延伸方向排列为两列，靠近主版图区10的一列为第二边缘接触垫图案121，远离主版图区10的一列为第二边缘接触垫图案122，每列中的第二边缘接触垫图案121、122可以不完全相同。且与所述主版图区10最近邻的一列所述第二边缘接触垫图案121与其最近邻的一列主接触垫图案131之间的间距为所述第二边缘间距D2，两列所述第二边缘接触垫图案121、122之间具有第三间距D3，所述第三间距D3大于所述第二边缘间距D2，也大于第五间距D5。可选地，所述第二边缘版图区12中，远离所述主版图区10的一列中的第二边缘接触垫图案122的形状包括长条形、向左放倒的U形、向右放倒的U形、向左放倒的L形、向右放倒的L形以及具有至少两个梳齿的梳子形中的至少两种。
请参考图14，本发明另一实施例提供一种半导体器件的接触垫版图，所述接触垫版图包括主版图区10、第一边缘版图区11和第二边缘版图区12。其中，所述主版图区10中设有多个主接触垫图案131，各个所述主接触垫图案131的形状和尺寸相似，且所有的主接触垫图案131呈棋盘状交错排布，相邻两行所述主接触垫图案131彼此之间具有第四间距D4，相邻两列主接触垫图案131彼此之间具有第五间距D5，D4可以等于D5，D4也可以不等于D5。第一边缘版图区11分布在所述主版图区10的一边外侧，所述第一边缘版图区11中设有一个具有锯齿状边缘的长条，以作为所述第一边缘接触垫图案111。可选地，所述锯齿状边缘面向所述主版图区10，所述锯齿状边缘中的各个锯齿111a与所述主版图区10中相应的主接触垫图案131对准排布(例如各个锯齿111a和相应的主接触垫图案131按列对准排布)，所述锯齿111a与对准的最近邻的主接触垫图案131之间的间距为所述第一边缘间距D1。即本实施例中，所述第一边缘版图区11中仅设有一行第一边缘接触垫图案111，该行第一边缘接触垫图案111连为一体。各个锯齿的形状和尺寸可以均相同，也可以不完全相同，锯齿111a的间距不完全相同。每个所述锯齿的面积可以 小于、等于或大于每个所述主接触垫图案131的面积，所述第一边缘间距D1不同于所述第四间距D4。所述第二边缘版图区12分布在所述主版图区10的所述一边的邻边外侧，所述第二边缘版图区12中设有多个第二边缘接触垫图案121和/或122，且每个所述第二边缘接触垫图案121、122不同于所述主接触垫图案131，且每个所述第二边缘接触垫图案121、122的面积大于每个所述主接触垫图案131的面积。所述第二边缘版图区12和所述主版图区10之间具有第二边缘间距D2，所述第二边缘间距D2不同于所述第四间距D4，也不同于第五间距D5，还可以不同于所述第一边缘间距D1。此外，所述第二边缘版图区12中的相应的所述第二边缘接触垫图案121、122与所述主版图区10中相应的主接触垫图案131对准排布，其余的第二边缘接触垫图案121、122与第一边缘接触垫图案111对准排布，例如所述第二边缘版图区12中相应的所述第二边缘接触垫图案121、122进一步沿所述邻边的延伸方向排列为两列，靠近主版图区10的一列为第二边缘接触垫图案121，远离主版图区10的一列为第二边缘接触垫图案122，每列中的第二边缘接触垫图案121、122可以不完全相同。且与所述主版图区10最近邻的一列所述第二边缘接触垫图案121与其最近邻的一列主接触垫图案131之间的间距为所述第二边缘间距D2，两列所述第二边缘接触垫图案121、122之间具有第三间距D3，所述第三间距D3大于所述第二边缘间距D2，也大于第五间距D5。本实施例中，所述第二边缘接触垫图案121为横长条结构，且其长度沿主版图区10的行方向延伸，所述第二边缘接触垫图案122为竖长条结构，且其长度沿主版图区10的列方向延伸。
请参考图15，本发明又一实施例提供一种半导体器件的接触垫版图，所述接触垫版图包括主版图区10、第一边缘版图区11和第二边缘版图区12。本实施例中的主版图区10中的结构可以与图13或图14所示的实施例中的版图区10的结构相同，在此不再赘述。第一边缘版图区11分布在所述主版图区10的一边外侧，所述第一边缘版图区11中设有两行结构，靠近主版图区10的一行设有多个第一边缘接触垫图案112，远离主版图区10的一行设有一个具有锯齿状边缘的长条，以作为所述第一边缘接触垫图案111，可选地，所 述锯齿状边缘面向所述主版图区10，所述锯齿状边缘中的各个锯齿111a以及相应的第一边缘接触垫图案112均与所述主版图区10中相应的主接触垫图案131对准排布(例如各个锯齿111a、第一边缘接触垫图案112和相应的主接触垫图案131按列对准排布)，所述第一边缘接触垫图案112与对准的最近邻的主接触垫图案131之间的间距为第一边缘间距D1(即一行第一边缘接触垫图案112与其最近邻的一行主接触垫图案131之间的行间距为第一边缘间距D1)，一行第一边缘接触垫图案112与一行具有锯齿状边缘的第一边缘接触垫图案111之间的行间距为第六间距D6。其中，第一边缘接触垫图案111连为一体，其各个锯齿111a的形状和尺寸可以均相同，也可以不完全相同，锯齿111a的间距可以不完全相同，也可以相同。每个所述锯齿111a的面积可以小于、等于或大于每个所述主接触垫图案131的面积，所述第一边缘间距D1不同于所述第四间距D4，所述第六间距D6不同于所述第一边缘间距D1。所述第二边缘版图区12分布在所述主版图区10的所述一边的邻边外侧，所述第二边缘版图区12中设有多个第二边缘接触垫图案121和/或122，且每个所述第二边缘接触垫图案121、122不同于所述主接触垫图案131，且每个所述第二边缘接触垫图案121、122的面积大于每个所述主接触垫图案131的面积。所述第二边缘版图区12和所述主版图区10之间具有第二边缘间距D2，所述第二边缘间距D2不同于所述第四间距D4，也不同于第五间距D5，还可以不同于所述第一边缘间距D1。此外，所述第二边缘版图区12中的相应的所述第二边缘接触垫图案121、122与所述主版图区10中相应的主接触垫图案131对准排布，其余的第二边缘接触垫图案121、122与第一边缘接触垫图案111对准排布，例如所述第二边缘版图区12中相应的所述第二边缘接触垫图案121、122进一步沿所述邻边的方向排列为两列，靠近主版图区10的一列为第二边缘接触垫图案121，远离主版图区10的一列为第二边缘接触垫图案122，每列中的第二边缘接触垫图案121、122可以不完全相同。且与所述主版图区10最近邻的一列所述第二边缘接触垫图案121与其最近邻的一列主接触垫图案131之间的间距为所述第二边缘间距D2，两列所述第二边缘接触垫图案121、122之间具有第三间距D3(在此为两列所述第二边缘接触垫图案121、 122之间最小的间隔为所述第三间距D3)，所述第三间距D3大于所述第二边缘间距D2，也大于第五间距D5。本实施例中，所述第二边缘接触垫图案121均为横长条结构，且其长度沿主版图区10的行方向延伸，所述第二边缘接触垫图案122的形状包括长条形、向左放倒的U形、向右放倒的U形、向左放倒的L形、向右放倒的L形以及具有至少两个梳齿的梳子形中的至少两种。
本发明的各实施例的半导体器件的接触垫版图中，主版图区对应于半导体器件的核心区的有效区域或者半导体器件的核心区的全部区域，且各个主接触垫图案用于制作半导体器件的核心区中的主接触垫，第一边缘版图区和第二边缘版图区分别对应于所述核心区的相应侧的边界处或者分别对应于半导体器件的核心区与相应侧的半导体器件的周边区之间的交界区，第一边缘接触垫图案和第二边缘接触垫图案均用于制作半导体器件的核心区相应侧的边界处或所述交界区中的虚拟接触垫。由于第一边缘版图区中每个所述第一边缘接触垫图案的面积大于每个所述主接触垫图案的面积，第二边缘版图区中每个所述第二边缘接触垫图案的面积大于每个所述主接触垫图案的面积，因此，基于本发明的各实施例的接触垫版图而形成核心区的主接触垫时，可以利用第一边缘接触垫图案和第二边缘接触垫图案形成相应的虚拟接触垫，且形成的虚拟接触垫的顶面面积大于形成的主接触垫的顶面面积，由此，能够增大后续在虚拟接触垫上上接的电学结构的尺寸，在主接触垫和虚拟接触垫上上接电学结构时能够改善核心区与周边区之间的电路图案的密集/稀疏效应，从而提高核心区内部的主接触垫上接的电学结构的一致性，同时还能避免核心区边界处的主接触垫上接的电学结构异常的问题，提高了最终形成的半导体器件的性能。
请参考图13～图15以及图16A，基于同一发明构思，本发明一实施例还提供一种利用图13～图15中任一项所示的半导体器件的接触垫版图形成的接触垫结构，所述接触垫结构包括：多个主接触垫131a以及至少一个第一边缘接触垫111b。各个主接触垫131a均是基于主版图区10中的相应的主接触垫图案131制作而成，并位于半导体器件的核心区I中且呈棋盘状交错排布，各个所述主接触垫131a的形状和尺寸相似，且所述主接触垫131a彼此之间具有 第四间距D4，各个主接触垫131a用于上接电容结构(如图24中的705a)等有效的电学结构。各个第一边缘接触垫111b基于第一边缘接触垫图案111或者基于第一边缘接触垫图案111和112制作而成，分布在所有的主接触垫排布区域的一边外侧，且每个所述第一边缘接触垫111b的顶面面积大于每个所述主接触垫的顶面面积(进一步地，每个所述第一边缘接触垫111b的横截面面积大于每个所述主接触垫的横截面面积)，紧挨所述主接触垫131a的所述第一边缘接触垫111b(基于第一边缘接触垫图案111制作而成)与所述主接触垫131a之间具有第一边缘间距D1。其中，所述第一边缘接触垫111b的尺寸不同于所述主接触垫131a的尺寸，所述第一边缘间距D1不同于所述第四间距D4。本实施例中，各个所述第一边缘接触垫111b分布在核心区I的边界处，且将核心区I边界处的至少最外侧的两个源漏区S/D1电连接在一起(例如图24中所示，各个第一边缘接触垫511b横跨在核心区I边界处的字线及其两侧的两个源漏区S/D1上)。第一边缘接触垫111b可以用作虚拟接触垫。由于每个所述第一边缘接触垫111b的顶面面积均大于每个所述主接触垫131a的顶面面积，因此，能够使得后续在第一边缘接触垫111b上上接的电学结构的尺寸相对主接触垫131a上上接的电学结构的尺寸增大(如图24中所示的电容结构705b的尺寸大于电容结构705a)，以降低第一边缘接触垫111b与其上接的电学结构之间的接触电阻，增强器件可靠性，更重要的是，在主接触垫131a和第一边缘接触垫111b上分别上接相应的电学结构时，能够利用第一边缘接触垫111b上接的电学结构的尺寸相对增大，来改善核心区I与周边区II之间的电路图案的密集/稀疏效应，从而提高核心区I内部的所有主接触垫131a上接的电学结构之间的一致性，同时还能避免核心区I边界处的主接触垫101a(即紧挨各个第一边缘接触垫111b的各个主接触垫101a)上接的电学结构异常的问题，提高了最终形成的半导体器件的性能。
请参考图13～图15以及图16B，本发明的另一实施例还提供一种利用图13～图15中任一项所示的半导体器件的接触垫版图形成的接触垫结构，所述接触垫结构包括：多个主接触垫131a以及至少一个第一边缘接触垫111b。各个主接触垫131a均是基于主版图区10中的相应的主接触垫图案131制作而 成，并位于半导体器件的核心区I中且呈棋盘状交错排布，各个所述主接触垫131a的形状和尺寸相似，且所述主接触垫131a彼此之间具有第四间距D4，各个主接触垫131a用于上接电容结构(如图24中的705a)等有效的电学结构。各个第一边缘接触垫111b基于第一边缘接触垫图案111或者基于第一边缘接触垫图案111和112制作而成，分布在所有的主接触垫排布区域的一边外侧，且每个所述第一边缘接触垫111b的顶面面积大于每个所述主接触垫的顶面面积(进一步地，每个所述第一边缘接触垫111b的横截面面积大于每个所述主接触垫的横截面面积)，紧挨所述主接触垫131a的所述第一边缘接触垫111b(基于第一边缘接触垫图案111制作而成)与所述主接触垫131a之间具有第一边缘间距D1。其中，所述第一边缘接触垫111b的尺寸不同于所述主接触垫131a的尺寸，所述第一边缘间距D1不同于所述第四间距D4。本实施例中，各个所述第一边缘接触垫111b分布在核心区I与周边区II之间的交界区III上，且与核心区I边界处的至少一个源漏区S/D1电连接在一起(例如图25中所示，各个第一边缘接触垫511b从交界区III延伸到核心区I边界处最外侧一个源漏区S/D1上，将交界区III的浅沟槽隔离结构STI411a和紧挨浅沟槽隔离结构STI411a的源漏区S/D1连接在一起)。第一边缘接触垫111b可以做为虚拟接触垫。由于每个所述第一边缘接触垫111b的顶面面积均大于每个所述主接触垫131a的顶面面积，因此，能够使得后续在第一边缘接触垫111b上上接的电学结构的尺寸相对主接触垫131a上上接的电学结构的尺寸增大(如图24中所示的电容结构705b的尺寸大于电容结构705a)，由此在主接触垫131a和第一边缘接触垫111b上分别上接相应的电学结构时，能够利用第一边缘接触垫111b上接的电学结构的尺寸相对增大，来改善核心区I与周边区II之间的电路图案的密集/稀疏效应，从而提高核心区I内部的所有主接触垫131a上接的电学结构之间的一致性，同时还能避免核心区I边界处的主接触垫131a(即紧挨各个第一边缘接触垫111b的各个主接触垫131a)上接的电学结构异常的问题，提高了最终形成的半导体器件的性能。此外，需要说明的是，在本发明的其他实施例中，各个第一边缘接触垫111b也可以整体上全部位于交界区III上。各个第一边缘接触垫111b至少部分形成于交界区III上的 情况，一方面，可以尽量减小第一边缘接触垫111b及其上接的电学结构对核心区I的占用面积，有利于提高核心区的有效面积利用率，进而有利于提高器件密度；另一方面，可以使得第一边缘接触垫111b及其上接的电学结构的尺寸尽量增大，从而使得在改善核心区I内部的所有主接触垫131a上接的电学结构之间的一致性等方面具有更好的效果。
需要说明的是，当本发明各个实施例中的接触垫结构是基于图13所示的接触垫版图制作而成时，所述第一边缘接触垫111b的数量为多个，并沿所述主接触垫131a排布区域(即核心区I的边界处以内的区域，可以称为核心区I的中央区域或内部区域)的所述一边的延伸方向排列为两行，各个所述第一边缘接触垫111b与相应的主接触垫131a对准排布，最靠近所述主接触垫131a排布区域的一行第一边缘接触垫111b(即基于第一边缘接触垫图案112形成的第一边缘接触垫111b)与最近邻的一行主接触垫131a之间的间距为第一边缘间距D1。而当本发明各个实施例中的接触垫结构是基于图14或图15所示的接触垫版图制作而成时，所述第一边缘接触垫111b包括一个具有锯齿状边缘的长条(未图示)，即对应于图14或图15中的第一边缘接触垫图案111，可选地，所述锯齿状边缘面向所述主接触垫131a的排布区域设置，所述长条的锯齿状边缘中的各个锯齿与相应的主接触垫131a对准排布，所述长条的所述锯齿与其对准的最近邻的主接触垫131a之间的间距为第一边缘间距D1。
此外，可选地，请参考图13至图15所示，本发明各个实施例的接触垫结构还可以包括多个第二边缘接触垫(未图示)，第二边缘接触垫基于第二边缘版图区12中的第二边缘接触垫图案121、122制作形成，第二边缘接触垫分布在所有的主接触垫排布区域的所述一边的邻边外侧，且每个所述第二边缘接触垫的顶面面积大于每个所述主接触垫的顶面面积(进一步地，每个所述第二边缘接触垫的横截面面积大于每个所述主接触垫的横截面面积)，紧挨所述主接触垫的所述第二边缘接触垫(即基于第二边缘接触垫图案121形成的第二边缘接触垫)与所述主接触垫之间具有第二边缘间距D2,所述第二边缘接触垫的形状不同于所述第一边缘接触垫的形状，所述第二边缘间距D2不同于所述第四间距D4。可选地，各个所述第二边缘接触垫与相应的主接触垫对 准排布，例如，所有的所述第二边缘接触垫沿所述邻边的延伸方向排列为两列，且与所述主接触垫排布区域最近邻的一列所述第二边缘接触垫与最近邻的一列主接触垫之间的间距为所述第二边缘间距D2，两列所述第二边缘接触垫之间具有第三间距D3，所述第三间距D3大于所述第二边缘间距D2。可选地，所有的所述第二边缘接触垫中，远离所述主接触垫排布区域的一列中的第二边缘接触垫的横截面形状(或顶面形状)包括长条形、向左放倒的U形、向右放倒的U形、向左放倒的L形、向右放倒的L形以及具有至少两个梳齿的梳子形中的至少两种。
此外，请参考图16A和图16B，本发明的各实施例的半导体器件的接触垫结构中，主接触垫131a、第一边缘接触垫111b和第二边缘接触垫可以与周边区II中的接触垫135同时形成，主接触垫131a通过相应的接触插塞133a与核心区I中的相应的有源区AA1(即相应的源区或漏区S/D1)连接，第一边缘接触垫111b和第二边缘接触垫通过相应的接触插塞133b与核心区I边界处的相应的有源区AA1(即相应的源区或漏区S/D1)连接或者与交界区III中的浅沟槽隔离结构100a连接，接触垫135通过接触插塞133c与周边区II中的相应的源区或漏区S/D2连接。其中，各个接触垫采用同一道填充工艺形成；而各个接触垫及其接触的接触插塞可以分开且单独制作，也可以通过同一道金属填充工艺形成，其中，当各个接触垫及其接触的接触插塞分开且单独制作时，可以先沉积层间介质层132并刻蚀形成接触孔、填充金属以及平坦化而形成接触插塞133a、133b、133c，然后再沉积层间介质层134并刻蚀形成沟槽、填充金属以及平坦化而形成主接触垫131a、第一边缘接触垫111b、第二边缘接触垫和接触垫135，当各个接触垫及其接触的接触插塞通过同一道金属填充工艺形成，可以一次性沉积较厚的层间介质层(例如其厚度等于层间介质层132和层间介质层134的厚度之和)，然后通过相应的刻蚀工艺等形成各个接触垫及其接触的接触插塞连通的通道，之后在各个通道中填充金属并平坦化，从而一道形成接触插塞133a、133b、133c以及主接触垫131a、第一边缘接触垫111b、第二边缘接触垫和接触垫135，此时，主接触垫131a及其接触的接触插塞133a一体成型、第一边缘接触垫111b及其接触的接触插塞 133b一体成型、第二边缘接触垫及其接触的接触插塞133b一体成型、接触垫135及其接触的接触插塞133c一体成型。
请参考图13～图15以及图16A～16B，基于同一发明构思，本发明一实施例还提供一种半导体器件，包括：半导体衬底100，层间介质层以及如本发明所述的半导体器件的接触垫结构。其中，所述半导体衬底具有核心区I、周边区II以及位于核心区I、周边区II之间的交界区III，所述核心区I中形成有多个核心元件，各个核心元件形成在相应的有源区AA1上且相邻有源区AA1之间形成有浅沟槽隔离结构(STI)100b，各个核心元件可以是MOS晶体管，具有形成在相应的有源区AA1中的埋入式栅极以及位于埋入式栅极两侧的源区或漏区S/D1。层间介质层具有依次覆盖在所述半导体衬底100上的层间介质层132和层间介质层134。交界区III中形成有用于隔离核心区I和周边区II的浅沟槽隔离结构(STI)100a。所述接触垫结构形成在所述层间介质层中134中，至少包括主接触垫131a和第一边缘接触111b，可以进一步包括第二边缘接触垫。所述半导体器件还包括各个接触垫下接的接触插塞和各个接触垫上接的电学结构(例如电容器或电阻器等)。各个接触插塞133a、133b、133c形成在所述层间介质层132中，各个接触插塞133a对准相应的主接触垫131a的底部和相应的核心元件的有源区AA1(即相应的源区或漏区S/D1)设置，以将相应的主接触垫131a和所述核心元件的有源区AA1电连接,各个接触插塞133b的顶部对准相应的第一边缘接触垫111b或第二边缘接触垫的底部，各个接触插塞133b的底部对准核心区I边界处的有源区AA1(即相应的源区或漏区S/D1)或者交界区III中的STI 100a设置，以将相应的第一边缘接触垫111b或第二边缘接触垫和所述核心区I边界处的有源区AA1或交界区III中的STI 100a连接。
请参考图17A和图17B，基于同一发明构思，本发明还提供一种用于制作本发明所述的半导体器件的接触垫结构的掩模板组合，包括：第一掩模板20和第二掩模板30。其中，第一掩模板20具有多条平行的第一线条201，相邻的两条第一线条201之间为第一间隔区202，且第一掩模板20最外侧的至少一条第一线条201的线宽大于其他的第一线条201，至少第一掩模板20最 外侧的至少一个第一间隔区202的线宽大于其他的第一间隔区202的线宽。例如，第一掩模板20最外侧的两条第一线条201(即最外侧的第一条第一线条201a、第二条第一线条201b)的线宽均大于其他的第一线条201，第一线条201a的线宽大于第一线条201b的线宽，第一线条201a、201b之间的第一间隔区202(即第一掩模板20最外侧的一个第一间隔区202)的线宽D6大于其他的第一间隔区202的线宽，且第一线条201b与另一相邻的第一线条201之间的第一间隔区202的线宽D1不同于其他第一间隔区202(即除第一线条201a、201b之间的第一间隔区202以外)的线宽D4。第二掩模板30具有多条平行且与每条第一线条201垂直相交的第二条纹311，相邻的两条第二线条311之间为第二间隔区312，且第二掩模板30最外侧的至少一条第二线条311的线宽大于其他的第二线条311，第二掩模板30最外侧的至少一个第二间隔区312的线宽大于其他的第二间隔区312的线宽，例如，第二掩模板30最外侧的两条第二线条(即最外侧的第一条第二线条311a、第二条第二线条311b)的线宽均大于其他的第二线条311，第二线条311a的线宽大于第二线条311b的线宽，第二线条311a、311b之间的第二间隔区312(即第二掩模板30最外侧的一个第二间隔区312)的线宽大于其他的第二间隔区312的线宽，且第二线条311b与另一相邻的第二线条311之间的第二间隔区312的线宽不同于其他第二间隔区302(即除第二线条301a、301b之间的第二间隔区302以外)的线宽。可选地，所述第二掩模板30中，除第一条第二线条311a和第二条第二线条311b以外的所有其他的第二线条311的末端313的线宽均大于该第二线条311的中间区域的线宽。
其中，请参考图18，当所述第一掩模板20和所述第二掩模板30为同性掩模板且所述第二掩模板30和所述第一掩模板20对准重叠时，各个第一线条201和各个第二线条311的重叠区域为形成接触垫的区域，由此，第一线条201a和除第二线条311a和311b以外的各个第二线条311的重叠区域定义出图13中的第一边缘版图区11中的各个第一边缘接触垫图案111，第一线条201b和除第二线条311a和311b以外的各个第二线条311的重叠区域定义出图13中的第一边缘版图区11中的各个第一边缘接触垫图案112；第二线条 311a和除第一线条201a和201b以外的各个第一线条201的重叠区域定义出图13中的第二边缘版图区12中的各个第二边缘接触垫图案122，第二线条311b和除第一线条201a和201b以外的各个第一线条201的重叠区域定义出图13中的第二边缘版图区12中的各个第二边缘接触垫图案121，除第一线条201a和201b以外的各个第一线条201与除第二线条311a和311b以外的各个第二线条311的重叠区域定义出图13中的主版图区10及其中的各个主接触垫图案111，第一线条201b与其内侧相邻的第一线条201之间的第一间隔区202定义出第一边缘版图区11和主版图区10之间的第一边缘间距D1，第一线条201b与其外侧相邻的第一线条201a之间的第一间隔区202的线宽定义出第一边缘版图区11中的两行第一边缘接触垫图案111、112之间的第六间距D6，其余的第一间隔区202定义出两行主接触垫图案之间的第四间距D4，第二线条311b与其内侧相邻的第二线条311之间的第二间隔区312定义出第二边缘版图区12和主版图区10之间的第二边缘间距D2，第二线条311b与其外侧相邻的第二线条311a之间的第二间隔区312的线宽定义出第二边缘版图区12中的两列第二边缘接触垫图案121、122之间的第三间距D3，其余的第二间隔区312定义出两列主接触垫图案之间的第五间距D5。其中，所述第一掩模板20和所述第二掩模板30为同性掩模板的含义是：两掩模板的图案显影性质相同，均保留其线条对应的部分或者均保留其间隔区对应的部分，例如两掩模板均为负性掩模板时，利用第一掩模板20和第二掩模板30分别光刻后会相应的保留第一间隔区和第二间隔区对应的部分做为下方膜层刻蚀的掩模结构，两掩模板均为正性掩模板时，利用第一掩模板20和第二掩模板30分别光刻后会相应的保留第一线条和第二线条对应的部分做为下方膜层刻蚀的掩模结构。
请参考图19，当所述第一掩模板20和第二掩模板30为异性掩模板且所述第二掩模板30和所述第一掩模板20对准重叠时，各个第一线条201和各个第二间隔区312的重叠区域为形成接触垫的区域，由此，第一线条201a和各个第二间隔区312的重叠区域定义出图15中的第一边缘版图区11中的各个第一边缘接触垫图案111，第一线条201b和各个第二间隔区312的重叠区 域定义出图15中的第一边缘版图区11中的各个第一边缘接触垫图案112；第二线条311a定义出图15中的第二边缘版图区12中的第三间距D3，第二线条311b定义出图15中的第二边缘版图区12与主版图区10之间的第二边缘间距D2，第二线条311a外侧暴露出的各个第一线条201的末端203定义出图15中的第二边缘版图区12中的各个第二边缘接触垫图案122，第二线条311a和第二线条311b之间的第二间隔区312暴露出的各个第一线条201的部分定义出图15中的第二边缘版图区12中的各个第二边缘接触垫图案121，其余的第二间隔区312暴露出的各个第一线条201的部分定义出图15中的主版图区10中的各个主接触垫图案131，且除第二线条311b和第二线条311a以外的第二线条311定义出图15中的主版图区10中两列主接触垫图案131之间的第五间距D5，除第一线条21b和第一线条201a以外的第一线条201定义出图15中的主版图区10中两行主接触垫图案131之间的第四间距D4。其中，所述第一掩模板20和所述第二掩模板30为异性掩模板的含义是：两掩模板的图案显影性质相反，一个保留其线条对应的部分，另一个均保留其间隔区对应的部分。例如当第一掩模板20为负性掩模板、第二掩模板30为正性掩模板时，利用第一掩模板20光刻后会相应的保留第一间隔区对应的部分做为下方膜层刻蚀的掩模结构，利用第二掩模板30光刻后会相应的保留第二线条对应的部分做为下方膜层刻蚀的掩模结构；当第一掩模板20为正性掩模板、第二掩模板30为负性掩模板时，利用第一掩模板20光刻后会相应的保留第一线条对应的部分做为下方膜层刻蚀的掩模结构，利用第二掩模板30光刻后会相应的保留第二间隔区对应的部分做为下方膜层刻蚀的掩模结构。
请参考图17A和图19，可选地，所述第一掩模板20的一侧，至少有两条第一线条201的末端203连接在一起，由此，可以使得定义出的第二边缘版图区中的最外侧一列第二边缘接触垫图案的形状不完全相同且包括长条形、向左放倒的U形、向右放倒的U形、向左放倒的L形、向右放倒的L形以及具有至少两个梳齿的梳子形中的至少两种。
请参考图18和图19，可选地，所述第二掩模板30和所述第一掩模板20对准重叠时，除所述第二掩模板30最外侧的第一条第二线条311a以外的所有 第二线条311(包括最外侧的第二条第二线条311b)的末端均未超出所述第一掩模板20最外侧的第一条第一线条201a。请参考图19，当所述第一掩模板20和第二掩模板30为异性掩模板且所述第二掩模板30和所述第一掩模板20对准重叠时，所述第二掩模板30最外侧的第一条第二线条311暴露出至少一条所述第一线条201的末端203。
需要说明的是，本发明各实施例中，第一掩模板20和第二掩模板30可以分别是能够通过一次光刻工艺就能将第一线条和第一间隔区、第二线条和第二间隔区的图案转移到用于形成接触垫结构的层上的掩模板，也可以分别是需要通过双重图案成型或多重图案成型的工艺才能在一些辅助层(例如用于形成接触垫结构的层上的硬掩模层)中形成所需的第一线条和第一间隔区的图案、第二线条和第二间隔区的图案，此时具有第一线条和第一间隔区的图案的辅助层为第一掩模板20，具有第二线条和第二间隔区的图案的辅助层为第一掩模板30，当然，在本发明的一些实施例中，亦可以通过双重图案成型或多重图案成型的工艺在同一辅助层(例如用于形成接触垫结构的层上的硬掩模层)中形成具有第一线条、第一间隔区、第二线条和第二间隔区对准重叠后的图案，此时该辅助层可以看做是第一掩模板20和第二掩模板30对准重叠后形成的掩模板组合。为了更清楚的了解如何通过双重图案成型或多重图案成型的工艺来形成第一掩模板20或第二掩模板30，下面结合附图20A～20D、附图21A～21D来进行详细描述。
请参考图20A～20D，在本发明的一个实施例中，通过双重图案成型的工艺来形成第一掩模板20或第二掩模板30的具体步骤包括：
首先，请参考图20A，提供半导体衬底800，在半导体衬底800上依次形成有刻蚀停止层801(例如氧化硅等)、层间介质层802(用于形成接触垫的层)、硬掩膜层803(例如氮化硅等)，第一辅助层804(例如有机介质层等)、底部抗反射层805以及光刻胶层806，可以通过一次光刻工艺图案化光刻胶层806，以形成相应的图案；
然后，请参考图20B，以图案化的光刻胶层806为掩模，刻蚀底部抗反射层805和第一辅助层804至硬掩膜层803的顶面，以将图案化的光刻胶层806 中的图案转移到第一辅助层804，剩余的底部抗反射层805和第一辅助层804形成多个芯核，然后去除图案化的光刻胶层806；
接着，请参考图20B和20C，覆盖第二辅助层807于底部抗反射层805和第一辅助层804以及硬掩膜层803上，并对第二辅助层807进行刻蚀，以在各个芯核(即底部抗反射层805和第一辅助层804)的侧壁上形成侧墙807a，然后去除各个芯核(即底部抗反射层805和第一辅助层804)，此时，所有侧墙807a及其间隔组成的板层即为第一掩模板20或第二掩模板30，例如，当为第一掩模板20时，侧墙807a为第一掩模板20中的第一间隔区202，相邻侧墙807a之间的间隔为第一掩模板20中的第一线条201。
之后，请参考图20C和20D，以侧墙807a为掩模，刻蚀硬掩膜层803和层间介质层802，以在层间介质层802中对应侧墙807a之间的间隔的位置形成沿第一方向延伸的沟槽(即对应第一掩模板20中的第一线条201)。
需要说明的是，当第一掩模板20和第二掩模板30均采用图20A～20D所示的方法形成时，会在层间介质层802中形成沿第一方向延伸的沟槽(即对应第一掩模板20中的第一线条201)以及沿垂直于第一方向的第二方向延伸的沟槽(即对应第二掩模板30中的第二线条311)，两个方向的沟槽交汇处即是用于形成接触垫的位置。
请参考图21A～21D，在本发明的另一个实施例中，通过双重图案成型的工艺来形成第一掩模板20或第二掩模板30的具体步骤包括：
首先，请参考图21A，提供半导体衬底800，在半导体衬底800上依次形成有刻蚀停止层801(例如氧化硅等)、层间介质层802(用于形成接触垫的层)、硬掩膜层803(例如氮化硅等)，第一辅助层804(例如有机介质层等)、底部抗反射层805以及光刻胶层806，可以通过一次光刻工艺图案化光刻胶层806，以形成相应的图案；
然后，请参考图21B，以图案化的光刻胶层806为掩模，刻蚀底部抗反射层805和第一辅助层804至硬掩膜层803的顶面，以将图案化的光刻胶层806中的图案转移到第一辅助层804，剩余的底部抗反射层805和第一辅助层804形成多个芯核，然后去除图案化的光刻胶层806；
接着，请参考图21B和21C，依次覆盖第二辅助层807、第三辅助层809于底部抗反射层805和第一辅助层804以及硬掩膜层803上，并平坦化第三辅助层809的顶部至暴露出底部抗反射层805的顶面，且刻蚀去除各个芯核(即底部抗反射层805和第一辅助层804)的侧壁上的第二辅助层807，以形成开口808。此时，剩余的第二辅助层807、第三辅助层809、底部抗反射层805和第一辅助层804以及开口808组成的板层结构即为第一掩模板20或第二掩模板30，例如，当为第一掩模板20时，开口808为第一掩模板20中的第一线条201，开口808每侧的第二辅助层807和第三辅助层809形成的堆叠结构或者底部抗反射层805和第一辅助层804膜层形成的堆叠结构为第一掩模板20中的第一间隔区202。
之后，可以采用相同的方法，在已形成的第一掩板20上制作第二掩模板30，或者在已形成的第二掩模板30上制作第一掩板20，从而形成对准重叠在一起的第一掩模板20和第二掩模板30，即掩模板组合，进而以该掩模板组合为掩模，刻蚀硬掩膜层803和层间介质层802，以在层间介质层802中形成用于制作接触垫的沟槽。
下面以半导体器件为动态随机存储器为例，并结合图22至图25，来详细说明具有本发明的接触垫版图的半导体器件的制作方法。
首先，请参考图22和23，提供具有多个核心元件(即存储晶体管)的半导体衬底410，具体过程包括：首先，提供一个半导体基底410a，其包含核心区I和周边区II以及交界区III。本实施例中，核心区I为存储区，核心区I上待形成的核心元件包括选择元件，后续在核心元件上方接数据存储元件，选择元件例如是MOS晶体管或二极管，数据存储元件例如是电容器、可变电阻器等，一个选择元件和相应的数据存储元件组成存储单元。周边区II中可形成外围电路(例如，NMOS晶体管和PMOS晶体管、二极管或电阻器)来控制存储单元。核心区I的半导体基底410a中形成有多个浅沟槽隔离结构411b，交界区III的半导体基底410a中形成有浅沟槽隔离结构411a，浅沟槽隔离结构411a在二维平面上界定出了核心区I和周边区II的分界处，浅沟槽隔离结构411b界定出了核心区I中的各个核心元件所对应的有源区AA1。其 中有源区AA1在二维平面上的分布呈现条形且均沿第一方向延伸，且有源区AA1在半导体基底410a的面上可呈现错位的排列设置。然后，在半导体基底410a中形成的埋入式字线WL，埋入式字线WL一般埋设在半导体基底410a中一预定深度位置，沿第二方向(即行方向)延伸并穿过浅沟槽隔离结构411b以及有源区AA1，第二方向与有源区AA1的第一方向相交但不垂直。埋入式字线WL作为栅极来控制存储单元的开关，通常埋入式字线WL的侧壁和底部被栅介质层(未图示)包围，埋入式字线WL的顶部被栅极盖层412掩埋在内。由于埋入式字线WL并非本发明的重点，其相关制作工艺可以参考本领域的已知技术方案，在此不再详述。此外，栅介质层可包括氧化硅或其他适合的介电材料，埋入式字线WL可包括铝、钨、铜、钛铝合金、多晶硅或其他适合的导电材料，而栅极盖层412可包括氮化硅、氮氧化硅、氮碳化硅或其他适合的绝缘材料。再者，在埋入式字线WL两旁的有源区AA1中可掺入第二类型的掺质，如P类型或N类型的掺质，来形成源区和漏区(统一定义为S/D1)，埋入式字线WL两旁的AA1中的一者位于AA1中心处对应预定的位线接触结构的位置，另一者位于有源区AA1末端预定的存储节点接触结构的位置。字线WL和S/D1可以构成或限定形成在半导体器件的核心区I上的多个MOS存储晶体管。此外，在形成S/D1的同时，也可以一并在周边区II中形成外围晶体管对应的源区和漏区(统一定义为S/D2)。在形成所述S/D1和S/D2之后，还可进一步形成刻蚀停止层413在所述半导体基底410a上，所述刻蚀停止层413覆盖所述S/D1和S/D2，其材料例如包括氮化硅(SiN)和/或氧化硅(SiO 2)等。然后，在核心区I的用作漏区的S/D1上形成多个位线接触插塞(bit line contact，未图示)以及位于所述位线接触插塞上方的位线BL，位线接触插塞可以通过如下方法形成：先刻蚀一个有源区AA1中形成的相邻两条WL之间的S/D1来形成凹槽，之后在凹槽中形成金属硅化物。多条位线BL相互平行且沿着垂直于埋入式字线WL的第三方向(即列方向)延伸，并同时横跨该有源区AA1与埋入式字线WL。各位线BL例如包含依序堆叠的一半导体层(例如多晶硅，未图示)、一阻障层(例如包括Ti或TiN等，未图示)、一金属层(例如钨、铝或铜等，无图示)与一掩模层(例如包含氧 化硅、氮化硅或碳氮化硅，未图示)。此外，在半导体基底410a的周边区II上，则形成有至少一栅极结构G1，其例如包含依序堆叠的一栅极介电层(未图示)和一栅极层(未图示)。在一具体示例中，栅极结构G1的栅极层与位线BL的半导体层或金属层是一并形成。进一步地，可采用不同工艺或同道工艺形成分别环绕各位线BL与栅极结构G1的侧墙414。举例来说，可先进行栅极结构G1的侧墙的制作工艺，使栅极结构G1的侧墙414包含氧化硅或氮氧化硅(SiON)，再进行位线BL的侧墙415的制作工艺，而使位线BL的侧墙可包含氮化硅。此外，在栅极结构G1的侧墙的制作工艺中，可再进行一回蚀刻(etching back)制作工艺，使栅极结构G1的整体高度低于各位线BL。
然后，可以采用本发明的图13～图15所示的接触垫版图或者图17A～图19所示的掩模板组合来形成存储节点接触结构。具体过程如下：
首先，请参考图24或25，在提供具有位线BL、核心元件的源区和漏区S/D1的半导体衬底410之后，在半导体衬底410上形成一层间介质层500，其材质例如包括氧化硅、氮化硅或低K介质等。具体地，先通过沉积工艺全面地在半导体衬底410上覆盖层间介质层500，并使得层间介质层500填满各位线BL之间的空间并将各位线BL与栅极结构G1及其侧墙414掩埋在内，然后通过化学机械研磨等工艺对层间介质层500进行平坦化，形成整体上具有平坦的顶表面的层间介质层500。其中，平坦化后的层间介质层500的顶表面至少不低于各位线BL的顶表面。
接着，请继续参照图24或25，通过相应的辅助层沉积、光刻、刻蚀一系列工艺，在层间介质层500上形成图18或图19所示的第一掩模板20和第二掩模板30对准重叠后的掩模板组合图案(未图示)，该掩模板组合图案即为图13～图15中任一种接触垫版图，以定义出各个存储节点接触结构的位置，然后，使用掩模板组合图案作为蚀刻掩模，各向异性地蚀刻层间介质层500，以形成贯穿所述层间介质层500且暴露出下方相应的用作源区的S/D1的接触孔以及暴露出周边区II中的源区S/D2或栅极G1的接触孔(未图示)。其中，对应接触垫版图中的第一边缘接触垫图案和第二边缘接触垫图案的接触孔可以形成在核心区I的边界处(此时该接触孔的顶部相联在一起并至少跨过核心 区I的边界处最外侧的一条字线WL)，也可以至少部分形成在交界区III的STI 411a上；对应接触垫版图中的主接触垫图案的接触孔形成在核心区I中。
接着，请继续参照图24或25，在形成接触孔之后，可以执行灰化工艺或湿式清洗或其他合适的工艺，以去除层间介质层500上方的膜层，并在各个接触孔中依次填充阻挡金属层(未图示)和导电金属层(未图示)，所述阻挡金属层可以以均匀的厚度覆盖接触孔的内壁与层间介质层500的顶表面，阻挡金属层能够减少或防止设置在接触孔中的金属材料扩散到层间介质层500中，其可以由Ta、TaN、TaSiN、Ti、Ti N、TiSiN、W、WN或它们的任何组合形成，可以使用化学气相沉积(CVD)、原子层沉积(ALD)或物理气相沉积(PVD)(例如，溅射)等工艺形成；导电金属层可以由(一种或多种)难熔金属(例如，钴、铁、镍、钨和/或钼)形成。另外，可以使用具有良好阶梯覆盖性质的沉积工艺形成导电金属层，例如，使用化学气相沉积(CVD)、原子层沉积(ALD)或物理气相沉积(PVD)(例如，溅射)形成。形成的导电金属层还覆盖在接触孔周围的层间介质层500的表面上，之后，可以采用化学机械抛光(CMP)工艺对沉积的导电金属层的顶面进行化学机械抛光，直至暴露出层间介质层500的顶面，以形成位于层间介质层500中的主接触垫511a、周边接触垫511d和511e以及第一边缘接触垫(或第二边缘接触垫)511b。主接触垫511a作为核心区I中的存储节点接触结构，用于与后续在核心区I上方形成的电容结构连接。第一边缘接触垫(或第二边缘接触垫)511b由核心区I的边界处中的至少两个顶部相连的接触插塞形成(如图24中所示)，或者，由交界区III中的接触插塞和核心区I的边界处的接触插塞顶部相联在一起形成(如图25中所示)，或者由交界区III中尺寸较大的接触结构形成(未图示)，作为核心区I的边界处或者交界区III中的虚拟存储节点接触结构，用于与后续在核心区I的边界处或者交界区III上方形成的电容结构连接，第一边缘接触垫(或第二边缘接触垫)511b与位线BL对准平行。第一边缘接触垫(或第二边缘接触垫)511b的剖面结构例如为倒U形电接触结构或者梳状电接触结构。周边接触垫511d作为周边区II的栅极结构G1的接触结构，用于将栅极结构G1向外引出，周边接触垫511e作为周边区II的源区或漏区S/D2的接 触结构，用于将周边区II的源区或漏区S/D2向外引出。主接触垫511a、周边接触垫511d和511e以及第一边缘接触垫(或第二边缘接触垫)511b分别可以是一体成型的结构，也可以是由焊盘及其下接的接触插塞组成。
之后，请继续参照图24或25，可以采用本领域常规的电容结构的制作方法来在核心区I上制作相应的电容结构，具体过程在此不再详述。核心区I的每个主接触垫511a上接电容结构705a，核心区I边界处和/或交界区III的第一边缘接触垫或第二边缘接触垫511b上接电容结构705b，每个电容器包括下电极层701、电容介质层702以及上电极层703，电容器之间具有横向支撑且间隔式层叠的底层支撑层600、中间支撑层601以及顶层支撑层602，其中底层支撑层600一方面用于对后续形成的下电极层进行底部支撑，另一方面还用于隔离半导体衬底400的内部元件与上方的电容器等元件。底层支撑层600的形成工艺还可以是热氧化工艺。所述底层支撑层600、中间支撑层601和顶层支撑层602的材质包含但不限于氮化硅。在本发明的其他实施例中，为了对下电极层进行更好的支撑，底层支撑层600和顶层支撑层602之间还可以层叠两层以上的中间支撑层601。电容结构705b具有第一宽度W1，电容结构705a具有第二宽度W2，可选地，W1大于W2，例如W1＝1.3*W2～2.3*W2。可选的，所有的电容结构可以呈六方密堆积排布。进一步的，所述下电极层701呈筒状结构，可以是多晶硅电极或金属电极。当下电极层701为金属电极时，还可以采用氮化钛(TiN)和Ti层叠结构。当下电极层701为多晶硅电极时，可以采用零掺杂和/或掺杂的多晶硅材料形成。所述电容介质层702覆盖所述下电极层701的筒状结构的内表面和外表面，以充分利用下电极层701的两个相对表面，构成具有较大电极表面积的电容器。优选的，所述电容介质层702可以为金属氧化物等高K介质层。进一步的，所述电容介质层702为多层结构，例如为氧化铪-氧化锆的两层结构。所述上电极层703可以为单层结构也可以为多层结构，当所述上电极层703为单层结构时，例如为多晶硅电极，也可以为金属电极，当上电极层703为金属电极时，例如可以采用氮化钛(TiN)形成。所述上电极层703在对应所述筒状结构的内部和所述筒状结构的外部均能够与所述电容介质层702以及所述下电极层701构成电容 器。此外，在核心区I边缘区域(即电容孔阵列的边界区域)上，由于横向支撑层(即中间支撑层601、顶层支撑层602)的存在，所述电容介质层702和所述上电极层703均具有凹凸不平形貌的侧壁结构，所述凹凸不平形貌的侧壁结构对应于在所述下电极层701的筒状结构筒外部的所述中间支撑层601、顶层支撑层602，由此使得所述上电极层703在所述核心区I边缘区域(即电容孔阵列的边界区域)上的部分，对应所述中间支撑层601、顶层支撑层602以远离所述下电极层701的方向凸出，使核心区I中的电容器阵列边界不平整。此外，本实施例中，所述电容介质层702和所述上电极层703还依次延伸覆盖在所述周边区II上保留的底层支撑层600的表面上。
请参考图24或图25所示，可以先采用化学气相沉积工艺在所述上电极层703表面形成一上电极填充层704，所述上电极填充层704填满所述上电极层703之间的间隙，也就是说，所述上电极填充层704填充满相邻的筒状结构之间的间隙并覆盖上述形成的结构。优选的，所述上电极填充层704的材质包括未掺杂或者硼掺杂的多晶硅。由此完成了电容器阵列的制作。
可以理解的是，由于第一边缘接触垫和第二边缘接触垫511b的顶面面积较大，因此可以为电容结构705b的制作提供足够的工艺余量，且使得电容结构705b对应的电容孔的宽度较大，避免该电容结构705b对应的电容孔发生异常变形或坍塌，同时电容结构705b和相应的第一边缘接触垫或第二边缘接触垫511b具有较大的接触面积，进而降低接触阻抗减小，有利于提高器件的电学性能。此外，因为电容结构705b对应的电容孔的宽度较大，能够缓冲周边区II和核心区I中的电路图案的密度差异，从而在执行电容孔的光刻工艺和/或蚀刻工艺时能够改善光学邻近效应，减小周边区II和核心区I中的电路图案的稀疏/密集负载效应，保护核心区I中的电容孔，保证核心区边界以内的电容孔和填充在核心区的电容孔中的电容器的一致性，防止出现核心区内的主接触垫上方的电容孔出现异常而引起后续形成的电容结构失效的问题。
需要说明的是，本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。以及，上述描述仅是对本发明较佳实施例的描述，并非对本 发明范围的任何限定，本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰，均属于本发明技术方案所要求的保护范围。
此外，还需要说明的是，除非特别说明或者指出，否则说明书中的术语“第一”、“第二”和“第三”等描述仅仅用于区分说明书中的各个组件、元素、步骤等，而不是用于表示各个组件、元素、步骤之间的逻辑关系或者顺序关系等。

Claims (40)

  1. 一种半导体器件的电接触结构，其特征在于，所述半导体器件包括核心区，所述核心区包括边界处和中央区，所述核心区中形成有多个核心元件，所述核心元件包括有源区，所述电接触结构包括：
    多个接触插塞，形成于所述半导体器件的核心区的核心元件的上方，且各个所述接触插塞的底部与相应的所述核心元件的有源区接触，
    其中，形成在所述核心区的边界处的至少两个所述接触插塞的顶部相联在一起，且顶部相联在一起的所有所述接触插塞中包括：位于所述边界处的最外侧的所述接触插塞。
  2. 如权利要求1所述的半导体器件的电接触结构，其特征在于，顶部相联在一起的所有所述接触插塞构成倒U形电接触结构或者梳状电接触结构。
  3. 如权利要求2所述的半导体器件的电接触结构，其特征在于，所述半导体器件的核心区中形成有与多个所述有源区相交的多条字线以及多条位线，其中，每条所述位线的延伸方向与每条所述字线的延伸方向垂直，所述顶部相联在一起的所有所述接触插塞构成的结构跨过至少一条所述字线并与所述位线对准。
  4. 如权利要求1所述的半导体器件的电接触结构，其特征在于，所述电接触结构还包括相互独立的多个接触垫，每个所述接触垫形成在所述核心区的不相联在一起的每个所述接触插塞的顶部，并一一对应地与相应的所述接触插塞的顶部电接触。
  5. 如权利要求1所述的半导体器件的电接触结构，其特征在于，顶部相联在一起的所有所述接触插塞为一体成型的结构，或者，所述边界处的至少两个所述接触插塞通过上接同一个接触垫而顶部相联在一起。
  6. 如权利要求1所述的半导体器件的电接触结构，其特征在于，所述电接触结构上接多个电容结构，其中，所述边界处的一个或多个电容结构具有第一宽度，所述中央区的一个或多个电容结构具有第二宽度，所述第一宽度大于所述第二宽度。
  7. 如权利要求6所述的半导体器件的电接触结构，其特征在于，所述第一宽度大于1.5倍的所述第二宽度。
  8. 一种半导体器件，其特征在于，包括：
    半导体衬底，所述半导体衬底包括核心区，所述核心区包括边界处和中央区，所述核心区中形成有多个核心元件，所述核心元件包括有源区；
    层间介质层，覆盖在所述半导体衬底上；以及，
    如权利要求1～7中任一项所述的半导体器件的电接触结构，所述电接触结构形成于所述层间介质层中，所述电接触结构的各个所述接触插塞的底部与相应的所述核心元件的有源区接触，且所述电接触结构中形成在所述核心区的边界处的至少两个所述接触插塞的顶部相联在一起，且顶部相联的所有所述接触插塞中包括：位于所述边界处的最外侧的所述接触插塞。
  9. 如权利要求8所述的半导体器件，其特征在于，所述半导体器件为DRAM，所述核心区为存储区，所述核心元件为存储晶体管，所述电接触结构为存储节点接触结构。
  10. 如权利要求9所述的半导体器件，其特征在于，所述半导体器件还包括：多个电容结构，形成于所述层间介质层上且底部与所述电接触结构相接触，所述边界处的一个或多个电容结构具有第一宽度，所述中央区的一个或多个电容结构具有第二宽度，所述第一宽度大于所述第二宽度。
  11. 如权利要求10所述的半导体器件，其特征在于，所述第一宽度大于1.5倍的所述第二宽度。
  12. 如权利要求9所述的半导体器件，其特征在于，所述半导体器件包括多条字线和多条位线，每条所述字线与所述核心区中的多个所述有源区相交，每条所述位线的延伸方向与每条所述字线的延伸方向垂直，顶部相联在一起的所有所述接触插塞构成的结构跨过至少一条所述字线并与所述位线对准。
  13. 一种半导体器件的电接触结构的制造方法，其特征在于，包括：
    提供半导体衬底，所述半导体衬底包括核心区，所述核心区包括边界处和中央区，所述核心区中形成有多个核心元件，所述核心元件包括有源区；
    在所述半导体衬底上形成层间介质层，并在所述层间介质层中形成多个接触孔，各个所述接触孔贯穿所述层间介质层并暴露出相应的所述核心元件的有源区；
    在每个所述接触孔中形成接触插塞，且每个所述接触插塞的底部与相应的所述核心元件的有源区接触，且形成在所述核心区的边界处的至少两个所述接触插塞的顶部相联在一起，顶部相联在一起的所有所述接触插塞中包括：位于所述边界处的最外侧的所述接触插塞。
  14. 如权利要求13所述的半导体器件的电接触结构的制造方法，其特征在于，在所述层间介质层中形成多个接触孔包括：先通过一次光刻工艺在所述层间介质层中形成相互独立的接触孔，然后通过另一次光刻工艺刻蚀所述层间介质层，以使得所述边界处的至少两个所述接触孔的顶部相连通，以用于形成顶部相联在一起的接触插塞；或者，
    在所述层间介质层中形成多个接触孔包括：通过一次光刻工艺在所述层间介质层中形成相互独立的接触孔；然后，在所述接触孔中形成相互独立的接触插塞后，通过另一次光刻工艺刻蚀所述层间介质层，以形成暴露出所述边界处的至少两个所述接触插塞的顶部侧壁的沟槽，以在所述沟槽中形成接触垫，以使得相应的至少两个所述接触插塞的顶部相联在一起；或者，
    在所述层间介质层中形成多个接触孔包括：通过一次光刻工艺在所述层间介质层中形成相互独立的接触孔；然后，在所述接触孔中形成相互独立的接触插塞后，形成另一层间介质层以覆盖具有所述接触插塞的层间介质层；然后通过另一次光刻工艺刻蚀所述另一层间介质层，以形成暴露出所述边界处的至少两个所述接触插塞的顶部的沟槽，在所述沟槽中形成接触垫，以使得相应的至少两个所述接触插塞的顶部相联在一起。
  15. 一种半导体器件的制造方法，其特征在于，包括：采用权利要求13或14所述的半导体器件的电接触结构的制造方法，在一半导体衬底上形成电接触结构，所述半导体衬底包括核心区，所述核心区中形成有多个核心元件，所述电接触结构与相应的所述核心元件电接触。
  16. 如权利要求15所述的半导体器件的制造方法，其特征在于，所述核 心区为存储区，所述核心元件为存储晶体管，所述电接触结构为存储节点接触结构，所述半导体器件的制造方法还包括：
    在所述电接触结构上形成一电容结构的下电极；
    形成覆盖所述下电极的电容介质；以及，
    在所述电容介质上形成所述电容结构的上电极。
  17. 如权利要求16所述的半导体器件的制造方法，其特征在于，提供半导体衬底的步骤包括：
    提供一半导体衬底，在所述半导体衬底中定义出多个有源区；
    在所述半导体衬底中形成字线，所述字线与所述有源区相交；
    在所述字线两侧的所述有源区中分别形成源区及漏区；
    在所述漏区上形成位线接触结构；以及
    在所述位线接触结构上形成位线，所述位线与所述字线相交，其中所述电接触结构中的接触插塞的底部与所述源区接触。
  18. 一种半导体器件的接触垫版图，其特征在于，所述接触垫版图包括：
    主版图区，所述主版图区中设有多个主接触垫图案，各个所述主接触垫图案的形状和尺寸相似，且所有的所述主接触垫图案呈棋盘状交错排布，各个所述主接触垫图案彼此之间具有第四间距；
    第一边缘版图区，分布在所述主版图区的一边外侧，所述第一边缘版图区中设有至少一个第一边缘接触垫图案，且每个所述第一边缘接触垫图案的面积大于每个所述主接触垫图案的面积，所述第一边缘版图区与所述主版图区之间具有第一边缘间距；
    其中，所述第一边缘接触垫图案不同于所述主接触垫图案，所述第一边缘间距不同于所述第四间距。
  19. 如权利要求18所述的接触垫版图，其特征在于，所述第一边缘版图区中设有一个具有锯齿状边缘的长条，以作为所述第一边缘接触垫图案。
  20. 如权利要求19所述的接触垫版图，其特征在于，所述锯齿状边缘面向所述主版图区，所述锯齿状边缘中的各个锯齿与所述主版图区中相应的主接触垫图案对准排布。
  21. 如权利要求18所述的接触垫版图，其特征在于，所述第一边缘版图区中设有多个沿所述主版图区的所述一边的延伸方向排列为两行的第一边缘接触垫图案，且各个所述第一边缘接触垫图案与所述主版图区中相应的主接触垫图案对准排布，最靠近所述主版图区的一行第一边缘接触垫图案与最近邻的一行所述主接触垫图案之间的间距为所述第一边缘间距。
  22. 如权利要求18所述的接触垫版图，其特征在于，所述接触垫版图还包括第二边缘版图区，所述第二边缘版图区分布在所述主版图区的所述一边的邻边外侧，所述第二边缘版图区中设有多个第二边缘接触垫图案，且每个所述第二边缘接触垫图案的面积大于每个所述主接触垫图案的面积，所述第二边缘版图区和所述主版图区之间具有第二边缘间距；
    其中，所述第二边缘接触垫图案不同于所述第一边缘接触垫图案，所述第二边缘间距不同于所述第四间距。
  23. 如权利要求22所述的接触垫版图，其特征在于，所述第二边缘间距不同于所述第一边缘间距。
  24. 如权利要求22所述的接触垫版图，其特征在于，所述第二边缘版图区中的各个所述第二边缘接触垫图案不完全相同。
  25. 如权利要求22所述的接触垫版图，其特征在于，所述第二边缘版图区中的各个所述第二边缘接触垫图案与所述主版图区中相应的主接触垫图案对准排布。
  26. 如权利要求25所述的接触垫版图，其特征在于，所述第二边缘版图区中包括沿所述邻边的延伸方向排列为两列的第二边缘接触垫图案，且与所述主版图区最近邻的一列所述第二边缘接触垫图案与最近邻的一列所述主接触垫图案之间的间距为所述第二边缘间距，两列所述第二边缘接触垫图案之间具有第三间距，所述第三间距大于所述第二边缘间距。
  27. 如权利要求26所述的接触垫版图，其特征在于，所述第二边缘版图区中，远离所述主版图区的一列所述第二边缘接触垫图案的形状包括长条形、向左放倒的U形、向右放倒的U形、向左放倒的L形、向右放倒的L形以及具有至少两个梳齿的梳子形中的至少两种。
  28. 一种利用权利要求18～27中任一项所述的半导体器件的接触垫版图形成的接触垫结构，其特征在于，包括：
    多个主接触垫，呈棋盘状交错排布，各个所述主接触垫的形状和尺寸相似，且所述主接触垫彼此之间具有第四间距；
    至少一个第一边缘接触垫，分布在所有的主接触垫排布区域的一边外侧，且每个所述第一边缘接触垫的顶面面积大于每个所述主接触垫的顶面面积，最靠近所述主接触垫的所述第一边缘接触垫与最近邻的所述主接触垫之间具有第一边缘间距；
    其中，所述第一边缘接触垫的尺寸不同于所述主接触垫的尺寸，所述第一边缘间距不同于所述第四间距。
  29. 如权利要求28所述的接触垫结构，其特征在于，所述第一边缘接触垫为一个具有锯齿状边缘的长条。
  30. 如权利要求29所述的接触垫结构，其特征在于，所述锯齿状边缘面向所述主接触垫设置，所述锯齿状边缘中的各个锯齿与相应的所述主接触垫对准排布。
  31. 如权利要求28所述的接触垫结构，其特征在于，所述第一边缘接触垫的数量为多个，并沿所述主接触垫排布区域的所述一边的延伸方向排列为两行，各个所述第一边缘接触垫与相应的所述主接触垫对准排布，最靠近所述主接触垫排布区域的一行第一边缘接触垫与最近邻的一行主接触垫之间的间距为所述第一边缘间距。
  32. 如权利要求28所述的接触垫结构，其特征在于，所述接触垫结构还包括：多个第二边缘接触垫，分布在所有的主接触垫排布区域的所述一边的邻边外侧，且每个所述第二边缘接触垫的顶面面积大于每个所述主接触垫的顶面面积，最靠近所述主接触垫的所述第二边缘接触垫与最近邻的所述主接触垫之间具有第二边缘间距；
    其中，所述第二边缘接触垫的形状不同于所述第一边缘接触垫的形状，所述第二边缘间距不同于所述第四间距。
  33. 如权利要求32所述的接触垫结构，其特征在于，各个所述第二边缘 接触垫与相应的所述主接触垫对准排布。
  34. 如权利要求33所述的接触垫结构，其特征在于，所有的所述第二边缘接触垫沿所述邻边的延伸方向排列为两列，且与所述主接触垫排布区域最近邻的一列所述第二边缘接触垫与最近邻的一列主接触垫之间的间距为所述第二边缘间距，两列所述第二边缘接触垫之间具有第三间距，所述第三间距大于所述第二边缘间距。
  35. 如权利要求34所述的接触垫结构，其特征在于，所有的所述第二边缘接触垫中，远离所述主接触垫排布区域的一列所述第二边缘接触垫的横截面形状包括长条形、向左放倒的U形、向右放倒的U形、向左放倒的L形、向右放倒的L形以及具有至少两个梳齿的梳子形中的至少两种。
  36. 一种半导体器件，其特征在于，包括：
    半导体衬底，所述半导体衬底包括核心区，所述核心区中形成有多个核心元件，所述核心元件包括有源区；
    层间介质层，覆盖在所述半导体衬底上；
    如权利要求28～35中任一项所述的半导体器件的接触垫结构，形成在所述层间介质层中；
    多个接触插塞，形成在所述层间介质层中，各个接触插塞对准所述接触垫结构中的相应接触垫设置，以将相应的所述接触垫和所述核心元件的有源区电连接，所述接触垫包括主接触垫或者第一边缘接触垫。
  37. 一种用于制作权利要求28～35中任一项所述的半导体器件的接触垫结构的掩模板组合，其特征在于，包括：
    第一掩模板，具有多条平行的第一线条，相邻的两条所述第一线条之间为第一间隔区，且所述第一掩模板最外侧的至少一条所述第一线条的线宽大于其他的所述第一线条，所述第一掩模板最外侧的至少一个所述第一间隔区的线宽大于其他的所述第一间隔区的线宽；
    第二掩模板，具有多条平行且与每条所述第一线条相交的第二条纹，相邻的两条所述第二线条之间为第二间隔区，且所述第二掩模板最外侧的至少一条所述第二线条的线宽大于其他的所述第二线条，所述第二掩模板最外侧 的至少一个所述第二间隔区的线宽大于其他的所述第二间隔区的线宽；
    其中，当所述第一掩模板和所述第二掩模板为同性掩模板且所述第二掩模板和所述第一掩模板对准重叠时，所述第一线条和所述第二线条的重叠区域为形成接触垫的区域；当所述第一掩模板和所述第二掩模板为异性掩模板且所述第二掩模板和所述第一掩模板对准重叠时，所述第一线条和所述第二间隔区的重叠区域为形成接触垫的区域。
  38. 如权利要求37所述的掩模板组合，其特征在于，所述第一掩模板的一侧，至少有两条所述第一线条的末端连接在一起。
  39. 如权利要求37所述的掩模板组合，其特征在于，所述第二掩模板和所述第一掩模板对准重叠时，所述第二掩模板最外侧第一条所述第二线条超出或者齐平于其他的所述第二线条的末端；所述第二掩模板最外侧第一条所述第二线条暴露出至少一条所述第一线条的末端。
  40. 如权利要求37所述的掩模板组合，其特征在于，所述第二掩模板中，所述其他的第二线条的末端的线宽大于所述其他的第二线条的中间区域的线宽。
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