CN104037176A - 接触结构以及采用所述接触结构的半导体存储元件 - Google Patents

接触结构以及采用所述接触结构的半导体存储元件 Download PDF

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CN104037176A
CN104037176A CN201410027852.XA CN201410027852A CN104037176A CN 104037176 A CN104037176 A CN 104037176A CN 201410027852 A CN201410027852 A CN 201410027852A CN 104037176 A CN104037176 A CN 104037176A
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semiconductor memory
dielectric layer
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memory component
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俞建安
吴奇煌
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Nanya Technology Corp
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Abstract

本发明公开了一种半导体存储元件，包含有一基材，其上包含一存储阵列区域以及一外围电路区域；一第一介电层，覆盖所述存储阵列区域以及所述外围电路区域；一第二介电层，位于所述第一介电层上，覆盖所述存储阵列区域以及所述外围电路区域；至少一电容结构，位于所述存储阵列区域内，且所述电容结构包含一电极材料层，埋设在所述第二介电层中；以及一接触结构，包含所述电极材料层。

Description

接触结构以及采用所述接触结构的半导体存储元件
技术领域
本发明涉及一种接触结构以及采用所述接触结构的半导体组件，尤其涉及一种设置于高密度内存阵列中的接触结构，用以拾接内存阵列区域内的地址线(address lines)。
背景技术
为了获得更高密度的动态随机存取内存(DRAM)芯片，半导体工业面临的挑战是如何将存储单元进一步的微缩。过去几十年间，DRAM制造业者已发展出各种存储单元布局，其目的在减少其所占芯片面积。最近的设计是将地址线埋入在硅基材中，再将晶体管及电容制作在上方，构成垂直堆叠，借此提高芯片密度。
目前的DRAM制作中，仍须要额外的工艺步骤，将第一层金属接触连接至靠近阵列边缘的外围区内的地址线，例如，位线。对于非常高密度的内存阵列来说，且各个存储单元大小约为4F2来说(F为工艺最小尺寸)，几乎已无空间在高密度的内存阵列区域内对位线进行拾接，尤其是在阵列中央，故会影响到电路布局的应用，并且使得芯片尺寸无法进一步缩小。由此可知，本技术领域仍需要改良的接触结构，使其可以被布置在高密度内存存储内，用以拾接地址线。
发明内容
本发明的主要目的即在于提供一种改良的接触结构，以解决上述现有技术的不足与缺点。
为达上述目的，本发明公开了一种半导体存储元件，包含有一基材，其上包含一存储阵列区域以及一外围电路区域；一第一介电层，覆盖所述存储阵列区域以及所述外围电路区域；一第二介电层，位于所述第一介电层上，覆盖所述存储阵列区域以及所述外围电路区域；至少一电容结构，位于所述存储阵列区域内，且所述电容结构包含一电极材料层埋设在所述第二介电层中；以及一接触结构，包含所述电极材料层。
为让本发明的上述目的、特征及优点能更为明显易懂，下文特举优选实施方式，并配合附图作详细说明如下。然而如下的优选实施方式与附图仅供参考与说明用，并非用来对本发明加以限制。
附图说明
图1至图5为依据本发明实施方法流程所绘示的与堆叠电容工艺相容的接触结构的横断面示意图。
其中，附图标记说明如下：
10 基材 24 电极材料层
12 第一介电层 26 牺牲层
14 第二介电层 32 第三介电层
16 硬掩膜层 32a 开口
20 插塞 32b 开口
20a 插塞 40 接触材料层
20b 插塞 40a 接触结构
22 开孔 40b 接触结构
22a 开孔 102 存储阵列区域
22b 开孔 104 外围电路区域
具体实施方式
在下文中将参照附图来说明本发明的实施细节，该些附图中的内容构成了本说明书一部分，并以可实行实施例的特例描述方式来绘示。下文的实施例已揭露足够的细节使得本领域的一般技术人员得以具以实施。当然，本发明中也可实行其它的实施例，或是在不悖离文中所述实施例的前提下作出任何结构性、逻辑性、及电性上的改变。因此，下文的细节描述将不欲被视为是一种限定，反之，其中所包含的实施例将由随附的权利要求来加以界定。
文中所提及的“晶圆”或“基材”等名称可以是在表面上已有的材料层或集成电路器件层的半导体基底，其中，基材可以被理解为包括半导体晶圆。基材也可以指在制作过程中的半导体基底或晶圆，其上形成有不同材料层。举例而言，晶圆或基材可以包括掺杂或未掺杂半导体、在绝缘材或半导体底材上形成的外延半导体、及其它已知的半导体结构。
本发明主要公开了一种置于高密度内存阵列中的接触结构，用以拾接内存阵列区域内的地址线，然而，熟习该项技术的人员应能理解所公开的接触结构也可以被应用在内存阵列外的外围电路区域。例如，所公开的接触结构还可能被应用在位线拾接接触、外围电路器件、字线编结(word line stitch)、或特殊的分层数字线的应用。此外，熟习该项技术的人员应理解一个存储单元通常由一个电容及一个晶体管所构成。
本发明特别适合被应用在动态随机存取内存单元结构中，其中具有堆叠式存储单元布局以及埋入式位线或字线，另外，也适合被应用在结合该等动态随机存取内存单元结构的集成电路，其中各个动态随机存取内存单元所占面积大小为4F2(F指工艺的最小尺寸)。
图1至图5例示出一种与目前堆叠电容工艺相容的接触结构的制作方法。如图1所示，先提供一基材10，其中为简化说明，已制作在基材10中的晶体管或绝缘结构将不显示于图中。在基材10表面上形成有一第一介电层12，在第一介电层12中有多个插塞20、20a及20b。举例来说，插塞20及20a是制作在存储阵列区域102内，而插塞20b(仅例示出其中一个)是制作在外围电路区域104内，其中外围电路区域104靠近存储阵列区域102。根据本发明实施例，插塞20、20a及20b可以是钨插塞。根据本发明实施例，插塞20用以耦接一电容，更明确的说，用来耦接存储单元的下电极。插塞20a及20b则作为相对应接触结构的基座，用来拾接如位线或编结字线。根据本发明实施例，插塞20可以电连结至一垂直通道晶体管的漏极或源极(图未示)。
仍然参阅图1，在形成插塞20、20a及20b之后，接着在第一介电层12上沉积一第二介电层14，例如，硼磷硅玻璃(BPSG)等，覆盖在第一介电层12以及插塞20、20a及20b上。然后，在第二介电层14上沉积一硬掩膜层16，例如氮化硅层。第二介电层14及硬掩膜层16的厚度总和大致上决定了在存储阵列区域102内存储胞的电容高度。接着，以光刻及刻蚀工艺在硬掩膜层16及第二介电层14内刻蚀出开孔22、22a及22b，其分别显露出插塞20、20a及20b。
如图2所示，在基材10上先沉积出均厚的电极材料层24，例如氮化钛层或类似材料，使电极材料层24共形的覆盖硬掩膜层16上表面以及开孔22、22a及22b的表面。值得注意的是，电极材料层24并不会填满开孔22、22a及22b。然后，在电极材料层24表面形成一牺牲层26，例如光阻材料，并填满开孔22、22a及22b再以化学机械抛光(CMP)工艺移除开孔22、22a及22b外的牺牲层26及电极材料层24，其中以硬掩膜层16作为抛光停止层。在完成CMP工艺后，硬掩膜层16的上表面约略与牺牲层26的上表面齐平。
如图3所示，接着以低温化学气相沉积工艺在基材10上沉积一第三介电层32，例如二氧化硅或氮化硅。根据本发明实施例，上述低温化学气相沉积工艺可以包括原子层沉积法。第三介电层32覆盖硬掩膜层16的上表面以及牺牲层26的上表面。然后，以光刻及刻蚀工艺在存储阵列区域102内形成开口32a，在外围电路区域104内形成开口32b，其中开口32a显露出位于开孔22a中的牺牲层26，开口32b显露出位于开孔22b中的牺牲层26。接下来，以图案化的第三介电层32作为硬掩膜，进行干刻蚀工艺，将显露出来的牺牲层26从开孔22a及22b完全去除，如此显露出开孔22a及22b的电极材料层24。
如图4所示，接着在基材10上沉积一接触材料层40。由于开孔22a及22b的尺寸通常非常小，因此较佳是采用原子层沉积法来沉积接触材料层40，以确保开孔22a及22b可以被完全填满，而无孔洞或间隙形成。根据本发明实施例，接触材料层40可以是钛、氮化钛或其它材料所构成。
如图5所示，沉积接触材料层40之后，继续进行CMP工艺，去除开孔22a及22b外多出的接触材料层40。在较佳的情况下，可以将第三介电层32在此步骤中一并移除，显露出开孔22的牺牲层26以及硬掩膜层16的上表面，如此在存储阵列区域102内形成接触结构40a，而在外围电路区域104内形成接触结构40b。接续上述接触结构制作方法，还可以另外进行存储阵列区域102内电容其余部分的制作，例如，先将开孔22内的牺牲层26移除以显露出电极材料层24，其可以作为电容的下电极。然后，可以在下电极上形成电容介电层(未示于图中)，再于电容介电层上形成上电极(未示于图中)。
本发明的优点在于接触结构工艺是与电容制作步骤整合，如此一来，第一层金属到位线的接触即可被布置在存储阵列的中央，用以拾接位线或地址线，因此，无需再将位线延伸至外围线路区域，这使得芯片面积可以进一步缩小。此外，在外围电路区域内的接触结构也可以与电容制作步骤整合在一起，如此，传统设置在阵列边缘的拾接接触即可省略以节省成本。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (14)

1.一种半导体存储元件，其特征在于，包含：
一基材，其上包含一存储阵列区域以及一外围电路区域；
一第一介电层，覆盖所述存储阵列区域以及所述外围电路区域；
一第二介电层，位于所述第一介电层上，覆盖所述存储阵列区域以及所述外围电路区域；
至少一电容结构，位于所述存储阵列区域内，且所述电容结构包含一电极材料层，埋设在所述第二介电层中；以及
一接触结构，包含所述电极材料层。
2.根据权利要求1所述的半导体存储元件，其特征在于，所述第一介电层中埋设有一第一插塞以及一第二插塞。
3.根据权利要求2所述的半导体存储元件，其特征在于，所述第一插塞电连接至所述电容结构的下电极。
4.根据权利要求2所述的半导体存储元件，其特征在于，所述第二插塞电连接至所述接触结构。
5.根据权利要求1所述的半导体存储元件，其特征在于，所述接触结构另包含一接触材料层，位于所述电极材料层上。
6.根据权利要求5所述的半导体存储元件，其特征在于，所述电容结构埋设在所述第二介电层的第一开孔中。
7.根据权利要求6所述的半导体存储元件，其特征在于，所述接触结构埋设在所述第二介电层的第二开孔中。
8.根据权利要求7所述的半导体存储元件，其特征在于，所述电极材料层覆盖在所述第一开孔与第二开孔的表面上。
9.根据权利要求2所述的半导体存储元件，其特征在于，所述第一插塞与所述第二插塞为钨插塞。
10.根据权利要求1所述的半导体存储元件，其特征在于，所述接触结构位于所述存储阵列区域内。
11.根据权利要求1所述的半导体存储元件，其特征在于，所述接触结构位于所述外围电路区域内。
12.根据权利要求1所述的半导体存储元件，其特征在于，所述电极材料层包含氮化钛。
13.根据权利要求5所述的半导体存储元件，其特征在于，所述接触结构包含钛或氮化钛。
14.根据权利要求7所述的半导体存储元件，其特征在于，所述接触材料层完全填满所述第二开孔。
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