WO2022064308A1 - 半導体装置の駆動方法 - Google Patents

半導体装置の駆動方法 Download PDF

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Publication number
WO2022064308A1
WO2022064308A1 PCT/IB2021/058181 IB2021058181W WO2022064308A1 WO 2022064308 A1 WO2022064308 A1 WO 2022064308A1 IB 2021058181 W IB2021058181 W IB 2021058181W WO 2022064308 A1 WO2022064308 A1 WO 2022064308A1
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WO
WIPO (PCT)
Prior art keywords
insulator
transistor
oxide
conductor
memory cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2021/058181
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English (en)
French (fr)
Japanese (ja)
Inventor
岡本佑樹
大貫達也
松嵜隆徳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to US18/245,784 priority Critical patent/US12437793B2/en
Priority to KR1020237009957A priority patent/KR20230069128A/ko
Priority to JP2022551440A priority patent/JP7719087B2/ja
Priority to CN202180061513.1A priority patent/CN116114018A/zh
Publication of WO2022064308A1 publication Critical patent/WO2022064308A1/ja
Anticipated expiration legal-status Critical
Priority to JP2025123748A priority patent/JP2025146893A/ja
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2253—Address circuits or decoders
    • G11C11/2257—Word-line or row circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2275—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/221—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using ferroelectric capacitors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2259—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2273—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2293—Timing circuits or methods

Definitions

  • One aspect of the present invention relates to a semiconductor device and a method for driving the semiconductor device.
  • one aspect of the present invention is not limited to the above technical fields.
  • the technical field of the invention disclosed in the present specification and the like relates to a product, a driving method, or a manufacturing method.
  • one aspect of the invention relates to a process, machine, manufacture, or composition (composition of matter). Therefore, more specifically, the technical fields of one aspect of the present invention disclosed in the present specification include semiconductor devices, display devices, liquid crystal display devices, light emitting devices, power storage devices, image pickup devices, storage devices, signal processing devices, and sensors. , Processors, electronic devices, systems, their driving methods, their manufacturing methods, or their inspection methods.
  • a CPU is an aggregate of semiconductor elements formed by processing a semiconductor wafer, having a chipped semiconductor integrated circuit (at least a transistor and a memory), and forming an electrode as a connection terminal.
  • IC chips Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, for example, printed wiring boards, and are used as one of various electronic device components.
  • a technique for forming a transistor by using a semiconductor thin film formed on a substrate having an insulating surface is attracting attention.
  • the transistor is widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also referred to simply as display devices).
  • ICs integrated circuits
  • image display devices also referred to simply as display devices.
  • Silicon-based semiconductor materials, oxide semiconductors, and the like are known as semiconductor thin films applicable to transistors.
  • Non-Patent Document 1 research and development of memory cells using a ferroelectric substance (ferroelectric) are being actively carried out. Also, for the next generation of ferroelectric memory, research on ferroelectric HfO 2 -based materials (Non-Patent Document 2), research on the ferroelectricity of hafnium oxide thin films (Non-Patent Document 3), and HfO. 2 Research on hafnium oxide, such as the ferroelectricity of thin films (Non-Patent Document 4), is also being actively conducted.
  • the polarization inversion in the ferroelectric substance may be repeated. As a result, fatigue deterioration may occur, and the polarization of the ferroelectric substance may be reduced when data is written to the memory cell. Therefore, the reliability of the semiconductor device may decrease.
  • One aspect of the present invention is to provide a highly reliable semiconductor device and a method for driving the same.
  • one aspect of the present invention is to provide a novel semiconductor device and a method for driving the same.
  • the problems of one aspect of the present invention are not limited to the problems listed above.
  • the issues listed above do not preclude the existence of other issues.
  • Other issues are issues not mentioned in this item, which are described below. Issues not mentioned in this item can be derived from the description of the description, drawings, etc. by those skilled in the art, and can be appropriately extracted from these descriptions.
  • one aspect of the present invention solves at least one of the above-listed problems and other problems. It should be noted that one aspect of the present invention does not need to solve all of the above-listed problems and other problems.
  • One aspect of the present invention is a method of driving a semiconductor device provided with a memory cell having a strong dielectric capacitor, in which binary data is written to the memory cell in the first period and the memory cell is written in the second period.
  • This is a method for driving a semiconductor device, in which binary data is read out from the above and the binary data is written back to the memory cell by causing polarization inversion in the strong dielectric capacitor in the third period.
  • the polarization inversion may occur in the ferroelectric capacitor in the third period regardless of the value of the binary data.
  • the semiconductor device has a reference memory cell, writes reference binary data to the reference memory cell in the first period, and references binary data from the reference memory cell in the second period. Is read, and in the second period, the logical operation of the binary data read from the memory cell and the reference binary data read from the reference memory cell may be performed.
  • the logical operation may be an exclusive OR.
  • the memory cell has a first transistor, a second transistor, and a third transistor, and one of the source and drain of the first transistor is the gate of the second transistor.
  • one of the sources or drains of the second transistor is electrically connected to one of the sources or drains of the third transistor and is electrically connected to one of the electrodes of the third transistor.
  • the other of the source or drain is electrically connected to the other of the source or drain of the first transistor, with the first transistor on and the third transistor off during the first and third periods.
  • the first transistor may be turned off and the third transistor may be turned on.
  • the ferroelectric capacitor may have a dielectric, and the dielectric may have hafnium oxide and / or zirconium oxide.
  • one aspect of the present invention is a method for driving a semiconductor device provided with a memory cell having a first strong dielectric capacitor and a reference memory cell having a second strong dielectric capacitor, and the first period.
  • the first binary data is written to the memory cell and the first reference binary data is written to the reference memory cell, and in the second period, the first binary data from the memory cell is written.
  • Reading and reading the first reference binary data from the reference memory cell are performed, and in the third period, the logical calculation of the first binary data and the first reference binary data is performed, and the first In the period of 4, the second binary data is written to the memory cell and the second reference binary data is written to the reference memory cell, and the value of the first binary data and the second 2 are performed.
  • It is a method of driving a semiconductor device, which is different from the value of the value data and different from the value of the first reference binary data and the value of the second reference binary data.
  • the semiconductor device has a first sense amplifier circuit and a second sense amplifier circuit, and the first sense amplifier circuit is electrically connected to a memory cell and has a second sense amplifier.
  • the circuit is electrically connected to the reference memory cell, and in the third period, the first sense amplifier circuit and the second sense amplifier circuit may be put into an activated state.
  • the memory cell has a first transistor, a second transistor, and a third transistor, and one of the source and drain of the first transistor is the gate of the second transistor.
  • one of the sources or drains of the second transistor is electrically connected to one of the sources or drains of the third transistor, which is electrically connected to one of the electrodes of the first strong dielectric capacitor.
  • the other of the source or drain of the transistor and the other of the source or drain of the third transistor are electrically connected to the first sense amplifier circuit, and in the first period and the fourth period, the first The transistor may be turned on, the third transistor may be turned off, and the first transistor may be turned off and the third transistor may be turned on in the second and third periods.
  • the first ferroelectric capacitor has a first dielectric
  • the second ferroelectric capacitor has a second dielectric
  • the first dielectric and the second dielectric.
  • the dielectric may have hafnium oxide and / or zirconium oxide.
  • the logical operation may be an exclusive OR.
  • a highly reliable semiconductor device and a driving method thereof can be provided.
  • a novel semiconductor device and a driving method thereof can be provided.
  • the effect of one aspect of the present invention is not limited to the effects listed above.
  • the effects listed above do not preclude the existence of other effects.
  • the other effects are the effects not mentioned in this item, which are described below. Effects not mentioned in this item can be derived from the description in the specification, drawings, etc. by those skilled in the art, and can be appropriately extracted from these descriptions.
  • one aspect of the present invention has at least one of the above-listed effects and other effects. Therefore, one aspect of the present invention may not have the effects listed above in some cases.
  • FIG. 1 is a block diagram showing a configuration example of a semiconductor device.
  • 2A and 2B are circuit diagrams showing a configuration example of a memory cell.
  • FIG. 3A is a graph showing an example of the hysteresis characteristic of the dielectric.
  • 3B1 and 3B2 are circuit diagrams showing an example of a method of driving a memory cell.
  • 4A and 4B are timing charts showing an example of a memory cell driving method.
  • FIG. 5A is a circuit diagram showing a configuration example of a memory cell.
  • 5B1 and 5B2 are timing charts showing an example of a memory cell driving method.
  • FIG. 6 is a schematic cross-sectional view showing a configuration example of a semiconductor device.
  • FIG. 7A to 7C are schematic cross-sectional views showing a configuration example of a transistor.
  • FIG. 8 is a schematic cross-sectional view showing a configuration example of a semiconductor device.
  • 9A and 9B are schematic cross-sectional views showing a configuration example of a transistor.
  • FIG. 10 is a schematic cross-sectional view showing a configuration example of a transistor.
  • 11A to 11C are schematic cross-sectional views showing a configuration example of a transistor.
  • FIG. 12 is a schematic cross-sectional view showing a configuration example of a transistor.
  • 13A and 13B are schematic cross-sectional views showing a configuration example of a transistor.
  • 14A and 14B are schematic cross-sectional views showing a configuration example of a transistor.
  • FIG. 15 is a schematic cross-sectional view showing a configuration example of a transistor.
  • FIG. 16 is a schematic cross-sectional view showing a configuration example of a semiconductor device.
  • FIG. 17 is a schematic cross-sectional view showing a configuration example of a semiconductor device.
  • FIG. 18A is a diagram for explaining the classification of the crystal structure of IGZO
  • FIG. 18B is a diagram for explaining the XRD spectrum of crystalline IGZO
  • FIG. 18C is a diagram for explaining the microelectron diffraction pattern of crystalline IGZO.
  • .. 19A is a perspective view showing an example of a semiconductor wafer
  • FIG. 19B is a perspective view showing an example of a chip
  • FIG. 20 is a block diagram illustrating a CPU.
  • 21A to 21J are perspective views or schematic views illustrating an example of the product.
  • 22A to 22E are perspective views or schematic views illustrating an example of the product.
  • a metal oxide is a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS) and the like. For example, when a metal oxide is used for the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can form a channel forming region of a transistor having at least one of an amplification action, a rectifying action, and a switching action, the metal oxide is referred to as a metal oxide semiconductor. be able to. Further, when the term "OS transistor" is used, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor.
  • a metal oxide having nitrogen may also be collectively referred to as a metal oxide. Further, the metal oxide having nitrogen may be referred to as a metal oxynitride.
  • the configuration shown in each embodiment can be appropriately combined with the configuration shown in other embodiments to form one aspect of the present invention. Further, when a plurality of configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other.
  • the content described in one embodiment (may be a part of the content) is different from the content described in the embodiment (may be a part of the content) and one or more different implementations. It is possible to apply, combine, or replace at least one content with the content described in the form of (may be a part of the content).
  • figure (which may be a part) described in one embodiment is different from another part of the figure, another figure (which may be a part) described in the embodiment, and one or more different figures.
  • the figure (which may be a part) described in the embodiment is different from another part of the figure, another figure (which may be a part) described in the embodiment, and one or more different figures.
  • more figures can be formed.
  • the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.
  • the drawings schematically show ideal examples, and are not limited to the shapes, values, and the like shown in the drawings. For example, it is possible to include variations in the signal, voltage, or current due to noise, or variations in the signal, voltage, or current due to timing deviation.
  • the ordinal numbers “first”, “second”, and “third” are added to avoid confusion of the components. Therefore, the number of components is not limited. Moreover, the order of the components is not limited. For example, the component referred to in “first” in one of the embodiments of the present specification and the like may be the other embodiment or the component referred to in “second” in the scope of claims. There can also be. Further, for example, the component referred to in “first” in one of the embodiments of the present specification and the like may be omitted in another embodiment or in the scope of claims.
  • the terms “upper” and “lower” do not limit the positional relationship of the components to be directly above or directly below and to be in direct contact with each other.
  • the electrode B does not have to be formed in direct contact with the insulating layer A, and another configuration is formed between the insulating layer A and the electrode B. Do not exclude those that contain elements.
  • the terms “film”, “layer” and the like can be interchanged with each other depending on the situation.
  • the terms “insulating layer” and “insulating film” may be changed to the term "insulator”.
  • Electrode may be used as part of a “wiring” and vice versa.
  • the term “electrode” or “wiring” includes the case where a plurality of “electrodes” or “wiring” are integrally formed.
  • a “terminal” may be used as part of a “wiring” or “electrode” and vice versa.
  • the term “terminal” includes a case where a plurality of "electrodes", “wiring”, “terminals” and the like are integrally formed.
  • the "electrode” can be a part of “wiring” or “terminal”, and for example, “terminal” can be a part of “wiring” or “electrode”.
  • terms such as “electrode”, “wiring”, and “terminal” may be replaced with terms such as "area” in some cases.
  • terms such as “wiring”, “signal line”, and “power line” can be interchanged with each other in some cases or depending on the situation.
  • the term “wiring” may be changed to a term such as "power line”.
  • the reverse is also true, and it may be possible to change terms such as “signal line” and “power line” to the term “wiring”.
  • a term such as “power line” may be changed to a term such as "signal line”.
  • terms such as “signal line” may be changed to terms such as "power line”.
  • the term “potential” applied to the wiring may be changed to the term “signal” or the like in some cases or depending on the situation.
  • terms such as “signal” may be changed to the term “potential”.
  • One aspect of the present invention relates to a semiconductor device having a memory cell, for example, a storage device.
  • the memory cell of the semiconductor device according to one aspect of the present invention is provided with a capacity using a material capable of having ferroelectricity as a dielectric.
  • binary data is written and held in a memory cell, and then the binary data is read and written back.
  • the dielectric is within the period of performing one read and one write back. Invert the body once.
  • the number of times of the polarization reversal of the dielectric when the value of the binary data held in the memory cell is "0" and the number of times of the polarization reversal of the dielectric when the value is "1" are made the same. ..
  • the dielectric is read and written back without polarization inversion, for example, the binary data held in the memory cell.
  • the reliability of the semiconductor device can be improved as compared with the case where the dielectric is polarized and inverted twice in total to read and write back.
  • FIG. 1 is a block diagram showing a configuration example of a semiconductor device 10 which is a semiconductor device according to an aspect of the present invention.
  • the semiconductor device 10 can be, for example, a storage device.
  • the semiconductor device 10 is provided with a memory cell array MCA in which memory cell MCs of m rows and n + 1 columns (m and n are integers of 1 or more) are arranged in a matrix. Further, the semiconductor device 10 includes a word line drive circuit WD, a plate line drive circuit PD, a potential generation circuit SD, and a bit line drive circuit BD.
  • the word line drive circuit WD is electrically connected to the memory cell MC via the wiring WWL, and is also electrically connected to the memory cell MC via the wiring RWL.
  • the plate wire drive circuit PD is electrically connected to the memory cell MC via the wiring PL.
  • the potential generation circuit SD is electrically connected to the memory cell MC via the wiring SL.
  • the bit line drive circuit BD is electrically connected to the memory cell MC via the wiring BL.
  • the memory cell MC in the same row can be electrically connected to the word line drive circuit WD via the same wiring WWL and the same wiring RWL, and the plate line drive circuit can be electrically connected via the same wiring PL. It can be electrically connected to the PD. Further, the memory cells MC in the same row can be electrically connected to the bit line drive circuit BD via the same wiring BL.
  • the memory cell MC in the first row and the first column is described as the memory cell MC [1,1] and the memory cell MC in the m row n + 1 column is referred to as the memory cell MC [m, n + 1]. Described and shown. Further, for example, the wiring WWL, wiring RWL, and wiring PL electrically connected to the memory cell MC in the first row are described as wiring WWL [1], wiring RWL [1], and wiring PL [1], respectively. The wiring WWL, wiring RWL, and wiring PL electrically connected to the memory cell MC in the m-th row are described as wiring WWL [m], wiring RWL [m], and wiring PL [m], respectively. Shown.
  • the wiring BL electrically connected to the memory cell MC in the first row is described as wiring BL [1]
  • the wiring BL electrically connected to the memory cell MC in the n + 1th column is designated as wiring BL [1]. It is described as wiring BL [n + 1].
  • the same description may be made for other elements.
  • the word line drive circuit WD has a function of controlling the potential of the wiring WWL and the potential of the wiring RWL. Specifically, the word line drive circuit WD has a function of selecting a memory cell MC for writing data by controlling the potential of the wiring WWL, and a memory for reading data by controlling the potential of the wiring RWL. It has a function of selecting a cell MC.
  • the plate wire drive circuit PD has a function of controlling the potential of the wiring PL.
  • the potential generation circuit SD has a function of controlling the potential of the wiring SL.
  • the potential generation circuit SD can supply a constant potential to the wiring SL, for example, and can supply a ground potential to the wiring SL, for example.
  • the bit line drive circuit BD has a function of generating data to be written in the memory cell MC and supplying the data to the memory cell MC in a predetermined column. Further, the bit line drive circuit BD has a function of reading and outputting the data written in the memory cell MC.
  • the bit line drive circuit BD includes a sense amplifier circuit SA [1] to a sense amplifier circuit SA [n + 1], a latch circuit LAT, and a logic operation circuit LC.
  • the sense amplifier circuit SA is electrically connected to the wiring BL, the wiring REFL, the wiring ENL, and the wiring PREL. Further, the sense amplifier circuit SA [1] to the sense amplifier circuit SA [n] are electrically connected to the logic operation circuit LC, and the sense amplifier circuit SA [n + 1] is connected to the logic operation circuit LC via the latch circuit LAT. It is electrically connected.
  • the logical operation circuit LC is electrically connected to the wiring OUT [1] to the wiring OUT [n].
  • the latch circuit LAT and the logical operation circuit LC may be outside the bit line drive circuit BD. Further, the semiconductor device 10 does not have to have the latch circuit LAT. When the semiconductor device 10 does not have the latch circuit LAT, the data output from the sense amplifier circuit SA [n + 1] can be directly input to the logic circuit LC, for example.
  • the sense amplifier circuit SA has a function of amplifying the difference between the potential of the wiring BL and the potential of the wiring REFL. For example, when the potential of the wiring BL is higher than the potential of the wiring REFL, the sense amplifier circuit SA can output a high potential. On the other hand, when the potential of the wiring BL is lower than the potential of the wiring REFL, the sense amplifier circuit SA can output a low potential. As a result, the bit line drive circuit BD can write binary data, specifically binary digital data, to the memory cell MC, and can read the binary data written to the memory cell MC. For example, when the potential of the wiring BL is higher than the potential of the wiring REFL, it can be assumed that "0" is written to the memory cell MC or "0" is read. On the other hand, when the potential of the wiring BL is lower than the potential of the wiring REFL, it can be assumed that "1" is written to the memory cell MC or "1" is read.
  • An enable signal that controls whether or not to activate the sense amplifier circuit SA can be supplied to the wiring ENL.
  • the enable signal can be, for example, a binary digital signal.
  • the sense amplifier circuit SA can be activated, and the difference between the potential of the wiring BL and the potential of the wiring REFL is amplified.
  • the sense amplifier circuit SA can be in the deactivated state, and the above amplification is not performed.
  • a precharge signal that controls whether or not to precharge the potentials of the wiring BL and the wiring REFL can be supplied to the wiring PREL.
  • the precharge signal can be, for example, a binary digital signal.
  • the wiring BL can be precharged to a high potential.
  • the potential of the wiring REFL is the potential of the wiring BL when the data having a value of "0" is read from the memory cell MC, and the data having a value of "1" is read from the memory cell MC. It can be a potential between the potential of the wiring BL in the case.
  • the potentials supplied to the wiring ENL [1] to the wiring ENL [n + 1] may be common to each other. In this case, the wiring ENL [1] to the wiring ENL [n + 1] can be electrically connected to each other. Further, the potentials supplied to the wiring PREL [1] to the wiring PREL [n + 1] may be common to each other. In this case, the wiring PREL [1] to the wiring PREL [n + 1] can be electrically connected to each other.
  • the latch circuit LAT has a function of holding data output from the sense amplifier circuit SA [n + 1]. That is, the latch circuit LAT can hold the data output from the memory cell MC in the n + 1th column.
  • the latch circuit LAT can have m latch circuits capable of holding 1-bit data. As a result, the latch circuit LAT can hold all the data read from the memory cells MC [1, n + 1] to the memory cells MC [m, n + 1].
  • the logical operation circuit LC has a function of performing a logical operation using the input data.
  • the logical operation circuit LC has, for example, a function of performing a logical operation of the data output from the sense amplifier circuit SA and the data output from the latch circuit LAT.
  • the data representing the calculation result is output from the wiring OUT.
  • the logical operation circuit LC performs a logical operation of, for example, the data output from the sense amplifier circuit SA [1] and the data output from the latch circuit LAT, and transfers the data representing the operation result from the wiring OUT [1]. Can be output.
  • the logical operation circuit LC performs a logical operation of, for example, the data output from the sense amplifier circuit SA [n] and the data output from the latch circuit LAT, and wires the data representing the operation result to the wiring OUT [n]. ] Can be output.
  • the logical operation circuit LC has logic with the data output from the sense amplifier circuit SA [n + 1] for each of the data output from the sense amplifier circuit SA [1] to the sense amplifier circuit SA [n]. Perform the operation. Further, the sense amplifier circuit SA [n + 1] has a function of amplifying the data read from the memory cell MC in the n + 1 column. From the above, the memory cell MC [1, n + 1] to the memory cell MC [m, n + 1] can be said to be a reference memory cell. Further, the data written in the reference memory cell and the data read from the reference memory cell can be referred to as reference data. Further, the binary reference data can be referred to as reference binary data.
  • FIG. 2A is a circuit diagram showing a configuration example of the memory cell MC.
  • the memory cell MC has a transistor M1, a transistor M2, a transistor M3, and a capacitance FEC.
  • the transistors M1 to M3 will be described as being n-channel transistors, but at least a part of the transistors M1 to M3 is a p-channel transistor by appropriately reversing the magnitude relationship of the potentials.
  • the following description can be applied.
  • the transistor M2 and the transistor M3 are p-channel type transistors, the potential of the wiring SL can be high.
  • One of the source and drain of the transistor M1 is electrically connected to the gate of the transistor M2.
  • the gate of the transistor M2 is electrically connected to one electrode of the capacitive FEC.
  • One of the source or drain of the transistor M2 is electrically connected to one of the source or drain of the transistor M3.
  • the other of the source or drain of the transistor M1 and the other of the source or drain of the transistor M3 are electrically connected to the wiring BL.
  • the other of the source or drain of the transistor M2 is electrically connected to the wiring SL.
  • the gate of the transistor M1 is electrically connected to the wiring WWL.
  • the gate of the transistor M3 is electrically connected to the wiring RWL.
  • the other electrode of the capacitive FEC is electrically connected to the wiring PL.
  • a node in which one of the source or drain of the transistor M1, the gate of the transistor M2, and one electrode of the capacitive FEC is electrically connected is referred to as a node N.
  • the transistor M1 and the transistor M3 have a function as a switching element.
  • the transistor M1 can be turned on by setting the potential of the gate of the transistor M1 to a high potential, and the transistor M1 can be turned off by setting the potential of the gate of the transistor M1 to a low potential. can do. That is, the transistor M1 can be turned on by setting the potential of the wiring WWL to a high potential, and the transistor M1 can be turned off by setting the potential of the wiring WWL to a low potential.
  • the transistor M3 can be turned on by setting the potential of the gate of the transistor M3 to a high potential, and the transistor M3 can be turned off by setting the potential of the gate of the transistor M3 to a low potential. Can be done.
  • the transistor M3 can be turned on by setting the potential of the wiring RWL to a high potential, and the transistor M3 can be turned off by setting the potential of the wiring RWL to a low potential. Since the transistor M1 and the transistor M3 have a function as a switching element, it is preferable to drive the transistor M1 and the transistor M3 in a linear region.
  • the transistor M2 has a function as an amplification transistor that amplifies the potential held in the node N. Therefore, it is preferable to drive the transistor M2 in the saturation region.
  • Capacitance FEC is a capacitance having a material that can have ferroelectricity as a dielectric.
  • a capacitance using a material capable of having ferroelectricity as a dielectric is referred to as a ferroelectric capacitor.
  • Materials that can have strong dielectric properties include hafnium oxide, zirconium oxide, HfZrOX ( X is a real number larger than 0), hafnium oxide and element J1 (here, element J1 is zirconium (Zr), silicon.
  • element J1 is zirconium (Zr), silicon.
  • Si aluminum (Al), gadrinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.
  • element J2 element J2 here is hafnium) to zirconium oxide.
  • Hf silicon
  • Si aluminum (Al), gadrinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.
  • PbTIO X barium titanate strontium (BST), barium titanate, lead zirconate titanate (PZT), strontium bismuthate tantanate (SBT), bismuth ferrite (BFO).
  • BST barium titanate strontium
  • PZT barium titanate
  • SBT strontium bismuthate tantanate
  • BFO bismuth ferrite
  • Barium titanate, etc., and a piezoelectric ceramic having a perovskite structure may be used.
  • a laminated structure composed of a plurality of materials selected from the materials listed above or a plurality of materials selected from the materials listed above may be used. can.
  • the crystal structure (characteristics) of hafnium oxide, zirconium oxide, HfZrOX , and materials obtained by adding the element J1 to hafnium oxide may change not only depending on the film forming conditions but also depending on various processes.
  • a material exhibiting ferroelectricity is referred to as a ferroelectric substance, but also a material capable of having ferroelectricity.
  • hafnium oxide As a material capable of having ferroelectricity, hafnium oxide, or a material having hafnium oxide and zirconium oxide is preferable because it can have ferroelectricity even when processed into a thin film of several nm.
  • the film thickness of the material having ferroelectricity may be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, still more preferably 10 nm or less (typically 2 nm or more and 9 nm or less).
  • HfZrOX is used as a material capable of having ferroelectricity
  • a material capable of having ferroelectricity is formed by using the thermal ALD method
  • a material containing no hydrocarbon also referred to as Hydro Carbon, HC
  • HC Hydro Carbon
  • the crystallization of the material which may have a ferroelectricity may be inhibited. Therefore, as described above, it is preferable to reduce the concentration of either one or both of hydrogen and carbon in the material which may have ferroelectricity by using a precursor containing no hydrocarbon.
  • a precursor containing no hydrocarbon a chlorine-based material can be mentioned.
  • HfZrO x hafnium oxide and zirconium oxide
  • HfCl 4 and / or ZrCl 4 may be used as the precursor.
  • the oxidizing agent of the thermal ALD method is not limited to this.
  • the oxidizing agent in the thermal ALD method may contain one or more selected from O 2 , O 3 , N 2 O, NO 2 , H 2 O, and H 2 O 2 .
  • the crystal structure of the material capable of having ferroelectricity is not particularly limited.
  • the crystal structure of the material capable of having strong dielectric property may be one or more selected from cubic, tetragonal, orthorhombic, and monoclinic.
  • a material capable of having ferroelectricity it is preferable to have an orthorhombic crystal structure because ferroelectricity is exhibited.
  • a composite structure having an amorphous structure and a crystal structure may be used as a material capable of having ferroelectricity.
  • a material that can have ferroelectricity is an insulator, which has the property that polarization occurs inside when an electric field is applied from the outside, and polarization remains even if the electric field is zero. Therefore, it is a non-volatile storage element. Can be applied as. Therefore, by using the material as a dielectric sandwiched between a pair of electrodes of the capacitance, the capacitance can be a "capacitor capable of having a ferroelectricity" or a "ferroelectric capacitor". Further, in the present specification and the like, a material capable of having ferroelectricity may be contained between one electrode of the capacitor and the other electrode.
  • a storage circuit using a capacitor capable of having ferroelectricity may be referred to as FeRAM (Ferroelectric Random Access Memory), a ferroelectric memory, or the like.
  • the circuit symbol of the ferroelectric capacitor (for example, the capacitance FEC) is the circuit symbol of the capacitance with diagonal lines added as shown in FIG. 2A. Further, as another circuit symbol, as shown in FIG. 2B, a plurality of diagonal lines may be added between two lines parallel to each other in the capacity circuit symbol.
  • a transistor having silicon in the channel forming region (hereinafter referred to as a Si transistor) can be applied.
  • a transistor having silicon in the channel forming region hereinafter referred to as a Si transistor
  • the on-current of the transistor M1 to the transistor M3 can be increased.
  • the memory cell MC can be driven at high speed, so that the semiconductor device 10 can be driven at high speed.
  • a transistor having amorphous silicon in the channel forming region may be applied as the transistor M1 to the transistor M3, a transistor having amorphous silicon in the channel forming region may be applied.
  • a transistor other than the Si transistor may be applied as the transistor M1 to the transistor M3.
  • an OS transistor can be applied as the transistor M1 to the transistor M3.
  • the OS transistor has a characteristic of having a high withstand voltage. Therefore, by using the transistors M1 to M3 as OS transistors, a high voltage can be applied to the transistors M1 to M3 even if the transistors M1 to M3 are miniaturized. By miniaturizing the transistors M1 to M3, the occupied area of the memory cell MC can be reduced. Therefore, the memory cells MC can be arranged at a high density. As a result, the semiconductor device 10 can be made into a semiconductor device having a large storage capacity.
  • the transistors M1 to M3 of the memory cell MC are used as OS transistors, and the transistors of the word line drive circuit WD, the plate line drive circuit PD, the potential generation circuit SD, and the bit line drive circuit BD are used as Si transistors. Can be done.
  • the memory cell array MCA can be stacked so as to have a region overlapping with the word line drive circuit WD, the plate line drive circuit PD, the potential generation circuit SD, or the bit line drive circuit BD.
  • the semiconductor device 10 can be miniaturized while maintaining the storage capacity of the semiconductor device 10.
  • the transistor included in the word line drive circuit WD, the plate line drive circuit PD, the potential generation circuit SD, and the bit line drive circuit BD is an OS transistor, these circuits and the memory cell array MCA are used. It can be laminated and provided so as to have overlapping regions.
  • the metal oxide contained in the channel forming region of the transistors M1 to M3 is preferably an oxide containing at least one of indium, gallium, and zinc.
  • indium, element M includes, for example, aluminum, gallium, ittrium, copper, vanadium, berylium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, lanthanum, etc.
  • cerium, neodymium, hafnium, tantalum, tungsten, gallium and the like can be mentioned), and oxides containing at least one of zinc may be used.
  • all of the transistors M1 to M3 do not have to be the same type of transistors.
  • a part of the transistors M1 to M3 may be a Si transistor, and the rest may be an OS transistor.
  • the transistor to which a high voltage is applied may be an OS transistor, and the other transistor may be a Si transistor.
  • the dielectric of a ferroelectric capacitor has a hysteresis characteristic.
  • FIG. 3A is a graph showing an example of the hysteresis characteristic.
  • the horizontal axis represents the voltage applied to the dielectric.
  • the voltage can be, for example, a value obtained by subtracting the potential of the other electrode of the capacitive FEC from the potential of one electrode of the capacitive FEC. That is, for example, the value obtained by subtracting the potential of the wiring PL from the potential of the node N can be used as the voltage applied to the dielectric.
  • the vertical axis indicates the polarization of the dielectric, and when the value is positive, the negative charge is biased to one electrode side of the capacitive FEC, and the positive charge is biased to the other electrode side of the capacitive FEC. Is shown. On the other hand, when the polarization has a negative value, it indicates that the negative charge is biased toward the other electrode side of the capacitive FEC and the positive charge is biased toward one electrode side of the capacitive FEC.
  • the voltage shown on the horizontal axis of the graph of FIG. 3A may be a value obtained by subtracting the potential of one electrode of the capacitive FEC from the potential of the other electrode of the capacitive FEC.
  • the polarization shown on the vertical axis of the graph of FIG. 3A is set as a positive value when the negative charge is biased to the other electrode side of the capacitive FEC and the positive charge is biased to one electrode side of the capacitive FEC, and the negative charge is set. May be biased toward one electrode side of the capacitive FEC, and may be a negative value when the positive charge is biased toward the other electrode side of the capacitive FEC.
  • the hysteresis characteristic of the dielectric can be represented by the curve 11 and the curve 12.
  • VSP and ⁇ VSP can be said to be saturated polarization voltages.
  • VSP may be referred to as a first saturated polarization voltage
  • ⁇ VSP may be referred to as a second saturation polarization voltage.
  • Vc the voltage applied to the dielectric when the polarization of the dielectric changes along the curve 11 and the polarization of the dielectric is 0
  • ⁇ Vc the voltage applied to the dielectric when the polarization of the dielectric changes along the curve 12 and the polarization of the dielectric is 0
  • Vc and -Vc can be said to be withstand voltage. It can be said that the value of Vc and the value of -Vc are values between -VSP and VSP.
  • Vc may be referred to as a first coercive voltage
  • ⁇ Vc may be referred to as a second coercive voltage.
  • the absolute value of the first saturated polarization voltage and the absolute value of the second saturated polarization voltage may be different. Further, the absolute value of the first coercive voltage and the absolute value of the second coercive voltage may be different.
  • the voltage applied to the dielectric of the capacitive FEC shall indicate the value obtained by subtracting the potential of the wiring PL from the potential of the node N.
  • 3B1 and 3B2 are circuit diagrams showing an example of a driving method of the semiconductor device 10.
  • "H” indicates a high potential
  • "L” indicates a low potential.
  • the same description is given in other drawings showing the driving method of the memory cell MC and the like.
  • the transistors in the off state are marked with a cross. Further, the voltage applied to the dielectric of the capacitive FEC is shown by the alternate long and short dash line for emphasis.
  • FIG. 3B1 shows an example of writing binary data having a value of “0” to the memory cell MC
  • FIG. 3B2 shows an example of writing binary data having a value of “1” to the memory cell MC.
  • the period during which the operation shown in FIG. 3B1 or FIG. 3B2 is performed can be referred to as a writing period.
  • the potential of the wiring WWL is set to a high potential and the potential of the wiring RWL is set to a low potential during the writing period.
  • the transistor M1 is turned on and the transistor M3 is turned off.
  • the potential of the wiring BL is set to GND and the potential of the wiring PL is set to Vw, as shown in FIG. 3B1.
  • GND can be, for example, a ground potential.
  • Vw is preferably VSP or higher.
  • the GND does not necessarily have to be the ground potential as long as the semiconductor device 10 can be driven so as to satisfy the gist of one aspect of the present invention.
  • Vw is a potential having a height higher than VSS and GND is a ground potential. Further, the potentials supplied to the wiring BL and the wiring PL will be described with Vw as a high potential and GND as a low potential.
  • a voltage ⁇ Vw is applied to the dielectric of the capacitive FEC.
  • the positive charge is biased to one electrode side (node N side) of the capacitive FEC, and the negative charge is biased to the other electrode side (wiring PL side) of the capacitive FEC. Therefore, binary data having a value of "0" can be written to the memory cell MC.
  • the voltage applied to the dielectric of the capacitive FEC is increased, the polarization of the dielectric increases along the curve 11 when the voltage of the dielectric is less than VSS.
  • the potential of the wiring BL is Vw and the potential of the wiring PL is GND, as shown in FIG. 3B2.
  • the voltage Vw is applied to the dielectric of the capacitive FEC. Therefore, the negative charge is biased to one electrode side (node N side) of the capacitive FEC, and the positive charge is biased to the other electrode side (wiring PL side) of the capacitive FEC.
  • binary data having a value of "1" can be written to the memory cell MC.
  • the voltage applied to the dielectric of the capacitive FEC is lowered, the polarization of the dielectric decreases along the curve 12 when the voltage of the dielectric is higher than ⁇ VSP.
  • FIGS. 4A and 4B are timing charts showing a driving method of the semiconductor device 10.
  • FIG. 4A shows an example in which binary data with a value of “0” is written and held in the memory cell MC, and the binary data is read and written back from the memory cell MC.
  • FIG. 4B shows an example in which binary data with a value of “1” is written and held in the memory cell MC, and the binary data is read and written back from the memory cell MC.
  • the transistors M1 to M3 are all n-channel transistors.
  • the potential of the wiring WWL is set to a low potential at time T10 to time T11.
  • the transistor M1 is turned off.
  • the potential of the wiring RWL is set to a low potential.
  • the transistor M3 is turned off.
  • the potential of the wiring PL is set to GND.
  • the potential of the wiring ENL is set to a low potential.
  • the sense amplifier circuit SA becomes inactive. It is assumed that the potential of the node N is GND.
  • the potential of the wiring PREL is set to a high potential.
  • the wiring BL and the wiring REFL are precharged. Therefore, the potential of the wiring BL becomes, for example, Vw, which is higher than the potential of the wiring SL. Further, the potential of the wiring REFL becomes the potential between GND and Vw.
  • the potential of the wiring RWL is set to a high potential.
  • the transistor M3 is turned on.
  • the potential of the wiring PREL is set to a low potential. As a result, the precharging of the wiring BL and the wiring REFL is completed.
  • the potential of the wiring PL is Vw.
  • the potential of the node N rises due to capacitive coupling by capacitive FEC or the like.
  • the capacitive coupling coefficient of the node N is less than 1 and the potential of the node N before the time T12 is GND, the potential of the node N after the potential rise is lower than Vw. It is assumed that the polarization inversion does not occur in the dielectric of the capacitive FEC even if the potential of the node N rises. That is, it is assumed that the value obtained by subtracting the potential of the wiring PL from the potential of the node N is Vc or less.
  • inversion of polarization in a dielectric of a ferroelectric capacitor such as a capacitive FEC may cause polarization inversion in the ferroelectric capacitor.
  • the potential of the wiring PL may be set to Vw at time T11 to time T12, and the potential of the wiring RWL may be set to high potential at time T12 to time T13. Further, the potential of the wiring PREL may be kept high at the time T11 to the time T12, and the potential of the wiring PREL may be set to the low potential at the time T12 to the time T13.
  • the transistor M3 is turned on and the potential of the node N rises. Since the potential of the wiring BL is precharged to be higher than the potential of the wiring SL, the potential of the wiring BL decreases according to the potential of the node N electrically connected to the gate of the transistor M2. As a result, it can be assumed that the data having a value of "0" held in the memory cell MC is read from the memory cell MC.
  • the potential of the wiring ENL is set to a high potential.
  • the sense amplifier circuit SA is activated, and the difference between the potential of the wiring BL and the potential of the wiring REFL is amplified.
  • the potential of the wiring BL is higher than the potential of the wiring REFL at the time when the wiring ENL becomes high potential
  • the potential of the wiring BL becomes Vw which is a high potential
  • the potential of the wiring REFL is low potential. It becomes GND.
  • the data read from the memory cell MC and having a value of "0" can be output from the sense amplifier circuit SA.
  • the time T10 to the time T14 can be said to be a read period.
  • the time T11 to the time T14 excluding the time T10 to the time T11, which is the period for precharging the wiring BL can be referred to as a read period.
  • the potential of the wiring WWL is set to a high potential.
  • the transistor M1 is turned on.
  • the potential of the wiring RWL is set to a low potential.
  • the transistor M3 is turned off.
  • the transistor M1 is turned on, the potential of the node N becomes Vw, which is the potential of the wiring BL.
  • the potential of the node N and the potential of the wiring PL are both Vw. Therefore, the voltage applied to the dielectric of the capacitive FEC is 0V. As shown in FIG. 3A and the like, even if the voltage applied to the dielectric of the capacitive FEC becomes 0V, the polarization inversion does not occur in the dielectric.
  • the potential of the wiring PL is set to GND.
  • the voltage applied to the dielectric of the capacitive FEC becomes Vw. Therefore, the polarization inversion occurs in the dielectric, and the data having a value of "1" is written in the memory cell MC. That is, the binary data obtained by inverting the value of the binary data read from the memory cell MC at the time T10 to the time T14 is written back to the memory cell MC.
  • the potential of the wiring ENL is set to a low potential.
  • the sense amplifier circuit SA becomes inactive.
  • the potential of the wiring BL is set to GND. Since the transistor M1 is in the ON state, the potential of the node N is GND.
  • the potential of the wiring WWL is set to a low potential.
  • the transistor M1 is turned off.
  • the time T14 to the time T17 can be said to be a write-back period. Further, among the time T14 to the time T17, the time T14 to the time T16 in which the sense amplifier circuit SA is in the activated state can be referred to as a write-back period.
  • the potential of the wiring WWL is set to a low potential at time T20 to time T21.
  • the transistor M1 is turned off.
  • the potential of the wiring RWL is set to a low potential.
  • the transistor M3 is turned off.
  • the potential of the wiring PL is set to GND.
  • the potential of the wiring ENL is set to a low potential.
  • the sense amplifier circuit SA becomes inactive. It is assumed that the potential of the node N is GND.
  • the potential of the wiring PREL is set to a high potential.
  • the wiring BL and the wiring REFL are precharged. Therefore, the potential of the wiring BL becomes, for example, Vw, which is higher than the potential of the wiring SL. Further, the potential of the wiring REFL becomes the potential between GND and Vw.
  • the potential of the wiring RWL is set to a high potential.
  • the transistor M3 is turned on.
  • the potential of the wiring PREL is set to a low potential. As a result, the precharging of the wiring BL and the wiring REFL is completed.
  • the potential of the wiring PL is Vw.
  • the potential of the node N rises due to capacitive coupling by capacitive FEC or the like.
  • the negative charge is biased to one electrode side (node N side) of the capacitance FEC. Therefore, the capacitive coupling coefficient of the node N is larger than the case where the data having the value “0” is held in the memory cell MC. Therefore, the increase width of the potential of the node N at the time T22 to the time T23 is larger than the increase width of the potential of the node N at the time T12 to the time T13 shown in FIG. 4A.
  • the capacitive coupling coefficient of the node N is less than 1 and the potential of the node N before the time T22 is GND, the potential of the node N after the potential rise is lower than Vw. Further, it is assumed that the polarization inversion does not occur in the dielectric of the capacitive FEC even if the potential of the node N rises. That is, it is assumed that the value obtained by subtracting the potential of the wiring PL from the potential of the node N is ⁇ Vc or more.
  • the potential of the wiring PL may be set to Vw at time T21 to time T22, and the potential of the wiring RWL may be set to high potential at time T22 to time T23. Further, the potential of the wiring PREL may be kept high at the time T21 to the time T22, and the potential of the wiring PREL may be set to the low potential at the time T22 to the time T23.
  • the transistor M3 is turned on and the potential of the node N rises. Since the potential of the wiring BL is precharged to be higher than the potential of the wiring SL, the potential of the wiring BL decreases according to the potential of the node N electrically connected to the gate of the transistor M2. Specifically, the decrease in the potential of the wiring BL at time T22 to T23 is larger than the decrease in the potential of the wiring BL at time T12 to T13 shown in FIG. 4A. Therefore, for example, the potential of the wiring BL at the time T23 is lower than the potential of the wiring BL at the time T13. As a result, it can be assumed that the data having a value of "1" held in the memory cell MC is read from the memory cell MC.
  • the potential of the wiring ENL is set to a high potential.
  • the sense amplifier circuit SA is activated, and the difference between the potential of the wiring BL and the potential of the wiring REFL is amplified.
  • the potential of the wiring BL is lower than the potential of the wiring REFL at the time when the wiring ENL becomes high potential
  • the potential of the wiring BL becomes GND which is a low potential
  • the potential of the wiring REFL is high potential. It becomes Vw.
  • the data with the value "1" read from the memory cell MC can be output from the sense amplifier circuit SA.
  • the time T20 to the time T24 can be said to be a read period.
  • the time T21 to the time T24 excluding the time T20 to the time T21, which is the period for precharging the wiring BL, can be referred to as a read period.
  • the potential of the node N may rise later than the potential rise of the wiring PL.
  • a large voltage (a large voltage in the negative direction) is instantaneously applied to the dielectric of the capacitive FEC.
  • polarization inversion may occur in the dielectric, and the data held in the memory cell MC may be destroyed.
  • the potential of the wiring WWL is set to a high potential.
  • the transistor M1 is turned on.
  • the potential of the wiring RWL is set to a low potential.
  • the transistor M3 is turned off.
  • the transistor M1 is turned on, the potential of the node N becomes GND, which is the potential of the wiring BL.
  • the potential of the node N becomes GND.
  • the potential of the wiring PL remains Vw. Therefore, the voltage applied to the dielectric of the capacitive FEC becomes ⁇ Vw. Therefore, the polarization inversion occurs in the dielectric, and the data having a value of "0" is written in the memory cell MC. That is, the binary data obtained by inverting the value of the binary data read from the memory cell MC at the time T20 to the time T24 is written back to the memory cell MC.
  • the polarization reversal in the dielectric of the capacitive FEC does not occur at the time T24 to the time T25.
  • the potential of the wiring PL becomes GND.
  • both the potential of the node N and the potential of the wiring PL become GND. Therefore, the voltage applied to the dielectric of the capacitive FEC is 0V. As shown in FIG. 3A and the like, even if the voltage applied to the dielectric of the capacitive FEC becomes 0V, the polarization inversion does not occur in the dielectric.
  • the potential of the wiring ENL is set to a low potential.
  • the sense amplifier circuit SA becomes inactive.
  • the potential of the wiring WWL is set to a low potential.
  • the transistor M1 is turned off.
  • the time T24 to the time T27 can be said to be a write-back period. Further, among the time T24 to the time T27, the time T24 to the time T26 in which the sense amplifier circuit SA is in the activated state can be referred to as a write-back period.
  • the memory cell MC shown in FIG. 5A has a configuration in which the transistor M2 and the transistor M3 are omitted from the memory cell MC shown in FIG. 2A.
  • the wiring WL is electrically connected to the gate of the transistor M1.
  • FIG. 5B1 and 5B2 are timing charts showing a driving method of the semiconductor device 10 when the memory cell MC has the configuration shown in FIG. 5A.
  • FIG. 5B1 shows an example in which binary data with a value of “0” is written and held in the memory cell MC, and the binary data is read and written back from the memory cell MC.
  • FIG. 5B2 shows an example in which binary data with a value of “1” is written and held in the memory cell MC, and the binary data is read and written back from the memory cell MC.
  • the data held in the memory cell MC is read out at time T30 to time T33. That is, the time T30 to the time T33 is a read period. Further, at time T33 to time T35, data is written back to the memory cell MC. That is, the time T33 to the time T35 is a write-back period. Since the binary data whose value is "0" is held before the time T30, the positive charge is biased to one electrode side (node N side) of the capacitance FEC, and the other electrode side (wiring PL) of the capacitance FEC. Negative charge is biased to the side).
  • the polarization inversion in the dielectric of the capacitive FEC does not occur. That is, when the value of the binary data held in the memory cell MC is “0”, the polarization inversion in the dielectric of the capacitive FEC does not occur throughout the read period and the write-back period.
  • the data held in the memory cell MC is read out at time T40 to time T43. That is, the time T40 to the time T43 is a read period. Further, at time T43 to time T45, data is written back to the memory cell MC. That is, the time T43 to the time T45 is a write-back period. Since the binary data whose value is "1" is held before the time T30, the negative charge is biased to one electrode side (node N side) of the capacitance FEC, and the other electrode side (wiring PL) of the capacitance FEC. The positive charge is biased to the side).
  • the polarization reversal in the dielectric of the capacitive FEC occurs at time T41 to time T42 and time T43 to time T44. That is, when the value of the binary data held in the memory cell MC is "1", the polarization inversion in the dielectric of the capacitive FEC occurs through one read period and one write back period. Occurs twice in total.
  • the polarization inversion occurs many times. As a result, fatigue deterioration is likely to occur in the dielectric. Therefore, when the memory cell MC included in the semiconductor device 10 has the configuration shown in FIG. 5A, the reliability of the semiconductor device 10 may decrease. On the other hand, when the memory cell MC included in the semiconductor device 10 has the configuration shown in FIG. 2A, for example, even if the value of the data held in the memory cell MC is "1", one read period and one read period. The number of polarization reversals in the dielectric of the capacitive FEC that occurs throughout the write-back period is one. From the above, by adopting the memory cell MC having the configuration shown in FIG. 2A, for example, the reliability of the semiconductor device 10 can be improved as compared with the case where the memory cell MC has the configuration shown in FIG. 5A.
  • the value of the data held in the memory cell MC is inverted every time the data is written back to the memory cell MC.
  • the value of the data output from the wiring OUT does not change even if the data is written back.
  • a logic operation circuit LC is provided between the sense amplifier circuit SA and the wiring OUT so that the value of the data output from the wiring OUT does not change even if the data is written back.
  • data read from memory cell MC [i, 1] to memory cell MC [i, n] (i is an integer of 1 or more and m or less) and memory cell MC [i, n + 1].
  • the logic calculation circuit LC performs the logic calculation of the read data.
  • the logical operation can be an exclusive OR.
  • the calculation result is output from the wiring OUT.
  • the data representing the exclusive OR of the data read from the memory cell MC [i, 1] and the data read from the memory cell MC [i, n + 1] is connected to the wiring OUT [. Output from 1].
  • data representing the exclusive OR of the data read from the memory cell MC [i, n] and the data read from the memory cell MC [i, n + 1] is transmitted from the wiring OUT [n].
  • Output As a result, for example, when data having a value of "0" is held in the memory cell MC [i, n + 1], it is held in the memory cell MC [i, 1] to the memory cell MC [i, n].
  • Data having the same value as the data is output from the wiring OUT [1] to the wiring OUT [n], respectively.
  • the data having a value of "1" is held in the memory cell MC [i, n + 1]
  • the data of the value obtained by inverting the value of is output from the wiring OUT [1] to the wiring OUT [n], respectively.
  • the values of the retained data are inverted for all of the memory cells MC [i, 1] to the memory cells MC [i, n + 1]. ..
  • the data of the desired value can be continuously output from the wiring OUT during the read period.
  • the data held in the memory cell MC in the n + 1 column can be data indicating whether or not to invert the value of the data read from the memory cell MC in the 1st to nth columns. Therefore, the memory cell MC in the n + 1 column can be called a reference memory cell. Further, the data held in the memory cell MC in the n + 1th column can be said to be reference data. Since the data held in the memory cell MC can be binary data, the data held in the memory cell MC in the n + 1 column can be said to be reference binary data.
  • Table 1 is a table showing an example of a driving method of the semiconductor device 10.
  • Table 1 shows an example in which the semiconductor device 10 is driven by the drive mode shown in steps S1 to S8.
  • Display 1 shows the memory cell MC [i, j1], the memory cell [i, j2] (j1 and j2 are integers of 1 or more and n or less), and the memory cell MC [i, after the operation of each step is performed.
  • the value of the data held in n + 1] and the value of the data output from the wiring OUT [j1] and the wiring OUT [j2] are shown.
  • step S1 data having a value of "0" is written to, for example, all memory cells MC. That is, for example, the operation shown in FIG. 3B1 is performed for all the memory cells MC. As a result, the data held in the memory cell MC is initialized.
  • step S2 desired data is written to the memory cells MC in the first to nth columns.
  • the memory cell MC for writing the data having the value “0” performs the operation shown in FIG. 3B1
  • the memory cell MC for writing the data having the value “1” performs the operation shown in FIG. 3B2.
  • Table 1 it is assumed that the data having a value of “0” is written in the memory cell MC [i, j1] and the data having a value “1” is written in the memory cell MC [i, j2].
  • step S2 data having a value of "0” is written in the memory cell MC in the n + 1th column.
  • step S3 after reading the data held in the memory cell MC, the data is written back. Specifically, the memory cell MC in which the data having the value "0" is held performs the operation shown in FIG. 4A, and the memory cell MC holding the data having the value "1" performs the operation shown in FIG. 4B. I do.
  • step S3 At the start time of step S3 (the end time of step S2), data having a value of "0" is held in the memory cell MC in the n + 1th column. Therefore, from the wiring OUT [1] to the wiring OUT [n], the data held in the memory cells MC in the first to nth columns at the start time of step S3 (the end time of step S2) is output as it is. As described above, the value of the data held in the memory cell MC [i, j1] at the start time of step S3 (the end time of step S2) is “0” and is held in the memory cell MC [i, j2]. The value of the data is "1".
  • the data held in the memory cell MC is inverted. Therefore, as shown in Table 1, at the end of step S3, the value of the data held in the memory cell MC [i, j1] is "1", and the data held in the memory cell MC [i, j2]. The value of is "0".
  • step S4 as well, as in step S3, the data held in the memory cell MC is read and then the data is written back.
  • step S4 At the start time of step S4 (the end time of step S3), data having a value of "1" is held in the memory cell MC in the n + 1th column. Therefore, from the wiring OUT [1] to the wiring OUT [n], the values of the data held in the memory cells MC in the first to nth columns at the start time of step S4 (the end time of step S3) are inverted. Value data is output. As described above, the value of the data held in the memory cell MC [i, j1] at the start time of step S4 (the end time of step S3) is "1" and is held in the memory cell MC [i, j2]. The value of the data is "0".
  • step S5 as well, as in step S3 and the like, the data held in the memory cell MC is read and then the data is written back.
  • step S3 the data having a value of "0" is output from the wiring OUT [j1], and the data having a value "1” is output from the wiring OUT [j2].
  • step S6 desired data is written to the memory cells MC in the first to nth columns.
  • the memory cell MC for writing the data having the value “0” performs the operation shown in FIG. 3B1
  • the memory cell MC for writing the data having the value “1” performs the operation shown in FIG. 3B2. I do.
  • the data held in the memory cells MC in the first to nth columns can be updated.
  • step S6 no data is written to the memory cell MC in the n + 1th column.
  • the data whose value is “1” is held in the memory cell MC in the n + 1 column. Therefore, at the end of step S6, the data having a value of "1" is continuously held in the memory cell MC in the n + 1th column.
  • step S6 data having a value of "0" may be written to the memory cell in the n + 1 column regardless of the value of the data held in the memory cell MC in the n + 1 column.
  • step S7 similarly to step S3 and the like, after reading the data held in the memory cell MC, the data is written back.
  • the memory cell MC in the n + 1th column holds data having a value of “1”. Therefore, from the wiring OUT [1] to the wiring OUT [n], the values of the data held in the memory cells MC in the first to nth columns at the start time of step S7 (the end time of step S6) are inverted. Value data is output. As described above, the value of the data held in the memory cell MC [i, j1] at the start time of step S7 (the end time of step S6) is “0” and is held in the memory cell MC [i, j2]. The value of the data is "1".
  • step S8 as well, as in step S7 and the like, the data held in the memory cell MC is read and then the data is written back.
  • the data having a value of "1" is output from the wiring OUT [j1]
  • the data having a value "0" is output from the wiring OUT [j2].
  • the wiring OUT is performed during the read period. It is possible to continue to output the data of the desired value from.
  • FIG. 6 is, as an example, the semiconductor device described in the above embodiment, and the semiconductor device has a transistor 300, a transistor 500, and a capacity 600.
  • 7A shows a cross-sectional view of the transistor 500 in the channel length direction
  • FIG. 7B shows a cross-sectional view of the transistor 500 in the channel width direction
  • FIG. 7C shows a cross-sectional view of the transistor 300 in the channel width direction.
  • the transistor 500 is a transistor (OS transistor) having a metal oxide in the channel forming region.
  • the transistor 500 has a characteristic that the off-current is small and the field effect mobility does not change easily even at a high temperature.
  • a semiconductor device for example, the transistor M1 or the like of the memory cell MC shown in FIG. 2A or the like described in the above embodiment, it is possible to realize a semiconductor device whose operating ability does not easily decrease even at high temperatures.
  • the transistor 500 is provided above the transistor 300, for example, and the capacitance 600 is provided above the transistor 300 and the transistor 500, for example.
  • the capacity 600 can be the capacity FEC or the like shown in FIG. 2A or the like described in the above embodiment.
  • the transistor 300 is provided on the substrate 310, and has an element separation layer 312, a conductor 316, an insulator 315, a semiconductor region 313 including a part of the substrate 310, a low resistance region 314a functioning as a source region or a drain region, and a low resistance region. It has a resistance region 314b.
  • the transistor 300 can be applied to, for example, the transistor M2 or the like shown in FIG. 2A or the like described in the above embodiment.
  • a semiconductor substrate for example, a single crystal substrate or a silicon substrate
  • the substrate 310 it is preferable to use a semiconductor substrate (for example, a single crystal substrate or a silicon substrate) as the substrate 310.
  • the transistor 300 is covered with the conductor 316 on the upper surface of the semiconductor region 313 and the side surface in the channel width direction via the insulator 315.
  • the on characteristic of the transistor 300 can be improved by increasing the effective channel width. Further, since the contribution of the electric field of the gate electrode can be increased, the off characteristic of the transistor 300 can be improved.
  • the transistor 300 may be either a p-channel type or an n-channel type.
  • a semiconductor such as a silicon-based semiconductor in a region of the semiconductor region 313 in which a channel is formed, a region in the vicinity thereof, a low resistance region 314a serving as a source region or a drain region, a low resistance region 314b, and the like.
  • It preferably contains crystalline silicon.
  • it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), GaN (gallium nitride) and the like.
  • a configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used.
  • the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs or the like.
  • n-type conductivity such as arsenic and phosphorus, or p-type conductivity such as boron are imparted.
  • the conductor 316 that functions as a gate electrode is a semiconductor material such as silicon, a metal material, or an alloy containing an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron.
  • a conductive material such as a material or a metal oxide material can be used.
  • the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embedding property, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten in terms of heat resistance.
  • the element separation layer 312 is provided for separating a plurality of transistors formed on the substrate 310.
  • the element separation layer can be formed by using, for example, a LOCOS (LOCOxidation of Silicon) method, an STI (Shallow Trench Isolation) method, a mesa separation method, or the like.
  • the transistor 300 shown in FIG. 6 is an example, and the transistor 300 is not limited to the structure thereof, and an appropriate transistor may be used depending on the circuit configuration, driving method, and the like.
  • the transistor 300 may have a planar type structure instead of the FIN type shown in FIG. 7C.
  • the transistor 300 may be configured in the same manner as the transistor 500 using an oxide semiconductor, as shown in FIG. The details of the transistor 500 will be described later.
  • the unipolar circuit means a circuit including a transistor having only one polarity of an n-channel transistor or a p-channel transistor.
  • the transistor 300 is provided on the substrate 310A.
  • a semiconductor substrate may be used in the same manner as the substrate 310 of the semiconductor device of FIG.
  • the substrate 310A includes, for example, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having a stainless steel still foil, a tungsten substrate, and a tungsten foil.
  • a substrate, a flexible substrate, a laminated film, a paper containing a fibrous material, a base film, or the like can be used.
  • the glass substrate examples include barium borosilicate glass, aluminoborosilicate glass, soda lime glass and the like.
  • the flexible substrate, the laminated film, the base film and the like are as follows.
  • plastics typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), and polytetrafluoroethylene (PTFE).
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • PES polyether sulfone
  • PTFE polytetrafluoroethylene
  • polypropylene polyester, polyvinyl fluoride, polyvinyl chloride and the like.
  • polyamide, polyimide, aramid epoxy resin, inorganic thin-film film, papers and the like.
  • the transistor 300 shown in FIG. 6 is provided with an insulator 320, an insulator 322, an insulator 324, and an insulator 326 stacked in this order from the substrate 310 side.
  • the insulator 320, the insulator 322, the insulator 324, and the insulator 326 for example, silicon oxide, silicon oxide, silicon nitride, silicon nitride, aluminum oxide, aluminum oxide, aluminum nitride, aluminum nitride, etc. are used. Just do it.
  • silicon oxide refers to a material having a higher oxygen content than nitrogen as its composition
  • silicon nitride as its composition refers to a material having a higher nitrogen content than oxygen as its composition. Is shown.
  • aluminum nitride refers to a material whose composition has a higher oxygen content than nitrogen
  • aluminum nitride refers to a material whose composition has a higher nitrogen content than oxygen. Is shown.
  • the insulator 322 may have a function as a flattening film for flattening a step generated by the insulator 320 and the transistor 300 covered with the insulator 322.
  • the upper surface of the insulator 322 may be flattened by a flattening treatment using a chemical mechanical polishing (CMP) method or the like in order to improve the flatness.
  • CMP chemical mechanical polishing
  • the insulator 324 it is preferable to use a film having a barrier property so that hydrogen, impurities and the like do not diffuse in the region where the transistor 500 is provided from the substrate 310 or the transistor 300 or the like.
  • silicon nitride formed by the CVD method can be used as an example of a film having a barrier property against hydrogen.
  • hydrogen may diffuse into a semiconductor element having an oxide semiconductor such as a transistor 500, which may deteriorate the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 300.
  • the membrane that suppresses the diffusion of hydrogen is a membrane in which the amount of hydrogen desorbed is small.
  • the amount of hydrogen desorbed can be analyzed using, for example, a heated desorption gas analysis method (TDS) or the like.
  • TDS heated desorption gas analysis method
  • the amount of hydrogen desorbed from the insulator 324 is the amount desorbed in terms of hydrogen atoms in the range of 50 ° C. to 500 ° C. in the surface temperature of the film, which is converted into the area of the insulator 324. It may be 10 ⁇ 10 15 atoms / cm 2 or less, preferably 5 ⁇ 10 15 atoms / cm 2 or less.
  • the insulator 326 preferably has a lower dielectric constant than the insulator 324.
  • the relative permittivity of the insulator 326 is preferably less than 4, more preferably less than 3.
  • the relative permittivity of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less the relative permittivity of the insulator 324.
  • the insulator 320, the insulator 322, the insulator 324, and the insulator 326 are embedded with a capacity of 600, a conductor 328 connected to the transistor 500, a conductor 330, and the like.
  • the conductor 328 and the conductor 330 have a function as a plug or wiring.
  • a plurality of structures may be collectively given the same reference numeral.
  • the wiring and the plug connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.
  • each plug and wiring As the material of each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is used as a single layer or laminated. be able to. It is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low resistance conductive material.
  • a wiring layer may be provided on the insulator 326 and the conductor 330.
  • the insulator 350, the insulator 352, and the insulator 354 are provided in order above the insulator 326 and the conductor 330 in order.
  • a conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354.
  • the conductor 356 has a function as a plug or wiring for connecting to the transistor 300.
  • the conductor 356 can be provided by using the same material as the conductor 328 and the conductor 330.
  • the insulator 350 it is preferable to use an insulator having a barrier property against impurities such as hydrogen and water, similarly to the insulator 324.
  • the insulator 352 and the insulator 354 it is preferable to use an insulator having a relatively low relative permittivity in order to reduce the parasitic capacitance generated between the wirings, similarly to the insulator 326.
  • the conductor 356 preferably contains a conductor having a barrier property against impurities such as hydrogen and water.
  • a conductor having a barrier property against hydrogen is formed in the opening of the insulator 350 having a barrier property against hydrogen.
  • the conductor having a barrier property against hydrogen for example, tantalum nitride or the like may be used. Further, by laminating tantalum nitride and tungsten having high conductivity, it is possible to suppress the diffusion of hydrogen from the transistor 300 while maintaining the conductivity as wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen has a structure in contact with the insulator 350 having a barrier property against hydrogen.
  • the insulator 360, the insulator 362, and the insulator 364 are laminated in this order on the insulator 354 and the conductor 356.
  • the insulator 360 it is preferable to use an insulator having a barrier property against impurities such as water and hydrogen, similarly to the insulator 324 and the like. Therefore, as the insulator 360, for example, a material applicable to the insulator 324 or the like can be used.
  • the insulator 362 and the insulator 364 have a function as an interlayer insulating film and a flattening film. Further, as the insulator 362 and the insulator 364, it is preferable to use an insulator having a barrier property against impurities such as water and hydrogen, similarly to the insulator 324. Therefore, as the insulator 362 and / or the insulator 364, a material applicable to the insulator 324 can be used.
  • an opening is formed in a region of each of the insulator 360, the insulator 362, and the insulator 364 that overlaps with a part of the conductor 356, and the conductor 366 is provided so as to fill the opening.
  • the conductor 366 is also formed on the insulator 362.
  • the conductor 366 has a function as a plug or wiring for connecting to the transistor 300.
  • the conductor 366 can be provided by using the same material as the conductor 328 and the conductor 330.
  • the insulator 510, the insulator 512, the insulator 514, and the insulator 516 are laminated in this order.
  • the insulator 510, the insulator 512, the insulator 514, and the insulator 516 it is preferable to use a substance having a barrier property against oxygen and hydrogen.
  • a film having a barrier property is used so that hydrogen and impurities do not diffuse from the region where the substrate 310 or the transistor 300 is provided to the region where the transistor 500 is provided. Is preferable. Therefore, the same material as the insulator 324 can be used.
  • silicon nitride formed by the CVD method can be used as an example of a film having a barrier property against hydrogen.
  • hydrogen may diffuse into a semiconductor element having an oxide semiconductor such as a transistor 500, which may deteriorate the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 300.
  • the membrane that suppresses the diffusion of hydrogen is a membrane in which the amount of hydrogen desorbed is small.
  • the film having a barrier property against hydrogen for example, it is preferable to use metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 510 and the insulator 514.
  • metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 510 and the insulator 514.
  • aluminum oxide has a high blocking effect that does not allow the membrane to permeate both oxygen and impurities such as hydrogen and water that cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from being mixed into the transistor 500 during and after the manufacturing process of the transistor. In addition, it is possible to suppress the release of oxygen from the oxides constituting the transistor 500. Therefore, it is suitable for use as a protective film for the transistor 500.
  • the same material as the insulator 320 can be used for the insulator 512 and the insulator 516. Further, by applying a material having a relatively low dielectric constant to these insulators, it is possible to reduce the parasitic capacitance generated between the wirings.
  • a silicon oxide film, a silicon nitride film, or the like can be used as the insulator 512 and the insulator 516.
  • the insulator 510, the insulator 512, the insulator 514, and the insulator 516 include a conductor 518, a conductor constituting the transistor 500 (for example, the conductor 503 shown in FIGS. 7A and 7B) and the like. It is embedded.
  • the conductor 518 has a capacity of 600, or a function as a plug or wiring for connecting to the transistor 300.
  • the conductor 518 can be provided by using the same material as the conductor 328 and the conductor 330.
  • the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor having a barrier property against oxygen, hydrogen, and water.
  • the transistor 300 and the transistor 500 can be separated by a layer having a barrier property against oxygen, hydrogen, and water, and the diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.
  • a transistor 500 is provided above the insulator 516.
  • the transistor 500 includes an insulator 516 on the insulator 514 and a conductor 503 (conductor 503a, and conductivity) arranged so as to be embedded in the insulator 514 or the insulator 516.
  • Body 503b insulator 522 on insulator 516, and insulator 503, insulator 524 on insulator 522, oxide 530a on insulator 524, and oxide 530b on oxide 530a.
  • the insulator 552 includes the upper surface of the insulator 522, the side surface of the insulator 524, the side surface of the oxide 530a, the side surface and the upper surface of the oxide 530b, and the side surface of the conductor 542.
  • the upper surface of the conductor 560 is arranged so as to substantially coincide in height with the upper surface of the insulator 554, the upper part of the insulator 550, the upper part of the insulator 552, and the upper surface of the insulator 580.
  • the insulator 574 is in contact with at least a part of the upper surface of the conductor 560, the upper part of the insulator 552, the upper part of the insulator 550, the upper part of the insulator 554, and the upper surface of the insulator 580.
  • the conductor 542a and the conductor 542b may be collectively referred to as a conductor 542, and the insulator 571a and the insulator 571b may be collectively referred to as an insulator 571.
  • Other elements may have similar expressions.
  • the insulator 580 and the insulator 544 are provided with an opening reaching the oxide 530b.
  • An insulator 552, an insulator 550, an insulator 554, and a conductor 560 are arranged in the opening. Further, in the channel length direction of the transistor 500, the conductor 560, the insulator 552, the insulator 550, and the insulator 554 are placed between the insulator 571a and the conductor 542a and the insulator 571b and the conductor 542b. It is provided.
  • the insulator 554 has a region in contact with the side surface of the conductor 560 and a region in contact with the bottom surface of the conductor 560.
  • the oxide 530 preferably has an oxide 530a arranged on the insulator 524 and an oxide 530b arranged on the oxide 530a.
  • the oxide 530a By having the oxide 530a under the oxide 530b, it is possible to suppress the diffusion of impurities from the structure formed below the oxide 530a to the oxide 530b.
  • the oxide 530 shows a structure in which two layers of the oxide 530a and the oxide 530b are laminated, but the present invention is not limited to this.
  • the transistor 500 can be configured to have a single layer of oxide 530b or a laminated structure of three or more layers.
  • each of the oxide 530a and the oxide 530b may have a laminated structure.
  • the conductor 560 functions as a first gate (also referred to as a top gate) electrode, and the conductor 503 functions as a second gate (also referred to as a back gate) electrode.
  • the insulator 552, the insulator 550, and the insulator 554 function as the first gate insulator, and the insulator 522 and the insulator 524 function as the second gate insulator.
  • the gate insulator may be referred to as a gate insulating layer or a gate insulating film.
  • the conductor 542a functions as one of the source or the drain, and the conductor 542b functions as the other of the source or the drain. Further, at least a part of the region overlapping with the conductor 560 of the oxide 530 functions as a channel forming region.
  • FIG. 9A an enlarged view of the vicinity of the channel formation region in FIG. 7A is shown in FIG. 9A.
  • the oxide 530b is provided so as to sandwich the region 530bc that functions as a channel forming region of the transistor 500, and the region 530ba and the region 530bb that function as a source region or a drain region. , Have.
  • At least a part of the region 530bc overlaps with the conductor 560.
  • the region 530bc is provided in the region between the conductor 542a and the conductor 542b.
  • the region 530ba is provided so as to be superimposed on the conductor 542a
  • the region 530bb is provided so as to be superimposed on the conductor 542b.
  • the region 530bc that functions as a channel forming region has more oxygen deficiency than the regions 530ba and 530bb (in the present specification and the like, the oxygen deficiency in the metal oxide may be referred to as VO (oxygen vacancy)). It is a high resistance region with a low carrier concentration because it is low or the impurity concentration is low. Therefore, it can be said that the region 530bc is i-type (intrinsic) or substantially i-type.
  • Transistors using metal oxides may have poor electrical characteristics and poor reliability if impurities or oxygen deficiencies (VOs) are present in the regions where channels are formed in the metal oxides. Further, hydrogen in the vicinity of oxygen deficiency (VO) forms a defect in which hydrogen is contained in oxygen deficiency (VO) (hereinafter, may be referred to as VOH ) to generate electrons as carriers. In some cases. Therefore, if oxygen deficiency is contained in the region where the channel is formed in the oxide semiconductor, the transistor has normal-on characteristics (the channel exists even if no voltage is applied to the gate electrode, and the current is applied to the transistor. Flowing characteristics). Therefore, it is preferable that impurities, oxygen deficiency, and VOH are reduced as much as possible in the region where channels are formed in the oxide semiconductor.
  • the region 530ba and the region 530bab that function as a source region or a drain region have a large amount of oxygen deficiency (VO) or a high concentration of impurities such as hydrogen, nitrogen, and metal elements, so that the carrier concentration increases and the resistance is low. It is an area that has become. That is, the region 530ba and the region 530bb are n-type regions having a high carrier concentration and low resistance as compared with the region 530bc.
  • VO oxygen deficiency
  • impurities such as hydrogen, nitrogen, and metal elements
  • the carrier concentration of the region 530 bc that functions as a channel forming region is preferably 1 ⁇ 10 18 cm -3 or less, more preferably less than 1 ⁇ 10 17 cm -3 , and 1 ⁇ 10 16 cm. It is more preferably less than -3 , still more preferably less than 1 ⁇ 10 13 cm -3 , and even more preferably less than 1 ⁇ 10 12 cm -3 .
  • the lower limit of the carrier concentration of the region 530 bc that functions as the channel forming region is not particularly limited, but may be, for example, 1 ⁇ 10 -9 cm -3 .
  • the carrier concentration between the region 530 bc and the region 530 ba or the region 530 bb is equal to or lower than the carrier concentration of the region 530 ba and the region 530 bb, and equal to or higher than the carrier concentration of the region 530 bc.
  • Regions may be formed. That is, the region functions as a junction region between the region 530 bc and the region 530 ba or the region 530 bb.
  • the hydrogen concentration may be equal to or lower than the hydrogen concentration in the regions 530ba and 530bb, and may be equal to or higher than the hydrogen concentration in the region 530bc.
  • the junction region may have an oxygen deficiency equal to or less than that of the regions 530ba and 530bb, and may be equal to or greater than that of the region 530bc.
  • FIG. 9A shows an example in which the region 530ba, the region 530bb, and the region 530bc are formed on the oxide 530b, but the present invention is not limited thereto.
  • each of the above regions may be formed not only with the oxide 530b but also with the oxide 530a.
  • the concentrations of the metal elements detected in each region and the impurity elements such as hydrogen and nitrogen are not limited to the stepwise changes in each region, but may be continuously changed in each region. That is, it suffices that the concentration of the metal element and the impurity element such as hydrogen and nitrogen decreases as the region is closer to the channel formation region.
  • a metal oxide hereinafter, also referred to as an oxide semiconductor that functions as a semiconductor for the oxide 530 (oxide 530a and oxide 530b) containing a channel forming region.
  • the metal oxide functioning as a semiconductor it is preferable to use a metal oxide having a band gap of 2 eV or more, preferably 2.5 eV or more. As described above, by using a metal oxide having a large bandgap, the off-current of the transistor can be reduced.
  • an In-M-Zn oxide having indium, element M and zinc (element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium).
  • Zinc, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. (one or more) and the like may be used.
  • an In-Ga oxide, an In-Zn oxide, or an indium oxide may be used as the oxide 530.
  • the atomic number ratio of In to the element M in the metal oxide used for the oxide 530b is larger than the atomic number ratio of In to the element M in the metal oxide used for the oxide 530a.
  • the oxide 530a under the oxide 530b By arranging the oxide 530a under the oxide 530b in this way, it is possible to suppress the diffusion of impurities and oxygen from the structure formed below the oxide 530a to the oxide 530b. ..
  • the oxide 530a and the oxide 530b have a common element (main component) other than oxygen, the defect level density at the interface between the oxide 530a and the oxide 530b can be lowered. Since the defect level density at the interface between the oxide 530a and the oxide 530b can be lowered, the influence of the interfacial scattering on the carrier conduction is small, and a high on-current can be obtained.
  • the oxide 530b preferably has crystallinity.
  • CAAC-OS c-axis aligned crystalline semiconductor semiconductor
  • CAAC-OS is a metal oxide having a highly crystalline and dense structure and having few impurities and defects (for example, oxygen deficiency (VO etc.). Especially after the formation of the metal oxide.
  • VO etc. oxygen deficiency
  • CAAC-OS By heat-treating at a temperature such that the metal oxide does not polycrystallize (for example, 400 ° C. or higher and 600 ° C. or lower), CAAC-OS can be made into a more crystalline and dense structure. Therefore, by increasing the density of CAAC-OS, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.
  • the metal oxide having CAAC-OS has stable physical properties. Therefore, the metal oxide having CAAC-OS is resistant to heat and has high reliability.
  • a transistor using an oxide semiconductor if impurities and oxygen deficiency are present in the region where a channel is formed in the oxide semiconductor, the electrical characteristics are liable to fluctuate and the reliability may be deteriorated. Further, hydrogen in the vicinity of the oxygen deficiency may form a defect in which hydrogen is contained in the oxygen deficiency (hereinafter, may be referred to as VOH) to generate an electron as a carrier. Therefore, if oxygen deficiency is contained in the region where the channel is formed in the oxide semiconductor, the transistor has normal-on characteristics (the channel exists even if no voltage is applied to the gate electrode, and the current is applied to the transistor. Flowing characteristics).
  • the region in which the channel is formed in the oxide semiconductor is preferably i-type (intrinsic) or substantially i-type with a reduced carrier concentration.
  • the oxide semiconductor is removed from the insulator.
  • Oxygen can be supplied to reduce oxygen deficiency and VOH.
  • the on-current of the transistor 500 may decrease or the field effect mobility may decrease.
  • the amount of oxygen supplied to the source region or the drain region varies in the surface of the substrate, so that the characteristics of the semiconductor device having the transistor vary.
  • the region 530bc that functions as a channel forming region is preferably i-type or substantially i-type because the carrier concentration is reduced, but the region 530ba that functions as a source region or a drain region and
  • the region 530bb has a high carrier concentration and is preferably n-type. That is, it is preferable to reduce oxygen deficiency and VOH in the region 530 bc of the oxide semiconductor so that an excessive amount of oxygen is not supplied to the region 530 ba and the region 530 bb.
  • microwave treatment is performed in an atmosphere containing oxygen to reduce oxygen deficiency and VOH in the region 530bc .
  • the microwave processing refers to processing using, for example, a device having a power source for generating high-density plasma using microwaves.
  • oxygen gas By performing microwave treatment in an atmosphere containing oxygen, oxygen gas can be turned into plasma by using a high frequency such as microwave or RF, and the oxygen plasma can be allowed to act. At this time, it is also possible to irradiate the region 530bc with a high frequency such as microwave or RF.
  • a high frequency such as microwave or RF.
  • the VO H in the region 530 bc can be divided, the hydrogen H can be removed from the region 530 bc, and the oxygen -deficient VO can be supplemented with oxygen. That is, in the region 530 bc, the reaction “VO H ⁇ H + VO” occurs, and the hydrogen concentration in the region 530 bc can be reduced. Therefore, oxygen deficiency and VOH in the region 530bc can be reduced, and the carrier concentration can be lowered.
  • the action of microwaves, high frequencies such as RF, oxygen plasma, etc. is shielded by the conductors 542a and 542b and does not reach the regions 530ba and 530bb. .. Further, the action of the oxygen plasma can be reduced by the insulator 571 and the insulator 580 provided overlying the oxide 530b and the conductor 542. As a result, during microwave treatment, the reduction of VOH and the supply of an excessive amount of oxygen do not occur in the regions 530ba and 530bab , so that the reduction of the carrier concentration can be prevented.
  • microwave treatment in an atmosphere containing oxygen after forming the insulating film to be the insulator 552 or after forming the insulating film to be the insulator 550.
  • microwave treatment in an atmosphere containing oxygen through the insulator 552 or the insulator 550 in this way, oxygen can be efficiently injected into the region 530 bc.
  • the insulator 552 so as to be in contact with the side surface of the conductor 542 and the surface of the region 530bc, the injection of more oxygen than necessary into the region 530bc is suppressed, and the oxidation of the side surface of the conductor 542 is suppressed. be able to. Further, it is possible to suppress the oxidation of the side surface of the conductor 542 when the insulating film to be the insulator 550 is formed.
  • oxygen injected into the region 530bc has various forms such as an oxygen atom, an oxygen molecule, and an oxygen radical (also referred to as an O radical, an atom or molecule having an unpaired electron, or an ion).
  • the oxygen injected into the region 530bc is preferably any one or more of the above-mentioned forms, and is particularly preferable to be an oxygen radical. Further, since the film quality of the insulator 552 and the insulator 550 can be improved, the reliability of the transistor 500 is improved.
  • oxygen deficiency and VOH can be selectively removed in the region 530bc of the oxide semiconductor to make the region 530bc i-type or substantially i-type. Further, it is possible to suppress the supply of excess oxygen to the region 530ba and the region 530bb that function as the source region or the drain region, and maintain the n-type electrical characteristics. As a result, it is possible to suppress fluctuations in the electrical characteristics of the transistor 500 and reduce variations in the electrical characteristics of the transistor 500 within the substrate surface.
  • a curved surface may be provided between the side surface of the oxide 530b and the upper surface of the oxide 530b in a cross-sectional view of the transistor 500 in the channel width direction. That is, the end portion of the side surface and the end portion of the upper surface may be curved (hereinafter, also referred to as a round shape).
  • the radius of curvature on the curved surface is preferably larger than 0 nm and smaller than the film thickness of the oxide 530b in the region overlapping the conductor 542, or smaller than half the length of the region having no curved surface.
  • the radius of curvature on the curved surface is larger than 0 nm and 20 nm or less, preferably 1 nm or more and 15 nm or less, and more preferably 2 nm or more and 10 nm or less.
  • the oxide 530 preferably has a laminated structure of a plurality of oxide layers having different chemical compositions.
  • the atomic number ratio of the element M to the metal element as the main component is the ratio of the element M to the metal element as the main component in the metal oxide used for the oxide 530b. It is preferably larger than the atomic number ratio.
  • the atomic number ratio of the element M to In is preferably larger than the atomic number ratio of the element M to In in the metal oxide used for the oxide 530b.
  • the atomic number ratio of In to the element M is preferably larger than the atomic number ratio of In to the element M in the metal oxide used for the oxide 530a.
  • the oxide 530b is preferably an oxide having crystallinity such as CAAC-OS.
  • Crystalline oxides such as CAAC-OS have a dense structure with high crystallinity with few impurities and defects (oxygen deficiency, etc.). Therefore, it is possible to suppress the extraction of oxygen from the oxide 530b by the source electrode or the drain electrode. As a result, oxygen can be reduced from being extracted from the oxide 530b even if heat treatment is performed, so that the transistor 500 is stable against a high temperature (so-called thermal budget) in the manufacturing process.
  • the lower end of the conduction band changes gently.
  • the lower end of the conduction band at the junction between the oxide 530a and the oxide 530b is continuously changed or continuously bonded. In order to do so, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxide 530a and the oxide 530b.
  • the oxide 530a and the oxide 530b have a common element other than oxygen as a main component, a mixed layer having a low defect level density can be formed.
  • the oxide 530b is an In-M-Zn oxide
  • the oxide 530a is an In-M-Zn oxide, an M-Zn oxide, an element M oxide, an In-Zn oxide, or an indium oxide. Etc. may be used.
  • a metal oxide having a composition in the vicinity thereof may be used.
  • a metal oxide having a composition may be used.
  • the composition in the vicinity includes a range of ⁇ 30% of the desired atomic number ratio. Further, it is preferable to use gallium as the element M.
  • the above-mentioned atomic number ratio is not limited to the atomic number ratio of the formed metal oxide, but is the atomic number ratio of the sputtering target used for forming the metal oxide. May be.
  • the interface between the oxide 530 and the insulator 552 and its vicinity thereof can be provided.
  • Indium contained in the oxide 530 may be unevenly distributed.
  • the vicinity of the surface of the oxide 530 has an atomic number ratio close to that of indium oxide or an atomic number ratio close to that of In—Zn oxide.
  • the atomic number ratio of indium in the vicinity of the surface of the oxide 530, particularly the oxide 530b, is increased, so that the field effect mobility of the transistor 500 can be improved.
  • the oxide 530a and the oxide 530b have the above-mentioned constitution, the defect level density at the interface between the oxide 530a and the oxide 530b can be lowered. Therefore, the influence of interfacial scattering on carrier conduction is reduced, and the transistor 500 can obtain a large on-current and high frequency characteristics.
  • At least one of the insulator 512, the insulator 514, the insulator 544, the insulator 571, the insulator 574, the insulator 576, and the insulator 581 has impurities such as water and hydrogen from the substrate side or the transistor 500. It is preferable to function as a barrier insulating film that suppresses diffusion from above to the transistor 500. Therefore, at least one of insulator 512, insulator 514, insulator 544, insulator 571, insulator 574, insulator 576, and insulator 581 is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, and the like.
  • an insulating material having a function of suppressing the diffusion of impurities such as nitrogen oxide molecules ( N2O, NO, NO2, etc.) and copper atoms (the above impurities are difficult to permeate).
  • impurities such as nitrogen oxide molecules ( N2O, NO, NO2, etc.) and copper atoms
  • an insulating material having a function of suppressing the diffusion of oxygen for example, at least one of oxygen atoms, oxygen molecules, etc.
  • the barrier insulating film refers to an insulating film having a barrier property.
  • the barrier property is a function of suppressing the diffusion of the corresponding substance (also referred to as low permeability).
  • the corresponding substance has a function of capturing and fixing (also referred to as gettering).
  • the insulator 512, the insulator 514, the insulator 544, the insulator 571, the insulator 574, the insulator 576, and the insulator 581 are insulators having a function of suppressing impurities such as water and hydrogen, and diffusion of oxygen.
  • insulators having a function of suppressing impurities such as water and hydrogen, and diffusion of oxygen.
  • aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, silicon nitride or the like can be used.
  • silicon nitride or the like it is preferable to use silicon nitride or the like having a higher hydrogen barrier property.
  • the insulator 514, the insulator 571, the insulator 574, and the insulator 581 it is preferable to use aluminum oxide, magnesium oxide, or the like having a high function of capturing hydrogen and fixing hydrogen. This makes it possible to prevent impurities such as water and hydrogen from diffusing from the substrate side to the transistor 500 side via the insulator 512 and the insulator 514. Alternatively, it is possible to suppress the diffusion of impurities such as water and hydrogen from the interlayer insulating film or the like arranged outside the insulator 581 to the transistor 500 side. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 524 or the like to the substrate side via the insulator 512 and the insulator 514.
  • the transistor 500 has an insulator 512, an insulator 514, an insulator 571, an insulator 544, an insulator 574, an insulator 576, and an insulator 512 having a function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. It is preferable to have a structure surrounded by an insulator 581.
  • an oxide having an amorphous structure as the insulator 512, the insulator 514, the insulator 544, the insulator 571, the insulator 574, the insulator 576, and the insulator 581.
  • a metal oxide such as AlO x (x is an arbitrary number larger than 0) or MgO y (y is an arbitrary number larger than 0).
  • an oxygen atom has a dangling bond, and the dangling bond may have a property of capturing or fixing hydrogen.
  • a metal oxide having such an amorphous structure as a component of the transistor 500 or providing it around the transistor 500, hydrogen contained in the transistor 500 or hydrogen existing around the transistor 500 is captured or fixed. be able to. In particular, it is preferable to capture or fix hydrogen contained in the channel forming region of the transistor 500.
  • a metal oxide having an amorphous structure as a component of the transistor 500 or providing it around the transistor 500, it is possible to manufacture the transistor 500 having good characteristics and high reliability and a semiconductor device.
  • the insulator 512, the insulator 514, the insulator 544, the insulator 571, the insulator 574, the insulator 576, and the insulator 581 preferably have an amorphous structure, but some regions have a polycrystal structure. It may be formed. Further, the insulator 512, the insulator 514, the insulator 544, the insulator 571, the insulator 574, the insulator 576, and the insulator 581 are multi-layered in which a layer having an amorphous structure and a layer having a polycrystal structure are laminated. It may be a structure. For example, a laminated structure in which a layer having a polycrystalline structure is formed on a layer having an amorphous structure may be used.
  • the film formation of the insulator 512, the insulator 514, the insulator 544, the insulator 571, the insulator 574, the insulator 576, and the insulator 581 may be performed by using, for example, a sputtering method. Since the sputtering method does not require the use of molecules containing hydrogen in the film forming gas, the hydrogen concentrations of the insulator 512, the insulator 514, the insulator 544, the insulator 571, the insulator 574, the insulator 576, and the insulator 581. Can be reduced.
  • the film forming method is not limited to the sputtering method, but is limited to a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, and a pulsed laser deposition (PLD) method.
  • CVD chemical vapor deposition
  • MBE molecular beam epitaxy
  • PLD pulsed laser deposition
  • atomic layer deposition ALD: Atomic Layer Deposition
  • the resistivity of the insulator 512, the insulator 544, and the insulator 576 it may be preferable to reduce the resistivity of the insulator 512, the insulator 544, and the insulator 576.
  • the insulator 512, the insulator 544, and the insulator 576 are used in the process of manufacturing the semiconductor device using plasma or the like.
  • the insulator 576 can alleviate the charge-up of the conductor 503, the conductor 542, the conductor 560, and the like.
  • the resistivity of the insulator 512, the insulator 544, and the insulator 576 is preferably 1 ⁇ 10 10 ⁇ cm or more and 1 ⁇ 10 15 ⁇ cm or less.
  • the insulator 516, the insulator 574, the insulator 580, and the insulator 581 have a lower dielectric constant than the insulator 514.
  • the insulator 516, the insulator 580, and the insulator 581 include silicon oxide, silicon oxide nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and pores. Silicon oxide or the like may be used as appropriate.
  • the insulator 581 is preferably an insulator that functions as an interlayer film, a flattening film, or the like, as an example.
  • the conductor 503 is arranged so as to overlap the oxide 530 and the conductor 560.
  • the conductor 503 is embedded in the opening formed in the insulator 516.
  • a part of the conductor 503 may be embedded in the insulator 514.
  • the conductor 503 has a conductor 503a and a conductor 503b.
  • the conductor 503a is provided in contact with the bottom surface and the side wall of the opening.
  • the conductor 503b is provided so as to be embedded in the recess formed in the conductor 503a.
  • the height of the upper part of the conductor 503b roughly coincides with the height of the upper part of the conductor 503a and the height of the upper part of the insulator 516.
  • the conductor 503a has a function of suppressing the diffusion of impurities such as hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitrogen oxide molecule ( N2O, NO, NO2 , etc.) and copper atom. It is preferable to use a conductive material having. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom and an oxygen molecule).
  • the conductor 503a By using a conductive material having a function of reducing the diffusion of hydrogen in the conductor 503a, impurities such as hydrogen contained in the conductor 503b are prevented from diffusing into the oxide 530 via the insulator 524 and the like. Can be prevented. Further, by using a conductive material having a function of suppressing the diffusion of oxygen for the conductor 503a, it is possible to prevent the conductor 503b from being oxidized and the conductivity from being lowered.
  • the conductive material having a function of suppressing the diffusion of oxygen for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide and the like are preferably used. Therefore, as the conductor 503a, the above-mentioned conductive material may be a single layer or a laminated material. For example, titanium nitride may be used for the conductor 503a.
  • the conductor 503b it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component.
  • tungsten may be used for the conductor 503b.
  • the conductor 503 may function as a second gate electrode.
  • the threshold voltage (Vth) of the transistor 500 can be controlled by independently changing the potential applied to the conductor 503 without interlocking with the potential applied to the conductor 560.
  • Vth threshold voltage
  • the electrical resistivity of the conductor 503 is designed in consideration of the potential applied to the conductor 503, and the film thickness of the conductor 503 is set according to the electrical resistivity.
  • the film thickness of the insulator 516 is substantially the same as that of the conductor 503.
  • the absolute amount of impurities such as hydrogen contained in the insulator 516 can be reduced, so that the impurities can be reduced from diffusing into the oxide 530. ..
  • the conductor 503 may be provided larger than the size of the region that does not overlap with the conductor 542a and the conductor 542b of the oxide 530 when viewed from the upper surface.
  • the conductor 503 is also stretched in a region outside the ends of the oxides 530a and 530b in the channel width direction. That is, it is preferable that the conductor 503 and the conductor 560 are superimposed on each other via an insulator on the outside of the side surface of the oxide 530 in the channel width direction.
  • the channel forming region of the oxide 530 is electrically surrounded by the electric field of the conductor 560 that functions as the first gate electrode and the electric field of the conductor 503 that functions as the second gate electrode. Can be done.
  • the structure of the transistor that electrically surrounds the channel forming region by the electric fields of the first gate and the second gate is called a curved channel (S-channel) structure.
  • the transistor having the S-channel structure represents the structure of the transistor that electrically surrounds the channel forming region by the electric fields of one and the other of the pair of gate electrodes.
  • the S-channel structure disclosed in the present specification and the like is different from the Fin type structure and the planar type structure.
  • the conductor 503 is stretched to function as wiring.
  • the present invention is not limited to this, and a conductor that functions as wiring may be provided under the conductor 503. Further, it is not always necessary to provide one conductor 503 for each transistor. For example, the conductor 503 may be shared by a plurality of transistors.
  • the conductor 503 shows a configuration in which the conductor 503a and the conductor 503b are laminated, but the present invention is not limited to this.
  • the conductor 503 may be provided as a single layer or a laminated structure having three or more layers.
  • the insulator 522 and the insulator 524 function as a gate insulator.
  • the insulator 522 preferably has a function of suppressing the diffusion of hydrogen (for example, at least one hydrogen atom, hydrogen molecule, etc.). Further, the insulator 522 preferably has a function of suppressing the diffusion of oxygen (for example, at least one oxygen atom, oxygen molecule, etc.). For example, the insulator 522 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 524.
  • the insulator 522 it is preferable to use an insulator containing oxides of one or both of aluminum and hafnium, which are insulating materials.
  • the insulator it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate) and the like.
  • the insulator 522 releases oxygen from the oxide 530 to the substrate side and diffuses impurities such as hydrogen from the peripheral portion of the transistor 500 to the oxide 530. And, it functions as a layer to suppress.
  • the insulator 522 impurities such as hydrogen can be suppressed from diffusing into the inside of the transistor 500, and the generation of oxygen deficiency in the oxide 530 can be suppressed. Further, it is possible to suppress the conductor 503 from reacting with the oxygen contained in the insulator 524 or the oxide 530.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may be added to the insulator.
  • these insulators may be nitrided.
  • the insulator 522 may be used by laminating silicon oxide, silicon oxide or silicon nitride on these insulators.
  • an insulator containing a so-called high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide and the like may be used in a single layer or in a laminated state.
  • a so-called high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide and the like
  • problems such as leakage current may occur due to the thinning of the gate insulator.
  • a high-k material for an insulator that functions as a gate insulator it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.
  • insulator 522 a substance having a high dielectric constant such as lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), (Ba, Sr) TiO 3 (BST) may be used.
  • PZT lead zirconate titanate
  • strontium titanate SrTiO 3
  • Ba, Sr Ba TiO 3
  • silicon oxide, silicon nitride nitride, or the like may be appropriately used.
  • the heat treatment may be performed, for example, at 100 ° C. or higher and 600 ° C. or lower, more preferably 350 ° C. or higher and 550 ° C. or lower.
  • the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more of an oxidizing gas, 1% or more, or 10% or more.
  • the heat treatment is preferably performed in an oxygen atmosphere.
  • oxygen can be supplied to the oxide 530 to reduce oxygen deficiency (VO).
  • the heat treatment may be performed in a reduced pressure state.
  • the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of oxidizing gas in order to supplement the desorbed oxygen after the heat treatment in an atmosphere of nitrogen gas or an inert gas. good.
  • the heat treatment may be performed in an atmosphere containing 10 ppm or more of an oxidizing gas, 1% or more, or 10% or more, and then continuously heat-treated in an atmosphere of nitrogen gas or an inert gas.
  • the oxygen deficiency in the oxide 530 can be repaired by the supplied oxygen, in other words, the reaction "VO + O ⁇ null" can be promoted. .. Further, the oxygen supplied to the hydrogen remaining in the oxide 530 reacts with the hydrogen, so that the hydrogen can be removed (dehydrated) as H2O . As a result, it is possible to suppress the hydrogen remaining in the oxide 530 from being recombined with the oxygen deficiency to form VOH.
  • the insulator 522 and the insulator 524 may have a laminated structure of two or more layers.
  • the laminated structure is not limited to the same material, and may be a laminated structure made of different materials.
  • the insulator 524 may be formed in an island shape by superimposing on the oxide 530a. In this case, the insulator 544 is in contact with the side surface of the insulator 524 and the upper surface of the insulator 522.
  • the conductor 542a and the conductor 542b are provided in contact with the upper surface of the oxide 530b.
  • the conductor 542a and the conductor 542b each function as a source electrode or a drain electrode of the transistor 500.
  • Examples of the conductor 542 include a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, and the like. It is preferable to use a nitride or the like containing titanium and aluminum. In one aspect of the invention, a nitride containing tantalum is particularly preferred. Further, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, and the like may be used. These materials are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when oxygen is absorbed.
  • Hydrogen contained in the oxide 530b or the like may diffuse into the conductor 542a or the conductor 542b.
  • hydrogen contained in the oxide 530b or the like is likely to diffuse into the conductor 542a or the conductor 542b, and the diffused hydrogen is the conductor. It may bind to the nitrogen contained in the 542a or the conductor 542b. That is, hydrogen contained in the oxide 530b or the like may be absorbed by the conductor 542a or the conductor 542b.
  • the conductor 542 it is preferable that no curved surface is formed between the side surface of the conductor 542 and the upper surface of the conductor 542.
  • the conductor 542 on which the curved surface is not formed the cross-sectional area of the conductor 542 in the cross section in the channel width direction can be increased.
  • the conductivity of the conductor 542 can be increased and the on-current of the transistor 500 can be increased.
  • the insulator 571a is provided in contact with the upper surface of the conductor 542a, and the insulator 571b is provided in contact with the upper surface of the conductor 542b.
  • the insulator 571 preferably functions as a barrier insulating film against at least oxygen. Therefore, it is preferable that the insulator 571 has a function of suppressing the diffusion of oxygen.
  • the insulator 571 preferably has a function of suppressing the diffusion of oxygen more than the insulator 580.
  • a nitride containing silicon such as silicon nitride may be used.
  • the insulator 571 preferably has a function of capturing impurities such as hydrogen.
  • a metal oxide having an amorphous structure for example, an insulator such as aluminum oxide or magnesium oxide may be used.
  • an insulator such as aluminum oxide or magnesium oxide
  • the insulator 544 is provided so as to cover the insulator 524, the oxide 530a, the oxide 530b, the conductor 542, and the insulator 571. It is preferable that the insulator 544 has a function of capturing hydrogen and fixing hydrogen. In that case, the insulator 544 preferably contains an insulator such as silicon nitride or a metal oxide having an amorphous structure, for example, aluminum oxide or magnesium oxide. Further, for example, as the insulator 544, a laminated film of aluminum oxide and silicon nitride on the aluminum oxide may be used.
  • the conductor 542 can be wrapped with the insulator having a barrier property against oxygen. That is, it is possible to prevent oxygen contained in the insulator 524 and the insulator 580 from diffusing into the conductor 542. As a result, the conductor 542 is directly oxidized by the oxygen contained in the insulator 524 and the insulator 580 to increase the resistivity and suppress the decrease in the on-current.
  • the insulator 552 functions as part of the gate insulator.
  • an insulator that can be used for the above-mentioned insulator 574 may be used.
  • an insulator containing an oxide of one or both of aluminum and hafnium may be used.
  • aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate) and the like can be used.
  • aluminum oxide is used as the insulator 552.
  • the insulator 552 is an insulator having at least oxygen and aluminum.
  • the insulator 552 is provided in contact with the upper surface and the side surface of the oxide 530b, the side surface of the oxide 530a, the side surface of the insulator 524, and the upper surface of the insulator 522. That is, the region of the oxide 530a, the oxide 530b, and the insulator 524 overlapping with the conductor 560 is covered with the insulator 552 in the cross section in the channel width direction. Thereby, when the heat treatment or the like is performed, the desorption of oxygen by the oxide 530a and the oxide 530b can be blocked by the insulator 552 having a barrier property against oxygen.
  • the insulator 580, the insulator 550, and the like contain an excessive amount of oxygen, it is possible to suppress the excessive supply of the oxygen to the oxide 530a and the oxide 530b. Therefore, it is possible to prevent the region 530ba and the region 530bb from being excessively oxidized via the region 530bc to cause a decrease in the on-current of the transistor 500 or a decrease in the field effect mobility.
  • the insulator 552 is provided in contact with the side surfaces of the conductor 542, the insulator 571, the insulator 544, and the insulator 580, respectively. Therefore, it is possible to reduce the oxidation of the side surface of the conductor 542 and the formation of an oxide film on the side surface. As a result, it is possible to suppress a decrease in the on-current of the transistor 500 or a decrease in the field effect mobility.
  • the insulator 552 needs to be provided in the opening formed in the insulator 580 or the like together with the insulator 554, the insulator 550, and the conductor 560. In order to miniaturize the transistor 500, it is preferable that the thickness of the insulator 552 is thin.
  • the film thickness of the insulator 552 is preferably 0.1 nm or more, 0.5 nm or more, or 1.0 nm or more, and preferably 1.0 nm or less, 3.0 nm or less, or 5.0 nm or less. ..
  • the above-mentioned lower limit value and upper limit value can be combined.
  • the insulator 552 may have a region having the above-mentioned film thickness at least in a part thereof. Further, the film thickness of the insulator 552 is preferably thinner than the film thickness of the insulator 550. In this case, the insulator 552 may have a region having a film thickness thinner than that of the insulator 550, at least in part.
  • the insulator 552 In order to form the insulator 552 with a thin film thickness as described above, it is preferable to form the insulator by using the ALD method.
  • the ALD method include a thermal ALD (Thermal ALD) method in which the reaction of the precursor and the reactor is performed only by thermal energy, and a PEALD (Plasma Enhanced ALD) method using a plasma-excited reactor.
  • a thermal ALD Thermal ALD
  • PEALD Laser ALD
  • the ALD method utilizes the characteristics of atoms, which are self-regulating properties, and can deposit atoms layer by layer, so ultra-thin film formation is possible, film formation into structures with a high aspect ratio is possible, pinholes, etc. It has the effects of being able to form a film with few defects, being able to form a film with excellent coverage, and being able to form a film at a low temperature. Therefore, the insulator 552 can be formed on the side surface of the opening formed in the insulator 580 or the like with good coverage and with a thin film thickness as described above.
  • the film provided by the ALD method may contain a large amount of impurities such as carbon as compared with the film provided by other film forming methods.
  • the quantification of impurities can be performed by using secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry) or X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy).
  • the insulator 550 functions as part of the gate insulator.
  • the insulator 550 is preferably arranged in contact with the upper surface of the insulator 552.
  • the insulator 550 includes silicon oxide, silicon nitriding, silicon nitride, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having holes, and the like. Can be used.
  • silicon oxide and silicon nitride nitride are preferable because they are stable against heat.
  • the insulator 550 is an insulator having at least oxygen and silicon.
  • the insulator 550 preferably has a reduced concentration of impurities such as water and hydrogen in the insulator 550.
  • the film thickness of the insulator 550 is preferably 1 nm or more, or 0.5 nm or more, and preferably 15 nm or less, or 20 nm or less.
  • the above-mentioned lower limit value and upper limit value can be combined.
  • the insulator 550 may have a region having the above-mentioned film thickness at least in a part thereof.
  • FIGS. 7A and 7B show a configuration in which the insulator 550 is a single layer
  • the present invention is not limited to this, and a laminated structure of two or more layers may be used.
  • the insulator 550 may have a two-layer laminated structure of the insulator 550a and the insulator 550b on the insulator 550a.
  • the lower insulator 550a is formed by using an insulator that easily permeates oxygen
  • the upper insulator 550b is a diffusion of oxygen. It is preferable to use an insulator having a function of suppressing the above. With such a configuration, oxygen contained in the insulator 550a can be suppressed from diffusing into the conductor 560. That is, it is possible to suppress a decrease in the amount of oxygen supplied to the oxide 530. Further, it is possible to suppress the oxidation of the conductor 560 by the oxygen contained in the insulator 550a.
  • the insulator 550a may be provided by using a material that can be used for the above-mentioned insulator 550, and the insulator 550b may be an insulator containing an oxide of one or both of aluminum and hafnium.
  • the insulator aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate) and the like can be used.
  • hafnium oxide is used as the insulator 550b.
  • the insulator 550b is an insulator having at least oxygen and hafnium.
  • the film thickness of the insulator 550b is preferably 0.5 nm or more, or 1.0 nm or more, and preferably 3.0 nm or less, or 5.0 nm or less.
  • the above-mentioned lower limit value and upper limit value can be combined.
  • the insulator 550b may have, at least in part, a region having the above-mentioned film thickness.
  • an insulating material which is a high-k material having a high relative permittivity may be used for the insulator 550b.
  • the gate insulator By forming the gate insulator into a laminated structure of the insulator 550a and the insulator 550b, it is possible to obtain a laminated structure that is stable against heat and has a high relative permittivity. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. Further, it is possible to reduce the equivalent oxide film thickness (EOT) of the insulator that functions as a gate insulator. Therefore, the withstand voltage of the insulator 550 can be increased.
  • EOT equivalent oxide film thickness
  • the insulator 554 functions as part of the gate insulator.
  • silicon nitride formed by the PEALD method may be used as the insulator 554.
  • the insulator 554 is an insulator having at least nitrogen and silicon.
  • the insulator 554 may further have a barrier property against oxygen. As a result, oxygen contained in the insulator 550 can be suppressed from diffusing into the conductor 560.
  • the insulator 554 needs to be provided in the opening formed in the insulator 580 or the like together with the insulator 552, the insulator 550, and the conductor 560. In order to miniaturize the transistor 500, it is preferable that the thickness of the insulator 554 is thin.
  • the film thickness of the insulator 554 is preferably 0.1 nm or more, 0.5 nm or more, or 1.0 nm or more, and preferably 3.0 nm or less, or 5.0 nm or less.
  • the above-mentioned lower limit value and upper limit value can be combined.
  • the insulator 554 may have a region having the above-mentioned film thickness at least in a part thereof.
  • the film thickness of the insulator 554 is preferably thinner than the film thickness of the insulator 550.
  • the insulator 554 may have a region having a film thickness thinner than that of the insulator 550, at least in part.
  • the conductor 560 functions as a first gate electrode of the transistor 500.
  • the conductor 560 preferably has a conductor 560a and a conductor 560b arranged on the conductor 560a.
  • the conductor 560a is preferably arranged so as to wrap the bottom surface and the side surface of the conductor 560b.
  • the position of the upper part of the conductor 560 substantially coincides with the position of the upper part of the insulator 550. In FIGS.
  • the conductor 560 is shown as a two-layer structure of the conductor 560a and the conductor 560b, but the conductor 560 has a single-layer structure or a three-layer structure other than the two-layer structure. It can be a laminated structure with more than one layer.
  • a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitrogen oxide molecule and copper atom.
  • a conductive material having a function of suppressing the diffusion of oxygen for example, at least one such as an oxygen atom and an oxygen molecule.
  • the conductor 560a has a function of suppressing the diffusion of oxygen, it is possible to prevent the conductor 560b from being oxidized by the oxygen contained in the insulator 550 and the conductivity from being lowered.
  • the conductive material having a function of suppressing the diffusion of oxygen for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide and the like are preferably used.
  • the conductor 560 also functions as wiring, it is preferable to use a conductor having high conductivity.
  • a conductor having high conductivity for example, as the conductor 560b, a conductive material containing tungsten, copper, or aluminum as a main component can be used.
  • the conductor 560b can have a laminated structure. Specifically, for example, the conductor 560b may have a laminated structure of titanium or titanium nitride and the conductive material.
  • the conductor 560 is self-aligned so as to fill the opening formed in the insulator 580 or the like.
  • the conductor 560 can be reliably arranged in the region between the conductor 542a and the conductor 542b without aligning the conductor 560.
  • the height is preferably lower than the height of the bottom surface of the oxide 530b.
  • the conductor 560 functioning as a gate electrode covers the side surface and the upper surface of the channel forming region of the oxide 530b via an insulator 550 or the like, so that the electric field of the conductor 560 can be applied to the channel forming region of the oxide 530b. It becomes easier to act on the whole. Therefore, the on-current of the transistor 500 can be increased and the frequency characteristics can be improved.
  • the difference is preferably 0 nm or more, 3 nm or more, or 5 nm or more, and preferably 20 nm or less, 50 nm or less, or 100 nm or less.
  • the above-mentioned lower limit value and upper limit value can be combined.
  • the insulator 580 is provided on the insulator 544, and an opening is formed in a region where the insulator 550 and the conductor 560 are provided. Further, the upper surface of the insulator 580 may be flattened.
  • the insulator 580 that functions as an interlayer film preferably has a low dielectric constant.
  • a material having a low dielectric constant as an interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings.
  • the insulator 580 is provided, for example, by using the same material as the insulator 516.
  • silicon oxide and silicon nitride nitride are preferable because they are thermally stable.
  • materials such as silicon oxide, silicon oxynitride, and silicon oxide having pores are preferable because they can easily form a region containing oxygen desorbed by heating.
  • the concentration of impurities such as water and hydrogen in the insulator 580 is reduced.
  • the insulator 580 may appropriately use an oxide containing silicon such as silicon oxide and silicon nitride nitride.
  • the insulator 574 preferably functions as a barrier insulating film that suppresses impurities such as water and hydrogen from diffusing into the insulator 580 from above, and preferably has a function of capturing impurities such as hydrogen. Further, the insulator 574 preferably functions as a barrier insulating film that suppresses the permeation of oxygen.
  • a metal oxide having an amorphous structure for example, an insulator such as aluminum oxide may be used. In this case, the insulator 574 is an insulator having at least oxygen and aluminum.
  • the insulator 574 which has a function of capturing impurities such as hydrogen in contact with the insulator 580, hydrogen and the like contained in the insulator 580 and the like are provided. Impurities can be captured and the amount of hydrogen in the region can be kept constant. In particular, it is preferable to use aluminum oxide having an amorphous structure as the insulator 574 because hydrogen may be captured or fixed more effectively. This makes it possible to manufacture a transistor 500 having good characteristics and high reliability, and a semiconductor device.
  • the insulator 576 functions as a barrier insulating film that suppresses impurities such as water and hydrogen from diffusing into the insulator 580 from above. Insulator 576 is placed on top of insulator 574.
  • a nitride containing silicon such as silicon nitride or silicon oxide.
  • silicon nitride formed by a sputtering method may be used as the insulator 576.
  • a silicon nitride film having a high density can be formed.
  • silicon nitride formed by the PEALD method or the CVD method may be further laminated on the silicon nitride formed by the sputtering method.
  • one of the first terminal or the second terminal of the transistor 500 is electrically connected to the conductor 540a functioning as a plug, and the other of the first terminal or the second terminal of the transistor 500 is connected to the conductor 540b. It is electrically connected.
  • the conductor 540a and the conductor 540b are collectively referred to as a conductor 540.
  • the conductor 540a is provided in a region overlapping with the conductor 542a. Specifically, in the region overlapping with the conductor 542a, the insulator 571, the insulator 544, the insulator 580, the insulator 574, the insulator 576, and the insulator 581 shown in FIG. 7A, and the insulator further shown in FIG. An opening is formed in the 582 and the insulator 586, and the conductor 540a is provided inside the opening. Further, the conductor 540b is provided, for example, in a region overlapping with the conductor 542b.
  • An opening is formed in the 582 and the insulator 586, and the conductor 540b is provided inside the opening.
  • the insulator 582 and the insulator 586 will be described later.
  • an insulator 541a may be provided as an insulator having a barrier property against impurities between the side surface of the opening of the region overlapping with the conductor 542a and the conductor 540a. ..
  • an insulator 541b may be provided as an insulator having a barrier property against impurities between the side surface of the opening of the region overlapping with the conductor 542b and the conductor 540b.
  • the insulator 541a and the insulator 541b are collectively referred to as an insulator 541.
  • the conductor 540a and the conductor 540b it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component. Further, the conductor 540a and the conductor 540b may have a laminated structure.
  • the insulator 574, the insulator 576, the insulator 581, the insulator 580, the insulator 544, and the first conductor arranged in the vicinity of the insulator 571 are included in the first conductor.
  • a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide and the like are preferably used.
  • the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or in a laminated manner. Further, it is possible to prevent impurities such as water and hydrogen contained in the layer above the insulator 576 from being mixed into the oxide 530 through the conductor 540a and the conductor 540b.
  • a barrier insulating film that can be used for the insulator 544 or the like may be used.
  • insulators such as silicon nitride, aluminum oxide, and silicon nitride may be used. Since the insulator 541a and the insulator 541b are provided in contact with the insulator 580, impurities such as water and hydrogen contained in the insulator 580 and the like are prevented from being mixed into the oxide 530 through the conductor 540a and the conductor 540b. It can be suppressed.
  • silicon nitride is suitable because it has a high blocking property against hydrogen. Further, it is possible to prevent oxygen contained in the insulator 580 from being absorbed by the conductor 540a and the conductor 540b.
  • the first insulator in contact with the inner wall of the opening such as the insulator 580 and the second insulator inside the insulator are against oxygen. It is preferable to use a barrier insulating film in combination with a barrier insulating film against hydrogen.
  • aluminum oxide formed by the ALD method may be used as the first insulator, and silicon nitride formed by the PEALD method may be used as the second insulator.
  • silicon nitride formed by the PEALD method may be used as the second insulator.
  • the insulator 541 may be provided as a single layer or a laminated structure having three or more layers.
  • the conductor 540 may be provided as a single layer or a laminated structure having three or more layers.
  • the conductor 610, the conductor 612, and the like which are in contact with the upper part of the conductor 540a and the upper part of the conductor 540b and function as wiring may be arranged.
  • the conductor 610 and the conductor 612 it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component.
  • the conductor may also have a laminated structure.
  • the conductor may be titanium or a laminate of titanium nitride and the conductive material.
  • the conductor may be formed so as to be embedded in an opening provided in the insulator.
  • the structure of the transistor included in the semiconductor device of one aspect of the present invention is not limited to the transistor 500 shown in FIGS. 6, 7A, 7B, and 8.
  • the structure of the transistor included in the semiconductor device of one aspect of the present invention may be changed depending on the situation.
  • the transistor 500 shown in FIGS. 6, 7A, 7B, and 8 may have the configuration shown in FIG.
  • the transistor of FIG. 10 differs from the transistor 500 shown in FIGS. 6, 7A, 7B, and 8 in that it has an oxide of 543a and an oxide of 543b.
  • the oxide 543a and the oxide 543b are collectively referred to as an oxide 543.
  • the cross section of the transistor in FIG. 10 in the channel width direction can be the same as the cross section of the transistor 500 shown in FIG. 7B.
  • the oxide 543a is provided between the oxide 530b and the conductor 542a, and the oxide 543b is provided between the oxide 530b and the conductor 542b.
  • the oxide 543a is preferably in contact with the upper surface of the oxide 530b and the lower surface of the conductor 542a.
  • the oxide 543b is preferably in contact with the upper surface of the oxide 530b and the lower surface of the conductor 542b.
  • the oxide 543 preferably has a function of suppressing the permeation of oxygen.
  • the oxide 543 is placed between the conductor 542 and the oxide 530b. It is preferable because the electric resistance is reduced. With such a configuration, the electrical characteristics, field effect mobility, and reliability of the transistor 500 may be improved.
  • a metal oxide having an element M may be used.
  • the element M aluminum, gallium, yttrium, or tin may be used.
  • the oxide 543 preferably has a higher concentration of the element M than the oxide 530b.
  • gallium oxide may be used as the oxide 543.
  • a metal oxide such as In—M—Zn oxide may be used.
  • the atomic number ratio of the element M to In is preferably larger than the atomic number ratio of the element M to In in the metal oxide used for the oxide 530b.
  • the film thickness of the oxide 543 is preferably 0.5 nm or more, or 1 nm or more, and preferably 2 nm or less, 3 nm or less, or 5 nm or less.
  • the above-mentioned lower limit value and upper limit value can be combined.
  • the oxide 543 preferably has crystallinity. When the oxide 543 has crystallinity, the release of oxygen in the oxide 530 can be suitably suppressed. For example, as the oxide 543, if it has a crystal structure such as a hexagonal crystal, it may be possible to suppress the release of oxygen in the oxide 530.
  • An insulator 582 is provided on the insulator 581, and an insulator 586 is provided on the insulator 582.
  • the insulator 582 it is preferable to use a substance having a barrier property against oxygen and hydrogen. Therefore, the same material as the insulator 514 can be used for the insulator 582. For example, it is preferable to use a metal oxide such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 582.
  • the same material as the insulator 320 can be used. Further, by applying a material having a relatively low dielectric constant to these insulators, it is possible to reduce the parasitic capacitance generated between the wirings.
  • a silicon oxide film, a silicon nitride film, or the like can be used as the insulator 586.
  • the capacity 600 and its peripheral wiring or plug will be described.
  • a capacity of 600, wiring, and / or a plug are provided above the transistor 500 shown in FIGS. 6 and 8.
  • the capacity 600 has, for example, a conductor 610, a conductor 620, and an insulator 630.
  • a conductor 610 is provided on one of the conductors 540a or 540b, the conductor 546, and the insulator 586.
  • the conductor 610 functions as one of a pair of electrodes having a capacity of 600.
  • the conductor 612 is provided on the other of the conductor 540a or the conductor 540b and on the insulator 586.
  • the conductor 612 has a function as a plug, wiring, terminal, or the like for electrically connecting the transistor 500 and a circuit element, wiring, or the like arranged above.
  • the conductor 612 and the conductor 610 may be formed at the same time.
  • the conductor 612 and the conductor 610 include a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above-mentioned elements as components.
  • a metal nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film and the like can be used.
  • indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon oxide are added. It is also possible to apply a conductive material such as indium tin oxide.
  • the conductor 612 and the conductor 610 show a single-layer structure, but the structure is not limited to this, and a laminated structure of two or more layers may be used.
  • a conductor having a barrier property and a conductor having a high adhesion to the conductor having a high conductivity may be formed between the conductor having the barrier property and the conductor having a high conductivity.
  • An insulator 630 is provided on the insulator 586 and the conductor 610.
  • the insulator 630 functions as a dielectric sandwiched between a pair of electrodes having a capacity of 600.
  • Examples of the insulator 630 include silicon oxide, silicon oxide, silicon nitride, silicon nitride, aluminum oxide, aluminum oxide, aluminum nitride, aluminum nitride, hafnium oxide, hafnium oxide, hafnium nitride, and hafnium nitride.
  • Aluminum oxide or the like can be used.
  • the insulator 630 can be provided as a laminated or a single layer by using the above-mentioned material.
  • the insulator 630 a laminated structure of a material having a large dielectric strength such as silicon oxide and a material having a high dielectric constant (high ⁇ k) may be used.
  • the capacity 600 can secure a sufficient capacity by having an insulator having a high dielectric constant (high-k), and by having an insulator having a large dielectric strength, the dielectric strength is improved and the capacity is 600. Can suppress electrostatic breakdown.
  • the insulator of the high dielectric constant (high-k) material material having a high specific dielectric constant
  • the insulator 630 may be, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ) or (Ba, Sr) TiO 3 (BST) or the like. Insulators containing high-k material may be used in a single layer or laminated. Further, as the insulator 630, a compound containing hafnium and zirconium may be used. As semiconductor devices become finer and more integrated, problems such as leakage currents in transistors and capacitive elements may occur due to the thinning of the gate insulator and the dielectric used in the capacitive element.
  • the gate insulator and the insulator that functions as a dielectric used for the capacitive element By using a high-k material for the gate insulator and the insulator that functions as a dielectric used for the capacitive element, it is possible to reduce the gate potential during transistor operation and secure the capacitance of the capacitive element while maintaining the physical film thickness. It will be possible.
  • the conductor 620 is provided so as to be superimposed on the conductor 610 via the insulator 630.
  • the conductor 610 functions as one of a pair of electrodes having a capacity of 600.
  • a conductive material such as a metal material, an alloy material, or a metal oxide material can be used. It is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. Further, when it is formed at the same time as another structure such as a conductor, Cu (copper), Al (aluminum) or the like, which are low resistance metal materials, may be used. Further, for example, as the conductor 620, a material applicable to the conductor 610 can be used. Further, the conductor 620 may have a laminated structure of two or more layers instead of a single layer structure.
  • An insulator 640 is provided on the conductor 620 and the insulator 630.
  • the insulator 640 for example, it is preferable to use a film having a barrier property so that hydrogen, impurities and the like do not diffuse in the region where the transistor 500 is provided. Therefore, the same material as the insulator 324 can be used.
  • An insulator 650 is provided on the insulator 640.
  • the insulator 650 can be provided by using the same material as the insulator 320. Further, the insulator 650 may function as a flattening film that covers the uneven shape below the insulator 650. Therefore, the insulator 650 can be, for example, a material applicable to the insulator 324.
  • the capacitance 600 shown in FIGS. 6 and 8 is a planar type, but the shape of the capacitance element is not limited to this.
  • the capacity 600 may be, for example, a cylinder type instead of the planar type.
  • a wiring layer may be provided above the capacity 600.
  • the insulator 411, the insulator 412, the insulator 413, and the insulator 414 are provided in order above the insulator 650.
  • the insulator 411, the insulator 412, and the insulator 413 are provided with a conductor 416 that functions as a plug or wiring.
  • the conductor 416 can be provided in a region superposed on the conductor 660, which will be described later.
  • the insulator 630, the insulator 640, and the insulator 650 are provided with an opening in a region overlapping with the conductor 612, and the conductor 660 is provided so as to fill the opening.
  • the conductor 660 functions as a plug and wiring that are electrically connected to the conductor 416 included in the wiring layer described above.
  • the insulator 411 and the insulator 414 for example, it is preferable to use an insulator having a barrier property against impurities such as water and hydrogen, similarly to the insulator 324 and the like. Therefore, as the insulator 411 and the insulator 414, for example, a material applicable to the insulator 324 or the like can be used.
  • the insulator 412 and the insulator 413 for example, like the insulator 326, it is preferable to use an insulator having a relatively low relative permittivity in order to reduce the parasitic capacitance generated between the wirings.
  • the conductor 612 and the conductor 416 can be provided, for example, by using the same materials as the conductor 328 and the conductor 330.
  • FIG. 11A shows an example of a transistor configuration in which a dielectric capable of having ferroelectricity is provided in the configuration of the transistor 500 shown in FIGS. 6 and 7A.
  • the transistor shown in FIG. 11A has a configuration in which the insulator 522 functioning as the second gate insulator is replaced with the insulator 520.
  • the insulator 520 as an example, a dielectric material capable of having ferroelectricity can be used.
  • a ferroelectric capacitor can be provided between the conductor 503 that functions as the second gate electrode and the oxide 530.
  • the transistor of FIG. 11A can be a FeFET (Ferroelectric FET) in which a dielectric material capable of having ferroelectricity is provided in a part of the second gate insulator.
  • the same material as the material that can be used for the dielectric of the capacitive FEC shown in the above embodiment can be used.
  • the insulator 520 is shown as one layer, but the insulator 520 may be an insulating film having two or more layers including a dielectric capable of having ferroelectricity.
  • a specific example transistor is shown in FIG. 11B.
  • the insulator 520 has an insulator 520a and an insulator 520b.
  • the insulator 520a is provided on the upper surface of each of the insulator 516 and the conductor 503, and the insulator 520b is provided on the upper surface of the insulator 520a.
  • insulator 520a for example, a dielectric material capable of having ferroelectricity can be used.
  • insulator 520b for example, silicon oxide or the like can be used.
  • silicon oxide may be used for the insulator 520a, and a dielectric material capable of having ferroelectricity may be used for the insulator 520b.
  • the conductor 503 functions as a gate electrode by using the insulator 520 as two layers, providing a dielectric capable of having ferroelectricity in one layer, and providing silicon oxide in the other layer.
  • the current leak flowing between the oxide 530 and the oxide 530 can be suppressed.
  • FIG. 11C shows a configuration example of a transistor having an insulator 520 as three layers.
  • the insulator 520 has, for example, an insulator 520a, an insulator 520b, and an insulator 520c.
  • the insulator 520c is provided on the upper surface of each of the insulator 516 and the conductor 503, the insulator 520a is provided on the upper surface of the insulator 520c, and the insulator 520b is provided on the upper surface of the insulator 520a. ing.
  • insulator 520a for example, a dielectric material capable of having ferroelectricity can be used. Further, as the insulator 520b and the insulator 520c, for example, silicon oxide or the like can be used.
  • Each configuration of the transistor and the ferroelectric capacitor shown in FIGS. 11A to 11C can be applied to, for example, the transistor M1 and the capacitive FEC shown in FIG. 2A and the like described in the above embodiment.
  • FIG. 12 shows an example of a transistor configuration in which a dielectric capable of having ferroelectricity is provided in the configuration of the transistor 500 of FIGS. 6 and 7A, which is different from the respective transistors of FIGS. 11A to 11C. ing.
  • the transistor shown in FIG. 12 is an insulator 552, an insulator 550, and an insulator 554 that function as a first gate insulator, a conductor 560 that functions as a first gate electrode, and a part of the insulator 580.
  • the insulator 561 is provided so as to be in contact with the insulator 552, the insulator 550, the insulator 554, the conductor 560, and a part of the region of the insulator 580.
  • the insulator 561 as an example, a dielectric material having a ferroelectricity, which can be applied to the insulator 520 of FIG. 11A, can be used.
  • a conductor 562 is provided in contact with the upper portion of the insulator 561.
  • the conductor 562 can be provided, for example, by using the same material as the conductor 328 and the conductor 330.
  • a ferroelectric capacitor can be provided between the conductor 503 that functions as the first gate electrode and the conductor 562.
  • the insulator 561 may have a laminated structure of two or more layers, similar to the insulator 520 shown in FIGS. 11B and 11C.
  • each configuration of the transistor and the ferroelectric capacitor shown in FIG. 12 can be applied to, for example, the transistor M2 and the capacitive FEC shown in FIG. 2A and the like described in the above embodiment.
  • 13A is a transistor configuration in which a dielectric capable of having ferroelectricity is provided in the configuration of the transistor 500 of FIGS. 6 and 7A, which is different from the respective transistors of FIGS. 11A to 11C and FIG. An example is shown.
  • the transistor shown in FIG. 13A is insulated in an opening provided in the insulator 544, the insulator 571b, the insulator 580, the insulator 574, the insulator 576, and the insulator 581 in the region superimposed on the conductor 542b.
  • a body 602 is provided. Specifically, in the opening, an insulator 541b is provided on the side surface of the opening, and a conductor 540b is provided on the insulator 541b and on the conductor 542b which is the bottom of the opening.
  • An insulator 602 is provided on a part of the region of the insulator 581 and on the conductor 540b, and a conductor 613 is provided on the insulator 602 so as to fill the remaining opening.
  • the insulator 541b is provided on the side surface of the opening, the conductor 540b is provided on the insulator 541b, and a part of the region of the insulator 581 is provided.
  • Insulator 602 is provided on the top, on the conductor 540b, and on the conductor 542b which is the bottom of the opening, and the conductor 613 is provided on the insulator 602 so as to fill the remaining opening. May be.
  • a dielectric material having a ferroelectricity which can be applied to the insulator 520 of FIG. 11A, can be used.
  • the conductor 613 can be provided, for example, by using the same material as the conductor 328 and the conductor 330.
  • a ferroelectric capacitor can be provided between the conductor 540b and the conductor 613 in the opening included in the region superimposed on the conductor 542b.
  • the insulator 602 may have a laminated structure of two or more layers, similar to the insulator 520 shown in FIGS. 11B and 11C.
  • the respective configurations of the transistor and the ferroelectric capacitor shown in FIG. 13A can be applied to, for example, the transistor M2 and the capacitive FEC shown in FIG. 2A and the like described in the above embodiment.
  • FIG. 13B is different from the transistors of FIGS. 11A to 11C, 12 and 13A, and the configuration of the transistor 500 of FIGS. 6 and 7A is provided with a dielectric capable of having ferroelectricity.
  • An example of the transistor configuration is shown.
  • the transistor shown in FIG. 13B has a configuration in which the insulator 552, the insulator 550, and the insulator 554 that function as the first gate insulator are replaced with the insulator 553.
  • the insulator 553 as an example, a dielectric material having a ferroelectricity, which can be applied to the insulator 520 of FIG. 11A, can be used.
  • a ferroelectric capacitor can be provided between the conductor 560 functioning as the first gate electrode and the oxide 530.
  • the transistor of FIG. 13B can be a FeFET in which a dielectric material capable of having ferroelectricity is provided in a part of the first gate insulator.
  • the insulator 553 may have a laminated structure of two or more layers, similar to the insulator 520 shown in FIGS. 11B and 11C.
  • the insulator 552, the insulator 550, and the insulator 554 are replaced with the insulator 553, but as another configuration example, the insulator 552, the insulator 550, and the insulator 554 are used. At least one may be replaced with the insulator 553 to form a laminated structure of the remaining insulator and the insulator 553.
  • the respective configurations of the transistor and the ferroelectric capacitor shown in FIG. 13B can be applied to, for example, the transistor M2 and the capacitive FEC shown in FIG. 2A and the like described in the above embodiment.
  • FIG. 14A shows an example of the configuration of the transistor 500 and the capacitance in which a capacitance including a dielectric capable of having ferroelectricity is provided around the transistor 500.
  • a plurality of openings are formed in the insulator 544, the insulator 571b, the insulator 580, the insulator 574, the insulator 576, and the insulator 581 in the region overlapping with the conductor 542b.
  • a conductor 540c that functions as a plug is provided inside one opening, and an insulator having a barrier property against impurities is provided between the side surface of the opening and the conductor 540c.
  • Insulator 541c is provided.
  • a conductor 540d that functions as a plug is provided inside another opening, and an insulator having a barrier property against impurities is provided between the side surface of the opening and the conductor 540d.
  • an insulator 541d is provided.
  • a material applicable to the conductor 540a and the conductor 540b can be used, and as the insulator 541c and the insulator 541d, for example, an insulator can be used. Materials applicable to the 541a and the insulator 541b can be used.
  • An insulator 601 is provided in contact with the conductor 540c and the upper part of the conductor 540d.
  • a dielectric material having a ferroelectricity which can be applied to the insulator 520 of FIG. 11A, can be used.
  • a conductor 611 is provided in contact with the upper portion of the insulator 601.
  • the conductor 611 can be provided, for example, by using the same material as the conductor 328 and the conductor 330.
  • a ferroelectric capacitor can be provided between the conductors 540c and 540d that function as plugs and the conductor 611.
  • the insulator 601 may have a laminated structure of two or more layers, similar to the insulator 520 shown in FIGS. 11B and 11C.
  • the number of plugs in contact with the insulator 601 is two (conductor 540c and conductor 540d), but the number of the plugs may be one or three or more. good.
  • FIG. 14A an example in which two openings having a conductor as a plug are provided in the region superimposed on the insulator 601 is shown, but the opening provided in the region superimposed on the insulator 601 is 1. It may be one, or three or more.
  • each configuration of the transistor and the ferroelectric capacitor shown in FIG. 14A can be applied to, for example, the transistor M2 and the capacitive FEC shown in FIG. 2A and the like described in the above embodiment.
  • FIG. 14B shows an example of the configuration of the transistor 500 and the capacitance, which is different from FIG. 14A and is provided with a capacitance including a dielectric having a ferroelectricity around the transistor 500.
  • the insulator 610 located on the conductor 540b functioning as a plug and the insulator 631 are provided on the upper surface of a part of the region of the insulator 581.
  • the insulator 631 as an example, a dielectric material having a ferroelectricity, which can be applied to the insulator 520 of FIG. 11A, can be used.
  • a conductor 620 is provided on the upper surface of the insulator 631, and insulation is provided on the upper surface of the insulator 581, the conductor 612, the conductor 620, and a part of the region of the insulator 631.
  • a body 640 and an insulator 650 are provided in order.
  • a ferroelectric capacitor can be provided between the conductor 610 and the conductor 620.
  • the insulator 631 may have a laminated structure of two or more layers, similar to the insulator 520 shown in FIGS. 11B and 11C.
  • Each configuration of the transistor and the ferroelectric capacitor shown in FIG. 14B can be applied to, for example, the transistor M1 and the capacitive FEC shown in FIG. 2A and the like described in the above embodiment.
  • FIG. 15 shows an example of the configuration of the transistor 500 and the capacitance, which is different from FIGS. 14A and 14B and in which a capacitance including a dielectric capable of having a ferroelectricity is provided around the transistor 500. ..
  • a plurality of openings are formed in the insulator 516, the conductor 503 is embedded in one opening, and the conductor 503A is embedded in another opening.
  • the conductor 503A for example, a material applicable to the conductor 503 can be used.
  • an insulator 517 and a conductor 519 are provided in order on the upper portion of the conductor 503A. Further, the insulator 522 described with the transistor 500 of FIG. 7A is covered on the insulator 517 and the conductor 519. Further, the insulator 544 described with reference to the transistor 500 of FIG. 7A is covered on the insulator 522.
  • insulator 517 As the insulator 517, as an example, a dielectric material having a ferroelectricity, which can be applied to the insulator 520 of FIG. 11A, can be used.
  • the conductor 519 can be provided, for example, by using the same material as the conductor 328 and the conductor 330.
  • a ferroelectric capacitor can be provided between the conductor 503A and the conductor 519.
  • the insulator 517 may have a laminated structure of two or more layers, similar to the insulator 520 shown in FIGS. 11B and 11C.
  • openings are formed in the insulator 522, the insulator 544, the insulator 580, the insulator 574, the insulator 576, and the insulator 581 in the region superposed on the conductor 503. .
  • a conductor 540e that functions as a plug is provided inside the opening, and an insulator having a barrier property against impurities is provided between the side surface of the opening and the conductor 540e.
  • An insulator 541e is provided.
  • the conductor 540e for example, a material applicable to the conductor 540a and the conductor 540b can be used
  • the insulator 541e for example, a material applicable to the insulator 541a and the insulator 541b. Can be used.
  • the conductors 540a and 540e that function as plugs and the conductor 611 are provided on the upper surface of a part of the region of the insulator 581.
  • the conductor 611 can be provided, for example, by using the same material as the conductor 328 and the conductor 330.
  • an insulator 640 and an insulator 650 are sequentially provided on the upper surfaces of the conductor 611 and a part of the insulator 581.
  • Each configuration of the transistor and the ferroelectric capacitor shown in FIG. 15 can be applied to, for example, the transistor M1 and the capacitive FEC shown in FIG. 2A and the like described in the above embodiment.
  • FIG. 16 shows an example in which the configuration of the insulator 582 and the capacity 600 located on the upper surface of the conductor 546 is changed in the semiconductor device shown in FIG.
  • the capacity 600 has, for example, a conductor 610, a conductor 620, an insulator 630, and an insulator 631.
  • a dielectric material capable of having ferroelectricity can be used as the insulator 631.
  • the conductor 610 and the conductor 612 can be made of the same material as the conductor 610 and the conductor 612 in FIG. Further, in FIG. 16, the conductor 610 and the conductor 612 can be formed in the same manner as the conductor 610 and the conductor 612 in FIG.
  • the insulator 630 is provided on the upper surface of the conductor 610 and a part of the region of the insulator 586. Further, the insulator 631 is provided on the upper surface of the insulator 630, and the conductor 620 is provided on the upper surface of the insulator 631.
  • insulator 630 for example, a material applicable to the insulator 630 of FIG. 6 can be used.
  • the insulator 640 is an upper surface of a region including an end portion of the insulator 630, a region including the end portion of the insulator 631, a conductor 620, and a part region of the insulator 586. It is provided in.
  • insulator 640 for example, a material applicable to the insulator 640 of FIG. 6 can be used.
  • the ferroelectric capacitor can be provided in the semiconductor device shown in FIG. 16.
  • the semiconductor device shown in FIG. 17 is a modification of the semiconductor device of FIG. 16, and is provided by an insulator 571, an insulator 544, an insulator 574, an insulator 576, an insulator 581, an insulator 641, an insulator 642, and the like. It has a structure that surrounds the transistor 500 and the capacity 600.
  • an opening is provided which reaches the insulator 514 after the substrate 310 to the insulator 574 are provided in order, but the semiconductor device of FIG. 17 has an opening. After the substrate 310 to the insulator 640 are provided in order, an opening extending to the insulator 514 is provided.
  • an insulator 641, an insulator 642, and an insulator 650 are sequentially provided on the bottom of the opening and the upper surface of the insulator 640.
  • the insulator 641 and the insulator 642 can function as a barrier insulating film that prevents impurities such as water and hydrogen from diffusing from above the transistor 500 and the capacity 600 into the transistor 500 and the capacity 600. preferable.
  • a sputtering method can be used as a film forming method for the insulator 641.
  • a sputtering method can be used as the insulator 641.
  • silicon nitride formed by a sputtering method can be used. Since the sputtering method does not require the use of molecules containing hydrogen in the film-forming gas, the hydrogen concentration of the insulator 641 can be reduced. By reducing the hydrogen concentration of the insulator 641, it is possible to suppress the diffusion of hydrogen from the insulator 641 to the conductor 610, the conductor 612, and the insulator 586.
  • the insulator 642 for example, it is preferable to form a film by using an ALD method, particularly a PEALD method.
  • ALD method particularly a PEALD method.
  • silicon nitride formed by the PEALD method can be used as the insulator 642.
  • the insulator 642 can be formed into a film with good coverage. Therefore, even if pinholes or step breaks are formed in the insulator 641 due to the unevenness of the base, hydrogen can be formed by covering them with the insulator 642. Can be reduced from diffusing into the conductor 610, the conductor 612, and the insulator 586.
  • impurities such as water and hydrogen diffuse to the transistor 500 and the capacity 600 side via the insulator 512, the insulator 514, the insulator 641, the insulator 642 and the like. Can be prevented. Further, oxygen contained in the insulator 580 or the like can be prevented from diffusing to the outside through the insulator 574, the insulator 641, the insulator 642 or the like.
  • the area of a circuit constituting the semiconductor device can be reduced by achieving a laminated structure, miniaturization, high integration, and the like.
  • a ferroelectric capacitor as a capacitive element included in a semiconductor device
  • the value of the capacitance of the capacitive element can be increased, so that the capacitive element can be miniaturized. Therefore, the area of the circuit including the capacitive element can be reduced.
  • the circuit scale can be increased while suppressing the increase in the circuit area of the semiconductor device.
  • the metal oxide preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. Moreover, in addition to them, it is preferable that aluminum, gallium, yttrium, tin and the like are contained. Further, one or more kinds selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt and the like may be contained. ..
  • FIG. 18A is a diagram illustrating the classification of the crystal structure of an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn).
  • IGZO a metal oxide containing In, Ga, and Zn
  • oxide semiconductors are roughly classified into “Amorphous”, “Crystalline”, and “Crystal”.
  • Amorphous includes “completable amorphous”.
  • Crystalline includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (Cloud-Aligned Complex).
  • single crystal, poly crystal, and single crystal amorphous are excluded from the classification of "Crystalline”.
  • “Crystal” includes single crystal and poly crystal.
  • the structure in the thick frame shown in FIG. 18A is an intermediate state between "Amorphous” and “Crystal", and belongs to a new boundary region (New crystal line phase). .. That is, the structure can be rephrased as a structure completely different from the energetically unstable "Amorphous” and "Crystal".
  • the crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD: X-Ray Diffraction) spectrum.
  • XRD X-ray diffraction
  • the GIXD method is also referred to as a thin film method or a Seemann-Bohlin method.
  • the XRD spectrum obtained by the GIXD measurement shown in FIG. 18B may be simply referred to as an XRD spectrum.
  • the thickness of the CAAC-IGZO film shown in FIG. 18B is 500 nm.
  • a peak showing clear crystallinity is detected in the XRD spectrum of the CAAC-IGZO film.
  • the crystal structure of the film or the substrate can be evaluated by a diffraction pattern (also referred to as a microelectron diffraction pattern) observed by a micro electron diffraction method (NBED: Nano Beam Electron Diffraction).
  • the diffraction pattern of the CAAC-IGZO film is shown in FIG. 18C.
  • FIG. 18C is a diffraction pattern observed by the NBED in which the electron beam is incident parallel to the substrate.
  • electron diffraction is performed with the probe diameter set to 1 nm.
  • oxide semiconductors may be classified differently from FIG. 18A.
  • oxide semiconductors are divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors.
  • the non-single crystal oxide semiconductor include the above-mentioned CAAC-OS and nc-OS.
  • the non-single crystal oxide semiconductor includes a polycrystal oxide semiconductor, a pseudo-amorphous oxide semiconductor (a-like OS: atomous-like oxide semiconductor), an amorphous oxide semiconductor, and the like.
  • CAAC-OS CAAC-OS
  • nc-OS nc-OS
  • a-like OS the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described.
  • CAAC-OS is an oxide semiconductor having a plurality of crystal regions, the plurality of crystal regions having the c-axis oriented in a specific direction.
  • the specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface to be formed of the CAAC-OS film, or the normal direction of the surface of the CAAC-OS film.
  • the crystal region is a region having periodicity in the atomic arrangement. When the atomic arrangement is regarded as a lattice arrangement, the crystal region is also a region in which the lattice arrangement is aligned. Further, the CAAC-OS has a region in which a plurality of crystal regions are connected in the ab plane direction, and the region may have distortion.
  • the strain refers to a region in which a plurality of crystal regions are connected in which the orientation of the lattice arrangement changes between a region in which the lattice arrangement is aligned and a region in which another grid arrangement is aligned. That is, CAAC-OS is an oxide semiconductor that is c-axis oriented and not clearly oriented in the ab plane direction.
  • Each of the plurality of crystal regions is composed of one or a plurality of minute crystals (crystals having a maximum diameter of less than 10 nm).
  • the maximum diameter of the crystal region is less than 10 nm.
  • the size of the crystal region may be about several tens of nm.
  • CAAC-OS has indium (In) and oxygen. It tends to have a layered crystal structure (also referred to as a layered structure) in which a layer (hereinafter, In layer) and a layer having elements M, zinc (Zn), and oxygen (hereinafter, (M, Zn) layer) are laminated. There is. Indium and element M can be replaced with each other. Therefore, the (M, Zn) layer may contain indium. In addition, the In layer may contain the element M. The In layer may contain Zn.
  • the layered structure is observed as a grid image, for example, in a high-resolution TEM image.
  • the position of the peak indicating the c-axis orientation may vary depending on the type, composition, and the like of the metal elements constituting CAAC-OS.
  • a plurality of bright spots are observed in the electron diffraction pattern of the CAAC-OS film. Note that a certain spot and another spot are observed at point-symmetrical positions with the spot of the incident electron beam transmitted through the sample (also referred to as a direct spot) as the center of symmetry.
  • the lattice arrangement in the crystal region is based on a hexagonal lattice, but the unit lattice is not limited to a regular hexagon and may be a non-regular hexagon. Further, in the above strain, it may have a lattice arrangement such as a pentagon or a heptagon.
  • a clear grain boundary cannot be confirmed even in the vicinity of strain. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction, the bond distance between atoms changes due to the replacement of metal atoms, and the like. It is thought that this is the reason.
  • CAAC-OS for which no clear crystal grain boundary is confirmed, is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of the transistor.
  • a configuration having Zn is preferable.
  • In-Zn oxide and In-Ga-Zn oxide are more suitable than In oxide because they can suppress the generation of grain boundaries.
  • CAAC-OS is an oxide semiconductor having high crystallinity and no clear grain boundary is confirmed. Therefore, it can be said that CAAC-OS is unlikely to cause a decrease in electron mobility due to grain boundaries. Further, since the crystallinity of the oxide semiconductor may be lowered due to the mixing of impurities, the generation of defects, etc., CAAC-OS can be said to be an oxide semiconductor having few impurities, defects (oxygen deficiency, etc.). Therefore, the oxide semiconductor having CAAC-OS has stable physical properties. Therefore, the oxide semiconductor having CAAC-OS is resistant to heat and has high reliability. CAAC-OS is also stable against high temperatures (so-called thermal budgets) in the manufacturing process. Therefore, if CAAC-OS is used for the OS transistor, the degree of freedom in the manufacturing process can be expanded.
  • nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less).
  • nc-OS has tiny crystals. Since the size of the minute crystal is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystal is also referred to as a nanocrystal.
  • nc-OS has no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film.
  • the nc-OS may be indistinguishable from the a-like OS and the amorphous oxide semiconductor depending on the analysis method. For example, when structural analysis is performed on an nc-OS film using an XRD device, a peak indicating crystallinity is not detected in the Out-of-plane XRD measurement using a ⁇ / 2 ⁇ scan. Further, when electron beam diffraction (also referred to as selected area electron diffraction) using an electron beam having a probe diameter larger than that of nanocrystals (for example, 50 nm or more) is performed on the nc-OS film, a diffraction pattern such as a halo pattern is performed. Is observed.
  • electron beam diffraction also referred to as selected area electron diffraction
  • nanocrystals for example, 50 nm or more
  • electron diffraction also referred to as nanobeam electron diffraction
  • an electron beam having a probe diameter for example, 1 nm or more and 30 nm or less
  • An electron diffraction pattern in which a plurality of spots are observed in a ring-shaped region centered on a direct spot may be acquired.
  • the a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor.
  • the a-like OS has a void or low density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS.
  • a-like OS has a higher hydrogen concentration in the membrane than nc-OS and CAAC-OS.
  • CAC-OS relates to the material composition.
  • CAC-OS is, for example, a composition of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof.
  • the metal oxide one or more metal elements are unevenly distributed, and the region having the metal element is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or a size in the vicinity thereof.
  • the mixed state is also called a mosaic shape or a patch shape.
  • the CAC-OS has a structure in which the material is separated into a first region and a second region to form a mosaic, and the first region is distributed in the film (hereinafter, also referred to as a cloud shape). It is said.). That is, the CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.
  • the atomic number ratios of In, Ga, and Zn with respect to the metal elements constituting CAC-OS in the In-Ga-Zn oxide are expressed as [In], [Ga], and [Zn], respectively.
  • the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film.
  • the second region is a region in which [Ga] is larger than [Ga] in the composition of the CAC-OS film.
  • the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region.
  • the second region is a region in which [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.
  • the first region is a region containing indium oxide, indium zinc oxide, or the like as a main component.
  • the second region is a region containing gallium oxide, gallium zinc oxide, or the like as a main component. That is, the first region can be rephrased as a region containing In as a main component. Further, the second region can be rephrased as a region containing Ga as a main component.
  • a region containing In as a main component (No. 1) by EDX mapping acquired by using energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectroscopy). It can be confirmed that the region (1 region) and the region containing Ga as a main component (second region) are unevenly distributed and have a mixed structure.
  • CAC-OS When CAC-OS is used for a transistor, the conductivity caused by the first region and the insulating property caused by the second region act in a complementary manner to switch the switching function (On / Off function). Can be added to CAC-OS. That is, the CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and has a function as a semiconductor in the whole material. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS for the transistor, high on -current (Ion), high field effect mobility ( ⁇ ), and good switching operation can be realized.
  • Ion on -current
  • ⁇ high field effect mobility
  • Oxide semiconductors have various structures, and each has different characteristics.
  • the oxide semiconductor of one aspect of the present invention has two or more of amorphous oxide semiconductor, polycrystalline oxide semiconductor, a-like OS, CAC-OS, nc-OS, and CAAC-OS. You may.
  • the oxide semiconductor as a transistor, a transistor having high field effect mobility can be realized. In addition, a highly reliable transistor can be realized.
  • the carrier concentration of the oxide semiconductor is 1 ⁇ 10 17 cm -3 or less, preferably 1 ⁇ 10 15 cm -3 or less, more preferably 1 ⁇ 10 13 cm -3 or less, and more preferably 1 ⁇ 10 11 cm ⁇ . It is 3 or less, more preferably less than 1 ⁇ 10 10 cm -3 , and more preferably 1 ⁇ 10 -9 cm -3 or more.
  • the impurity concentration in the oxide semiconductor film may be lowered to lower the defect level density.
  • a low impurity concentration and a low defect level density is referred to as high-purity intrinsic or substantially high-purity intrinsic.
  • An oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.
  • the trap level density may also be low.
  • the charge captured at the trap level of the oxide semiconductor takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel forming region is formed in an oxide semiconductor having a high trap level density may have unstable electrical characteristics.
  • Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.
  • the concentrations of silicon and carbon in the oxide semiconductor and the concentrations of silicon and carbon near the interface with the oxide semiconductor are 2 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 17 atoms / cm 3 or less.
  • the oxide semiconductor contains an alkali metal or an alkaline earth metal
  • defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Therefore, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less.
  • the nitrogen concentration in the oxide semiconductor obtained by SIMS is less than 5 ⁇ 10 19 atoms / cm 3 , preferably 5 ⁇ 10 18 atoms / cm 3 or less, and more preferably 1 ⁇ 10 18 atoms / cm 3 or less. , More preferably 5 ⁇ 10 17 atoms / cm 3 or less.
  • hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to become water, which may form an oxygen deficiency.
  • oxygen deficiency When hydrogen enters the oxygen deficiency, electrons that are carriers may be generated.
  • a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have a normally-on characteristic. Therefore, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible.
  • the hydrogen concentration obtained by SIMS is less than 1 ⁇ 10 20 atoms / cm 3 , preferably less than 1 ⁇ 10 19 atoms / cm 3 , and more preferably 5 ⁇ 10 18 atoms / cm. Less than 3 , more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
  • This embodiment shows an example of a semiconductor wafer on which the semiconductor device and the like shown in the above embodiment are formed, and an electronic component in which the semiconductor device is incorporated.
  • the semiconductor wafer 4800 shown in FIG. 19A has a wafer 4801 and a plurality of circuit units 4802 provided on the upper surface of the wafer 4801.
  • the portion without the circuit portion 4802 is the spacing 4803, which is a dicing region.
  • the semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 by the previous step. Further, after that, the opposite surface on which the plurality of circuit portions 4802 of the wafer 4801 are formed may be ground to reduce the thickness of the wafer 4801. By this step, the warp of the wafer 4801 and the like can be reduced, and the size of the wafer can be reduced.
  • a dicing step is performed. Dicing is performed along the scribe line SCL1 and the scribe line SCL2 (sometimes referred to as a dicing line or a cutting line) indicated by a alternate long and short dash line.
  • the spacing 4803 is provided so that the plurality of scribe lines SCL1 are parallel to each other and the plurality of scribe lines SCL2 are parallel to each other in order to facilitate the dicing process. It is preferable to provide it so that it is vertical.
  • the chip 4800a as shown in FIG. 19B can be cut out from the semiconductor wafer 4800.
  • the chip 4800a has a wafer 4801a, a circuit unit 4802, and a spacing 4803a.
  • the spacing 4803a is preferably made as small as possible. In this case, the width of the spacing 4803 between the adjacent circuit portions 4802 may be substantially the same as the cutting margin of the scribe line SCL1 or the cutting margin of the scribe line SCL2.
  • the shape of the element substrate of one aspect of the present invention is not limited to the shape of the semiconductor wafer 4800 shown in FIG. 19A.
  • the shape of the element substrate can be appropriately changed depending on the process of manufacturing the device and the device for manufacturing the device.
  • FIG. 19C shows a perspective view of a board (mounting board 4704) on which the electronic component 4700 and the electronic component 4700 are mounted.
  • the electronic component 4700 shown in FIG. 19C has a chip 4800a in the mold 4711.
  • the chip 4800a shown in FIG. 19C shows a configuration in which circuit units 4802 are laminated. That is, the semiconductor device described in the above embodiment can be applied as the circuit unit 4802. In FIG. 19C, a part is omitted in order to show the inside of the electronic component 4700.
  • the electronic component 4700 has a land 4712 on the outside of the mold 4711.
  • the land 4712 is electrically connected to the electrode pad 4713, and the electrode pad 4713 is electrically connected to the chip 4800a by a wire 4714.
  • the electronic component 4700 is mounted on, for example, a printed circuit board 4702. A plurality of such electronic components are combined and electrically connected to each other on the printed circuit board 4702 to complete the mounting board 4704.
  • FIG. 19D shows a perspective view of the electronic component 4730.
  • the electronic component 4730 is an example of SiP (System in package) or MCM (Multi Chip Module).
  • the electronic component 4730 is provided with an interposer 4731 on a package substrate 4732 (printed circuit board), and a semiconductor device 4735 and a plurality of semiconductor devices 4710 are provided on the interposer 4731.
  • the electronic component 4730 has a semiconductor device 4710.
  • the semiconductor device 4710 can be, for example, the semiconductor device described in the above embodiment, a wideband memory (HBM: High Bandwidth Memory), or the like.
  • HBM High Bandwidth Memory
  • an integrated circuit semiconductor device such as a CPU, GPU, FPGA, and storage device can be used.
  • the package substrate 4732 a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used.
  • the interposer 4731 a silicon interposer, a resin interposer, or the like can be used.
  • the interposer 4731 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits having different terminal pitches.
  • the plurality of wirings are provided in a single layer or multiple layers.
  • the interposer 4731 has a function of electrically connecting the integrated circuit provided on the interposer 4731 to the electrode provided on the package substrate 4732.
  • the interposer may be referred to as a "rewiring board” or an "intermediate board”.
  • a through electrode may be provided on the interposer 4731, and the integrated circuit and the package substrate 4732 may be electrically connected using the through electrode.
  • a TSV Through Silicon Via
  • interposer 4731 It is preferable to use a silicon interposer as the interposer 4731. Since it is not necessary to provide an active element in the silicon interposer, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring of the silicon interposer can be formed by a semiconductor process, it is easy to form fine wiring, which is difficult with a resin interposer.
  • the interposer on which the HBM is mounted is required to form fine and high-density wiring. Therefore, it is preferable to use a silicon interposer as an interposer for mounting HBM.
  • the reliability is unlikely to be lowered due to the difference in the expansion coefficient between the integrated circuit and the interposer. Further, since the surface of the silicon interposer is high, poor connection between the integrated circuit provided on the silicon interposer and the silicon interposer is unlikely to occur. In particular, in a 2.5D package (2.5-dimensional mounting) in which a plurality of integrated circuits are arranged side by side on an interposer, it is preferable to use a silicon interposer.
  • a heat sink may be provided so as to be overlapped with the electronic component 4730.
  • the heat sink it is preferable that the heights of the integrated circuits provided on the interposer 4731 are the same.
  • the heights of the semiconductor device 4710 and the semiconductor device 4735 are the same.
  • an electrode 4733 may be provided on the bottom of the package substrate 4732.
  • FIG. 19D shows an example in which the electrode 4733 is formed of a solder ball.
  • BGA Ball Grid Array
  • the electrode 4733 may be formed of a conductive pin.
  • PGA Peripheral Component Interconnect
  • the electronic component 4730 can be mounted on another substrate by using various mounting methods, not limited to BGA and PGA.
  • BGA Base-Chip
  • PGA Stepgered Pin Grid Array
  • LGA Land Grid Array
  • QFP Quad Flat Package
  • QFJ Quad Flat J-leaded package
  • QFN QuadFN
  • FIG. 20 is a block diagram showing a configuration of an example of a CPU using the semiconductor device described in the above embodiment as a part.
  • the CPU shown in FIG. 20 has an ALU 1191 (ALU: Arithmetic logic unit, arithmetic unit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, and a bus interface 1198 on a substrate 1190. It has a (Bus I / F), a rewritable ROM 1199, and a ROM interface 1189 (ROM I / F).
  • the substrate 1190 a semiconductor substrate, an SOI substrate, a glass substrate, or the like is used.
  • the ROM 1199 and the ROM interface 1189 may be provided on separate chips.
  • the configuration including the CPU or the arithmetic circuit shown in FIG. 20 may be regarded as one core, and a configuration including a plurality of the cores and each core operating in parallel, that is, a configuration such as a GPU may be used.
  • the number of bits that the CPU can handle in the internal calculation circuit and the data bus can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, and the like.
  • Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195.
  • the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191. Further, the interrupt controller 1194 determines and processes an interrupt request from an external input / output device, a peripheral circuit, or the like from the priority and the mask state during the execution of the CPU program. The register controller 1197 generates the address of the register 1196, and reads or writes the register 1196 according to the state of the CPU.
  • the timing controller 1195 generates a signal for controlling the operation timing of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197.
  • the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal based on the reference clock signal, and supplies the internal clock signal to the above-mentioned various circuits.
  • the register 1196 may include, for example, the semiconductor device shown in the previous embodiment.
  • the register controller 1197 selects the holding operation in the register 1196 according to the instruction from the ALU 1191. That is, in the memory cell of the register 1196, it is selected whether to hold the data by the flip-flop or the data by the capacitive element. When data retention by flip-flop is selected, the power supply voltage is supplied to the memory cells in the register 1196. When the retention of data in the capacitive element is selected, the data is rewritten to the capacitive element, and the supply of the power supply voltage to the memory cell in the register 1196 can be stopped.
  • the information terminal 5500 shown in FIG. 21A is a mobile phone (smartphone) which is a kind of information terminal.
  • the information terminal 5500 has a housing 5510 and a display unit 5511, and as an input interface, a touch panel is provided in the display unit 5511 and a button is provided in the housing 5510.
  • the information terminal 5500 can hold a temporary file (for example, a cache when using a web browser) generated when the application is executed.
  • a temporary file for example, a cache when using a web browser
  • FIG. 21B illustrates an information terminal 5900, which is an example of a wearable terminal.
  • the information terminal 5900 has a housing 5901, a display unit 5902, an operation button 5903, an operator 5904, a band 5905, and the like.
  • the wearable terminal can hold a temporary file generated when the application is executed by applying the semiconductor device described in the above embodiment.
  • FIG. 21C shows a desktop type information terminal 5300.
  • the desktop type information terminal 5300 has a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.
  • the desktop information terminal 5300 can hold a temporary file generated when the application is executed by applying the semiconductor device described in the above embodiment.
  • smartphones, wearable terminals, and desktop information terminals are taken as examples as electronic devices and are shown in FIGS. 21A to 21C, respectively, but information terminals other than smartphones, wearable terminals, and desktop information terminals can be applied. can. Examples of information terminals other than smartphones, wearable terminals, and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, workstations, and the like.
  • PDAs Personal Digital Assistants
  • FIG. 21D shows an electric freezer / refrigerator 5800 as an example of an electric appliance.
  • the electric freezer / refrigerator 5800 has a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.
  • the electric freezer / refrigerator 5800 can be used as, for example, IoT (Internet of Things).
  • IoT Internet of Things
  • the electric refrigerator-freezer 5800 can send and receive information such as foodstuffs stored in the electric refrigerator-freezer 5800 and the expiration date of the foodstuffs to the above-mentioned information terminal or the like via the Internet or the like. can. Further, when the electric refrigerator / freezer 5800 transmits the information, the information can be held in the semiconductor device as a temporary file.
  • an electric refrigerator / freezer has been described as an electric appliance, but other electric appliances include, for example, a vacuum cleaner, a microwave oven, an electric oven, a rice cooker, a water heater, an IH cooker, a water server, and an air conditioner. Examples include appliances, washing machines, dryers, audiovisual equipment, and the like.
  • FIG. 21E illustrates a portable game machine 5200, which is an example of a game machine.
  • the portable game machine 5200 has a housing 5201, a display unit 5202, a button 5203, and the like.
  • FIG. 21F illustrates a stationary game machine 7500, which is an example of a game machine.
  • the stationary game machine 7500 has a main body 7520 and a controller 7522.
  • the controller 7522 can be connected to the main body 7520 wirelessly or by wire.
  • the controller 7522 can be provided with a display unit for displaying a game image, a touch panel as an input interface other than buttons, a stick, a rotary knob, a slide knob, and the like.
  • the controller 7522 is not limited to the shape shown in FIG. 21F, and the shape of the controller 7522 may be variously changed according to the genre of the game.
  • a controller having a shape imitating a gun can be used by using a trigger as a button.
  • a controller having a shape imitating a musical instrument, a music device, or the like can be used.
  • the stationary game machine may be provided with a camera, a depth sensor, a microphone, or the like instead of using a controller, and may be operated by a game player's gesture and / or voice.
  • the video of the game machine described above can be output by a display device such as a television device, a personal computer display, a game display, or a head-mounted display.
  • a display device such as a television device, a personal computer display, a game display, or a head-mounted display.
  • 21E and 21F show a portable game machine and a stationary game machine as an example of the game machine, but the electronic device of one aspect of the present invention is not limited thereto.
  • Examples of the electronic device of one aspect of the present invention include an arcade game machine installed in an entertainment facility (game center, amusement park, etc.), a pitching machine for batting practice installed in a sports facility, and the like.
  • the semiconductor device described in the above embodiment can be applied to an automobile which is a mobile body and around the driver's seat of the automobile.
  • FIG. 21G shows an automobile 5700 which is an example of a moving body.
  • an instrument panel that provides various information by displaying a speedometer, a tachometer, a mileage, a fuel gauge, a gear status, an air conditioner setting, and the like is provided. Further, a display device showing such information may be provided around the driver's seat.
  • the computer may be used in an automatic driving system for an automobile 5700, the computer may be used in a road guidance system, a danger prediction system, or the like. It can be used to retain necessary temporary information.
  • the display device may be configured to display temporary information such as road guidance and danger prediction. Further, the image of the driving recorder installed in the automobile 5700 may be retained.
  • the automobile is described as an example of the moving body, but the moving body is not limited to the automobile.
  • moving objects include trains, monorails, ships, flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, rockets) and the like.
  • FIG. 21H illustrates a digital camera 6240, which is an example of an image pickup apparatus.
  • the digital camera 6240 has a housing 6241, a display unit 6242, an operation button 6243, a shutter button 6244, and the like, and a removable lens 6246 is attached to the digital camera 6240.
  • the digital camera 6240 is configured so that the lens 6246 can be removed from the housing 6241 and replaced here, the lens 6246 and the housing 6241 may be integrated. Further, the digital camera 6240 may be configured so that a strobe device, a viewfinder, or the like can be separately attached.
  • Video camera The semiconductor device described in the above embodiment can be applied to a video camera.
  • FIG. 21I illustrates a video camera 6300, which is an example of an image pickup apparatus.
  • the video camera 6300 has a first housing 6301, a second housing 6302, a display unit 6303, an operation key 6304, a lens 6305, a connection unit 6306, and the like.
  • the operation key 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302.
  • the first housing 6301 and the second housing 6302 are connected by the connecting portion 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connecting portion 6306. be.
  • the image on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 on the connection unit 6306.
  • the video camera 6300 When recording the video captured by the video camera 6300, it is necessary to encode the data according to the recording format. By utilizing the above-mentioned semiconductor device, the video camera 6300 can hold a temporary file generated during encoding.
  • ICD implantable cardioverter-defibrillator
  • FIG. 21J is a schematic cross-sectional view showing an example of an ICD.
  • the ICD body 5400 has at least a battery 5401, an electronic component 4700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.
  • the ICD body 5400 is surgically placed in the body, and two wires are passed through the subclavian vein 5405 and the superior vena cava 5406 of the human body, and one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium. To be done.
  • the ICD body 5400 has a function as a pacemaker and paces the heart when the heart rate is out of the specified range. If pacing does not improve heart rate (fast ventricular tachycardia, ventricular fibrillation, etc.), treatment with electric shock is performed.
  • the ICD body 5400 needs to constantly monitor the heart rate in order to properly perform pacing and electric shock. Therefore, the ICD main body 5400 has a sensor for detecting the heart rate. Further, the ICD main body 5400 can store the heart rate data acquired by the sensor or the like, the number of times of treatment by pacing, the time, etc. in the electronic component 4700.
  • the ICD main body 5400 has a plurality of batteries, so that the safety can be enhanced. Specifically, even if a part of the battery of the ICD main body 5400 becomes unusable, the remaining battery can function, so that it also functions as an auxiliary power source.
  • the antenna 5404 that can receive power it may have an antenna that can transmit physiological signals.
  • physiological signals such as pulse, respiratory rate, heart rate, and body temperature can be confirmed by an external monitoring device.
  • a system for monitoring various cardiac activities may be configured.
  • the semiconductor device described in the above embodiment can be applied to a computer such as a PC (Personal Computer) and an expansion device for an information terminal.
  • a computer such as a PC (Personal Computer) and an expansion device for an information terminal.
  • FIG. 22A shows, as an example of the expansion device, an expansion device 6100 externally attached to a PC, which is equipped with a portable chip capable of storing information.
  • the expansion device 6100 can store information by the chip by connecting to a PC by, for example, USB (Universal Serial Bus) or the like.
  • USB Universal Serial Bus
  • FIG. 22A illustrates a portable expansion device 6100, but the expansion device according to one aspect of the present invention is not limited to this, and is relatively equipped with, for example, a cooling fan or the like. It may be a large form of expansion device.
  • the expansion device 6100 has a housing 6101, a cap 6102, a USB connector 6103, and a substrate 6104.
  • the substrate 6104 is housed in the housing 6101.
  • the substrate 6104 is provided with a circuit for driving the semiconductor device or the like described in the above embodiment.
  • an electronic component 4700 and a controller chip 6106 are attached to the substrate 6104.
  • the USB connector 6103 functions as an interface for connecting to an external device.
  • SD card The semiconductor device described in the above embodiment can be applied to an SD card that can be attached to an electronic device such as an information terminal or a digital camera.
  • FIG. 22B is a schematic diagram of the appearance of the SD card
  • FIG. 22C is a schematic diagram of the internal structure of the SD card.
  • the SD card 5110 has a housing 5111, a connector 5112, and a substrate 5113.
  • the connector 5112 functions as an interface for connecting to an external device.
  • the substrate 5113 is housed in the housing 5111.
  • the substrate 5113 is provided with a semiconductor device and a circuit for driving the semiconductor device.
  • an electronic component 4700 and a controller chip 5115 are attached to the substrate 5113.
  • the circuit configurations of the electronic component 4700 and the controller chip 5115 are not limited to the above description, and the circuit configurations may be appropriately changed depending on the situation.
  • the write circuit, low driver, read circuit, etc. provided in the electronic component may be configured to be incorporated in the controller chip 5115 instead of the electronic component 4700.
  • the capacity of the SD card 5110 can be increased.
  • a wireless chip having a wireless communication function may be provided on the substrate 5113. As a result, wireless communication can be performed between the external device and the SD card 5110, and the data of the electronic component 4700 can be read and written.
  • SSD Solid State Drive
  • electronic device such as an information terminal.
  • FIG. 22D is a schematic diagram of the appearance of the SSD
  • FIG. 22E is a schematic diagram of the internal structure of the SSD.
  • the SSD 5150 has a housing 5151, a connector 5152, and a substrate 5153.
  • the connector 5152 functions as an interface for connecting to an external device.
  • the board 5153 is housed in the housing 5151.
  • the substrate 5153 is provided with a semiconductor device and a circuit for driving the semiconductor device.
  • an electronic component 4700, a memory chip 5155, and a controller chip 5156 are attached to the substrate 5153.
  • a work memory is built in the memory chip 5155.
  • a DRAM chip may be used for the memory chip 5155.
  • a processor, an ECC circuit, and the like are incorporated in the controller chip 5156.
  • the circuit configurations of the electronic component 4700, the memory chip 5155, and the controller chip 5115 are not limited to the above description, and the circuit configurations may be appropriately changed depending on the situation.
  • the controller chip 5156 may also be provided with a memory that functions as a work memory.
  • the SSD 5150 with high reliability can be realized.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
  • Thin Film Transistor (AREA)
PCT/IB2021/058181 2020-09-22 2021-09-09 半導体装置の駆動方法 Ceased WO2022064308A1 (ja)

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KR1020237009957A KR20230069128A (ko) 2020-09-22 2021-09-09 반도체 장치의 구동 방법
JP2022551440A JP7719087B2 (ja) 2020-09-22 2021-09-09 半導体装置の駆動方法
CN202180061513.1A CN116114018A (zh) 2020-09-22 2021-09-09 半导体装置的驱动方法
JP2025123748A JP2025146893A (ja) 2020-09-22 2025-07-24 半導体装置の駆動方法

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US20240029773A1 (en) 2024-01-25
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