WO2020015547A1 - 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置 - Google Patents

移位寄存器单元及其驱动方法、栅极驱动电路及显示装置 Download PDF

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Publication number
WO2020015547A1
WO2020015547A1 PCT/CN2019/095108 CN2019095108W WO2020015547A1 WO 2020015547 A1 WO2020015547 A1 WO 2020015547A1 CN 2019095108 W CN2019095108 W CN 2019095108W WO 2020015547 A1 WO2020015547 A1 WO 2020015547A1
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WIPO (PCT)
Prior art keywords
transistor
signal
node
circuit
shift register
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PCT/CN2019/095108
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English (en)
French (fr)
Inventor
冯雪欢
李永谦
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to EP19835218.9A priority Critical patent/EP3825994B8/en
Priority to US16/633,068 priority patent/US11024235B2/en
Priority to JP2020562189A priority patent/JP2021531490A/ja
Publication of WO2020015547A1 publication Critical patent/WO2020015547A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0465—Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel

Definitions

  • Embodiments of the present disclosure relate to a shift register unit and a driving method thereof, a gate driving circuit, and a display device.
  • a pixel array of a liquid crystal display panel or an organic light emitting diode (OLED) display panel generally includes a plurality of rows of gate lines and a plurality of columns of data lines interlaced therewith.
  • the gate line can be driven by a gate driving circuit.
  • the gate driving circuit is usually integrated in a gate driving chip (Gate IC).
  • At least one embodiment of the present disclosure provides a shift register unit including a blanking input circuit, a display input circuit, and an output circuit; wherein the blanking input circuit is configured to perform blanking according to a blanking input signal and a blanking control signal. Input a blanking pull-up signal to the first control node during a period and compensate the blanking input circuit itself; the display input circuit is configured to input a display pull-up signal to the display during a display period in response to the display input signal A first control node; the output circuit is configured to output a composite output signal to an output terminal under the control of the level of the first control node.
  • the shift register unit provided by an embodiment of the present disclosure further includes a noise reduction circuit and a first control circuit; wherein the noise reduction circuit is configured to control the first control node under the control of the level of the second control node.
  • the control node and the output terminal perform noise reduction;
  • the first control circuit is configured to control the level of the second control node under the control of the level of the first control node.
  • the blanking input circuit includes a charging sub-circuit configured to input the blanking input signal to a first node in response to the blanking control signal.
  • a compensation sub-circuit configured to store the blanking input signal input by the charging sub-circuit, and compensate the level of the first node in response to a first clock signal, and perform the level of the second node Coupling control; an isolation sub-circuit configured to input the blanking pull-up signal to the first control node under the control of the level of the second node.
  • the blanking input circuit further includes a control sub-circuit configured to control the level of the second control node to control the sub-circuit.
  • the level of the second node is controlled.
  • the charging sub-circuit includes a first transistor, and a gate of the first transistor is configured to be connected to a random signal terminal to receive a random signal as the blanking.
  • a control signal a first pole of the first transistor is configured to be connected to a blanking input signal terminal to receive the blanking input signal, and a second pole of the first transistor is configured to be connected to the first node;
  • the compensation sub-circuit includes a second transistor and a first capacitor, a gate of the second transistor is configured to be connected to the first node, and a first electrode of the second transistor is configured to be connected to a first clock signal terminal to Receiving the first clock signal, the second pole of the second transistor is configured to be connected to the second node, the first pole of the first capacitor is configured to be connected to the first node, and the first The second pole of the capacitor is configured to be connected to the second node;
  • the isolation sub-circuit includes a third transistor, and the gate of the third transistor is configured to
  • the display input circuit includes a fifth transistor; a gate of the fifth transistor is configured to be connected to a display input signal terminal to receive the display input signal, A first pole of the fifth transistor is configured to be connected to a first voltage terminal to receive a first voltage as the display pull-up signal, and a second pole of the fifth transistor is configured to be connected to the first control node.
  • the output circuit includes at least one shift signal output terminal and at least one pixel scan signal output terminal.
  • the output circuit includes a sixth transistor, a seventh transistor, and a second capacitor; a gate of the sixth transistor is configured to be connected to the first control node. Connected, the first pole of the sixth transistor is configured to be connected to a second clock signal terminal to receive a second clock signal as the composite output signal, and the second pole of the sixth transistor is configured to be connected to the shift signal
  • the output terminal is connected; the gate of the seventh transistor is configured to be connected to the first control node, and the first electrode of the seventh transistor is configured to be connected to the second clock signal terminal to receive the second clock
  • the signal is used as the composite output signal.
  • the second pole of the seventh transistor is configured to be connected to the pixel scanning signal output terminal.
  • the first pole of the second capacitor is configured to be connected to the first control node.
  • the second pole of the second capacitor is configured to be connected to the second pole of the sixth transistor or the second pole of the seventh transistor.
  • the noise reduction circuit includes an eighth transistor, a ninth transistor, and a tenth transistor; and a gate of the eighth transistor is configured to control the second transistor.
  • the first pole of the eighth transistor is configured to be connected to the first control node, and the second pole of the eighth transistor is configured to be connected to a third voltage terminal to receive a third voltage; the ninth The gate of the transistor is configured to be connected to the second control node, the first electrode of the ninth transistor is configured to be connected to the shift signal output terminal, and the second electrode of the ninth transistor is configured to be connected to the second control node.
  • a third voltage terminal is connected to receive the third voltage; a gate of the tenth transistor is configured to be connected to the second control node, and a first pole of the tenth transistor is configured to output the pixel scan signal The second terminal of the tenth transistor is configured to be connected to a fourth voltage terminal to receive a fourth voltage.
  • the first control circuit includes an eleventh transistor, a twelfth transistor, and a thirteenth transistor; a gate of the eleventh transistor and a first And the second pole of the eleventh transistor is configured to be connected to the second control node; the gate of the twelfth transistor and the first Connected to the sixth voltage terminal to receive the sixth voltage, the second pole of the twelfth transistor is configured to be connected to the second control node, and the gate of the thirteenth transistor is configured to be and The first control node is connected, the first pole of the thirteenth transistor is configured to be connected to the second control node, and the second pole of the thirteenth transistor is configured to be connected to a third voltage terminal to receive the first Three voltages.
  • the shift register unit provided in an embodiment of the present disclosure further includes a blanking reset circuit, wherein the blanking reset circuit is configured to reset the first control node in response to a blanking reset signal.
  • the blanking reset circuit includes a fourteenth transistor; a gate of the fourteenth transistor is configured to be connected to a blanking reset signal terminal to receive the blanking reset signal terminal.
  • a first pole of the fourteenth transistor is configured to be connected to the first control node, and a second pole of the fourteenth transistor is configured to be connected to a third voltage terminal to receive a third voltage.
  • the shift register unit provided in an embodiment of the present disclosure further includes a display reset circuit, wherein the display reset circuit is configured to reset the first control node in response to a display reset signal.
  • the display reset circuit includes a fifteenth transistor; a gate of the fifteenth transistor is configured to be connected to a display reset signal terminal to receive the display reset. Signal, the first pole of the fifteenth transistor is configured to be connected to the first control node, and the second pole of the fifteenth transistor is configured to be connected to a third voltage terminal to receive a third voltage.
  • the shift register unit provided in an embodiment of the present disclosure further includes a second control circuit, wherein the second control circuit is configured to respond to the second control node in response to a first clock signal or the display input signal. To control the level.
  • the second control circuit includes a sixteenth transistor and a seventeenth transistor; a gate of the sixteenth transistor is configured to be connected to a first clock signal terminal Connected to receive the first clock signal, a first pole of the sixteenth transistor is configured to be connected to the second control node, and a second pole of the sixteenth transistor is configured to receive a third voltage terminal Voltage; the gate of the seventeenth transistor is configured to be connected to a display input signal terminal to receive the display input signal, the first pole of the seventeenth transistor is configured to be connected to the second control node, and The second pole of the seventeenth transistor is configured to be connected to the third voltage terminal to receive the third voltage.
  • At least one embodiment of the present disclosure further provides a gate driving circuit including the shift register unit according to any one of the embodiments of the present disclosure.
  • each four-stage shift register unit shares the same charging sub-circuit, the same compensation sub-circuit, and the same control sub-circuit.
  • the signal end is connected to the random signal line.
  • the first clock signal end of the 4n-3th stage shift register unit is connected to the first clock line, and n is an integer greater than 0.
  • a gate driving circuit provided in an embodiment of the present disclosure includes a first sub-clock signal line, a second sub-clock signal line, a third sub-clock signal line, and a fourth sub-clock signal line, wherein the 4n-3th stage The second clock signal end of the shift register unit is connected to the first sub clock signal line; the second clock signal end of the 4n-2 stage shift register unit is connected to the second sub clock signal line; the 4n- The second clock signal terminal of the first-stage shift register unit is connected to the third sub-clock signal line; the second clock signal terminal of the 4n-stage shift register unit is connected to the fourth sub-clock signal line; n is greater than An integer of 0.
  • a blanking input signal terminal of an n + 1th-stage shift register unit and a shift signal output terminal of an n-th stage shift register unit are connected;
  • the display input signal terminal of the 2-stage shift register unit is connected to the shift signal output terminal of the n-th stage shift register unit;
  • the display reset signal terminal of the n-stage shift register unit is connected to the n + 3-stage shift register unit.
  • the shift signal output is connected; n is an integer greater than 0.
  • At least one embodiment of the present disclosure further provides a display device including a shift register unit according to any one of the embodiments of the present disclosure or a gate driving circuit according to any one of the embodiments of the present disclosure.
  • At least one embodiment of the present disclosure further provides a method for driving a shift register unit according to any one of the embodiments of the present disclosure, including a display period and a blanking period for processing a frame of an image, wherein the display period includes In the first input stage, the display input circuit inputs the display pull-up signal to the first control node in response to the display input signal; in the first output stage, the output circuit is in the first control node Output the composite output signal to the output terminal under the control of the level; the blanking period includes: a second input stage, the blanking input circuit according to the blanking input signal and the blanking The control signal inputs the blanking pull-up signal to the first control node and compensates the blanking input circuit itself; in a second output stage, the output circuit is at a level of the first control node And output the composite output signal to the output terminal.
  • the display period includes In the first input stage, the display input circuit inputs the display pull-up signal to the first control node in response to the display input signal; in the first output
  • FIG. 1 is a schematic block diagram of a shift register unit according to some embodiments of the present disclosure
  • FIG. 2 is a schematic block diagram of a blanking input circuit of a shift register unit according to some embodiments of the present disclosure
  • FIG. 3 is a schematic block diagram of a blanking input circuit of another shift register unit provided by some embodiments of the present disclosure
  • FIG. 4 is a schematic block diagram of another shift register unit provided by some embodiments of the present disclosure.
  • FIG. 5 is a schematic block diagram of another shift register unit provided by some embodiments of the present disclosure.
  • FIG. 6 is a circuit diagram of a specific implementation example of the shift register unit shown in FIG. 4;
  • FIG. 7 is a circuit diagram of a specific implementation example of the shift register unit shown in FIG. 5;
  • FIG. 8 is a circuit diagram of another specific implementation example of the shift register unit shown in FIG. 5;
  • 9A-9C are circuit diagrams of specific implementation examples of a blanking input circuit of a shift register unit provided by some embodiments of the present disclosure.
  • FIG. 10 is a circuit diagram of a specific implementation example of a display input circuit of a shift register unit provided by some embodiments of the present disclosure
  • FIG. 11 is a circuit diagram of a specific implementation example of a second control circuit of a shift register unit provided by some embodiments of the present disclosure.
  • 13 is a signal timing diagram of another shift register unit provided by some embodiments of the present disclosure.
  • FIG. 14 is a schematic block diagram of a gate driving circuit provided by some embodiments of the present disclosure.
  • 15A-15C are circuit diagrams of specific implementation examples of blanking input circuits of adjacent four-stage shift register units in the gate driving circuit shown in FIG. 14;
  • FIG. 16 is a signal timing diagram of a gate driving circuit provided by some embodiments of the present disclosure.
  • FIG. 17 is a schematic block diagram of a display device provided by some embodiments of the present disclosure.
  • a gate drive circuit composed of a shift register unit needs to provide a driving signal for a scanning transistor and a sensing transistor to a sub-pixel unit in a display panel, for example, for a display period of one frame.
  • the scan driving signal (ie, the display output signal) of the scan transistor provides a sensing drive signal (ie, the blanking output signal) for the sensing transistor during a blanking period of one frame.
  • a shift register unit of a gate driving circuit generally includes a sensing unit, a display unit, and a connection unit (or gate circuit or Hiz circuit) that outputs both composite pulses.
  • the shift register unit can output a composite waveform output pulse composed of two waveforms with different widths and timings, thereby providing a display output signal and a blanking output for the scan transistor and the sense transistor, respectively. signal.
  • the circuit structure of the above-mentioned shift register unit is complicated, and its size is large, which is not conducive to achieving high resolution and narrow bezels, and it is not conducive to reducing the chip area to reduce costs.
  • the detection unit, the display unit, and the connection unit may be integrated to make the blanking output signal and The display output signal of the display period is output through the same output circuit, thereby simplifying the circuit structure.
  • level control for example, pull-up
  • this function exists because the function is implemented by a circuit composed of multiple transistors.
  • a large threshold voltage loss affects the potential of the pull-up node, for example, the potential of the pull-up node cannot reach a predetermined high potential, thereby affecting the output of the blanking output signal.
  • the gate drive circuit generally adopts the sequential scanning method for external compensation, but long-term progressive compensation will bring some problems, for example, there will be a scanning line that moves progressively during the display process, due to the difference in compensation time. There are large differences in brightness in different areas.
  • At least one embodiment of the present disclosure provides a shift register unit and a driving method thereof, a gate driving circuit, and a display device.
  • the circuit structure of the shift register unit is simple and can improve the first control of the blanking input circuit during the blanking period.
  • At least one embodiment of the present disclosure provides a shift register unit including a blanking input circuit, a display input circuit, and an output circuit.
  • the blanking input circuit is configured to input a blanking pull-up signal to the first control node during the blanking period according to the blanking input signal and the blanking control signal, and compensate the blanking input circuit itself;
  • the display input circuit is configured to respond to The display input signal inputs the display pull-up signal to the first control node during the display period;
  • the output circuit is configured to output the composite output signal to the output terminal under the control of the level of the first control node.
  • FIG. 1 is a schematic block diagram of a shift register unit according to some embodiments of the present disclosure.
  • the shift register unit 10 includes a blanking input circuit 100, a display input circuit 200, and an output circuit 300.
  • the shift register unit 10 further includes a noise reduction circuit 400 and a first control circuit 500.
  • a plurality of the shift register units 10 may be cascaded to construct a gate driving circuit provided by any embodiment of the present disclosure.
  • the blanking input circuit 100 is configured to input a blanking pull-up signal to a first control node (for example, a pull-up node Q) during a blanking period according to the blanking input signal and the blanking control signal, and perform the blanking input circuit 100 itself. make up.
  • the blanking input circuit 100 is electrically connected to the blanking input signal terminal STU1, the blanking control signal terminal Bcon, the blanking pull-up signal terminal Bla_up, and the pull-up node Q.
  • the blanking input circuit 100 further includes a first node N1 and a second node N2 (not shown in FIG. 1). The blanking input circuit 100 responds to the blanking input signal and blanking control provided by the blanking input signal terminal STU1.
  • the blanking control signal provided by the signal terminal Bcon charges the first node N1, compensates the level of the first node N1, and performs coupling control on the level of the second node N2, so that the level at the second node N2
  • the blanking pull-up signal provided by the blanking pull-up signal terminal Bla_up is input to the pull-up node Q to charge the pull-up node Q and make it high.
  • the blanking input circuit 100 is provided in the shift register unit 10 so that a blanking output signal can be output during a blanking period of one frame.
  • the “blanking” in the blanking input circuit 100 only indicates that the circuit is related to the blanking period, and does not limit the circuit to work only in the blanking period.
  • the blanking input circuit 100 charges the first node N1 during the display period and keeps the high level of the first node N1 to the blanking period; the blanking input circuit 100 controls the level of the first node N1 during the blanking period. Compensate, perform coupling control on the level of the second node N2, and charge the pull-up node Q to make it high.
  • the blanking input circuit 100 may be implemented as a plurality of transistors.
  • the process of charging the pull-up node Q by compensating the level of the first node N1 and controlling the level of the second node N2 by coupling, Compensate the threshold voltage loss generated by multiple transistors, so that the level of the second node N2 reaches a predetermined value (for example, a predetermined high level), so that the voltage of the pull-up node Q is controlled under the control of the level of the second node N2.
  • the level also reaches a predetermined value (for example, a predetermined high level) to avoid the loss of the threshold voltage from affecting the level of the pull-up node Q.
  • a random signal may be adopted as the blanking control signal.
  • the random signal is provided by a separate random signal generating circuit (for example, an FPGA).
  • the random signal provided to the gate driving circuit is not a timing of progressive scanning, but a random or other regular timing, thereby realizing a random detection function. That is, the pixel circuits in any row are compensated and detected in any frame. Therefore, when the gate driving circuit outputs a blanking output signal under the control of a random signal to externally compensate the pixel circuit, the scanning line and brightness deviation appearing in the screen can be eliminated by a function of random detection.
  • the display input circuit 200 is configured to input a display pull-up signal to a first control node (for example, a pull-up node Q) during a display period in response to a display input signal.
  • a first control node for example, a pull-up node Q
  • the display input circuit 200 is electrically connected to the display input signal terminal STU2, the display pull-up signal terminal Dis_up, and the pull-up node Q, and is configured to be turned on under the control of the display input signal provided by the display input signal terminal STU2, so that the display is pulled up.
  • the signal terminal Dis_up is electrically connected to the pull-up node Q, so that the display pull-up signal provided by the display pull-up signal terminal Dis_up is input to the pull-up node Q, and the pull-up node Q is pulled up to a high level.
  • the output circuit 300 is configured to output the composite output signal to the output terminal OP under the control of the level of the first control node (for example, the pull-up node Q).
  • the output circuit 300 is electrically connected to the pull-up node Q, the composite output signal terminal Com, and the output terminal OP, and is configured to be turned on under the control of the level of the pull-up node Q so that the composite output signal provided by the composite output signal terminal Com Output to output OP.
  • the output signal of the output terminal OP may include a display output signal and a blanking output signal, where the display output signal and the blanking output signal may be two independent waveforms having different widths and timings.
  • the output circuit 300 outputs a display output signal via the output terminal OP under the control of the level of the pull-up node Q to drive the scanning transistor in the pixel unit to perform display; during the blanking period, the output circuit 300 Under the control of the level of the pull-up node Q, a blanking output signal is output via the output terminal OP to drive the sensing transistor in the pixel unit to perform compensation detection.
  • the noise reduction circuit 400 is configured to perform noise reduction on the first control node (for example, the pull-up node Q) and the output terminal OP under the control of the level of the second control node (for example, the pull-down node QB).
  • the noise reduction circuit 400 is connected to the pull-down node QB, the pull-up node Q, and the output terminal OP, and is configured to control the level of the pull-down node QB so that the pull-up node Q and the output terminal OP are connected to a separately provided voltage terminal ( For example, the low voltage terminal) is electrically connected to pull down the pull-up node Q and the output terminal OP to a non-working level (for example, a low level) to achieve noise reduction.
  • a non-working level for example, a low level
  • the first control circuit 500 is configured to control the level of the second control node (for example, the pull-down node QB) under the control of the level of the first control node (for example, the pull-up node Q).
  • the first control circuit 500 is electrically connected to the pull-up node Q and the pull-down node QB, and is configured to pull down the pull-down node QB to a low level when the pull-up node Q is high, and to pull down the pull-up node Q when it is low. Pull-down node QB is pulled high.
  • the first control circuit 500 may be an inverter circuit.
  • FIG. 2 is a schematic block diagram of a blanking input circuit of a shift register unit provided by some embodiments of the present disclosure.
  • the blanking input circuit 100 includes a charging sub-circuit 110, a compensation sub-circuit 120, and an isolation sub-circuit 130.
  • the charging sub-circuit 110 is configured to input a blanking input signal to the first node N1 in response to the blanking control signal.
  • the charging sub-circuit 110 is connected to the blanking input signal terminal STU1, the blanking control signal terminal Bcon, and the first node N1, and is configured to be turned on under the control of the blanking control signal provided by the blanking control signal terminal Bcon to enable the blanking
  • the hidden input signal terminal STU1 is electrically connected to the first node N1, so that the blanked input signal is input to the first node N1.
  • the charging sub-circuit 110 is turned on under the control of the blanking control signal, and the blanking input signal is at a high level at this time, thereby charging the first node N1 and pulling the first node N1 high. Level.
  • the compensation sub-circuit 120 is configured to store a blanking input signal input from the charging sub-circuit 110, and compensate the level of the first node N1 in response to the first clock signal, and perform coupling control on the level of the second node N2.
  • the compensation sub-circuit 120 is connected to the first node N1, the second node N2, and the first clock signal terminal CLKA, and is configured to store the blanking input signal written to the first node N1, and provide it at the first clock signal terminal CLKA.
  • the level of the first clock signal changes (for example, from a low level to a high level)
  • the level of the first node N1 is compensated (for example, the level of the first node N1 is further pulled up to the (One level), so that the level of the second node N2 is coupled and controlled.
  • the compensation sub-circuit 120 is fully turned on under the control of the first level of the first node N1, so that the first clock signal is sufficiently written into the second node N2.
  • the level of the second node N2 is equal to the high level of the first clock signal at this time, that is, the level of the second node N2 reaches Predetermined value.
  • the embodiment of the present disclosure is not limited to this, and the level of the second node N2 may also be slightly lower than the high level of the first clock signal, as long as the isolation sub-circuit 130 can be controlled to be turned on or fully turned on.
  • the isolation sub-circuit 130 is configured to input a blanking pull-up signal to the first control node (for example, the pull-up node Q) under the control of the level of the second node N2.
  • the isolation sub-circuit 130 is connected to the second node N2, the pull-up node Q, and the blanking pull-up signal terminal Bla_up, and is configured to be turned on under the control of the level of the second node N2, so that the blanking pull-up signal terminal Bla_up It is electrically connected to the pull-up node Q, so that the blanking pull-up signal provided by the blanking pull-up signal terminal Bla_up is input to the pull-up node Q.
  • the isolation sub-circuit 130 is turned on under the control of the level of the second node N2, and the blanking pull-up signal is at a high level at this time, thereby charging the pull-up node Q and pulling up the node Q Pull-up is high.
  • the level of the second node N2 reaches a predetermined value, so that the isolation sub-circuit 130 is fully turned on, and the high level of the blanking pull-up signal is fully written into the pull-up node Q , So that the level of the pull-up node Q reaches a predetermined value.
  • the threshold voltage loss when the blanking input circuit 100 pulls up the pull-up node Q during the blanking period can be improved, and the potential of the pull-up node Q can be prevented from being affected, thereby improving the accuracy of the blanking output signal.
  • FIG. 3 is a schematic block diagram of a blanking input circuit of another shift register unit provided by some embodiments of the present disclosure.
  • the blanking input circuit 100 in this embodiment further includes a control sub-circuit 140, and other structures are basically the same as the blanking input circuit 100 shown in FIG.
  • the control sub-circuit 140 is configured to control (for example, pull-down) the level of the second node N2 under the control of the level of the second control node (for example, the pull-down node QB).
  • control sub-circuit 140 is connected to the second node N2 and the pull-down node QB, and is configured to be turned on under the control of the level of the pull-down node QB, so that the second node N2 is connected to a voltage terminal (for example, a low voltage terminal) provided separately. It is electrically connected to pull the second node N2 to a low level.
  • control sub-circuit 140 is not limited to be connected to the pull-down node QB, and may also be connected to a separately provided clock signal terminal or other applicable signal terminals, so that the clock signal or other applicable The second node N2 is pulled down under the control of the signal.
  • the control sub-circuit 140 By setting the control sub-circuit 140, it can be ensured that the second node N2 remains at a low level when it needs to be at a low level, thereby ensuring that the isolation sub-circuit 130 is turned off, and the blanking pull-up signal is prevented from affecting the pull-up node Q. For example, in some examples, during the display period, the second node N2 is pulled down by the control sub-circuit 140 to avoid blanking the pull-up signal from affecting the potential of the pull-up node Q, thereby realizing a normal display function.
  • the blanking input circuit 100 may include any applicable sub-circuit, and is not limited to the above-mentioned charging sub-circuit 110, compensation sub-circuit 120, isolation sub-circuit 130, and control sub-circuit 140, as long as Can achieve the corresponding function.
  • the blanking reset circuit 600 is configured to reset the first control node (for example, the pull-up node Q) in response to the blanking reset signal.
  • the blanking reset circuit 600 is connected to the blanking reset signal terminal TRST and the pull-up node Q, and is configured to be turned on under the control of the blanking reset signal provided by the blanking reset signal terminal TRST, so that the pull-up node Q and a separately provided
  • the voltage terminal (for example, the low voltage terminal) is electrically connected to reset the pull-up node Q. For example, during the blanking period, after the output circuit 300 finishes outputting the signal, the pull-up node Q is reset by the blanking reset circuit 600.
  • the “blanking” in the blanking reset circuit 600 only indicates that the circuit is related to the blanking period, and does not limit the circuit to work only in the blanking period.
  • the following The embodiments are the same and will not be described again.
  • the display reset circuit 700 is configured to reset the first control node (for example, the pull-up node Q) in response to a display reset signal.
  • the display reset circuit 700 is connected to the display reset signal terminal STD and the pull-up node Q, and is configured to be turned on under the control of the display reset signal provided by the display reset signal terminal STD, so that the pull-up node Q and a voltage terminal provided separately ( For example, the low voltage terminal) is electrically connected to reset the pull-up node Q.
  • the pull-up node Q is reset by the display reset circuit 700.
  • FIG. 5 is a schematic block diagram of another shift register unit provided by some embodiments of the present disclosure.
  • the shift register unit 10 in this embodiment further includes a second control circuit 800, and other structures are basically the same as those of the shift register unit 10 shown in FIG. 4.
  • the second control circuit 800 is configured to control a level of a second control node (for example, a pull-down node QB) in response to a first clock signal or a display input signal.
  • the second control circuit 800 is connected to the first clock signal terminal CLKA, the display input signal terminal STU2 and the pull-down node QB, and is configured to display the first clock signal provided at the first clock signal terminal CLKA or the display provided by the display input signal terminal STU2.
  • the pull-down node QB is electrically connected to a voltage terminal (for example, a low-voltage terminal) provided separately, thereby pulling down the pull-down node QB to a low level.
  • a voltage terminal for example, a low-voltage terminal
  • the second control circuit 800 pulls down the pull-down node QB in response to the first clock signal; during the display period, the second control circuit 800 pulls down the pull-down node QB in response to the display input signal.
  • the embodiment of the present disclosure is not limited to this, and the second control circuit 800 may also pull down the pull-down node QB only during the blanking period or only during the display period.
  • the second control circuit 800 By setting the second control circuit 800, it is possible to ensure that the pull-down node QB is at a low level, which helps to blank the input circuit 100 or the display input circuit 200 to write a high level to the pull-up node Q so that the level of the pull-up node Q It reaches the predetermined value, so it can prevent the output signal from being affected after the threshold voltage of the transistor drifts, which enhances the reliability of the circuit.
  • FIG. 6 is a circuit diagram of a specific implementation example of the shift register unit shown in FIG. 4.
  • each transistor is described as an N-type transistor, but this does not constitute a limitation on the embodiments of the present disclosure.
  • the shift register unit 10 includes first to fifteenth transistors M1-M15, and further includes a first capacitor C1 and a second capacitor C2.
  • the blanking input circuit 100 includes a charging sub-circuit 110, a compensation sub-circuit 120, an isolation sub-circuit 130, and a control sub-circuit 140.
  • the charging sub-circuit 110 may be implemented as a first transistor M1.
  • the gate of the first transistor M1 is configured to be connected to the random signal terminal OE to receive a random signal (here, the random signal terminal OE is used as the aforementioned blanking control signal terminal Bcon, and the random signal is used as the aforementioned blanking control signal).
  • a first pole of a transistor M1 is configured to be connected to the blanking input signal terminal STU1 to receive the blanking input signal, and a second pole of the first transistor M1 is configured to be connected to the first node N1.
  • the first transistor M1 When the random signal is at an active level (for example, a high level), the first transistor M1 is turned on, thereby writing a blanking input signal to the first node N1. For example, the blanking input signal is at a high level at this time to charge the first node N1.
  • an active level for example, a high level
  • the compensation sub-circuit 120 may be implemented as a second transistor M2 and a first capacitor C1.
  • the gate of the second transistor M2 is configured to be connected to the first node N1
  • the first pole of the second transistor M2 is configured to be connected to the first clock signal terminal CLKA to receive the first clock signal
  • the second pole of the second transistor M2 is configured To connect to the second node N2.
  • a first pole of the first capacitor C1 is configured to be connected to a first node N1
  • a second pole of the first capacitor C1 is configured to be connected to a second node N2.
  • the first node N1 After the blanking input signal is written to the first node N1, the first node N1 is charged to a high level, and the first capacitor C1 stores the high level and maintains the first node N1 at a high level, so as to be in a subsequent stage use.
  • the second transistor M2 is turned on, and the first clock signal is written into the second node N2.
  • the first clock signal changes from low level to high level, due to the bootstrapping effect of the first capacitor C1
  • the level of the first node N1 is further raised to the first level, so that the second transistor M2 is fully turned on.
  • the high level of the first clock signal is sufficiently written into the second node N2, so that the level of the second node N2 reaches a predetermined value, for example, equal to the high level of the first clock signal.
  • the isolation sub-circuit 130 may be implemented as a third transistor M3.
  • the gate of the third transistor M3 is configured to be connected to the second node N2, and the first electrode of the third transistor M3 is configured to be connected to the first voltage terminal VDD to receive the first voltage (here, the first voltage terminal VDD is equivalent to blanking
  • the pull-up signal terminal Bla_up uses the first voltage as a blanking pull-up signal), and the second pole of the third transistor M3 is configured to be connected to the first control node (for example, the pull-up node Q).
  • the third transistor M3 When the second node N2 is at a high level (for example, the high level reaches a predetermined value), the third transistor M3 is fully or approximately fully turned on, and the first voltage is written into the pull-up node Q, so that the pull-up node Q The level is high.
  • the control sub-circuit 140 may be implemented as a fourth transistor M4.
  • the gate of the fourth transistor M4 is configured to be connected to a second control node (for example, the pull-down node QB), the first pole of the fourth transistor M4 is configured to be connected to the second node N2, and the second pole of the fourth transistor M4 is configured to be and The second voltage terminal VGL2 is connected to receive a second voltage.
  • the pull-down node QB is high, the fourth transistor M4 is turned on, and the second node N2 is pulled down to a low level, thereby ensuring that the third transistor M3 is turned off to avoid blanking the pull-up signal during the display period (for example, the first The first voltage of a voltage terminal VDD) affects the pull-up node Q.
  • the first voltage terminal VDD is configured to provide a DC high-level signal, and the DC high-level signal is referred to as a first voltage;
  • the second voltage terminal VGL2 is configured to provide a DC low-level signal, such as ground, and the DC low signal is
  • the level signal is called the second voltage.
  • the display input circuit 200 may be implemented as a fifth transistor M5.
  • the gate of the fifth transistor M5 is configured to be connected to the display input signal terminal STU2 to receive the display input signal
  • the first electrode of the fifth transistor M5 is configured to be connected to the first voltage terminal VDD to receive the first voltage (here, the first voltage
  • the terminal VDD is equivalent to the display pull-up signal terminal Dis_up, and the first voltage is used as the display pull-up signal.
  • the second pole of the fifth transistor M5 is configured to be connected to the first control node (for example, the pull-up node Q).
  • the fifth transistor M5 When the display input signal is at an active level (for example, a high level), the fifth transistor M5 is turned on, thereby writing the first voltage to the pull-up node Q, so that the pull-up node Q is at a high level.
  • the output terminal OP of the output circuit 300 includes at least one shift signal output terminal CR and at least one pixel scan signal output terminal Out to improve the driving capability of the shift register unit 10.
  • the shift signal output terminal CR is used to provide a blanking input signal for the next-stage shift register unit 10
  • the pixel scan signal output terminal Out is used to provide a driving signal for the pixel circuit.
  • the output signals of the shift signal output terminal CR and the pixel scan signal output terminal Out are the same.
  • the output circuit 300 may be implemented as a sixth transistor M6, a seventh transistor M7, and a second capacitor C2.
  • the gate of the sixth transistor M6 is configured to be connected to a first control node (for example, a pull-up node Q), and the first pole of the sixth transistor M6 is configured to be connected to a second clock signal terminal CLKB to receive a second clock signal (here, The second clock signal terminal CLKB is equivalent to the composite output signal terminal Com, and the second clock signal is used as the composite output signal.
  • the second pole of the sixth transistor M6 is configured to be connected to the shift signal output terminal CR.
  • the gate of the seventh transistor M7 is configured to be connected to a first control node (such as a pull-up node Q), and the first pole of the seventh transistor M7 is configured to be connected to a second clock signal terminal CLKB to receive the second clock signal as a composite output Signal, the second pole of the seventh transistor M7 is configured to be connected to the pixel scanning signal output terminal Out.
  • a first pole of the second capacitor C2 is configured to be connected to a first control node (for example, a pull-up node Q), and a second pole of the second capacitor C2 is configured to be connected to a second pole of the sixth transistor M6.
  • the embodiments of the present disclosure are not limited thereto.
  • the second pole of the second capacitor C2 may be connected to the second pole of the seventh transistor M7.
  • the pull-up node Q is at an active level (for example, a high level)
  • the sixth transistor M6 and the seventh transistor M7 are both turned on, thereby outputting the second clock signal to the shift signal output terminal CR and the pixel scanning signal, respectively. Output Out.
  • the noise reduction circuit 400 may be implemented as an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10.
  • the gate of the eighth transistor M8 is configured to be connected to a second control node (for example, pull-down node QB), the first electrode of the eighth transistor M8 is configured to be connected to a first control node (for example, pull-up node Q), and the eighth transistor M8
  • the second pole is configured to be connected to the third voltage terminal VGL1 to receive the third voltage.
  • the gate of the ninth transistor M9 is configured to be connected to a second control node (for example, a pull-down node QB), the first pole of the ninth transistor M9 is configured to be connected to the shift signal output terminal CR, and the second pole of the ninth transistor M9 is configured It is connected to the third voltage terminal VGL1 to receive the third voltage.
  • the gate of the tenth transistor M10 is configured to be connected to a second control node (for example, the pull-down node QB).
  • the first pole of the tenth transistor M10 is configured to be connected to the pixel scanning signal output Out.
  • the second pole of the tenth transistor M10 is configured. It is connected to the fourth voltage terminal to receive the fourth voltage (here, the second voltage terminal VGL2 is used as the fourth voltage terminal, and the second voltage is used as the fourth voltage).
  • the third voltage terminal VGL1 is configured to provide a DC low-level signal, such as ground, and the DC low-level signal is referred to as a third voltage.
  • a third voltage is lower than the second voltage at the second voltage terminal VGL2; in other examples, the third voltage at the third voltage terminal VGL1 is equal to that of the second voltage terminal VGL2 Second voltage.
  • the third voltage and the second voltage may be the same or different, which may be determined according to actual needs.
  • the noise reduction circuit 400 when there are multiple shift signal output terminals CR and / or pixel scan signal output terminals Out, the noise reduction circuit 400 also includes multiple corresponding shift signal output terminals CR. And / or the pixel scanning signal output terminal Out is correspondingly connected to the transistor, so as to perform noise reduction on the plurality of shift signal output terminals CR and / or the pixel scanning signal output terminal Out.
  • the first control circuit 500 may be implemented as an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13.
  • the gate of the eleventh transistor M11 is connected to the first electrode and is configured to be connected to the fifth voltage terminal VDD_A to receive the fifth voltage
  • the second electrode of the eleventh transistor M11 is configured to be connected to the second control node (for example, the pull-down node QB). )connection.
  • the gate of the twelfth transistor M12 is connected to the first electrode and is configured to be connected to the sixth voltage terminal VDD_B to receive the sixth voltage.
  • the second electrode of the twelfth transistor M12 is configured to be connected to a second control node (for example, the pull-down node QB). )connection.
  • the gate of the thirteenth transistor M13 is configured to be connected to a first control node (for example, pull-up node Q), and the first pole of the thirteenth transistor M13 is configured to be connected to a second control node (for example, pull-down node QB).
  • the second pole of the three transistor M13 is configured to be connected to the third voltage terminal VGL1 to receive the third voltage.
  • the fifth voltage terminal VDD_A and the sixth voltage terminal VDD_B are configured to alternately provide a DC high-level signal, so that the eleventh transistor M11 and the twelfth transistor M12 are alternately turned on to prevent the transistor from being turned on for a long time. Performance drift caused by communication. For example, when the fifth voltage terminal VDD_A provides a high-level signal, the sixth voltage terminal VDD_B provides a low-level signal, at this time the eleventh transistor M11 is turned on and the twelfth transistor M12 is turned off; when the sixth voltage terminal VDD_B is provided When the high-level signal is supplied, the fifth voltage terminal VDD_A provides a low-level signal.
  • the twelfth transistor M12 is turned on and the eleventh transistor M11 is turned off.
  • the signal provided by the fifth voltage terminal VDD_A is referred to as a fifth voltage
  • the signal provided by the sixth voltage terminal VDD_B is referred to as a sixth voltage.
  • the following embodiments are the same, and will not be described again.
  • the thirteenth transistor M13 When the pull-up node Q is an active level (for example, a high level), the thirteenth transistor M13 is turned on. By designing the thirteenth transistor M13 and the turned on eleventh transistor M11 or the twelfth transistor M12, The track width-to-length ratio can pull down the pull-down node QB to a low level. When the pull-up node Q is at a low level, the thirteenth transistor M13 is turned off. At this time, the eleventh transistor M11 or the twelfth transistor M12 that is turned on supplies the high voltage provided by the fifth voltage terminal VDD_A or the sixth voltage terminal VDD_B. The flat signal is written to the pull-down node QB to pull up the pull-down node QB to a high level.
  • the blanking reset circuit 600 may be implemented as a fourteenth transistor M14.
  • the gate of the fourteenth transistor M14 is configured to be connected to the blanking reset signal terminal TRST to receive the blanking reset signal
  • the first pole of the fourteenth transistor M14 is configured to be connected to a first control node (such as a pull-up node Q).
  • the second pole of the fourteenth transistor M14 is configured to be connected to the third voltage terminal VGL1 to receive the third voltage.
  • the fourteenth transistor M14 is turned on, so that the pull-up node Q is electrically connected to the third voltage terminal VGL1, so as to Pull node Q to reset.
  • the display reset circuit 700 may be implemented as a fifteenth transistor M15.
  • the gate of the fifteenth transistor M15 is configured to be connected to the display reset signal terminal STD to receive a display reset signal.
  • the first pole of the fifteenth transistor M15 is configured to be connected to a first control node (such as a pull-up node Q).
  • the second pole of the five transistor M15 is configured to be connected to the third voltage terminal VGL1 to receive the third voltage.
  • the fifteenth transistor M15 is turned on, so that the pull-up node Q is electrically connected to the third voltage terminal VGL1, so that the pull-up node Q reset.
  • FIG. 7 is a circuit diagram of a specific implementation example of the shift register unit shown in FIG. 5.
  • the shift register unit 10 includes first to seventeenth transistors M1-M17, and further includes a first capacitor C1 and a second capacitor C2.
  • the connection relationship between the first to fifteenth transistors M1-M15, the first capacitor C1, and the second capacitor C2 is basically the same as that of the shift register unit 10 shown in FIG. 6, and details are not described herein again.
  • the second control circuit 800 may be implemented as a sixteenth transistor M16 and a seventeenth transistor M17.
  • the gate of the sixteenth transistor M16 is configured to be connected to the first clock signal terminal CLKA to receive the first clock signal.
  • the first pole of the sixteenth transistor M16 is configured to be connected to a second control node (such as the pull-down node QB).
  • the second pole configuration of the sixteen transistor M16 is connected to the third voltage terminal VGL1 to receive the third voltage.
  • the gate of the seventeenth transistor M17 is configured to be connected to the display input signal terminal STU2 to receive a display input signal.
  • the first pole of the seventeenth transistor M17 is configured to be connected to a second control node (such as the pull-down node QB).
  • the second pole of the transistor M17 is configured to be connected to the third voltage terminal VGL1 to receive a third voltage.
  • the sixteenth transistor M16 is turned on, so that the pull-down node QB is electrically connected to the third voltage terminal VGL1, thereby pulling down the pull-down node QB. Is low.
  • the seventeenth transistor M17 is turned on, so that the pull-down node QB is electrically connected to the third voltage terminal VGL1, thereby pulling down the pull-down node QB to low. Level.
  • the specific implementation of the second control circuit 800 is not limited to the above-described manner, and may be any applicable implementation, such as a conventional connection manner well known to those skilled in the art, and only needs to ensure that the corresponding functions are implemented.
  • FIG. 8 is a circuit diagram of another specific implementation example of the shift register unit shown in FIG. 5.
  • the shift register unit 10 of this embodiment includes a plurality of leakage prevention circuits, two second control nodes (for example, the first pull-down node QB_A and the second pull-down node QB_B), and two pixel scanning signal output terminals.
  • the first pixel scanning signal output terminal Out1 and the second pixel scanning signal output terminal Out2 are basically the same as those of the shift register unit 10 shown in FIG. 7.
  • the first capacitor C1 can be used to maintain the high level of the first node N1
  • the second capacitor C2 can be used to maintain the high level of the pull-up node Q.
  • the first pole is connected to the pull-up node Q and / or the first node N1
  • the second pole is connected to the low-level signal line. Even when a non-conducting signal is input to the gates of these transistors, leakage may occur due to a voltage difference between the first and second poles of the transistors, causing the circuit to pull up the nodes Q and / Or, the effect of maintaining the high level of the first node N1 becomes worse. Therefore, the shift register unit 10 shown in FIG. 8 adds multiple leakage prevention circuits to improve the effect of maintaining the high level of the pull-up node Q and / or the first node N1.
  • the first leakage prevention circuit may be implemented as a first leakage prevention transistor M1_b and a second leakage prevention transistor M1_c, and is configured to prevent the charge at the first node N1 from passing through the third node when the first node N1 is at a high level.
  • a transistor M1 leaks to the blanking input signal terminal STU1.
  • the gate of the first leakage prevention transistor M1_b is connected to the gate of the first transistor M1 (random signal terminal OE), the first pole is connected to the second pole of the first transistor M1, and the second pole is connected to the first node N1.
  • the gate of the second leakage prevention transistor M1_c is connected to the first node N1, the first pole is connected to the first voltage terminal VDD, and the second pole is connected to the first pole of the first leakage prevention transistor M1_b.
  • the second leakage prevention transistor M1_c When the first node N1 is at a high level, the second leakage prevention transistor M1_c is turned on under the control of the first node N1, and the first voltage (high voltage) is written to the first pole of the first leakage prevention transistor M1_b. As a result, both the first pole and the second pole of the first leakage prevention transistor M1_b are in a high-level state to prevent the charge at the first node N1 from leaking through the first leakage prevention transistor M1_b. At this time, since the gate of the first transistor M1 is connected to the gate of the first leakage prevention transistor M1_b, the combination of the first leakage prevention transistor M1_b and the first transistor M1 can achieve the same function as the aforementioned first transistor M1. And also has the effect of preventing leakage.
  • the same leakage prevention circuit as the foregoing principle can be used to achieve leakage prevention Effect.
  • the second leakage prevention circuit may be implemented as a third leakage prevention transistor M8_b, a fourth leakage prevention transistor M14_b, a fifth leakage prevention transistor M15_b, a sixth leakage prevention transistor 22_b, and a seventh leakage prevention transistor M23.
  • the connection manner of the second leakage prevention circuit is similar to the foregoing first leakage prevention circuit, and is not repeated here.
  • the seventh leakage prevention transistor M23 When the pull-up node Q is at a high level, the seventh leakage prevention transistor M23 is turned on, and the leakage prevention node is turned off to a high level, thereby causing the third leakage prevention transistor M8_b, the fourth leakage prevention transistor M14_b, and the fifth leakage prevention transistor
  • the first and second poles of each of M15_b and the sixth leakage prevention transistor M22_b are in a high-level state to prevent the charge at the pull-up node Q from leaking.
  • the combination of the eighth transistor M8, the fourteenth transistor M14, the fifteenth transistor M15, and the twenty-second transistor M22 and the second leakage prevention circuit can realize the eighth transistor M8, the fourteenth transistor M14,
  • the fifteenth transistor M15 has the same function and has the effect of preventing leakage.
  • FIG. 8 illustrates only an exemplary circuit structure including a leakage prevention circuit, and does not constitute a limitation on the embodiment of the present disclosure.
  • the shift register unit 10 includes two second control nodes, for example, including a first pull-down node QB_A and a second pull-down node QB_B. Accordingly, the eleventh transistor M11 and the thirteenth transistor M13 collectively control the level of the first pull-down node QB_A, and the twelfth transistor M12 and the twenty-fourth transistor M24 collectively control the level of the second pull-down node QB_B.
  • the fifth voltage terminal VDD_A and the sixth voltage terminal VDD_B provide high-level signals alternately, when the pull-up node Q is low-level, the first pull-down node QB_A and the second pull-down node QB_B alternately high; when When the pull node Q is high, the first pull-down node QB_A and the second pull-down node QB_B are both low. In this way, the threshold voltage of the transistor can be prevented from drifting.
  • the circuit connection mode and the related working principle of the two second control nodes refer to a conventional double pull-down node shift register unit, which is not repeated here.
  • the second control circuit 800 is also implemented as two sets of transistors, the twenty-fifth transistor M25, the twenty-sixth transistor M26, and the twenty-seventh transistor M27 as a group, the sixteenth transistor M16, and the seventeenth transistor M17 And the twenty-eighth transistor M28 are another group, and the above two groups of transistors are respectively connected to the first pull-down node QB_A and the second pull-down node QB_B to pull down the first pull-down node QB_A and the second pull-down node QB_B, respectively.
  • the sixteenth transistor M16 and the twenty-eighth transistor M28 are connected in series between the second pull-down node QB_B and the third voltage terminal VGL1, the gate of the sixteenth transistor M16 is connected to the first clock signal terminal CLKA, and the twentieth The gate of the eight transistor M28 is connected to the first node N1.
  • the sixteenth transistor M16 and the twenty-eighth transistor M28 are both turned on, thereby pulling down the second pull-down node QB_B to low Level.
  • the pull-down control method of the second pull-down node QB_A by the second control circuit 800 is similar to that of the second pull-down node QB_B, and details are not described herein again.
  • the above manner can cause the first pull-down node QB_A and the second pull-down node QB_B of the shift register unit 10 to be output to be pulled low, and other stages are shifted.
  • the first pull-down node QB_A and the second pull-down node QB_B of the register unit 10 will not be pulled low to avoid the shift signal output terminal CR, the first pixel scan signal output terminal Out1, and the second pixel shift signal output terminal CR of other stages of the shift register unit 10
  • the pixel scanning signal output terminal Out2 is in a floating state, thereby reducing the noise of the output signal.
  • the shift register unit 10 includes two pixel scanning signal output terminals, namely a first pixel scanning signal output terminal Out1 and a second pixel scanning signal output terminal Out2.
  • the connection manner of the first pixel scanning signal output terminal Out1 is similar to the aforementioned pixel scanning signal output terminal Out.
  • the second pixel scan signal output terminal Out2 is connected to the second pole of the twentieth transistor M20, the gate of the twentieth transistor M20 is connected to the pull-up node Q, and the first pole of the twentieth transistor M20 is connected to the third clock signal terminal. CLKC connection.
  • the third capacitor C3 is connected between the gate and the second electrode of the twentieth transistor M20.
  • the seventh transistor M7 and the twentieth transistor M20 are turned on, and the second clock signal of the second clock signal terminal CLKB is output to the first pixel scanning signal output terminal Out1 and the third clock signal terminal.
  • the third clock signal of CLKC is output to the second pixel scanning signal output terminal Out2.
  • the clock signals provided by the second clock signal terminal CLKB and the third clock signal terminal CLKC are the same, so the signals output by the first pixel scan signal output terminal Out1 and the second pixel scan signal output terminal Out2 are the same, and Further improve driving ability.
  • the signals provided by the second clock signal terminal CLKB and the third clock signal terminal CLKC are different, so that the signals output by the first pixel scan signal output terminal Out1 and the second pixel scan signal output terminal Out2 are different.
  • the signals provided by the second clock signal terminal CLKB and the third clock signal terminal CLKC are different, so that the signals output by the first pixel scan signal output terminal Out1 and the second pixel scan signal output terminal Out2 are different.
  • the signals provided by the second clock signal terminal CLKB and the third clock signal terminal CLKC are different, so that the signals output by the first pixel scan signal output terminal Out1 and the second pixel scan signal output terminal Out2 are different.
  • the signals provided by the second clock signal terminal CLKB and the third clock signal terminal CLKC are different, so that the signals output by the first pixel scan signal output terminal Out1 and the second pixel scan signal output terminal Out2 are different.
  • two transistors M21_a and M21_b need to be provided, and their gates are connected to the first pull-down node QB_A and the second pull-down node QB_B, respectively.
  • the gates of the transistors M9 and M18 are connected to the first pull-down node QB_A and the second pull-down node QB_B, respectively, to pull down the noise of the shift signal output terminal CR.
  • the gates of the transistors M10 and M19 are connected to the first pull-down node QB_A and the second pull-down node QB_B, respectively, to perform pull-down noise reduction on the first pixel scan signal output terminal Out1.
  • the gates of the transistors M4_a and M4_b are connected to the first pull-down node QB_A and the second pull-down node QB_B, respectively, to perform pull-down control on the second node N2.
  • FIGS. 9A-9C are circuit diagrams of specific implementation examples of a blanking input circuit of a shift register unit provided by some embodiments of the present disclosure.
  • the blanking input circuit 100 has an anti-leakage circuit to prevent the first node N1 from leaking electricity.
  • the working principle of the anti-leakage circuit is similar to the aforementioned anti-leakage circuit, and is not repeated here.
  • the gate of the fourth transistor M4 is configured to be connected to the fourth clock signal terminal CLKD to receive a fourth clock signal, and to control the fourth clock signal under the control of the fourth clock signal. Two nodes N2 pull down. It should be noted that the embodiments of the present disclosure are not limited thereto.
  • the gate of the fourth transistor M4 may be connected to the pull-down node QB, the fourth clock signal terminal CLKD, or other applicable signal terminals, as long as the fourth transistor M4 can be controlled to be turned on. And the second node N2 can be pulled down.
  • FIG. 9B compared with the blanking input circuit 100 shown in FIG. 9A, the control manner of the gate of the fourth transistor M4 in this example is different.
  • the gate of the fourth transistor M4 is high and the fourth transistor M4 is turned on, thereby pulling down the second node N2.
  • FIG. 9C compared with the blanking input circuit 100 shown in FIG.
  • the blanking input circuit 100 in this example further includes a leakage prevention circuit for the third transistor M3 to prevent leakage of the pull-up node Q, and a leakage prevention circuit
  • the working principle is similar to the aforementioned anti-leakage circuit, and is not repeated here.
  • the first pole of the third transistor M3 is connected to the fifth clock signal terminal CLKE, and receives the fifth clock signal as a blanking pull-up signal.
  • FIG. 10 is a circuit diagram of a specific implementation example of a display input circuit of a shift register unit provided by some embodiments of the present disclosure.
  • the gate of the fifth transistor M5 is connected to the first electrode, and is configured to be connected to the display input signal terminal STU2.
  • FIG. 10 (2) compared with the connection method shown in FIG. 10 (1), this example adds a leakage prevention circuit to prevent leakage of the pull-up node Q.
  • FIG. 10 (3) compared with the display input circuit 200 in the shift register unit 10 shown in FIG. 6, a diode-connected transistor M5_b may be connected in series between the fifth transistor M5 and the pull-up node Q. Play a role in preventing leakage.
  • FIG. 11 is a circuit diagram of a specific implementation example of a second control circuit of a shift register unit provided by some embodiments of the present disclosure.
  • FIG. 11 (1) compared with the second control circuit 800 in the shift register unit 10 shown in FIG. 8, in this example, the twenty-sixth transistor M26 and the twenty-eighth in FIG. 8 are omitted. Transistor M28.
  • the second control circuit 800 of this example can implement corresponding functions and simplify the circuit structure.
  • FIG. 11 (2) compared with the circuit shown in FIG.
  • the transistors M25 and M16 are omitted, so the second control circuit 800 in this example responds to the display input only during the display period
  • the display input signal provided by the signal end STU2 pulls down the first pull-down node QB_A and the second pull-down node QB_B, and does not pull down during the blanking period, thereby simplifying the circuit structure and not affecting the display effect.
  • the first capacitor C1, the second capacitor C2, and the third capacitor C3 may be capacitor devices manufactured through a process, for example, a capacitor device is realized by manufacturing a special capacitor electrode.
  • Each of the electrodes can be implemented by a metal layer, a semiconductor layer (such as doped polysilicon), and the first capacitor C1, the second capacitor C2, and the third capacitor C3 can also be parasitic capacitances between various devices, which can be achieved by the transistor itself. And other devices, circuits to achieve.
  • the connection manners of the first capacitor C1, the second capacitor C2, and the third capacitor C3 are not limited to those described above, and may also be other applicable connection methods, as long as the corresponding levels can be stored.
  • the first control node, the second control node, the first node N1, the second node N2, the pull-up node Q, the pull-down node QB, and the first pull-down node QB_A, the second pull-down node QB_B, and the anti-leakage node OFF indicate the meeting point of the related electrical connections in the circuit diagram, or may be a wire or a plurality of interconnected wires of the related electrical connections in the circuit diagram. The embodiments of the present disclosure do not make this happen. limit.
  • all the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics.
  • the thin film transistors are used as an example for description.
  • the source and drain of the transistor used here can be symmetrical in structure, so there can be no difference in structure of the source and drain of the transistor.
  • one pole is directly described as the first pole and the other pole is the second pole.
  • the transistors in the embodiments of the present disclosure are described by taking N-type transistors as an example.
  • the first electrode of the transistor is a drain
  • the second electrode is a source.
  • the present disclosure includes but is not limited to this.
  • one or more transistors in the shift register unit 10 provided by the embodiment of the present disclosure may also be a P-type transistor.
  • the first pole of the transistor is the source and the second pole is the drain.
  • the poles of a certain type of transistor are connected with reference to the poles of the corresponding transistor in the embodiment of the present disclosure, and the corresponding voltage terminal may provide a corresponding high voltage or low voltage.
  • ITZO Indium Gallium Zinc Oxide
  • LTPS Low Temperature Polysilicon
  • amorphous silicon such as (Crystalline silicon
  • pulse-up means charging a node or an electrode of a transistor so that the power of the node or the electrode is The absolute value of the level is increased, thereby realizing the operation of the corresponding transistor (for example, turning on);
  • pulseling down means discharging a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode is reduced, Thus, operation (for example, turning off) of the corresponding transistor is realized.
  • pulse-up means discharging a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode is reduced, thereby realizing the corresponding transistor.
  • Operation (such as turning on);
  • pulse-down means charging a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode increases, thereby realizing the operation of the corresponding transistor (such as turning off) .
  • FIG. 12 is a signal timing diagram of a shift register unit provided by some embodiments of the present disclosure.
  • the working principle of the shift register unit 10 shown in FIG. 6 will be described below with reference to the signal timing diagram shown in FIG. 12.
  • each transistor is described as an N-type transistor, but the embodiment of the present disclosure is not limited to this. this.
  • 1F indicates the timing of operation of the shift register unit 10 while the gate driving circuit displays a frame of picture
  • DS indicates a display period of one frame
  • BL indicates a blanking period of one frame.
  • STU1, STU2, TRST, OE, VDD_A, VDD_B, CLKA, CLKB, Out, CR, etc. are used to indicate both the corresponding signal end and the corresponding signal. The following embodiments are the same and will not be described again.
  • both the random signal OE and the blanking reset signal TRST are high.
  • the first transistor M1 is turned on, and the blanking input signal STU1 is at a low level at this time, thereby resetting the first node N1.
  • the fourteenth transistor M14 is turned on, thereby resetting the pull-up node Q.
  • the first node N1 and the pull-up node Q of the plurality of shift register units 10 may be globally reset.
  • the display input signal STU2 and the sixth voltage VDD_B are at a high level.
  • the fifth transistor M5 is turned on, and the pull-up node Q is pulled up to a high level.
  • the sixth transistor M6 and the seventh transistor M7 are turned on under the control of the pull-up node Q, and output the second clock signal CLKB to the shift signal output terminal CR and the pixel scan signal output terminal Out. Since the second clock signal CLKB is at a low level at this time, the shift signal output terminal CR and the pixel scanning signal output terminal Out both output a low level.
  • the thirteenth transistor M13 is turned on and the twelfth transistor M12 is turned on. Due to the voltage-dividing effect of the thirteenth transistor M13 and the twelfth transistor M12, the pull-down node QB is at a low level.
  • the random signal OE and the blanking input signal STU1 are at a high level
  • the first transistor M1 is turned on
  • the first node N1 is pulled up to a high level, and is stored by the first capacitor C1.
  • the second transistor M2 is turned on under the control of the first node N1, and writes the first clock signal CLKA into the second node N2. Since the first clock signal CLKA is at a low level at this time, the second node N2 is also at a low level, thereby turning off the third transistor M3.
  • the first capacitor C1 stores the high-level signal of the first node N1 and keeps it until the end of the display period of one frame for use in the blanking period.
  • the pull-up node Q is kept at a high level
  • the sixth transistor M6 and the seventh transistor M7 are kept on, and a low-level signal is output.
  • the second clock signal CLKB changes from low level to high level. Due to the bootstrapping effect of the second capacitor C2, the potential of the pull-up node Q further rises, and the sixth transistor M6 and the seventh transistor M7 It is fully turned on, and the high level of the second clock signal CLKB is output to the shift signal output terminal CR and the pixel scanning signal output terminal Out.
  • the second clock signal CLKB becomes a low level. Due to the bootstrapping effect of the second capacitor C2, the potential of the pull-up node Q is reduced but remains high.
  • the sixth transistor M6 and the seventh The transistor M7 remains on, and the low level of the second clock signal CLKB is output to the shift signal output terminal CR and the pixel scanning signal output terminal Out to complete the reset of the output signal.
  • the display reset signal STD (not shown in the figure) is at a high level, and the fifteenth transistor M15 is turned on, thereby resetting the pull-up node Q, so that the pull-up node Q becomes a low level.
  • the sixth transistor M6 and the seventh transistor M7 are turned off.
  • the thirteenth transistor M13 is turned off, and the pull-down node QB is pulled up to a high level by the twelfth transistor M12 that is turned on.
  • the eighth transistor M8 is turned on by the high level of the pull-down node QB to further reduce the noise on the pull-up node Q.
  • the ninth transistor M9 and the tenth transistor M10 are also turned on by the high level of the pull-down node QB, thereby reducing noise on the shift signal output terminal CR and the pixel scanning signal output terminal Out.
  • the fourth transistor M4 is turned on by the high level of the pull-down node QB, thereby pulling down the second node N2 to ensure that the third transistor M3 is turned off.
  • the pull-down node QB is kept at a high level, and the fourth transistor M4 is kept on, so that the third transistor M3 is kept off to avoid the write noise of the pull-up node Q through the third transistor M3.
  • the third transistor M3 is in an off state because the second node N2 has been kept at a low level, thereby isolating the first voltage terminal VDD and the pull-up node Q to avoid the first voltage influence of the first voltage terminal VDD.
  • the level of the pull-up node Q affects the output signal of the display period.
  • the level of the pull-up node Q has a tower-shaped waveform.
  • the pull-up and reset of the output signal of the shift signal output terminal CR are achieved by the sixth transistor M6.
  • the pull-up and reset of the output signal of the pixel scan signal output Out are both passed.
  • the seventh transistor M7 is implemented, and the ninth transistor M9 and the tenth transistor M10 play an auxiliary pull-down function on the output signals of the shift signal output terminal CR and the pixel scanning signal output terminal Out, so that the ninth transistor M9 and the tenth transistor can be reduced
  • the size of M10 is conducive to reducing the area of the circuit layout.
  • the first node N1 remains at the high level written in the display period, and the second transistor M2 remains on.
  • the first clock signal CLKA becomes a high level. Due to the bootstrapping effect of the first capacitor C1, the level of the first node N1 further rises to a first level, for example, the first level is higher than the first voltage VDD. Therefore, the threshold voltage lost due to the first transistor M1 when the first node N1 is charged in the display period is compensated.
  • the high level of the first node N1 causes the second transistor M2 to be fully turned on, and the high level of the first clock signal CLKA is sufficiently written to the second node N2.
  • the level of the second node N2 is equal to the first clock signal CLKA High.
  • the third transistor M3 is turned on under the control of the high level of the second node N2, and pulls up the pull-up node Q to a high level.
  • the sixth transistor M6 and the seventh transistor M7 are turned on, and the second clock signal CLKB is output to the shift signal output terminal CR and the pixel scanning signal output terminal Out.
  • the second clock signal CLKB is at a low level, so the shift signal output terminal CR and the pixel scanning signal output terminal Out both output a low level.
  • the thirteenth transistor M13 is turned on and the twelfth transistor M12 is turned on. Due to the voltage-dividing effect of the thirteenth transistor M13 and the twelfth transistor M12, the pull-down node QB is at a low level.
  • the first clock signal CLKA becomes a low level
  • the third transistor M3 is turned off, so that the pull-up node Q does not leak electricity through the third transistor M3.
  • the sixth transistor M6 and the seventh transistor M7 remain on.
  • the second clock signal CLKB becomes high level. Due to the bootstrapping effect of the second capacitor C2, the potential of the pull-up node Q further rises, and the sixth transistor M6 and the seventh transistor M7 are fully turned on.
  • the high level is output to the shift signal output terminal CR and the pixel scan signal output terminal Out.
  • the second clock signal CLKB becomes low level. Due to the bootstrapping effect of the second capacitor C2, the potential of the pull-up node Q is reduced but remains high.
  • the sixth transistor M6 and the seventh transistor The transistor M7 remains on, and the low level of the second clock signal CLKB is output to the shift signal output terminal CR and the pixel scanning signal output terminal Out to complete the reset of the output signal.
  • the blanking reset signal TRST and the random signal OE are at a high level, and the fourteenth transistor M14 and the first transistor M1 are turned on, so that the pull-up node Q and the first One node N1 is reset.
  • the first node N1 can be kept at a high level for a short time, so as to reduce the risk of a threshold voltage drift (for example, a positive drift) of a transistor connected to the first node N1, and help improve the reliability of the circuit.
  • a threshold voltage drift for example, a positive drift
  • the blanking input circuit 100 may compensate the level of the first node N1 to compensate for the threshold voltage loss generated during the charging of the first node N1, and perform the level of the second node N2. Coupling control to make the level of the second node N2 reach a predetermined value (for example, equal to or slightly lower than the high level of the first clock signal CLKA), so that the pull-up node Q is controlled by the level of the second node N2 The level also reaches a predetermined value (for example, equal to or slightly less than the first voltage VDD) to avoid the loss of the threshold voltage from affecting the level of the pull-up node Q, thereby improving the accuracy of the blanking output signal.
  • a predetermined value for example, equal to or slightly less than the first voltage VDD
  • the threshold voltage of each transistor is set to + 10V and the high level of the first clock signal CLKA is set to + 24V
  • the level of the second node N2 of the shift register unit 10 shown in FIG. 6 It can reach + 24V, which is equal to the high level of the first clock signal CLKA.
  • the level of the first node N1 can be raised above + 35V under the bootstrapping effect of the first capacitor C1.
  • FIG. 13 is a signal timing diagram of another shift register unit provided by some embodiments of the present disclosure.
  • the blanking input circuit 100 of the shift register unit 10 is implemented as the circuit structure shown in FIG. 9A, and other structures of the shift register unit 10 are basically the same as the shift register unit 10 shown in FIG. .
  • the gate of the fourth transistor M4 is connected to the fourth clock signal terminal CLKD to receive the fourth clock signal.
  • CLKD is used to indicate both the fourth clock signal terminal and the fourth clock signal. As shown in FIG.
  • the fourth clock signal CLKD is kept at a high level, and the fourth transistor M4 is kept on, so that the second node N2 is continuously pulled down to ensure that the third transistor M3 is in the display period. Cut-off state.
  • the fourth clock signal CLKD becomes a low level, and the fourth transistor M4 is turned off. Therefore, the second node N2 can be pulled up under the action of the first clock signal CLKA, so that the third transistor M3 is turned on, thereby pulling up the pull-up node Q to a high level.
  • the working principle of the shift register unit 10 under the timing shown in FIG. 13 is basically the same as the working principle described above, and is not repeated here.
  • At least one embodiment of the present disclosure also provides a gate driving circuit.
  • the gate driving circuit includes a shift register unit according to any embodiment of the present disclosure.
  • the gate driving circuit has a simple circuit structure, which can improve the threshold voltage loss when the blanking input circuit performs level control (for example, pull-up) on the first control node (for example, pull-up node) during the blanking period, so as to avoid affecting the first Control the potential of the node to improve the accuracy of the blanking output signal.
  • FIG. 14 is a schematic block diagram of a gate driving circuit according to some embodiments of the present disclosure.
  • the gate driving circuit 20 includes a plurality of cascaded shift register units (A1, A2, A3, A4, etc.). The number of multiple shift register units is not limited and can be determined according to actual needs.
  • the shift register unit adopts the shift register unit 10 according to any embodiment of the present disclosure.
  • the gate driving circuit 20 a part or all of the shift register units may adopt the shift register unit 10 described in any embodiment of the present disclosure.
  • the gate driving circuit 20 can be directly integrated on the array substrate of the display device by using the same process as the thin film transistor to form a GOA (Gate Driver On Array), so as to realize the progressive scanning driving function.
  • GOA Gate Driver On Array
  • each four-stage shift register unit shares the same charging sub-circuit 110, the same compensation sub-circuit 120, and the same control sub-circuit 140 to simplify the circuit structure and facilitate the implementation of a narrow frame.
  • each of the four stages of the shift register unit shares the transistors M1, M1_b, M1_c, M2, M4_a, M4_b, and the first capacitor C1, and each stage of the shift register unit
  • the cells each have a third transistor M3 (isolation sub-circuit 130), and a second node N2 is connected to the gate of each third transistor M3 in the four-stage shift register unit.
  • the four-stage shift register unit outputs a blanking output signal at the same time, that is, performs compensation detection at the same time.
  • the first-stage shift register unit A1 includes transistors M1, M1_b, M1_c, M2, M4_a, M4_b, and a first capacitor C1, and also includes a third transistor M3 ⁇ n>.
  • the second to fourth stage shift register units A2-A4 include third transistors M3 ⁇ n + 1>, M3 ⁇ n + 2>, and M3 ⁇ n + 3>, and the gates are connected to the first stage shift The second node N2 in the register unit A1.
  • the third transistors M3 ⁇ n>, M3 ⁇ n + 1>, M3 ⁇ n + 2>, and M3 ⁇ n + 3> in the above-mentioned four shift register units A1-A4 Are all turned on, thereby pulling up the pull-up nodes Q ⁇ n>, Q ⁇ n + 1>, Q ⁇ n + 2>, and Q ⁇ n + 3> in the above-mentioned four shift register units A1-A4 Level to further output the blanking output signal.
  • FIG. 15B is a circuit diagram of another implementation example in a sharing situation.
  • the charging sub-circuit 110, the compensation sub-circuit 120, and the control sub-circuit 140 are implemented as the circuit structure shown in FIG. 9A, and other parts are basically the same as the circuit shown in FIG. 15A. , Will not repeat them here.
  • FIG. 15C is a circuit diagram of another implementation example in a shared case.
  • the isolation sub-circuit 130 of each stage of the shift register unit adds an anti-leakage circuit to prevent the pull-up nodes Q ⁇ n>, Q ⁇ n + 1>, Q ⁇ n + 2>, and Q ⁇ n + 3> are leaking.
  • the first transistors of the third transistors M3 ⁇ n>, M3 ⁇ n + 1>, M3 ⁇ n + 2>, and M3 ⁇ n + 3> of the shift register units at all levels are connected to the fifth clock signal terminal CLKE To receive the fifth clock signal as a blanking pull-up signal.
  • the number of shift register units sharing the same charging sub-circuit 110, the same compensation sub-circuit 120, and the same control sub-circuit 140 is not limited, and may be any number. Four examples are used for illustration, but this does not constitute a limitation on the present disclosure.
  • a plurality of shift register units sharing the above-mentioned sub-circuit may be adjacent or non-adjacent, which is not limited in the embodiments of the present disclosure.
  • each four-stage shift register unit shares the same charging sub-circuit 110, the same compensation sub-circuit 120, and the same control sub-circuit 140, and each of the common sub-circuits is disposed at the 4th- In a 3-stage shift register unit, n is an integer greater than 0.
  • Each shift register unit adopts a circuit structure as shown in FIG. 8. A specific cascade relationship of the gate driving circuit 20 is described below.
  • each shift register unit has a blanking input signal terminal STU1, a display input signal terminal STU2, a display reset signal terminal STD, a shift signal output terminal CR, a first pixel scanning signal output terminal Out1, and a second pixel scanning signal output.
  • Terminal Out2 blanking reset signal terminal TRST, second clock signal terminal CLKB, third clock signal terminal CLKC, and so on.
  • the 4n-3th stage shift register unit further has a random signal terminal OE and a first clock signal terminal CLKA.
  • the random signal terminal OE of the 4n-3 stage shift register unit is connected to the random signal line OE_1
  • the first clock signal terminal CLKA of the 4n-3 stage shift register unit is connected to the first clock line CLKA_1.
  • the blanking reset signal terminal TRST of each stage of the shift register unit is connected to the blanking reset line TRST_1.
  • the blanking input signal terminal STU1 of the n + 1th stage shift register unit is connected to the shift signal output terminal CR of the nth stage shift register unit.
  • the display input signal terminal STU2 of the n + 2th stage shift register unit is connected to the shift signal output terminal CR of the nth stage shift register unit.
  • the display reset signal terminal STD of the n-th stage shift register unit is connected to the shift signal output terminal CR of the n + 3-th stage shift register unit.
  • the blanking input signal terminal STU1 and the display input signal terminal STU2 of the first-stage shift register unit A1 are connected to the trigger signal line STU, and the display input signal terminal STU2 of the second-stage shift register unit A2 is also connected to the trigger signal line STU. connection.
  • the display reset signal terminal STD of the last three-stage shift register unit is connected to a reset signal line provided separately.
  • the first pixel scanning signal output terminal Out1 and the second pixel scanning signal output terminal Out2 of each shift register unit are connected to the pixel units of the corresponding row to output a driving signal to the pixel units of the row.
  • the gate driving circuit 20 further includes a first sub-clock signal line CLKB_1, a second sub-clock signal line CLKB_2, a third sub-clock signal line CLKB_3, and a fourth sub-clock signal line CLKB_4.
  • CLKB_1 a first sub-clock signal line
  • CLKB_2 a second sub-clock signal line
  • CLKB_3 a third sub-clock signal line
  • CLKB_4 a fourth sub-clock signal line CLKB_4.
  • the connection of each sub-clock signal line is described below and so on.
  • the second clock signal terminal CLKB of the 4n-3 stage shift register unit is connected to the first sub clock signal line CLKB_1, and the second clock signal terminal CLKB of the 4n-2 stage shift register unit and the second sub clock signal line CLKB_2 Connected, the second clock signal terminal CLKB of the 4n-1 stage shift register unit and the third sub clock signal line CLKB_3 are connected, and the second clock signal terminal CLKB of the 4n stage shift register unit and the fourth sub clock signal line CLKB_4 connection.
  • the gate driving circuit 20 further includes a fifth sub-clock signal line CLKC_1, a sixth sub-clock signal line CLKC_2, a seventh sub-clock signal line CLKC_3, and an eighth sub-clock signal line CLKC_4.
  • CLKC_1 a fifth sub-clock signal line
  • CLKC_2 a sixth sub-clock signal line
  • CLKC_3 a seventh sub-clock signal line
  • CLKC_4 an eighth sub-clock signal line
  • the third clock signal terminal CLKC of the 4n-3 stage shift register unit is connected to the fifth sub clock signal line CLKC_1, and the third clock signal terminal CLKC of the 4n-2 stage shift register unit and the sixth sub clock signal line CLKC_2 Connected, the third clock signal terminal CLKC of the 4n-1 stage shift register unit and the seventh sub clock signal line CLKC_3 are connected, the third clock signal terminal CLKC of the 4n stage shift register unit and the eighth sub clock signal line CLKC_4 connection.
  • the gate driving circuit 20 may further include a timing controller T-CON.
  • the timing controller T-CON is configured to provide the above-mentioned clock signals to the shift register units at various levels.
  • the timing controller T-CON may also be configured to Provide trigger signal and reset signal. It should be noted that the phase relationship between the multiple clock signals provided by the timing controller T-CON can be determined according to actual needs. In different examples, more clock signals may be provided to the gate driving circuit 20 according to different configurations.
  • the gate driving circuit 20 further includes a plurality of voltage lines to provide a plurality of voltage signals to the shift register units of each stage.
  • the gate driving circuit 20 when used to drive a display panel, the gate driving circuit 20 may be disposed on one side of the display panel.
  • the display panel includes multiple rows of gate lines, and the first pixel scan signal output terminal Out1 and the second pixel scan signal output terminal Out2 of the shift register units in each stage of the gate driving circuit 20 may be configured to sequentially and multiple rows.
  • the gate line is connected for outputting a driving signal.
  • the gate driving circuit 20 can also be provided on both sides of the display panel to achieve bilateral driving. The embodiment of the present disclosure does not limit the manner of setting the gate driving circuit 20.
  • FIG. 16 is a signal timing diagram of a gate driving circuit according to some embodiments of the present disclosure.
  • the signal timing diagram is the timing of the gate driving circuit 20 shown in FIG. 14.
  • the waveforms of the output signals Out2 ⁇ 3> and Out2 ⁇ 4> of the second pixel scan signal output terminal Out2 of the third and fourth stage shift register units A3 and A4 during the display period of one frame are the same as those of the first
  • the output signal Out1 ⁇ 3> and Out1 ⁇ 4> of the pixel scanning signal output terminal Out1 have the same waveform, and are sequentially shifted during the blanking period of each frame and are the same as the output signal Out1 ⁇ 3> of the first pixel scanning signal output terminal Out1.
  • the waveform is different from Out1 ⁇ 4> to meet the requirements of many applications.
  • the waveforms of the first sub-clock signal CLKB_1, the second sub-clock signal CLKB_2, the third sub-clock signal CLKB_3, and the fourth sub-clock signal CLKB_4 in the display period of one frame sequentially overlap by 50% of the effective pulse width in each frame.
  • the waveforms within the blanking period are sequentially shifted.
  • the output signals Out1 ⁇ 3> and Out1 ⁇ 4> of the first pixel scan signal output terminal Out1 of the third and fourth stage shift register units A3 and A4 sequentially overlap the effective pulse width by 50 during the display period of one frame.
  • the waveforms in the blanking period of each frame are sequentially shifted.
  • the output signals of the gate driving circuit 20 in the display period overlap in time sequence, so that a pre-charging function can be implemented, the charging time of the pixel circuit can be shortened, and a high refresh rate is facilitated.
  • the waveforms of the fifth to eighth sub-clock signals CLKC_1-CLKC_4 in the display period of one frame sequentially overlap by 50% of the effective pulse width, and the waveforms in the blanking period of each frame are sequentially shifted, so that the second pixel can be scanned.
  • the output signal of the signal output terminal Out2 in the display period also has an overlapping portion in timing.
  • the gate driving circuit 20 is not limited to the cascade manner described in FIG. 14, and may be any applicable cascade manner.
  • the waveform overlapped part of the output signal of the first pixel scan signal output terminal Out1 or the second pixel scan signal output terminal Out2 of the shift register units at each stage will also change accordingly. For example, it overlaps 33% or 0% (that is, does not overlap) to meet the requirements of multiple applications.
  • At least one embodiment of the present disclosure also provides a display device.
  • the display device includes a shift register unit according to any embodiment of the present disclosure or a gate driving circuit according to any embodiment of the present disclosure.
  • the circuit structure of the shift register unit or the gate driving circuit in the display device is simple, which can improve when the blanking input circuit performs level control (for example, pull-up) on the first control node (for example, pull-up node) during the blanking period. Loss of the threshold voltage to avoid affecting the potential of the first control node, thereby improving the accuracy of the blanking output signal.
  • FIG. 17 is a schematic block diagram of a display device provided by some embodiments of the present disclosure.
  • the display device 30 includes a gate driving circuit 20.
  • the gate driving circuit 20 is a gate driving circuit according to any embodiment of the present disclosure.
  • the display device 30 may be an OLED display panel, an OLED TV, an OLED display, a liquid crystal display panel, an LCD TV, etc., or an eBook, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, etc.
  • the product or component is not limited by the embodiments of the present disclosure.
  • the display device 30 includes a display panel 3000, a gate driver 3010, a timing controller 3020, and a data driver 3030.
  • the display panel 3000 includes a plurality of pixel units P defined according to the intersection of a plurality of scan lines GL and a plurality of data lines DL; a gate driver 3010 is used to drive a plurality of scan lines GL; a data driver 3030 is used to drive a plurality of data lines DL;
  • the timing controller 3020 is configured to process the image data RGB input from the outside of the display device 30, provide the processed image data RGB to the data driver 3030, and output the scan control signal GCS and the data control signal DCS to the gate driver 3010 and the data driver 3030.
  • the gate driver 3010 and the data driver 3030 are controlled.
  • the gate driver 3010 includes the gate driving circuit 20 provided in any of the above embodiments.
  • the pixel scanning signal output terminals Out of the plurality of shift register units 10 in the gate driving circuit 20 are correspondingly connected to the plurality of scanning lines GL.
  • the plurality of scanning lines GL are correspondingly connected to the pixel units P arranged in a plurality of rows.
  • the pixel scan signal output terminals Out of the shift register units 10 in the gate driving circuit 20 sequentially output signals to the multiple scan lines GL, so that the multiple rows of pixel units P in the display panel 3000 are realized.
  • the gate driver 3010 may be implemented as a semiconductor chip, or may be integrated in the display panel 3000 to constitute a GOA circuit.
  • the data driver 3030 converts the digital image data RGB input from the timing controller 3020 into a data signal according to a plurality of data control signals DCS originating from the timing controller 3020 using a reference gamma voltage.
  • the data driver 3030 provides the converted data signals to the plurality of data lines DL.
  • the data driver 3030 may be implemented as a semiconductor chip.
  • the timing controller 3020 processes the externally input image data RGB to match the size and resolution of the display panel 3000, and then provides the processed image data to the data driver 3030.
  • the timing controller 3020 generates a plurality of scan control signals GCS and a plurality of data control signals DCS using synchronization signals (such as the dot clock DCLK, the data enable signal DE, the horizontal synchronization signal Hsync, and the vertical synchronization signal Vsync) input from the outside of the display device 30. .
  • the timing controller 3020 provides the scan control signal GCS and the data control signal DCS to the gate driver 3010 and the data driver 3030, respectively, for controlling the gate driver 3010 and the data driver 3030.
  • the display device 30 may further include other components, such as a signal decoding circuit, a voltage conversion circuit, and the like. These components may use existing conventional components, for example, and will not be described in detail here.
  • At least one embodiment of the present disclosure also provides a method for driving a shift register unit, which can be used to drive a shift register unit provided by any embodiment of the present disclosure.
  • a plurality of the shift register units can be cascaded to form a gate driving circuit.
  • the gate driving circuit is used for driving the display panel to display at least one frame.
  • the driving method of the shift register unit 10 includes a display period and a blanking period for processing a frame of image, the display period includes a first input phase and a first output phase, and the blanking period includes a second Input stage and second output stage.
  • the driving method of the shift register unit 10 includes the following operations:
  • Display periods include:
  • the display input circuit 200 inputs a display pull-up signal to a first control node (for example, a pull-up node Q) in response to a display input signal;
  • a first control node for example, a pull-up node Q
  • the output circuit 300 outputs the composite output signal to the output terminal OP under the control of the level of the first control node (for example, the pull-up node Q);
  • the blanking period includes:
  • the blanking input circuit 100 inputs the blanking pull-up signal to the first control node (for example, the pull-up node Q) according to the blanking input signal and the blanking control signal, and compensates the blanking input circuit 100 itself. ;
  • the output circuit 300 outputs the composite output signal to the output terminal OP under the control of the level of the first control node (for example, the pull-up node Q).

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Abstract

一种移位寄存器单元(10)及其驱动方法、栅极驱动电路(20)及显示装置(30)，移位寄存器单元(10)包括消隐输入电路(100)、显示输入电路(200)和输出电路(300)。消隐输入电路(100)配置为根据消隐输入信号和消隐控制信号在消隐时段(BL)将消隐上拉信号输入到第一控制节点(Q)，并对消隐输入电路(100)自身进行补偿；显示输入电路(200)配置为响应于显示输入信号在显示时段(DS)将显示上拉信号输入到第一控制节点(Q)；输出电路(300)配置为将复合输出信号输出至输出端(OP)。移位寄存器单元(10)可改善消隐输入电路(100)对第一控制节点(Q)进行电平控制时的阈值电压损失，避免影响第一控制节点(Q)的电位。

Description

移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
本申请要求于2018年7月18日递交的中国专利申请第201810792877.7号的优先权，该中国专利申请的全文以引入的方式并入以作为本申请的一部分。
技术领域
本公开的实施例涉及一种移位寄存器单元及其驱动方法、栅极驱动电路及显示装置。
背景技术
在显示技术领域，例如液晶显示面板或有机发光二极管(Organic Light Emitting Diode,OLED)显示面板的像素阵列通常包括多行栅线和与之交错的多列数据线。对栅线的驱动可以通过栅极驱动电路实现。栅极驱动电路通常集成在栅极驱动芯片(Gate IC)中。
发明内容
本公开至少一个实施例提供一种移位寄存器单元，包括消隐输入电路、显示输入电路和输出电路；其中，所述消隐输入电路配置为根据消隐输入信号和消隐控制信号在消隐时段将消隐上拉信号输入到第一控制节点，并对所述消隐输入电路自身进行补偿；所述显示输入电路配置为响应于显示输入信号在显示时段将显示上拉信号输入到所述第一控制节点；所述输出电路配置为在所述第一控制节点的电平的控制下，将复合输出信号输出至输出端。
例如，本公开一实施例提供的移位寄存器单元还包括降噪电路和第一控制电路；其中，所述降噪电路配置为在第二控制节点的电平的控制下，对所述第一控制节点和所述输出端进行降噪；所述第一控制电路配置为在所述第一控制节点的电平的控制下，对所述第二控制节点的电平进行控制。
例如，在本公开一实施例提供的移位寄存器单元中，所述消隐输入电路包括：充电子电路，配置为响应于所述消隐控制信号将所述消隐输入信号输入到第一节点；补偿子电路，配置为存储所述充电子电路输入的所述消隐输 入信号，并响应于第一时钟信号对所述第一节点的电平进行补偿，以及对第二节点的电平进行耦合控制；隔离子电路，配置为在所述第二节点的电平的控制下，将所述消隐上拉信号输入到所述第一控制节点。
例如，在本公开一实施例提供的移位寄存器单元中，所述消隐输入电路还包括控制子电路，所述控制子电路配置为在所述第二控制节点的电平的控制下，对所述第二节点的电平进行控制。
例如，在本公开一实施例提供的移位寄存器单元中，所述充电子电路包括第一晶体管，所述第一晶体管的栅极配置为和随机信号端连接以接收随机信号作为所述消隐控制信号，所述第一晶体管的第一极配置为和消隐输入信号端连接以接收所述消隐输入信号，所述第一晶体管的第二极配置为和所述第一节点连接；所述补偿子电路包括第二晶体管和第一电容，所述第二晶体管的栅极配置为和所述第一节点连接，所述第二晶体管的第一极配置为和第一时钟信号端连接以接收所述第一时钟信号，所述第二晶体管的第二极配置为和所述第二节点连接，所述第一电容的第一极配置为和所述第一节点连接，所述第一电容的第二极配置为和所述第二节点连接；所述隔离子电路包括第三晶体管，所述第三晶体管的栅极配置为和所述第二节点连接，所述第三晶体管的第一极配置为和第一电压端连接以接收第一电压作为所述消隐上拉信号，所述第三晶体管的第二极配置为和所述第一控制节点连接；所述控制子电路包括第四晶体管，所述第四晶体管的栅极配置为和所述第二控制节点连接，所述第四晶体管的第一极配置为和所述第二节点连接，所述第四晶体管的第二极配置为和第二电压端连接以接收第二电压。
例如，在本公开一实施例提供的移位寄存器单元中，所述显示输入电路包括第五晶体管；所述第五晶体管的栅极配置为和显示输入信号端连接以接收所述显示输入信号，所述第五晶体管的第一极配置为和第一电压端连接以接收第一电压作为所述显示上拉信号，所述第五晶体管的第二极配置为和所述第一控制节点连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述输出电路包括至少一个移位信号输出端和至少一个像素扫描信号输出端。
例如，在本公开一实施例提供的移位寄存器单元中，所述输出电路包括第六晶体管、第七晶体管和第二电容；所述第六晶体管的栅极配置为和所述第一控制节点连接，所述第六晶体管的第一极配置为和第二时钟信号端连接 以接收第二时钟信号作为所述复合输出信号，所述第六晶体管的第二极配置为和所述移位信号输出端连接；所述第七晶体管的栅极配置为和所述第一控制节点连接，所述第七晶体管的第一极配置为和所述第二时钟信号端连接以接收所述第二时钟信号作为所述复合输出信号，所述第七晶体管的第二极配置为和所述像素扫描信号输出端连接；所述第二电容的第一极配置为和所述第一控制节点连接，所述第二电容的第二极配置为和所述第六晶体管的第二极或所述第七晶体管的第二极连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述降噪电路包括第八晶体管、第九晶体管和第十晶体管；所述第八晶体管的栅极配置为和所述第二控制节点连接，所述第八晶体管的第一极配置为和所述第一控制节点连接，所述第八晶体管的第二极配置为和第三电压端连接以接收第三电压；所述第九晶体管的栅极配置为和所述第二控制节点连接，所述第九晶体管的第一极配置为和所述移位信号输出端连接，所述第九晶体管的第二极配置为和所述第三电压端连接以接收所述第三电压；所述第十晶体管的栅极配置为和所述第二控制节点连接，所述第十晶体管的第一极配置为和所述像素扫描信号输出端连接，所述第十晶体管的第二极配置为和第四电压端连接以接收第四电压。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一控制电路包括第十一晶体管、第十二晶体管和第十三晶体管；所述第十一晶体管的栅极和第一极连接且配置为和第五电压端连接以接收第五电压，所述第十一晶体管的第二极配置为和所述第二控制节点连接；所述第十二晶体管的栅极和第一极连接且配置为和第六电压端连接以接收第六电压，所述第十二晶体管的第二极配置为和所述第二控制节点连接；所述第十三晶体管的栅极配置为和所述第一控制节点连接，所述第十三晶体管的第一极配置为和所述第二控制节点连接，所述第十三晶体管的第二极配置为和第三电压端连接以接收第三电压。
例如，在本公开一实施例提供的移位寄存器单元还包括消隐复位电路，其中，所述消隐复位电路配置为响应于消隐复位信号对所述第一控制节点进行复位。
例如，在本公开一实施例提供的移位寄存器单元中，所述消隐复位电路包括第十四晶体管；所述第十四晶体管的栅极配置为和消隐复位信号端连接 以接收所述消隐复位信号，所述第十四晶体管的第一极配置为和所述第一控制节点连接，所述第十四晶体管的第二极配置为和第三电压端连接以接收第三电压。
例如，在本公开一实施例提供的移位寄存器单元还包括显示复位电路，其中，所述显示复位电路配置为响应于显示复位信号对所述第一控制节点进行复位。
例如，在本公开一实施例提供的移位寄存器单元中，所述显示复位电路包括第十五晶体管；所述第十五晶体管的栅极配置为和显示复位信号端连接以接收所述显示复位信号，所述第十五晶体管的第一极配置为和所述第一控制节点连接，所述第十五晶体管的第二极配置为和第三电压端连接以接收第三电压。
例如，在本公开一实施例提供的移位寄存器单元还包括第二控制电路，其中，所述第二控制电路配置为响应于第一时钟信号或所述显示输入信号对所述第二控制节点的电平进行控制。
例如，在本公开一实施例提供的移位寄存器单元中，所述第二控制电路包括第十六晶体管和第十七晶体管；所述第十六晶体管的栅极配置为和第一时钟信号端连接以接收所述第一时钟信号，所述第十六晶体管的第一极配置为和所述第二控制节点连接，所述第十六晶体管的第二极配置为接收第三电压端的第三电压；所述第十七晶体管的栅极配置为和显示输入信号端连接以接收所述显示输入信号，所述第十七晶体管的第一极配置为和所述第二控制节点连接，所述第十七晶体管的第二极配置为和所述第三电压端连接以接收所述第三电压。
本公开至少一个实施例还提供一种栅极驱动电路，包括本公开任一实施例所述的移位寄存器单元。
例如，在本公开一实施例提供的栅极驱动电路中，每四级移位寄存器单元共用同一充电子电路、同一补偿子电路和同一控制子电路，第4n-3级移位寄存器单元的随机信号端和随机信号线连接，第4n-3级移位寄存器单元的第一时钟信号端和第一时钟线连接，n为大于0的整数。
例如，在本公开一实施例提供的栅极驱动电路包括第一子时钟信号线、第二子时钟信号线、第三子时钟信号线和第四子时钟信号线，其中，第4n-3级移位寄存器单元的第二时钟信号端和所述第一子时钟信号线连接；第4n-2 级移位寄存器单元的第二时钟信号端和所述第二子时钟信号线连接；第4n-1级移位寄存器单元的第二时钟信号端和所述第三子时钟信号线连接；第4n级移位寄存器单元的第二时钟信号端和所述第四子时钟信号线连接；n为大于0的整数。
例如，在本公开一实施例提供的栅极驱动电路中，第n+1级移位寄存器单元的消隐输入信号端和第n级移位寄存器单元的移位信号输出端连接；第n+2级移位寄存器单元的显示输入信号端和第n级移位寄存器单元的移位信号输出端连接；第n级移位寄存器单元的显示复位信号端和第n+3级移位寄存器单元的移位信号输出端连接；n为大于0的整数。
本公开至少一个实施例还提供一种显示装置，包括本公开任一实施例所述的移位寄存器单元或本公开任一实施例所述的栅极驱动电路。
本公开至少一个实施例还提供一种如本公开任一实施例所述的移位寄存器单元的驱动方法，包括用于处理一帧图像的显示时段和消隐时段，其中，所述显示时段包括：第一输入阶段，所述显示输入电路响应于所述显示输入信号将所述显示上拉信号输入到所述第一控制节点；第一输出阶段，所述输出电路在所述第一控制节点的电平的控制下，将所述复合输出信号输出至所述输出端；所述消隐时段包括：第二输入阶段，所述消隐输入电路根据所述消隐输入信号和所述消隐控制信号将所述消隐上拉信号输入到所述第一控制节点，并对所述消隐输入电路自身进行补偿；第二输出阶段，所述输出电路在所述第一控制节点的电平的控制下，将所述复合输出信号输出至所述输出端。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开一些实施例提供的一种移位寄存器单元的示意框图；
图2为本公开一些实施例提供的一种移位寄存器单元的消隐输入电路的示意框图；
图3为本公开一些实施例提供的另一种移位寄存器单元的消隐输入电路的示意框图；
图4为本公开一些实施例提供的另一种移位寄存器单元的示意框图；
图5为本公开一些实施例提供的另一种移位寄存器单元的示意框图；
图6为图4中所示的移位寄存器单元的一种具体实现示例的电路图；
图7为图5中所示的移位寄存器单元的一种具体实现示例的电路图；
图8为图5中所示的移位寄存器单元的另一种具体实现示例的电路图；
图9A-9C为本公开一些实施例提供的一种移位寄存器单元的消隐输入电路的具体实现示例的电路图；
图10为本公开一些实施例提供的一种移位寄存器单元的显示输入电路的具体实现示例的电路图；
图11为本公开一些实施例提供的一种移位寄存器单元的第二控制电路的具体实现示例的电路图；
图12为本公开一些实施例提供的一种移位寄存器单元的信号时序图；
图13为本公开一些实施例提供的另一种移位寄存器单元的信号时序图；
图14为本公开一些实施例提供的一种栅极驱动电路的示意框图；
图15A-15C为图14中所示的栅极驱动电路中相邻的四级移位寄存器单元的消隐输入电路的具体实现示例的电路图；
图16为本公开一些实施例提供的一种栅极驱动电路的信号时序图；以及
图17为本公开一些实施例提供的一种显示装置的示意框图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机 械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在通常的OLED显示面板中，需要通过补偿技术来提高显示质量。在对OLED显示面板中的子像素单元进行补偿时，除了在子像素单元中设置像素补偿电路进行内部补偿外，还可以通过设置感测晶体管进行外部补偿。在进行外部补偿时，由移位寄存器单元构成的栅极驱动电路需要向显示面板中的子像素单元分别提供用于扫描晶体管和感测晶体管的驱动信号，例如，在一帧的显示时段提供用于扫描晶体管的扫描驱动信号(即显示输出信号)，在一帧的消隐时段提供用于感测晶体管的感测驱动信号(即消隐输出信号)。
在IC设计中芯片的面积是影响芯片成本的主要因素，如何有效地减小芯片面积是技术开发人员需要着重考虑的问题。在OLED显示面板中，栅极驱动电路的移位寄存器单元一般包括检测单元(sense unit)、显示单元(scan unit)和输出两者复合脉冲的连接单元(或门电路或Hiz电路)。利用包括上述三个部分的电路结构，移位寄存器单元可以输出具有不同宽度和时序的两个波形组成的复合波形的输出脉冲，从而为扫描晶体管和感测晶体管分别提供显示输出信号和消隐输出信号。但是，上述移位寄存器单元的电路结构复杂，且尺寸较大，不利于实现高分辨率和窄边框，也不利于减小芯片面积以降低成本。
为了进一步减小移位寄存器单元以及包括移位寄存器单元的栅极驱动电路的尺寸，例如，可以将检测单元、显示单元和连接单元整合，使一帧画面的消隐时段的消隐输出信号和显示时段的显示输出信号通过同一个输出电路输出，从而简化电路结构。然而，在整合后的电路中，在消隐时段中对第一控制节点(例如上拉节点)进行电平控制(例如上拉)时，由于该功能由多个晶体管组成的电路实现，因此存在较大的阈值电压损失，从而影响上拉节点的电位，例如使上拉节点的电位无法达到预定的高电位，进而影响消隐输出信号的输出。并且，栅极驱动电路一般采用顺序扫描的方式进行外部补偿，但是长时间的逐行补偿会带来一些问题，例如，显示过程中会有一条逐行移动的扫描线、由于补偿时间的差异导致不同区域的亮度差异大等。
本公开至少一实施例提供一种移位寄存器单元及其驱动方法、栅极驱动电路及显示装置，该移位寄存器单元的电路结构简单，可以改善消隐时段中 消隐输入电路对第一控制节点(例如上拉节点)进行电平控制(例如上拉)时的阈值电压损失，避免影响第一控制节点的电位，从而提高消隐输出信号的准确性。
下面，将参考附图详细地说明本公开的实施例。应当注意的是，不同的附图中相同的附图标记将用于指代已描述的相同的元件。
本公开至少一实施例提供一种移位寄存器单元，该移位寄存器单元包括消隐输入电路、显示输入电路和输出电路。消隐输入电路配置为根据消隐输入信号和消隐控制信号在消隐时段将消隐上拉信号输入到第一控制节点，并对消隐输入电路自身进行补偿；显示输入电路配置为响应于显示输入信号在显示时段将显示上拉信号输入到第一控制节点；输出电路配置为在第一控制节点的电平的控制下，将复合输出信号输出至输出端。
图1为本公开一些实施例提供的一种移位寄存器单元的示意框图。参考图1，该移位寄存器单元10包括消隐输入电路100、显示输入电路200和输出电路300。例如，在一些示例中，移位寄存器单元10还进一步包括降噪电路400和第一控制电路500。多个该移位寄存器单元10可以级联构建本公开任一实施例提供的栅极驱动电路。
消隐输入电路100配置为根据消隐输入信号和消隐控制信号在消隐时段将消隐上拉信号输入到第一控制节点(例如上拉节点Q)，并对消隐输入电路100自身进行补偿。例如，消隐输入电路100与消隐输入信号端STU1、消隐控制信号端Bcon、消隐上拉信号端Bla_up和上拉节点Q电连接。例如，消隐输入电路100还包括第一节点N1和第二节点N2(图1中未示出)，消隐输入电路100响应于消隐输入信号端STU1提供的消隐输入信号和消隐控制信号端Bcon提供的消隐控制信号对第一节点N1充电，并对第一节点N1的电平进行补偿，以及对第二节点N2的电平进行耦合控制，从而在第二节点N2的电平的控制下将消隐上拉信号端Bla_up提供的消隐上拉信号输入到上拉节点Q，以对上拉节点Q进行充电并使其为高电平。
需要说明的是，在本公开的实施例中，在移位寄存器单元10中设置消隐输入电路100是为了实现在一帧的消隐时段中可以输出消隐输出信号。消隐输入电路100中的“消隐”仅是表示该电路和消隐时段有关，而并不限定该电路仅工作在消隐时段中，以下各实施例与此相同，不再赘述。例如，消隐输入电路100在显示时段对第一节点N1充电，并使第一节点N1的高电平保 持至消隐时段；消隐输入电路100在消隐时段对第一节点N1的电平进行补偿，并对第二节点N2的电平进行耦合控制，以及对上拉节点Q充电以使其为高电平。
例如，消隐输入电路100可以实现为多个晶体管，在对上拉节点Q充电的过程中，通过对第一节点N1的电平进行补偿以及对第二节点N2的电平进行耦合控制，可以补偿多个晶体管产生的阈值电压损失，使第二节点N2的电平达到预定值(例如，预定的高电平)，从而在第二节点N2的电平的控制下使上拉节点Q的电平也达到预定值(例如，预定的高电平)，以避免阈值电压的损失影响上拉节点Q的电平。
例如，可以采用随机信号作为消隐控制信号。例如，随机信号由另行设置的随机信号发生电路(例如FPGA)提供。当多个移位寄存器单元10级联为栅极驱动电路时，提供给该栅极驱动电路的随机信号不是逐行扫描的时序，而是随机的或按照其他规律的时序，从而实现随机检测功能，即在任意帧对任意行的像素电路进行补偿检测。因此，当该栅极驱动电路在随机信号的控制下输出消隐输出信号以对像素电路进行外部补偿时，可以通过随机检测的功能消除出现在屏幕中的扫描线以及亮度偏差。
显示输入电路200配置为响应于显示输入信号在显示时段将显示上拉信号输入到第一控制节点(例如上拉节点Q)。例如，显示输入电路200与显示输入信号端STU2、显示上拉信号端Dis_up和上拉节点Q电连接，配置为在显示输入信号端STU2提供的显示输入信号的控制下导通，使显示上拉信号端Dis_up和上拉节点Q电连接，从而使显示上拉信号端Dis_up提供的显示上拉信号输入到上拉节点Q，将上拉节点Q上拉为高电平。
输出电路300配置为在第一控制节点(例如上拉节点Q)的电平的控制下，将复合输出信号输出至输出端OP。例如，输出电路300与上拉节点Q、复合输出信号端Com和输出端OP电连接，配置为在上拉节点Q的电平的控制下导通，使复合输出信号端Com提供的复合输出信号输出至输出端OP。例如，输出端OP的输出信号可以包括显示输出信号和消隐输出信号，其中显示输出信号和消隐输出信号可以是具有不同宽度和时序的相互独立的两个波形。例如，在显示时段，输出电路300在上拉节点Q的电平的控制下经由输出端OP输出显示输出信号，以驱动像素单元中的扫描晶体管，从而进行显示；在消隐时段，输出电路300在上拉节点Q的电平的控制下经由输出端OP输 出消隐输出信号，以驱动像素单元中的感测晶体管，从而进行补偿检测。
降噪电路400配置为在第二控制节点(例如下拉节点QB)的电平的控制下，对第一控制节点(例如上拉节点Q)和输出端OP进行降噪。例如，降噪电路400与下拉节点QB、上拉节点Q和输出端OP连接，配置为在下拉节点QB的电平的控制下，使上拉节点Q和输出端OP与另行提供的电压端(例如，低电压端)电连接，从而将上拉节点Q和输出端OP下拉为非工作电平(例如，低电平)，以实现降噪。
第一控制电路500配置为在第一控制节点(例如上拉节点Q)的电平的控制下，对第二控制节点(例如下拉节点QB)的电平进行控制。例如，第一控制电路500与上拉节点Q和下拉节点QB电连接，配置为当上拉节点Q为高电平时将下拉节点QB下拉为低电平，当上拉节点Q为低电平时将下拉节点QB上拉为高电平。例如，第一控制电路500可以为反相电路。
图2为本公开一些实施例提供的一种移位寄存器单元的消隐输入电路的示意框图。参考图2，消隐输入电路100包括充电子电路110、补偿子电路120和隔离子电路130。
充电子电路110配置为响应于消隐控制信号将消隐输入信号输入到第一节点N1。例如，充电子电路110与消隐输入信号端STU1、消隐控制信号端Bcon和第一节点N1连接，配置为在消隐控制信号端Bcon提供的消隐控制信号的控制下导通，使消隐输入信号端STU1和第一节点N1电连接，从而将消隐输入信号输入到第一节点N1。例如，在一些示例中，充电子电路110在消隐控制信号的控制下导通，消隐输入信号此时为高电平，从而对第一节点N1充电，将第一节点N1上拉为高电平。
补偿子电路120配置为存储充电子电路110输入的消隐输入信号，并响应于第一时钟信号对第一节点N1的电平进行补偿，以及对第二节点N2的电平进行耦合控制。例如，补偿子电路120与第一节点N1、第二节点N2和第一时钟信号端CLKA连接，配置为存储写入到第一节点N1的消隐输入信号，并在第一时钟信号端CLKA提供的第一时钟信号的电平改变(例如，从低电平变为高电平)时，对第一节点N1的电平进行补偿(例如，将第一节点N1的电平进一步拉高至第一电平)，从而对第二节点N2的电平进行耦合控制。例如，补偿子电路120在第一节点N1的第一电平的控制下充分导通，使第一时钟信号被充分写入第二节点N2。例如，在一些示例中，由于第一时钟信号 被充分写入第二节点N2，因此第二节点N2的电平等于第一时钟信号此时的高电平，即第二节点N2的电平达到预定值。当然，本公开的实施例不限于此，第二节点N2的电平也可以略小于第一时钟信号的高电平，只要能够控制隔离子电路130导通或充分导通即可。
隔离子电路130配置为在第二节点N2的电平的控制下，将消隐上拉信号输入到第一控制节点(例如上拉节点Q)。例如，隔离子电路130与第二节点N2、上拉节点Q和消隐上拉信号端Bla_up连接，配置为在第二节点N2的电平的控制下导通，使消隐上拉信号端Bla_up和上拉节点Q电连接，从而将消隐上拉信号端Bla_up提供的消隐上拉信号输入到上拉节点Q。例如，在一些示例中，隔离子电路130在第二节点N2的电平的控制下导通，消隐上拉信号此时为高电平，从而对上拉节点Q充电，将上拉节点Q上拉为高电平。例如，在补偿子电路120的作用下，第二节点N2的电平达到预定值，从而使隔离子电路130充分导通，使消隐上拉信号的高电平充分写入到上拉节点Q，进而使上拉节点Q的电平达到预定值。
通过上述方式，可以改善消隐时段中消隐输入电路100对上拉节点Q进行上拉时的阈值电压损失，避免影响上拉节点Q的电位，从而提高消隐输出信号的准确性。
图3为本公开一些实施例提供的另一种移位寄存器单元的消隐输入电路的示意框图。参考图3，该实施例中消隐输入电路100还包括控制子电路140，其他结构与图2中所示的消隐输入电路100基本相同。控制子电路140配置为在第二控制节点(例如下拉节点QB)的电平的控制下，对第二节点N2的电平进行控制(例如下拉)。例如，控制子电路140与第二节点N2和下拉节点QB连接，配置为在下拉节点QB的电平的控制下导通，使第二节点N2与另行提供的电压端(例如，低电压端)电连接，从而将第二节点N2下拉为低电平。需要说明的是，本公开的实施例中，控制子电路140不局限于与下拉节点QB连接，也可以与另行提供的时钟信号端或其他适用的信号端连接，从而在时钟信号或其他适用的信号的控制下对第二节点N2进行下拉。
通过设置控制子电路140，可以确保第二节点N2在需要为低电平时一直保持为低电平，从而确保隔离子电路130关闭，避免消隐上拉信号对上拉节点Q产生影响。例如，在一些示例中，在显示时段，通过控制子电路140对第二节点N2进行下拉，以避免消隐上拉信号影响上拉节点Q的电位，从而 实现正常的显示功能。
需要说明的是，本公开的实施例中，消隐输入电路100可以包括任意适用的子电路，不局限于上述充电子电路110、补偿子电路120、隔离子电路130和控制子电路140，只要能实现相应功能即可。
图4为本公开一些实施例提供的另一种移位寄存器单元的示意框图。参考图4，该实施例中移位寄存器单元10还包括消隐复位电路600和显示复位电路700，其他结构与图1所示的移位寄存器单元10基本相同。
消隐复位电路600配置为响应于消隐复位信号对第一控制节点(例如上拉节点Q)进行复位。例如，消隐复位电路600与消隐复位信号端TRST和上拉节点Q连接，配置为在消隐复位信号端TRST提供的消隐复位信号的控制下导通，使上拉节点Q与另行提供的电压端(例如，低电压端)电连接，从而对上拉节点Q复位。例如，在消隐时段，当输出电路300完成信号输出后，通过消隐复位电路600对上拉节点Q复位。需要说明的是，在本公开的实施例中，消隐复位电路600中的“消隐”仅是表示该电路和消隐时段有关，而并不限定该电路仅工作在消隐时段中，以下各实施例与此相同，不再赘述。
显示复位电路700配置为响应于显示复位信号对第一控制节点(例如上拉节点Q)进行复位。例如，显示复位电路700与显示复位信号端STD和上拉节点Q连接，配置为在显示复位信号端STD提供的显示复位信号的控制下导通，使上拉节点Q与另行提供的电压端(例如，低电压端)电连接，从而对上拉节点Q复位。例如，在显示时段，当输出电路300完成信号输出后，通过显示复位电路700对上拉节点Q复位。
图5为本公开一些实施例提供的另一种移位寄存器单元的示意框图。参考图5，该实施例中移位寄存器单元10还包括第二控制电路800，其他结构与图4所示的移位寄存器单元10基本相同。第二控制电路800配置为响应于第一时钟信号或显示输入信号对第二控制节点(例如下拉节点QB)的电平进行控制。例如，第二控制电路800与第一时钟信号端CLKA、显示输入信号端STU2和下拉节点QB连接，配置为在第一时钟信号端CLKA提供的第一时钟信号或显示输入信号端STU2提供的显示输入信号的控制下导通，使下拉节点QB与另行提供的电压端(例如，低电压端)电连接，从而将下拉节点QB下拉为低电平。
例如，在消隐时段，第二控制电路800响应于第一时钟信号对下拉节点 QB进行下拉；在显示时段，第二控制电路800响应于显示输入信号对下拉节点QB进行下拉。当然，本公开的实施例不限于此，第二控制电路800也可以仅在消隐时段或仅在显示时段对下拉节点QB进行下拉。通过设置第二控制电路800，可以确保下拉节点QB处于低电平，有助于消隐输入电路100或显示输入电路200将高电平写入上拉节点Q，使上拉节点Q的电平达到预定值，因此可防止晶体管阈值电压漂移后影响输出信号，增强了电路的信赖性。
图6为图4中所示的移位寄存器单元的一种具体实现示例的电路图。在下面的说明中以各晶体管为N型晶体管为例进行说明，但这并不构成对本公开实施例的限制。
参考图6，该移位寄存器单元10包括第一至第十五晶体管M1-M15，以及还包括第一电容C1和第二电容C2。
消隐输入电路100包括充电子电路110、补偿子电路120、隔离子电路130和控制子电路140。充电子电路110可以实现为第一晶体管M1。第一晶体管M1的栅极配置为和随机信号端OE连接以接收随机信号(这里，将随机信号端OE作为前述的消隐控制信号端Bcon，将随机信号作为前述的消隐控制信号)，第一晶体管M1的第一极配置为和消隐输入信号端STU1连接以接收消隐输入信号，第一晶体管M1的第二极配置为和第一节点N1连接。当随机信号为有效电平(例如，高电平)时，第一晶体管M1导通，从而将消隐输入信号写入第一节点N1。例如，此时消隐输入信号为高电平，以对第一节点N1充电。
补偿子电路120可以实现为第二晶体管M2和第一电容C1。第二晶体管M2的栅极配置为和第一节点N1连接，第二晶体管M2的第一极配置为和第一时钟信号端CLKA连接以接收第一时钟信号，第二晶体管M2的第二极配置为和第二节点N2连接。第一电容C1的第一极配置为和第一节点N1连接，第一电容C1的第二极配置为和第二节点N2连接。当消隐输入信号被写入到第一节点N1后，第一节点N1被充电至高电平，第一电容C1存储该高电平并将第一节点N1维持在高电平，以在后续阶段使用。并且，第二晶体管M2导通，将第一时钟信号写入第二节点N2。当第一时钟信号由低电平变为高电平时，由于第一电容C1的自举作用，第一节点N1的电平被进一步抬升至第一电平，使第二晶体管M2充分导通，从而使第一时钟信号的高电平充分写入第二节点N2，以使第二节点N2的电平达到预定值，例如等于第一时钟信 号的高电平。
隔离子电路130可以实现为第三晶体管M3。第三晶体管M3的栅极配置为和第二节点N2连接，第三晶体管M3的第一极配置为和第一电压端VDD连接以接收第一电压(这里，第一电压端VDD相当于消隐上拉信号端Bla_up，将第一电压作为消隐上拉信号)，第三晶体管M3的第二极配置为和第一控制节点(例如上拉节点Q)连接。当第二节点N2为高电平(例如，该高电平达到预定值)时，第三晶体管M3充分或近似充分导通，将第一电压写入上拉节点Q，从而使上拉节点Q的电平为高电平。
控制子电路140可以实现为第四晶体管M4。第四晶体管M4的栅极配置为和第二控制节点(例如下拉节点QB)连接，第四晶体管M4的第一极配置为和第二节点N2连接，第四晶体管M4的第二极配置为和第二电压端VGL2连接以接收第二电压。当下拉节点QB为高电平时，第四晶体管M4导通，将第二节点N2下拉为低电平，从而确保第三晶体管M3截止，以避免在显示时段中消隐上拉信号(例如，第一电压端VDD的第一电压)对上拉节点Q产生影响。
例如，第一电压端VDD配置为提供直流高电平信号，将该直流高电平信号称为第一电压；第二电压端VGL2配置为提供直流低电平信号，例如接地，将该直流低电平信号称为第二电压。以下各实施例与此相同，不再赘述。
显示输入电路200可以实现为第五晶体管M5。第五晶体管M5的栅极配置为和显示输入信号端STU2连接以接收显示输入信号，第五晶体管M5的第一极配置为和第一电压端VDD连接以接收第一电压(这里，第一电压端VDD相当于显示上拉信号端Dis_up，将第一电压作为显示上拉信号)，第五晶体管M5的第二极配置为和第一控制节点(例如上拉节点Q)连接。当显示输入信号为有效电平(例如，高电平)时，第五晶体管M5导通，从而将第一电压写入上拉节点Q，使上拉节点Q为高电平。
例如，在一些示例中，输出电路300的输出端OP包括至少一个移位信号输出端CR和至少一个像素扫描信号输出端Out，以提高该移位寄存器单元10的驱动能力。例如，移位信号输出端CR用于为下一级移位寄存器单元10提供消隐输入信号，像素扫描信号输出端Out用于为像素电路提供驱动信号。移位信号输出端CR和像素扫描信号输出端Out的输出信号相同。
输出电路300可以实现为第六晶体管M6、第七晶体管M7和第二电容 C2。第六晶体管M6的栅极配置为和第一控制节点(例如上拉节点Q)连接，第六晶体管M6的第一极配置为和第二时钟信号端CLKB连接以接收第二时钟信号(这里，第二时钟信号端CLKB相当于复合输出信号端Com，将第二时钟信号作为复合输出信号)，第六晶体管M6的第二极配置为和移位信号输出端CR连接。第七晶体管M7的栅极配置为和第一控制节点(例如上拉节点Q)连接，第七晶体管M7的第一极配置为和第二时钟信号端CLKB连接以接收第二时钟信号作为复合输出信号，第七晶体管M7的第二极配置为和像素扫描信号输出端Out连接。第二电容C2的第一极配置为和第一控制节点(例如上拉节点Q)连接，第二电容C2的第二极配置为和第六晶体管M6的第二极连接。当然，本公开的实施例不限于此，例如，在另一些示例中，第二电容C2的第二极也可以和第七晶体管M7的第二极连接。当上拉节点Q为有效电平(例如，高电平)时，第六晶体管M6和第七晶体管M7均导通，从而分别将第二时钟信号输出到移位信号输出端CR和像素扫描信号输出端Out。
降噪电路400可以实现为第八晶体管M8、第九晶体管M9和第十晶体管M10。第八晶体管M8的栅极配置为和第二控制节点(例如下拉节点QB)连接，第八晶体管M8的第一极配置为和第一控制节点(例如上拉节点Q)连接，第八晶体管M8的第二极配置为和第三电压端VGL1连接以接收第三电压。第九晶体管M9的栅极配置为和第二控制节点(例如下拉节点QB)连接，第九晶体管M9的第一极配置为和移位信号输出端CR连接，第九晶体管M9的第二极配置为和第三电压端VGL1连接以接收第三电压。第十晶体管M10的栅极配置为和第二控制节点(例如下拉节点QB)连接，第十晶体管M10的第一极配置为和像素扫描信号输出端Out连接，第十晶体管M10的第二极配置为和第四电压端连接以接收第四电压(这里，将第二电压端VGL2作为第四电压端，将第二电压作为第四电压)。
例如，第三电压端VGL1配置为提供直流低电平信号，例如接地，将该直流低电平信号称为第三电压，以下各实施例与此相同，不再赘述。例如，在一些示例中，第三电压端VGL1的第三电压低于第二电压端VGL2的第二电压；在另一些示例中，第三电压端VGL1的第三电压等于第二电压端VGL2的第二电压。第三电压和第二电压可以相同也可以不同，这可以根据实际需求而定。
当下拉节点QB为有效电平(例如，高电平)时，第八晶体管M8、第九 晶体管M9和第十晶体管M10均导通，使上拉节点Q和移位信号输出端CR与第三电压端VGL1电连接，使像素扫描信号输出端Out与第二电压端VGL2电连接，从而对上拉节点Q、移位信号输出端CR和像素扫描信号输出端Out降噪。需要说明的是，本公开的实施例中，当移位信号输出端CR和/或像素扫描信号输出端Out为多个时，降噪电路400也相应地包括多个与移位信号输出端CR和/或像素扫描信号输出端Out对应连接的晶体管，以对多个移位信号输出端CR和/或像素扫描信号输出端Out进行降噪。
第一控制电路500可以实现为第十一晶体管M11、第十二晶体管M12和第十三晶体管M13。第十一晶体管M11的栅极和第一极连接且配置为和第五电压端VDD_A连接以接收第五电压，第十一晶体管M11的第二极配置为和第二控制节点(例如下拉节点QB)连接。第十二晶体管M12的栅极和第一极连接且配置为和第六电压端VDD_B连接以接收第六电压，第十二晶体管M12的第二极配置为和第二控制节点(例如下拉节点QB)连接。第十三晶体管M13的栅极配置为和第一控制节点(例如上拉节点Q)连接，第十三晶体管M13的第一极配置为和第二控制节点(例如下拉节点QB)连接，第十三晶体管M13的第二极配置为和第三电压端VGL1连接以接收第三电压。
例如，在一些示例中，第五电压端VDD_A和第六电压端VDD_B配置为交替提供直流高电平信号，从而使第十一晶体管M11和第十二晶体管M12交替导通，以避免晶体管长期导通引起的性能漂移。例如，当第五电压端VDD_A提供高电平信号时，第六电压端VDD_B提供低电平信号，此时第十一晶体管M11导通，第十二晶体管M12截止；当第六电压端VDD_B提供高电平信号时，第五电压端VDD_A提供低电平信号，此时第十二晶体管M12导通，第十一晶体管M11截止。例如，将第五电压端VDD_A提供的信号称为第五电压，将第六电压端VDD_B提供的信号称为第六电压，以下各实施例与此相同，不再赘述。
当上拉节点Q为有效电平(例如，高电平)时，第十三晶体管M13导通，通过设计第十三晶体管M13与导通的第十一晶体管M11或第十二晶体管M12的沟道宽长比，可以将下拉节点QB下拉为低电平。当上拉节点Q为低电平时，第十三晶体管M13截止，此时，导通的第十一晶体管M11或第十二晶体管M12将第五电压端VDD_A或第六电压端VDD_B提供的高电平信号写入下拉节点QB，以将下拉节点QB上拉至高电平。
消隐复位电路600可以实现为第十四晶体管M14。第十四晶体管M14的栅极配置为和消隐复位信号端TRST连接以接收消隐复位信号，第十四晶体管M14的第一极配置为和第一控制节点(例如上拉节点Q)连接，第十四晶体管M14的第二极配置为和第三电压端VGL1连接以接收第三电压。例如，在消隐时段，当消隐复位信号为有效电平(例如，高电平)时，第十四晶体管M14导通，使上拉节点Q与第三电压端VGL1电连接，从而对上拉节点Q复位。
显示复位电路700可以实现为第十五晶体管M15。第十五晶体管M15的栅极配置为和显示复位信号端STD连接以接收显示复位信号，第十五晶体管M15的第一极配置为和第一控制节点(例如上拉节点Q)连接，第十五晶体管M15的第二极配置为和第三电压端VGL1连接以接收第三电压。例如，在显示时段，当显示复位信号为有效电平(例如，高电平)时，第十五晶体管M15导通，使上拉节点Q与第三电压端VGL1电连接，从而对上拉节点Q复位。
图7为图5中所示的移位寄存器单元的一种具体实现示例的电路图。参考图7，该移位寄存器单元10包括第一至第十七晶体管M1-M17，以及还包括第一电容C1和第二电容C2。第一至第十五晶体管M1-M15、第一电容C1和第二电容C2的连接关系与图6所示的移位寄存器单元10基本相同，此处不再赘述。
第二控制电路800可以实现为第十六晶体管M16和第十七晶体管M17。第十六晶体管M16的栅极配置为和第一时钟信号端CLKA连接以接收第一时钟信号，第十六晶体管M16的第一极配置为和第二控制节点(例如下拉节点QB)连接，第十六晶体管M16的第二极配置和第三电压端VGL1连接以接收第三电压。第十七晶体管M17的栅极配置为和显示输入信号端STU2连接以接收显示输入信号，第十七晶体管M17的第一极配置为和第二控制节点(例如下拉节点QB)连接，第十七晶体管M17的第二极配置为和第三电压端VGL1连接以接收第三电压。在消隐时段，当第一时钟信号为有效电平(例如，高电平)时，第十六晶体管M16导通，使下拉节点QB与第三电压端VGL1电连接，从而将下拉节点QB下拉为低电平。在显示时段，当显示输入信号为有效电平(例如，高电平)时，第十七晶体管M17导通，使下拉节点QB与第三电压端VGL1电连接，从而将下拉节点QB下拉为低电平。
需要说明的是，本公开的实施例中，消隐输入电路100、显示输入电路200、输出电路300、降噪电路400、第一控制电路500、消隐复位电路600、显示复位电路700和第二控制电路800的具体实现方式不局限于上面描述的方式，可以为任意适用的实现方式，例如为本领域技术人员熟知的常规连接方式，只需保证实现相应功能即可。
图8为图5中所示的移位寄存器单元的另一种具体实现示例的电路图。参考图8，该实施例的移位寄存器单元10包括多个防漏电电路、2个第二控制节点(例如为第一下拉节点QB_A和第二下拉节点QB_B)、2个像素扫描信号输出端(第一像素扫描信号输出端Out1和第二像素扫描信号输出端Out2)，其他结构与图7中所示的移位寄存器单元10基本相同。
在图7所示的移位寄存器单元10中，可以利用第一电容C1维持第一节点N1的高电平，利用第二电容C2维持上拉节点Q的高电平，此时，存在一些晶体管其第一极连接上拉节点Q和/或第一节点N1，第二极连接低电平的信号线。即使当这些晶体管的栅极输入的是非导通信号的情况下，由于其第一极和第二极之间存在电压差，也可能出现漏电的现象，从而使得该电路对上拉节点Q和/或第一节点N1的高电平的维持效果变差。因此，图8所示的移位寄存器单元10增加了多个防漏电电路，以改善对上拉节点Q和/或第一节点N1的高电平的维持效果。
例如，参考图8，第一防漏电电路可以实现为第一防漏电晶体管M1_b和第二防漏电晶体管M1_c，配置为在第一节点N1为高电平时，防止第一节点N1处的电荷经由第一晶体管M1漏电到消隐输入信号端STU1。第一防漏电晶体管M1_b的栅极连接到第一晶体管M1的栅极(随机信号端OE)，第一极连接到第一晶体管M1的第二极，第二极连接到第一节点N1。第二防漏电晶体管M1_c的栅极连接到第一节点N1，第一极连接到第一电压端VDD，第二极连接到第一防漏电晶体管M1_b的第一极。
当第一节点N1为高电平时，第二防漏电晶体管M1_c在第一节点N1的控制下导通，并将第一电压(高电压)写入到第一防漏电晶体管M1_b的第一极，从而使第一防漏电晶体管M1_b的第一极和第二极都处于高电平的状态，以防止第一节点N1处的电荷通过第一防漏电晶体管M1_b漏电。此时，由于第一晶体管M1的栅极与第一防漏电晶体管M1_b的栅极连接，因此第一防漏电晶体管M1_b和第一晶体管M1的结合可以实现与前述的第一晶体管 M1相同的功能，并同时具有防漏电的效果。
类似地，对于连接到上拉节点Q的第八晶体管M8、第十四晶体管M14、第十五晶体管M15和第二十二晶体管M22，也可以采用与前述原理相同的防漏电电路以实现防漏电的效果。例如，第二防漏电电路可以实现为第三防漏电晶体管M8_b、第四防漏电晶体管M14_b、第五防漏电晶体管M15_b、第六防漏电晶体管22_b和第七防漏电晶体管M23。第二防漏电电路的连接方式与前述第一防漏电电路类似，此处不再赘述。
当上拉节点Q为高电平时，第七防漏电晶体管M23导通，使防漏电节点OFF为高电平，从而使第三防漏电晶体管M8_b、第四防漏电晶体管M14_b、第五防漏电晶体管M15_b、第六防漏电晶体管M22_b各自的第一极和第二极都处于高电平状态，以防止上拉节点Q处的电荷漏电。此时，第八晶体管M8、第十四晶体管M14、第十五晶体管M15和第二十二晶体管M22与第二防漏电电路的结合可以实现与前述的第八晶体管M8、第十四晶体管M14、第十五晶体管M15相同的功能，且具有防漏电效果。
需要说明的是，本领域技术人员可以理解，根据本公开的实施例提供的具有防漏电功能的电路的实施例，可以根据实际情况选择移位寄存器单元10中的一个或多个晶体管增加防漏电的电路结构。图8仅示出了包括防漏电电路的一种示例性的电路结构，而不构成对本公开实施例的限制。
如图8所示，该移位寄存器单元10包括2个第二控制节点，例如包括第一下拉节点QB_A和第二下拉节点QB_B。相应地，第十一晶体管M11和第十三晶体管M13共同控制第一下拉节点QB_A的电平，第十二晶体管M12和第二十四晶体管M24共同控制第二下拉节点QB_B的电平。由于第五电压端VDD_A和第六电压端VDD_B交替提供高电平信号，因此当上拉节点Q为低电平时，第一下拉节点QB_A和第二下拉节点QB_B交替为高电平；当上拉节点Q为高电平时，第一下拉节点QB_A和第二下拉节点QB_B均为低电平。通过这种方式，可以防止晶体管的阈值电压漂移。关于上述2个第二控制节点的电路连接方式和相关工作原理可以参考常规的双下拉节点移位寄存器单元，此处不再赘述。
相应地，第二控制电路800也实现为两组晶体管，第二十五晶体管M25、第二十六晶体管M26和第二十七晶体管M27为一组，第十六晶体管M16、第十七晶体管M17和第二十八晶体管M28为另一组，上述两组晶体管分别与 第一下拉节点QB_A和第二下拉节点QB_B连接，以分别对第一下拉节点QB_A和第二下拉节点QB_B进行下拉。例如，第十六晶体管M16和第二十八晶体管M28串联在第二下拉节点QB_B和第三电压端VGL1之间，第十六晶体管M16的栅极和第一时钟信号端CLKA连接，第二十八晶体管M28的栅极和第一节点N1连接。
当第一时钟信号和第一节点N1均为有效电平(例如，高电平)时，第十六晶体管M16和第二十八晶体管M28均导通，从而将第二下拉节点QB_B下拉为低电平。第二控制电路800对第一下拉节点QB_A的下拉控制方式与第二下拉节点QB_B类似，此处不再赘述。例如，在多个移位寄存器单元10级联的情形下，上述方式可以使进行输出的移位寄存器单元10的第一下拉节点QB_A和第二下拉节点QB_B被拉低，而其他级移位寄存器单元10的第一下拉节点QB_A和第二下拉节点QB_B不会被拉低，以避免其他级移位寄存器单元10的移位信号输出端CR、第一像素扫描信号输出端Out1和第二像素扫描信号输出端Out2处于浮置状态，从而减小输出信号的噪声。
该移位寄存器单元10包括2个像素扫描信号输出端，即第一像素扫描信号输出端Out1和第二像素扫描信号输出端Out2。第一像素扫描信号输出端Out1的连接方式与前述的像素扫描信号输出端Out类似。第二像素扫描信号输出端Out2与第二十晶体管M20的第二极连接，第二十晶体管M20的栅极与上拉节点Q连接，第二十晶体管M20的第一极与第三时钟信号端CLKC连接。第三电容C3连接在第二十晶体管M20的栅极与第二极之间。
当上拉节点Q为高电平时，第七晶体管M7和第二十晶体管M20导通，第二时钟信号端CLKB的第二时钟信号输出到第一像素扫描信号输出端Out1，第三时钟信号端CLKC的第三时钟信号输出到第二像素扫描信号输出端Out2。例如，在一些示例中，第二时钟信号端CLKB和第三时钟信号端CLKC提供的时钟信号相同，因此第一像素扫描信号输出端Out1和第二像素扫描信号输出端Out2输出的信号相同，以进一步提高驱动能力。例如，在另一些示例中，第二时钟信号端CLKB和第三时钟信号端CLKC提供的信号不同，从而使得第一像素扫描信号输出端Out1和第二像素扫描信号输出端Out2输出的信号不同，以便为像素单元提供多种驱动信号。
相应地，为了对第二像素扫描信号输出端Out2进行下拉降噪，需要设置2个晶体管M21_a和M21_b，且其栅极分别与第一下拉节点QB_A和第二下 拉节点QB_B连接。同样地，晶体管M9和M18的栅极分别与第一下拉节点QB_A和第二下拉节点QB_B连接，以对移位信号输出端CR进行下拉降噪。晶体管M10和M19的栅极分别与第一下拉节点QB_A和第二下拉节点QB_B连接，以对第一像素扫描信号输出端Out1进行下拉降噪。相应地，晶体管M4_a和M4_b的栅极分别与第一下拉节点QB_A和第二下拉节点QB_B连接，以对第二节点N2进行下拉控制。
图9A-9C为本公开一些实施例提供的一种移位寄存器单元的消隐输入电路的具体实现示例的电路图。参考图9A，该消隐输入电路100具有防漏电电路，以防止第一节点N1漏电，防漏电电路的工作原理与前述的防漏电电路类似，此处不再赘述。与图7所示的实施例不同，在该示例中，第四晶体管M4的栅极配置为和第四时钟信号端CLKD连接以接收第四时钟信号，并在第四时钟信号的控制下对第二节点N2进行下拉。需要说明的是，本公开的实施例不限于此，第四晶体管M4的栅极可以连接到下拉节点QB、第四时钟信号端CLKD或其他适用的信号端，只要能控制第四晶体管M4导通并对第二节点N2进行下拉即可。参考图9B，与图9A所示的消隐输入电路100相比，该示例中的第四晶体管M4的栅极的控制方式不同。通过晶体管M4_1和M4_2构成的电路结构，当第四时钟信号端CLKD提供高电平时，第四晶体管M4的栅极为高电平，第四晶体管M4导通，从而对第二节点N2进行下拉。参考图9C，与图9A所示的消隐输入电路100相比，该示例中的消隐输入电路100还包括针对第三晶体管M3的防漏电电路，以防止上拉节点Q漏电，防漏电电路的工作原理与前述的防漏电电路类似，此处不再赘述。并且，在该示例中，第三晶体管M3的第一极与第五时钟信号端CLKE连接，以接收第五时钟信号作为消隐上拉信号。
图10为本公开一些实施例提供的一种移位寄存器单元的显示输入电路的具体实现示例的电路图。参考图10(1)，在一些示例中，第五晶体管M5的栅极与第一极连接，且配置为和显示输入信号端STU2连接。参考图10(2)，与图10(1)所示的连接方式相比，该示例增加了防漏电电路，以防止上拉节点Q漏电。参考图10(3)，与图6所示的移位寄存器单元10中的显示输入电路200相比，在第五晶体管M5和上拉节点Q之间串联了二极管连接方式的晶体管M5_b，也可以起到防漏电的作用。
图11为本公开一些实施例提供的一种移位寄存器单元的第二控制电路的 具体实现示例的电路图。参考图11(1)，与图8所示的移位寄存器单元10中的第二控制电路800相比，在该示例中，省略了图8中的第二十六晶体管M26和第二十八晶体管M28。该示例的第二控制电路800可以实现相应功能，且简化了电路结构。参考图11(2)，与图11(1)所示的电路相比，在该示例中，省略了晶体管M25和M16，因此该示例中的第二控制电路800仅在显示时段响应于显示输入信号端STU2提供的显示输入信号的对第一下拉节点QB_A和第二下拉节点QB_B进行下拉，而在消隐时段不进行下拉，从而在简化电路结构的同时不影响显示效果。
需要说明的是，本公开的实施例中，第一电容C1、第二电容C2和第三电容C3可以是通过工艺制程制作的电容器件，例如通过制作专门的电容电极来实现电容器件，该电容的各个电极可以通过金属层、半导体层(例如掺杂多晶硅)等实现，并且，第一电容C1、第二电容C2和第三电容C3也可以是各个器件之间的寄生电容，可以通过晶体管本身与其他器件、线路来实现。第一电容C1、第二电容C2和第三电容C3的连接方式不局限于上面描述的方式，也可以为其他适用的连接方式，只要能存储相应的电平即可。
需要注意的是，在本公开的各个实施例的说明中，第一控制节点、第二控制节点、第一节点N1、第二节点N2、上拉节点Q、下拉节点QB、第一下拉节点QB_A、第二下拉节点QB_B和防漏电节点OFF表示电路图中相关电连接的汇合点，也可以是电路图中相关电连接汇合的一条导线，或多条互相连接导线，本公开的实施例对此不作限制。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管、场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
另外，本公开的实施例中的晶体管均以N型晶体管为例进行说明，此时，晶体管的第一极是漏极，第二极是源极。需要说明的是，本公开包括但不限于此。例如，本公开的实施例提供的移位寄存器单元10中的一个或多个晶体管也可以采用P型晶体管，此时，晶体管第一极是源极，第二极是漏极，只需将选定类型的晶体管的各极参照本公开的实施例中的相应晶体管的各极相 应连接，并且使相应的电压端提供对应的高电压或低电压即可。当采用N型晶体管时，可以采用氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)作为薄膜晶体管的有源层，相对于采用低温多晶硅(Low Temperature Poly Silicon，LTPS)或非晶硅(例如氢化非晶硅)作为薄膜晶体管的有源层，可以有效减小晶体管的尺寸以及防止漏电流。
在本公开的各个实施例的说明中，例如，当各个电路实现为N型晶体管时，术语“上拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如导通)；“下拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如截止)。又例如，当各个电路实现为P型晶体管时，术语“上拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如导通)；“下拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如截止)。
图12为本公开一些实施例提供的一种移位寄存器单元的信号时序图。下面结合图12所示的信号时序图，对图6所示的移位寄存器单元10的工作原理进行说明，并且这里以各个晶体管为N型晶体管为例进行说明，但是本公开的实施例不限于此。
在图12中以及下面的描述中，1F表示栅极驱动电路显示一帧画面过程中移位寄存器单元10工作的时序，DS表示一帧的显示时段，BL表示一帧的消隐时段。STU1、STU2、TRST、OE、VDD_A、VDD_B、CLKA、CLKB、Out、CR等既用于表示相应的信号端，也用于表示相应的信号。以下各实施例与此相同，不再赘述。
在初始阶段0(图中未示出)，随机信号OE和消隐复位信号TRST均为高电平。第一晶体管M1导通，此时消隐输入信号STU1为低电平，从而对第一节点N1进行复位。第十四晶体管M14导通，从而对上拉节点Q进行复位。例如，当多个移位寄存器单元10级联时，该阶段可以对多个移位寄存器单元10的第一节点N1和上拉节点Q进行全局复位。
在显示时段DS，在第一阶段1，显示输入信号STU2和第六电压VDD_B为高电平。第五晶体管M5导通，将上拉节点Q上拉为高电平。第六晶体管 M6和第七晶体管M7在上拉节点Q的控制下导通，将第二时钟信号CLKB输出至移位信号输出端CR和像素扫描信号输出端Out。由于此时第二时钟信号CLKB为低电平，因此移位信号输出端CR和像素扫描信号输出端Out均输出低电平。第十三晶体管M13导通，第十二晶体管M12导通，由于第十三晶体管M13和第十二晶体管M12的分压作用，使下拉节点QB为低电平。
在第二阶段2，随机信号OE和消隐输入信号STU1为高电平，第一晶体管M1导通，将第一节点N1上拉至高电平，并被第一电容C1存储。第二晶体管M2在第一节点N1的控制下导通，将第一时钟信号CLKA写入第二节点N2。由于此时第一时钟信号CLKA为低电平，因此第二节点N2也为低电平，从而使第三晶体管M3截止。在该阶段中，第一电容C1存储了第一节点N1的高电平信号并保持到一帧的显示时段结束，以用于在消隐时段使用。上拉节点Q保持为高电平，第六晶体管M6和第七晶体管M7保持导通，并保持输出低电平信号。
在第三阶段3，第二时钟信号CLKB由低电平变为高电平，由于第二电容C2的自举作用，上拉节点Q的电位进一步升高，第六晶体管M6和第七晶体管M7充分导通，第二时钟信号CLKB的高电平输出至移位信号输出端CR和像素扫描信号输出端Out。
在第四阶段4，第二时钟信号CLKB变为低电平，由于第二电容C2的自举作用，上拉节点Q的电位有所降低但仍然保持高电平，第六晶体管M6和第七晶体管M7保持导通，第二时钟信号CLKB的低电平输出至移位信号输出端CR和像素扫描信号输出端Out以完成输出信号的复位。
在第五阶段5，显示复位信号STD(图中未示出)为高电平，第十五晶体管M15导通，从而对上拉节点Q进行复位，使上拉节点Q变为低电平。第六晶体管M6和第七晶体管M7截止。第十三晶体管M13截止，下拉节点QB被导通的第十二晶体管M12上拉为高电平。第八晶体管M8在下拉节点QB的高电平的作用下导通，以进一步对上拉节点Q降噪。第九晶体管M9和第十晶体管M10也在下拉节点QB的高电平的作用下导通，从而对移位信号输出端CR和像素扫描信号输出端Out降噪。第四晶体管M4在下拉节点QB的高电平的作用下导通，从而对第二节点N2进行下拉，以确保第三晶体管M3截止。在显示时段DS的后续阶段中，下拉节点QB保持为高电平，第四晶体管M4保持导通，从而使第三晶体管M3保持截止，以避免通过第三晶体管 M3向上拉节点Q写入噪声。
在上述各个阶段，第三晶体管M3由于第二节点N2一直保持低电平而处于截止状态，从而隔离了第一电压端VDD和上拉节点Q，以避免第一电压端VDD的第一电压影响上拉节点Q的电平，进而影响显示时段的输出信号。上拉节点Q的电平呈塔状波形，移位信号输出端CR的输出信号的上拉和复位都通过第六晶体管M6实现，像素扫描信号输出端Out的输出信号的上拉和复位都通过第七晶体管M7实现，第九晶体管M9和第十晶体管M10对移位信号输出端CR和像素扫描信号输出端Out的输出信号起辅助下拉的作用，因此可以减小第九晶体管M9和第十晶体管M10的尺寸，有利于减小电路版图的面积。
在消隐时段BL，在第六阶段6，第一节点N1保持在显示时段写入的高电平，第二晶体管M2保持导通。第一时钟信号CLKA变为高电平，由于第一电容C1的自举作用，第一节点N1的电平进一步升高至第一电平，例如，第一电平高于第一电压VDD。因此，在显示时段中对第一节点N1充电时由于第一晶体管M1而损失的阈值电压被补偿。第一节点N1的高电平使得第二晶体管M2充分导通，第一时钟信号CLKA的高电平充分写入第二节点N2，例如，使得第二节点N2的电平等于第一时钟信号CLKA的高电平。第三晶体管M3在第二节点N2的高电平的控制下导通，将上拉节点Q上拉为高电平。第六晶体管M6和第七晶体管M7导通，将第二时钟信号CLKB输出至移位信号输出端CR和像素扫描信号输出端Out。此时第二时钟信号CLKB为低电平，因此移位信号输出端CR和像素扫描信号输出端Out均输出低电平。第十三晶体管M13导通，第十二晶体管M12导通，由于第十三晶体管M13和第十二晶体管M12的分压作用，使下拉节点QB为低电平。
在第七阶段7，第一时钟信号CLKA变为低电平，第三晶体管M3截止，使得上拉节点Q不会通过第三晶体管M3漏电。第六晶体管M6和第七晶体管M7保持导通。第二时钟信号CLKB变为高电平，由于第二电容C2的自举作用，上拉节点Q的电位进一步升高，第六晶体管M6和第七晶体管M7充分导通，第二时钟信号CLKB的高电平输出至移位信号输出端CR和像素扫描信号输出端Out。
在第八阶段8，第二时钟信号CLKB变为低电平，由于第二电容C2的自举作用，上拉节点Q的电位有所降低但仍然保持高电平，第六晶体管M6和 第七晶体管M7保持导通，第二时钟信号CLKB的低电平输出至移位信号输出端CR和像素扫描信号输出端Out以完成输出信号的复位。
在第九阶段9(消隐时段BL的末段)，消隐复位信号TRST和随机信号OE为高电平，第十四晶体管M14和第一晶体管M1导通，从而对上拉节点Q和第一节点N1复位。这样可以使第一节点N1保持为高电平的时间较短，以降低与第一节点N1连接的晶体管阈值电压漂移(例如正漂)的风险，有助于提高该电路的信赖性。
在该实施例中，消隐输入电路100可以对第一节点N1的电平进行补偿，以补偿在对第一节点N1充电过程中产生的阈值电压损失，并对第二节点N2的电平进行耦合控制，使第二节点N2的电平达到预定值(例如，等于或略小于第一时钟信号CLKA的高电平)，从而在第二节点N2的电平的控制下使上拉节点Q的电平也达到预定值(例如，等于或略小于第一电压VDD)，以避免阈值电压的损失影响上拉节点Q的电平，进而提高消隐输出信号的准确性。通过软件仿真可知，将各个晶体管的阈值电压设置为+10V，将第一时钟信号CLKA的高电平设置为+24V，则图6所示的移位寄存器单元10的第二节点N2的电平可以达到+24V，即等于第一时钟信号CLKA的高电平。第一节点N1的电平在第一电容C1的自举作用下可以升高至+35V以上。
图13为本公开一些实施例提供的另一种移位寄存器单元的信号时序图。例如，在该实施例中，移位寄存器单元10的消隐输入电路100实现为图9A所示的电路结构，移位寄存器单元10的其他结构与图6所示的移位寄存器单元10基本相同。第四晶体管M4的栅极与第四时钟信号端CLKD连接以接收第四时钟信号。例如，在图13中以及下文的说明中，CLKD既用于表示第四时钟信号端，也用于表示第四时钟信号。如图13所示，在显示时段DS，第四时钟信号CLKD一直保持为高电平，第四晶体管M4保持导通，从而对第二节点N2持续下拉，以确保第三晶体管M3在显示时段处于截止状态。在消隐时段，第四时钟信号CLKD变为低电平，第四晶体管M4截止。因此，第二节点N2可以在第一时钟信号CLKA的作用下被拉高，使第三晶体管M3导通，从而将上拉节点Q上拉为高电平。该移位寄存器单元10在图13所示的时序下的工作原理与上文描述的工作原理基本相同，此处不再赘述。
本公开至少一实施例还提供一种栅极驱动电路。该栅极驱动电路包括本公开任一实施例所述的移位寄存器单元。该栅极驱动电路的电路结构简单， 可以改善消隐时段中消隐输入电路对第一控制节点(例如上拉节点)进行电平控制(例如上拉)时的阈值电压损失，避免影响第一控制节点的电位，从而提高消隐输出信号的准确性。
图14为本公开一些实施例提供的一种栅极驱动电路的示意框图。参考图14，该栅极驱动电路20包括多个级联的移位寄存器单元(A1、A2、A3、A4等)。多个移位寄存器单元的数量不受限制，可以根据实际需求而定。例如，移位寄存器单元采用本公开任一实施例所述的移位寄存器单元10。例如，在栅极驱动电路20中，可以部分或全部移位寄存器单元采用本公开任一实施例所述的移位寄存器单元10。例如，该栅极驱动电路20可以采用与薄膜晶体管同样制程的工艺直接集成在显示装置的阵列基板上以构成GOA(Gate Driver On Array)，以实现逐行扫描驱动功能。
例如，在一些示例中，每四级移位寄存器单元共用同一充电子电路110、同一补偿子电路120和同一控制子电路140，以简化电路结构，有利于实现窄边框。例如，当移位寄存器单元实现为图8所示的电路时，每四级移位寄存器单元共用晶体管M1、M1_b、M1_c、M2、M4_a、M4_b和第一电容C1，而每一级移位寄存器单元各自具有第三晶体管M3(隔离子电路130)，且第二节点N2连接到该四级移位寄存器单元中的每一个第三晶体管M3的栅极。在消隐时段，当第二节点N2为高电平时，该四级移位寄存器单元同时输出消隐输出信号，即同时进行补偿检测。
例如，参考图14和图15A，第一级移位寄存器单元A1包括晶体管M1、M1_b、M1_c、M2、M4_a、M4_b和第一电容C1，以及还包括第三晶体管M3<n>。第二至第四级移位寄存器单元A2-A4分别包括第三晶体管M3<n+1>、M3<n+2>和M3<n+3>，且栅极均连接到第一级移位寄存器单元A1中的第二节点N2。当第二节点N2为高电平时，上述4个移位寄存器单元A1-A4中的第三晶体管M3<n>、M3<n+1>、M3<n+2>和M3<n+3>均导通，从而将上述4个移位寄存器单元A1-A4中的上拉节点Q<n>、Q<n+1>、Q<n+2>和Q<n+3>均上拉至高电平，以进一步输出消隐输出信号。
图15B为共用情形下的另一种实现示例的电路图，充电子电路110、补偿子电路120和控制子电路140实现为图9A所示的电路结构，其他部分与图15A所示的电路基本相同，此处不再赘述。图15C为共用情形下的再一种实现示例的电路图，与图15B的示例相比，各级移位寄存器单元的隔离子电路 130增加了防漏电电路，以防止上拉节点Q<n>、Q<n+1>、Q<n+2>和Q<n+3>漏电。并且，各级移位寄存器单元的第三晶体管M3<n>、M3<n+1>、M3<n+2>和M3<n+3>的第一极均与第五时钟信号端CLKE连接，以接收第五时钟信号作为消隐上拉信号。
需要说明的是，本公开的实施例中，共用同一充电子电路110、同一补偿子电路120和同一控制子电路140的移位寄存器单元的数量不受限制，可以为任意个数，上文以4个为例进行说明，但这并不构成对本公开的限制。并且，共用上述子电路的多个移位寄存器单元可以是相邻的，也可以是不相邻的，本公开的实施例对此不作限制。
在图14所示的栅极驱动电路20中，每四级移位寄存器单元共用同一充电子电路110、同一补偿子电路120和同一控制子电路140，且各个共用的子电路设置在第4n-3级移位寄存器单元中，n为大于0的整数。各个移位寄存器单元采用如图8所示的电路结构。该栅极驱动电路20的具体级联关系说明如下。
例如，每个移位寄存器单元具有消隐输入信号端STU1、显示输入信号端STU2、显示复位信号端STD、移位信号输出端CR、第一像素扫描信号输出端Out1、第二像素扫描信号输出端Out2、消隐复位信号端TRST、第二时钟信号端CLKB和第三时钟信号端CLKC等。第4n-3级移位寄存器单元还具有随机信号端OE和第一时钟信号端CLKA。例如，第4n-3级移位寄存器单元的随机信号端OE和随机信号线OE_1连接，第4n-3级移位寄存器单元的第一时钟信号端CLKA和第一时钟线CLKA_1连接。每一级移位寄存器单元的消隐复位信号端TRST和消隐复位线TRST_1连接。
除第一级以外，第n+1级移位寄存器单元的消隐输入信号端STU1和第n级移位寄存器单元的移位信号输出端CR连接。除第一级和第二级以外，第n+2级移位寄存器单元的显示输入信号端STU2和第n级移位寄存器单元的移位信号输出端CR连接。除最后三级以外，第n级移位寄存器单元的显示复位信号端STD和第n+3级移位寄存器单元的移位信号输出端CR连接。例如，第一级移位寄存器单元A1的消隐输入信号端STU1和显示输入信号端STU2与触发信号线STU连接，第二级移位寄存器单元A2的显示输入信号端STU2也与触发信号线STU连接。最后三级移位寄存器单元的显示复位信号端STD与另行提供的复位信号线连接。每个移位寄存器单元的第一像素扫描信号输 出端Out1和第二像素扫描信号输出端Out2与对应行的像素单元连接，以向该行像素单元输出驱动信号。
例如，该栅极驱动电路20还包括第一子时钟信号线CLKB_1、第二子时钟信号线CLKB_2、第三子时钟信号线CLKB_3和第四子时钟信号线CLKB_4，各级移位寄存器单元与上述各子时钟信号线的连接方式说明如下并以此类推。第4n-3级移位寄存器单元的第二时钟信号端CLKB和第一子时钟信号线CLKB_1连接，第4n-2级移位寄存器单元的第二时钟信号端CLKB和第二子时钟信号线CLKB_2连接，第4n-1级移位寄存器单元的第二时钟信号端CLKB和第三子时钟信号线CLKB_3连接，第4n级移位寄存器单元的第二时钟信号端CLKB和第四子时钟信号线CLKB_4连接。
例如，该栅极驱动电路20还包括第五子时钟信号线CLKC_1、第六子时钟信号线CLKC_2、第七子时钟信号线CLKC_3和第八子时钟信号线CLKC_4，各级移位寄存器单元与上述各子时钟信号线的连接方式说明如下并以此类推。第4n-3级移位寄存器单元的第三时钟信号端CLKC和第五子时钟信号线CLKC_1连接，第4n-2级移位寄存器单元的第三时钟信号端CLKC和第六子时钟信号线CLKC_2连接，第4n-1级移位寄存器单元的第三时钟信号端CLKC和第七子时钟信号线CLKC_3连接，第4n级移位寄存器单元的第三时钟信号端CLKC和第八子时钟信号线CLKC_4连接。
例如，该栅极驱动电路20还可以包括时序控制器T-CON，时序控制器T-CON例如配置为向各级移位寄存器单元提供上述各个时钟信号，时序控制器T-CON还可以配置为提供触发信号和复位信号。需要说明的是，时序控制器T-CON提供的多个时钟信号彼此之间的相位关系可以根据实际需求而定。在不同的示例中，根据不同的配置，还可以向栅极驱动电路20提供更多的时钟信号。例如，该栅极驱动电路20还包括多条电压线，以向各级移位寄存器单元提供多个电压信号。
例如，当采用该栅极驱动电路20驱动一显示面板时，可以将该栅极驱动电路20设置于显示面板的一侧。例如，该显示面板包括多行栅线，栅极驱动电路20中的各级移位寄存器单元的第一像素扫描信号输出端Out1和第二像素扫描信号输出端Out2可以配置为依序和多行栅线连接，以用于输出驱动信号。当然，还可以分别在显示面板的两侧设置该栅极驱动电路20，以实现双边驱动，本公开的实施例对栅极驱动电路20的设置方式不作限制。
图16为本公开一些实施例提供的一种栅极驱动电路的信号时序图，该信号时序图为图14中所示的栅极驱动电路20的时序。栅极驱动电路20的工作原理可参考本公开的实施例中对于移位寄存器单元10的相应描述，这里不再赘述。
参考图16，第三、第四级移位寄存器单元A3、A4的第二像素扫描信号输出端Out2的输出信号Out2<3>和Out2<4>在一帧的显示时段内的波形与第一像素扫描信号输出端Out1的输出信号Out1<3>和Out1<4>的波形相同，在各帧的消隐时段内依次移位且与第一像素扫描信号输出端Out1的输出信号Out1<3>和Out1<4>的波形不同，以满足多种应用需求。
例如，第一子时钟信号CLKB_1、第二子时钟信号CLKB_2、第三子时钟信号CLKB_3和第四子时钟信号CLKB_4在一帧的显示时段内的波形依次重叠有效脉宽的50％，在各帧的消隐时段内的波形依次移位。第三、第四级移位寄存器单元A3、A4的第一像素扫描信号输出端Out1的输出信号Out1<3>和Out1<4>在一帧的显示时段内的波形依次重叠有效脉宽的50％，在各帧的消隐时段内的波形依次移位。该栅极驱动电路20在显示时段内的输出信号在时序上有重叠，因此可以实现预充电功能，可缩短像素电路的充电时间，有利于实现高刷新率。第五至第八子时钟信号CLKC_1-CLKC_4在一帧的显示时段内的波形依次重叠有效脉宽的50％，在各帧的消隐时段内的波形依次移位，因此可以使第二像素扫描信号输出端Out2在显示时段的输出信号在时序上也具有重叠部分。
需要说明的是，本公开的实施例中，栅极驱动电路20不局限于图14中描述的级联方式，可以为任意适用的级联方式。当级联方式或时钟信号改变时，各级移位寄存器单元的第一像素扫描信号输出端Out1或第二像素扫描信号输出端Out2的输出信号在显示时段内的波形重叠部分也会相应变化，例如重叠33％或0％(即不重叠)，以满足多种应用需求。
本公开至少一实施例还提供一种显示装置。该显示装置包括本公开任一实施例所述的移位寄存器单元或本公开任一实施例所述的栅极驱动电路。该显示装置中的移位寄存器单元或栅极驱动电路的电路结构简单，可以改善消隐时段中消隐输入电路对第一控制节点(例如上拉节点)进行电平控制(例如上拉)时的阈值电压损失，避免影响第一控制节点的电位，从而提高消隐输出信号的准确性。
图17为本公开一些实施例提供的一种显示装置的示意框图。参考图17，显示装置30包括栅极驱动电路20，栅极驱动电路20为本公开任一实施例所述的栅极驱动电路。例如，显示装置30可以为OLED显示面板、OLED电视、OLED显示器、液晶显示面板、液晶电视等，也可以为电子书、手机、平板电脑、笔记本电脑、数码相框、导航仪等任意具有显示功能的产品或部件，本公开的实施例对此不作限制。显示装置30的技术效果可以参考上述实施例中关于移位寄存器单元10和栅极驱动电路20的相应描述，这里不再赘述。
例如，在一些示例中，显示装置30包括显示面板3000、栅极驱动器3010、定时控制器3020和数据驱动器3030。显示面板3000包括根据多条扫描线GL和多条数据线DL交叉限定的多个像素单元P；栅极驱动器3010用于驱动多条扫描线GL；数据驱动器3030用于驱动多条数据线DL；定时控制器3020用于处理从显示装置30外部输入的图像数据RGB，向数据驱动器3030提供处理的图像数据RGB以及向栅极驱动器3010和数据驱动器3030输出扫描控制信号GCS和数据控制信号DCS，以对栅极驱动器3010和数据驱动器3030进行控制。
例如，栅极驱动器3010包括上述任一实施例中提供的栅极驱动电路20。栅极驱动电路20中的多个移位寄存器单元10的像素扫描信号输出端Out与多条扫描线GL对应连接。多条扫描线GL与排列为多行的像素单元P对应连接。在显示时段内，栅极驱动电路20中的各级移位寄存器单元10的像素扫描信号输出端Out依序输出信号到多条扫描线GL，以使显示面板3000中的多行像素单元P实现逐行扫描；在消隐时段内，栅极驱动电路20中的各级移位寄存器单元10的像素扫描信号输出端Out随机输出信号到一条或多条扫描线GL，以使显示面板3000中的一行或多行像素单元P实现补偿检测。例如，栅极驱动器3010可以实现为半导体芯片，也可以集成在显示面板3000中以构成GOA电路。
例如，数据驱动器3030使用参考伽玛电压根据源自定时控制器3020的多个数据控制信号DCS将从定时控制器3020输入的数字图像数据RGB转换成数据信号。数据驱动器3030向多条数据线DL提供转换的数据信号。例如，数据驱动器3030可以实现为半导体芯片。
例如，定时控制器3020对外部输入的图像数据RGB进行处理以匹配显示面板3000的大小和分辨率，然后向数据驱动器3030提供处理后的图像数 据。定时控制器3020使用从显示装置30外部输入的同步信号(例如点时钟DCLK、数据使能信号DE、水平同步信号Hsync以及垂直同步信号Vsync)产生多条扫描控制信号GCS和多条数据控制信号DCS。定时控制器3020分别向栅极驱动器3010和数据驱动器3030提供产生的扫描控制信号GCS和数据控制信号DCS，以用于栅极驱动器3010和数据驱动器3030的控制。
该显示装置30还可以包括其他部件，例如信号解码电路、电压转换电路等，这些部件例如可以采用已有的常规部件，这里不再详述。
本公开至少一实施例还提供一种移位寄存器单元的驱动方法，可以用于驱动本公开任一实施例提供的移位寄存器单元，多个该移位寄存器单元可以级联构成栅极驱动电路，该栅极驱动电路用于驱动显示面板显示至少一帧画面。通过该驱动方法，可以改善消隐时段中消隐输入电路对第一控制节点(例如上拉节点)进行电平控制(例如上拉)时的阈值电压损失，避免影响第一控制节点的电位，从而提高消隐输出信号的准确性。
例如，在一些示例中，该移位寄存器单元10的驱动方法包括用于处理一帧图像的显示时段和消隐时段，显示时段包括第一输入阶段和第一输出阶段，消隐时段包括第二输入阶段和第二输出阶段。在上述各个阶段，该移位寄存器单元10的驱动方法包括如下操作：
显示时段包括：
第一输入阶段，显示输入电路200响应于显示输入信号将显示上拉信号输入到第一控制节点(例如上拉节点Q)；
第一输出阶段，输出电路300在第一控制节点(例如上拉节点Q)的电平的控制下，将复合输出信号输出至输出端OP；
消隐时段包括：
第二输入阶段，消隐输入电路100根据消隐输入信号和消隐控制信号将消隐上拉信号输入到第一控制节点(例如上拉节点Q)，并对消隐输入电路100自身进行补偿；
第二输出阶段，输出电路300在第一控制节点(例如上拉节点Q)的电平的控制下，将复合输出信号输出至输出端OP。
需要说明的是，关于该驱动方法的详细描述以及技术效果可以参考本公开的实施例中对于移位寄存器单元10和栅极驱动电路20的相应描述，这里不再赘述。
有以下几点需要说明：
(1)本公开实施例附图只涉及到本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (22)

  1. 一种移位寄存器单元，包括消隐输入电路、显示输入电路和输出电路；其中，
    所述消隐输入电路配置为根据消隐输入信号和消隐控制信号在消隐时段将消隐上拉信号输入到第一控制节点，并对所述消隐输入电路自身进行补偿；
    所述显示输入电路配置为响应于显示输入信号在显示时段将显示上拉信号输入到所述第一控制节点；
    所述输出电路配置为在所述第一控制节点的电平的控制下，将复合输出信号输出至输出端。
  2. 根据权利要求1所述的移位寄存器单元，还包括降噪电路和第一控制电路；其中，
    所述降噪电路配置为在第二控制节点的电平的控制下，对所述第一控制节点和所述输出端进行降噪；
    所述第一控制电路配置为在所述第一控制节点的电平的控制下，对所述第二控制节点的电平进行控制。
  3. 根据权利要求2所述的移位寄存器单元，其中，所述消隐输入电路包括：
    充电子电路，配置为响应于所述消隐控制信号将所述消隐输入信号输入到第一节点；
    补偿子电路，配置为存储所述充电子电路输入的所述消隐输入信号，并响应于第一时钟信号对所述第一节点的电平进行补偿，以及对第二节点的电平进行耦合控制；
    隔离子电路，配置为在所述第二节点的电平的控制下，将所述消隐上拉信号输入到所述第一控制节点。
  4. 根据权利要求3所述的移位寄存器单元，其中，所述消隐输入电路还包括控制子电路，
    所述控制子电路配置为在所述第二控制节点的电平的控制下，对所述第二节点的电平进行控制。
  5. 根据权利要求4所述的移位寄存器单元，其中，
    所述充电子电路包括第一晶体管，所述第一晶体管的栅极配置为和随机 信号端连接以接收随机信号作为所述消隐控制信号，所述第一晶体管的第一极配置为和消隐输入信号端连接以接收所述消隐输入信号，所述第一晶体管的第二极配置为和所述第一节点连接；
    所述补偿子电路包括第二晶体管和第一电容，所述第二晶体管的栅极配置为和所述第一节点连接，所述第二晶体管的第一极配置为和第一时钟信号端连接以接收所述第一时钟信号，所述第二晶体管的第二极配置为和所述第二节点连接，所述第一电容的第一极配置为和所述第一节点连接，所述第一电容的第二极配置为和所述第二节点连接；
    所述隔离子电路包括第三晶体管，所述第三晶体管的栅极配置为和所述第二节点连接，所述第三晶体管的第一极配置为和第一电压端连接以接收第一电压作为所述消隐上拉信号，所述第三晶体管的第二极配置为和所述第一控制节点连接；
    所述控制子电路包括第四晶体管，所述第四晶体管的栅极配置为和所述第二控制节点连接，所述第四晶体管的第一极配置为和所述第二节点连接，所述第四晶体管的第二极配置为和第二电压端连接以接收第二电压。
  6. 根据权利要求1-5任一所述的移位寄存器单元，其中，所述显示输入电路包括第五晶体管；
    所述第五晶体管的栅极配置为和显示输入信号端连接以接收所述显示输入信号，所述第五晶体管的第一极配置为和第一电压端连接以接收第一电压作为所述显示上拉信号，所述第五晶体管的第二极配置为和所述第一控制节点连接。
  7. 根据权利要求2-5任一所述的移位寄存器单元，其中，所述输出电路包括至少一个移位信号输出端和至少一个像素扫描信号输出端。
  8. 根据权利要求7所述的移位寄存器单元，其中，所述输出电路包括第六晶体管、第七晶体管和第二电容；
    所述第六晶体管的栅极配置为和所述第一控制节点连接，所述第六晶体管的第一极配置为和第二时钟信号端连接以接收第二时钟信号作为所述复合输出信号，所述第六晶体管的第二极配置为和所述移位信号输出端连接；
    所述第七晶体管的栅极配置为和所述第一控制节点连接，所述第七晶体管的第一极配置为和所述第二时钟信号端连接以接收所述第二时钟信号作为所述复合输出信号，所述第七晶体管的第二极配置为和所述像素扫描信号输 出端连接；
    所述第二电容的第一极配置为和所述第一控制节点连接，所述第二电容的第二极配置为和所述第六晶体管的第二极或所述第七晶体管的第二极连接。
  9. 根据权利要求7所述的移位寄存器单元，其中，所述降噪电路包括第八晶体管、第九晶体管和第十晶体管；
    所述第八晶体管的栅极配置为和所述第二控制节点连接，所述第八晶体管的第一极配置为和所述第一控制节点连接，所述第八晶体管的第二极配置为和第三电压端连接以接收第三电压；
    所述第九晶体管的栅极配置为和所述第二控制节点连接，所述第九晶体管的第一极配置为和所述移位信号输出端连接，所述第九晶体管的第二极配置为和所述第三电压端连接以接收所述第三电压；
    所述第十晶体管的栅极配置为和所述第二控制节点连接，所述第十晶体管的第一极配置为和所述像素扫描信号输出端连接，所述第十晶体管的第二极配置为和第四电压端连接以接收第四电压。
  10. 根据权利要求2-5任一所述的移位寄存器单元，其中，所述第一控制电路包括第十一晶体管、第十二晶体管和第十三晶体管；
    所述第十一晶体管的栅极和第一极连接且配置为和第五电压端连接以接收第五电压，所述第十一晶体管的第二极配置为和所述第二控制节点连接；
    所述第十二晶体管的栅极和第一极连接且配置为和第六电压端连接以接收第六电压，所述第十二晶体管的第二极配置为和所述第二控制节点连接；
    所述第十三晶体管的栅极配置为和所述第一控制节点连接，所述第十三晶体管的第一极配置为和所述第二控制节点连接，所述第十三晶体管的第二极配置为和第三电压端连接以接收第三电压。
  11. 根据权利要求1-5任一所述的移位寄存器单元，还包括消隐复位电路，
    其中，所述消隐复位电路配置为响应于消隐复位信号对所述第一控制节点进行复位。
  12. 根据权利要求11所述的移位寄存器单元，其中，所述消隐复位电路包括第十四晶体管；
    所述第十四晶体管的栅极配置为和消隐复位信号端连接以接收所述消隐复位信号，所述第十四晶体管的第一极配置为和所述第一控制节点连接，所 述第十四晶体管的第二极配置为和第三电压端连接以接收第三电压。
  13. 根据权利要求1-5任一所述的移位寄存器单元，还包括显示复位电路，
    其中，所述显示复位电路配置为响应于显示复位信号对所述第一控制节点进行复位。
  14. 根据权利要求13所述的移位寄存器单元，其中，所述显示复位电路包括第十五晶体管；
    所述第十五晶体管的栅极配置为和显示复位信号端连接以接收所述显示复位信号，所述第十五晶体管的第一极配置为和所述第一控制节点连接，所述第十五晶体管的第二极配置为和第三电压端连接以接收第三电压。
  15. 根据权利要求2-5任一所述的移位寄存器单元，还包括第二控制电路，
    其中，所述第二控制电路配置为响应于第一时钟信号或所述显示输入信号对所述第二控制节点的电平进行控制。
  16. 根据权利要求15所述的移位寄存器单元，其中，所述第二控制电路包括第十六晶体管和第十七晶体管；
    所述第十六晶体管的栅极配置为和第一时钟信号端连接以接收所述第一时钟信号，所述第十六晶体管的第一极配置为和所述第二控制节点连接，所述第十六晶体管的第二极配置为接收第三电压端的第三电压；
    所述第十七晶体管的栅极配置为和显示输入信号端连接以接收所述显示输入信号，所述第十七晶体管的第一极配置为和所述第二控制节点连接，所述第十七晶体管的第二极配置为和所述第三电压端连接以接收所述第三电压。
  17. 一种栅极驱动电路，包括如权利要求1-16任一所述的移位寄存器单元。
  18. 根据权利要求17所述的栅极驱动电路，其中，每四级移位寄存器单元共用同一充电子电路、同一补偿子电路和同一控制子电路，
    第4n-3级移位寄存器单元的随机信号端和随机信号线连接，第4n-3级移位寄存器单元的第一时钟信号端和第一时钟线连接，n为大于0的整数。
  19. 根据权利要求17所述的栅极驱动电路，还包括第一子时钟信号线、第二子时钟信号线、第三子时钟信号线和第四子时钟信号线，其中，
    第4n-3级移位寄存器单元的第二时钟信号端和所述第一子时钟信号线连接；
    第4n-2级移位寄存器单元的第二时钟信号端和所述第二子时钟信号线连接；
    第4n-1级移位寄存器单元的第二时钟信号端和所述第三子时钟信号线连接；
    第4n级移位寄存器单元的第二时钟信号端和所述第四子时钟信号线连接；
    n为大于0的整数。
  20. 根据权利要求17所述的栅极驱动电路，其中，
    第n+1级移位寄存器单元的消隐输入信号端和第n级移位寄存器单元的移位信号输出端连接；
    第n+2级移位寄存器单元的显示输入信号端和第n级移位寄存器单元的移位信号输出端连接；
    第n级移位寄存器单元的显示复位信号端和第n+3级移位寄存器单元的移位信号输出端连接；
    n为大于0的整数。
  21. 一种显示装置，包括如权利要求1-16任一所述的移位寄存器单元或权利要求17-20任一所述的栅极驱动电路。
  22. 一种如权利要求1所述的移位寄存器单元的驱动方法，包括用于处理一帧图像的显示时段和消隐时段，其中，
    所述显示时段包括：
    第一输入阶段，所述显示输入电路响应于所述显示输入信号将所述显示上拉信号输入到所述第一控制节点；
    第一输出阶段，所述输出电路在所述第一控制节点的电平的控制下，将所述复合输出信号输出至所述输出端；
    所述消隐时段包括：
    第二输入阶段，所述消隐输入电路根据所述消隐输入信号和所述消隐控制信号将所述消隐上拉信号输入到所述第一控制节点，并对所述消隐输入电路自身进行补偿；
    第二输出阶段，所述输出电路在所述第一控制节点的电平的控制下，将所述复合输出信号输出至所述输出端。
PCT/CN2019/095108 2018-07-18 2019-07-08 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置 WO2020015547A1 (zh)

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