WO2019218713A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2019218713A1
WO2019218713A1 PCT/CN2019/071187 CN2019071187W WO2019218713A1 WO 2019218713 A1 WO2019218713 A1 WO 2019218713A1 CN 2019071187 W CN2019071187 W CN 2019071187W WO 2019218713 A1 WO2019218713 A1 WO 2019218713A1
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WIPO (PCT)
Prior art keywords
pole
transistor
line
gate
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/071187
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English (en)
French (fr)
Chinese (zh)
Inventor
许晨
郝学光
乔勇
吴新银
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Beijing BOE Technology Development Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Beijing BOE Technology Development Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Beijing BOE Technology Development Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to EP19734657.0A priority Critical patent/EP3796302A4/en
Priority to US16/477,308 priority patent/US11380257B2/en
Priority to JP2019570502A priority patent/JP7402053B2/ja
Publication of WO2019218713A1 publication Critical patent/WO2019218713A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing

Definitions

  • Embodiments of the present disclosure relate to a display panel and a display device.
  • Embodiments of the present disclosure provide a display panel including a pixel circuit structure, a data line, and a voltage signal line, wherein the data line is connected to the pixel circuit structure to provide a data signal; the voltage signal line and the pixel circuit The structure is coupled to provide a voltage signal, the voltage signal being a constant voltage signal; the pixel circuit structure comprising a first stable capacitance provided between the data line and the voltage signal line.
  • the display panel further includes a gate line and a light emitting element, wherein the gate line is connected to the pixel circuit structure to provide a scan signal;
  • the pixel circuit structure further includes a driving transistor, and the driving transistor and the light emitting element are electrically Connecting, and outputting a driving current under the control of the scanning signal and the data signal to drive the light emitting element to emit light.
  • the voltage signal line is disposed in the same layer and in the same direction as the data line, and the first capacitor electrode is located on a side of the data line adjacent to the substrate; the display panel further includes the data line and the An interlayer insulating layer between the first capacitor electrodes is electrically connected to the voltage signal line through a via hole penetrating the interlayer insulating layer.
  • the display panel further includes a compensation transistor, the first pole and the second pole of the driving transistor respectively connecting the voltage signal line and the light emitting component; the first pole and the second pole of the compensation transistor respectively A second electrode of the driving transistor is connected to a gate, and a gate of the compensation transistor is connected to the scan line.
  • the pixel circuit structure further includes a storage capacitor, and the first pole and the second pole of the storage capacitor are electrically connected to the voltage signal line and the gate of the driving transistor, respectively, wherein the storage capacitor is One pole is disposed in the same layer as the first capacitor electrode, and overlaps with a gate of the driving transistor in a direction perpendicular to the substrate.
  • an opening is disposed on a first pole of the storage capacitor, and the first connection electrode is electrically connected to a gate of the driving transistor through the opening.
  • the pixel circuit structure further includes a second stabilizing capacitor, the second stabilizing capacitor is located between the data line and the first pole of the driving transistor, or the second stabilizing capacitor is located at the voltage signal line And the first pole of the driving transistor; or the pixel circuit structure further includes a second stabilizing capacitor and a third stabilizing capacitor, wherein one of the second stabilizing capacitor and the third stabilizing capacitor is located on the data line The other of the first poles of the drive transistor is between the voltage signal line and the first pole of the drive transistor.
  • the display panel further includes an illumination control signal line, a reset control signal line, and an initialization signal line
  • the pixel circuit structure further including a data write transistor, a first illumination control transistor, a second illumination control transistor, and a first reset a transistor and a second reset transistor, wherein the first and second poles of the data write transistor are electrically connected to the data line and the first electrode of the drive transistor, respectively, and the gate of the data write transistor is The scan line is electrically connected; the gate of the first light-emitting control transistor is electrically connected to the light-emission control signal line, and the first and second poles of the first light-emitting control transistor are respectively connected to the voltage signal line and the driving a first pole of the transistor is electrically connected; a gate of the second light-emitting control transistor is electrically connected to the light-emitting control signal line, and a first pole and a second pole of the second light-emitting control transistor are respectively connected to the driving transistor a second pole and a second pole of the light emitting element
  • the voltage signal line includes a power line.
  • An embodiment of the present disclosure further provides a display panel including a substrate, a pixel circuit structure on the substrate, a light emitting element, a gate line, a data line, a first power line, a second power line, an emission control signal line, an initialization signal line, and And resetting the signal line, the pixel circuit includes a storage capacitor, a driving transistor, a data writing transistor, a compensation transistor, a first lighting control transistor, a second lighting control transistor, a first reset transistor, and a second reset transistor.
  • a first pole of the storage capacitor is electrically connected to the first power line, and a second pole of the storage capacitor is electrically connected to a second pole of the compensation transistor through a first connection electrode; a gate is electrically connected to the gate line, and a first pole and a second pole of the data writing transistor are electrically connected to the data line and a first pole of the driving transistor respectively; a gate of the compensation transistor The gate lines are electrically connected, and the first and second poles of the compensation transistor are electrically connected to the second pole and the gate of the driving transistor, respectively; the gate of the first light-emitting control transistor and the light-emitting control The signal lines are electrically connected, and the first and second poles of the first light-emitting control transistor are electrically connected to the first power line and the first pole of the driving transistor, respectively; the gate of the second light-emitting control transistor Electrically connecting with the light emission control signal line, the first pole and the second pole of the second light emission control transistor are electrically connected to the second pole of the driving transistor and the first
  • the gate line, the gate of the driving transistor, and the second pole of the storage capacitor are disposed in the same layer; the first capacitor electrode, the initialization signal line, and the first pole of the storage capacitor are in the same layer.
  • the data line, the first power line, and the first connection electrode are disposed in the same layer.
  • the first capacitor electrode and the data line overlap each other in a direction perpendicular to the substrate.
  • the compensation transistor and the first reset transistor are metal oxide semiconductor thin film transistors or double gate thin film transistors.
  • the first capacitor electrode is electrically connected to the first power line
  • the first stabilizing capacitor further includes a second capacitor electrode
  • the second capacitor electrode is electrically connected to the data line
  • the first capacitor The electrode and the second capacitor electrode overlap each other in a direction perpendicular to the substrate.
  • the first capacitor electrode is located on a side of the data line adjacent to the substrate; the display panel further includes an interlayer insulating layer between the data line and the first capacitor electrode, A capacitor electrode is electrically connected to the first power line through a via extending through the interlayer insulating layer.
  • a first pole of the storage capacitor and a gate of the driving transistor overlap each other in a direction perpendicular to the substrate; a first pole of the storage capacitor and the data line are perpendicular to the substrate
  • the first overlapping electrodes of the storage capacitor are provided with openings, and the first connection electrode is electrically connected to the gate of the driving transistor through the opening.
  • the pixel circuit structure further includes a second stabilizing capacitor, the second stabilizing capacitor is located between the data line and the first pole of the driving transistor, or the second stabilizing capacitor is located at the first power source Between the line and the first pole of the driving transistor; or the pixel circuit structure further includes a second stabilizing capacitor and a third stabilizing capacitor, one of the second stabilizing capacitor and the third stabilizing capacitor being located
  • the data line is between the first pole of the drive transistor and the other is between the first power line and the first pole of the drive transistor.
  • Embodiments of the present disclosure also provide a display device including the above display panel.
  • FIG. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure
  • FIG. 2 is a schematic plan view of a display panel according to an embodiment of the present disclosure
  • FIG. 3 is a timing signal diagram of a pixel unit in a display panel according to an embodiment of the present disclosure
  • FIG. 4 is a schematic structural diagram of a display panel according to another embodiment of the present disclosure.
  • FIG. 5 is a schematic plan view of a display panel according to an embodiment of the present disclosure.
  • Figure 6 is a cross-sectional view of the display panel of Figure 5 taken along section line I-I';
  • Figure 7 is a cross-sectional view of the display panel of Figure 5 taken along section line II-II'.
  • the driving transistor is connected to the organic light emitting element, and a driving current is output to the organic light emitting element under the control of a signal such as a data signal or a scanning signal, thereby driving the organic light emitting element to emit light. Since the magnitude of the gate voltage of the driving transistor is directly related to the magnitude of the driving current in the organic light emitting element, the stabilization of the gate signal is an important factor for achieving stable light emission of the organic light emitting element and display stability of the display panel.
  • the inventors found that when the data signal is transmitted on the data line, the fluctuation of the data signal easily interferes with the gate signal of the driving transistor, for example, the parasitic capacitance formed by the data signal between the data line and the gate of the driving transistor. Interference with the gate signal affects the stability of the gate signal.
  • FIG. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of a planar structure of a display panel according to an embodiment of the present disclosure.
  • the display panel 100 includes a plurality of pixel units 101 arranged in a matrix, each of the pixel units 101 including a pixel circuit structure 10, a light emitting element 20, a gate line 11, a data line 12, and a voltage signal. line.
  • the light-emitting element 20 is an organic light-emitting element OLED, and the light-emitting element 20 emits red light, green light, blue light, or white light, etc., driven by its corresponding pixel circuit structure 10.
  • the voltage signal line may be one or more than one.
  • the voltage signal line may include a signal line that provides a constant voltage signal, such as the first power line 13, the second power line 14, the initialization signal line 16, and the like.
  • the first power line 13 is configured to provide a constant first voltage signal ELVDD to the pixel circuit structure 10
  • the second power line 14 is configured to provide a constant second voltage signal ELVSS
  • the first voltage signal ELVDD is greater than the second voltage signal ELVSS
  • the illumination control signal line 15 is configured to provide an illumination control signal EM.
  • the initialization signal line 16 and the reset control signal line 17 are respectively configured to provide an initialization signal Vint and a reset control signal Reset, wherein the initialization signal Vint is a constant voltage signal, which may be, for example, between the first voltage signal ELVDD and the second voltage signal Between ELVSS, but is not limited thereto, for example, less than or equal to the second voltage signal ELVSS.
  • the pixel circuit structure 10 includes a driving transistor T1, a data writing transistor T2, a compensation transistor T3, a first emission control transistor T4, a second emission control transistor T5, a first reset transistor T6, a second reset transistor T7, and a storage capacitor Cst.
  • the driving transistor T1 is electrically connected to the light emitting element 20, and outputs a driving current under the control of signals such as the scanning signal Scan, the data signal Data, the first voltage signal ELVDD, and the second voltage signal ELVSS to drive the light emitting element 20 to emit light.
  • the pixel circuit structure 10 further includes a first stabilizing capacitor C1 between the data line 12 and the voltage signal line, and the voltage signal line shown in FIG. 1 refers to the first power line 13.
  • the first stabilizing capacitor C1 can reduce the interference of the parasitic capacitance between the data line 12 and the gate of the driving transistor T1 on the gate signal of the driving transistor T1.
  • the first stable capacitor C1 can be arranged in a variety of ways.
  • the first stabilizing capacitor may include a first capacitor electrode and a second capacitor electrode, the first capacitor electrode is electrically connected to the first power source line 13 , and the second capacitor electrode is electrically connected to the data line 12 .
  • the first capacitor electrode may be a part of the first power line 13 or an electrode that is separately provided and electrically connected to the first power line 13 , and both of the cases are included in the “first capacitor electrode and the first power source”. Line electrical connection”.
  • the second capacitor electrode may be a part of the data line 12 or an electrode that is separately provided to be electrically connected to the data line 12, both of which are included in the range in which the "second capacitor electrode is electrically connected to the data line”.
  • a pixel circuit structure including a laminated circuit layer, an insulating layer, and the like is prepared by a semiconductor process on a substrate of the display panel 100.
  • the first capacitor electrode and the second capacitor electrode may overlap each other in a direction perpendicular to the substrate of the display panel 100, and are spaced apart from each other by an insulating layer (dielectric layer), thereby constituting a capacitor.
  • the first stabilizing capacitor C1 can be adjusted by designing a distance between the first capacitor electrode and the second capacitor electrode, a material of the intermediate insulating layer (ie, a dielectric constant), and an overlapping area between the two. Capacitance value.
  • the first pole of the storage capacitor Cst is electrically connected to the first power line 13 and the second pole of the storage capacitor Cst is electrically connected to the second pole of the compensation transistor T3.
  • the gate of the data writing transistor T2 is electrically connected to the gate line 11, and the first and second poles of the data writing transistor T2 are electrically connected to the data line 12 and the first electrode of the driving transistor T1, respectively.
  • the gate of the compensation transistor T3 is electrically connected to the gate line 11, and the first and second poles of the compensation transistor T3 are electrically connected to the second electrode and the gate of the driving transistor T1, respectively.
  • the gate of the first light emission controlling transistor T4 is electrically connected to the light emission control signal line 15, and the first pole and the second pole of the first light emission controlling transistor T4 are electrically connected to the first power source line 13 and the first pole of the driving transistor T1, respectively.
  • the gate of the second light-emitting control transistor T5 is electrically connected to the light-emission control signal line 15.
  • the first pole and the second pole of the second light-emitting control transistor T5 are respectively connected to the second pole of the driving transistor T1 and the first pole of the light-emitting element 20 connection.
  • the gate of the first reset transistor T6 is electrically connected to the reset control signal line 17, and the first and second poles of the first reset transistor T6 are electrically connected to the initialization signal line 16 and the gate of the driving transistor T1, respectively.
  • the gate of the second reset transistor T7 is electrically connected to the reset control signal line 17, and the first and second poles of the second reset transistor T7 are electrically connected to the initialization signal line 16 and the first electrode of the light-emitting element 20, respectively.
  • the second pole of the light emitting element 20 is electrically connected to the second power source line 14. It should be noted that the transistors used in the embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other switching devices having the same characteristics.
  • the source and drain of the transistor used here may be structurally symmetrical, so that the source and the drain may be structurally indistinguishable.
  • the first pole of the transistor of the embodiment of the present disclosure may be a source, and the second pole may be a drain; or the first extreme drain of the transistor and the second source of the second.
  • the transistors can be divided into N-type and P-type transistors according to the characteristics of the transistors.
  • Embodiments of the present disclosure are described by taking a P-type transistor as an example. Based on the description and teaching of the implementation of the present disclosure, those skilled in the art can easily imagine that at least some of the transistors in the pixel circuit structure of the embodiment of the present disclosure adopt an N-type transistor, that is, adopt N. The implementation of a type transistor or a combination of an N-type transistor and a P-type transistor is therefore within the scope of the present disclosure.
  • the transistors employed in the embodiments of the present disclosure may include various structures such as a top gate type, a bottom gate type, or a double gate structure.
  • the compensation transistor T3 and the first reset transistor T6 directly connected to the gate of the driving transistor T1 are double-gate thin film transistors, which can contribute to lowering the gate leakage current of the driving transistor T1.
  • the display panel 100 provided by the embodiment of the present disclosure further includes: a data driver 102, a scan driver 103, and a controller 104.
  • the data driver 102 is configured to provide the data signal Data to the pixel unit 101 according to an instruction of the controller 104;
  • the scan driver 103 is configured to provide the pixel unit 101 with the light emission control signal EM, the scan signal Scan, and the reset control signal according to an instruction of the controller 104. Reset, etc.
  • the scan driver 103 is a GOA (Gate On Array) structure mounted on the display panel, or a driver chip (IC) structure that is bonded to the display panel.
  • GOA Gate On Array
  • the display panel 100 further includes a power source (not shown) to provide the above voltage signal, which may be a voltage source or a current source as needed, and the power source is configured to pass through the first power line 13 and the second power line 14, respectively.
  • the initialization signal line 16 supplies the pixel unit 101 with the first power source voltage ELVDD, the second power source voltage ELVSS, and the initialization signal Vint and the like.
  • FIG. 3 is a timing signal diagram of a pixel unit in a display panel according to an embodiment of the present disclosure. A driving method of one pixel unit in the display panel provided by the embodiment of the present disclosure will be described below with reference to FIG. 3 .
  • the driving method of the pixel unit in one frame display period includes a reset phase t1, a data writing and threshold compensation phase t2, and an illumination phase t3.
  • the illumination control signal EM is set to the off voltage
  • the reset control signal Reset is set to the on voltage
  • the scan signal Scan is set to the off voltage.
  • the lighting control signal EM is set to the off voltage
  • the reset control signal Reset is set to the off voltage
  • the scan signal Scan is set to the turn-on voltage.
  • the lighting control signal EM is set to the turn-on voltage
  • the reset control signal Reset is set to the turn-off voltage
  • the scan signal Scan is set to the turn-off voltage.
  • the turn-on voltage in the embodiment of the present disclosure refers to a voltage that enables the first and second stages of the respective transistors to be turned on
  • the turn-off voltage refers to a voltage that can turn off the first and second stages of the respective transistors.
  • the turn-on voltage is a low voltage (for example, 0V)
  • the turn-off voltage is a high voltage (for example, 5V)
  • the turn-on voltage is a high voltage (for example, 5V)
  • the voltage is a low voltage (eg, 0V).
  • the driving waveforms shown in FIG. 3 are all described by taking a P-type transistor as an example, that is, the turn-on voltage is a low voltage (for example, 0 V), and the turn-off voltage is a high voltage (for example, 5 V).
  • the illumination control signal EM is the off voltage
  • the reset control signal Reset is the on voltage
  • the scan signal Scan is the off voltage.
  • the first reset transistor T6 and the second reset transistor T7 are in an on state
  • the data write transistor T2, the compensation transistor T3, the first light emission control transistor T4, and the second light emission control transistor T5 are in an off state.
  • the first reset transistor T6 transmits an initialization signal (initialization voltage) Vint to the gate of the driving transistor T1 and is stored by the storage capacitor Cst, resets the driving transistor T1 and eliminates data stored when the last (previous frame) is illuminated, and second The reset transistor T7 transmits an initialization signal Vint to the first pole of the light emitting element 20 to reset the light emitting element 20.
  • the lighting control signal EM is the off voltage
  • the reset control signal Reset is the off voltage
  • the scanning signal Scan is the on voltage.
  • the data writing transistor T2 and the compensation transistor T3 are in an on state
  • the first lighting control transistor T4, the second lighting control transistor T5, the first reset transistor T6, and the second reset transistor T7 are in a closed state.
  • the data writing transistor T2 transmits the data signal voltage Vdata to the first pole of the driving transistor T1, that is, the data writing transistor T2 receives the scanning signal Scan and the data signal Data and according to the scanning signal Scan to the first of the driving transistor T1.
  • the pole writes the data signal Data.
  • the compensation transistor T3 is turned on to connect the driving transistor T1 into a diode structure, whereby the gate of the driving transistor T1 can be charged.
  • the gate voltage of the driving transistor T1 is Vdata+Vth, where Vdata is the data signal voltage, and Vth is the threshold voltage of the driving transistor T1, that is, the compensation transistor T3 receives the scanning signal Scan and scans the driving transistor according to the scanning signal Scan.
  • the gate voltage of T1 performs threshold voltage compensation.
  • the voltage difference across the storage capacitor Cst is ELVDD-Vdata-Vth.
  • the light-emission control signal EM is the turn-on voltage
  • the reset control signal Reset is the turn-off voltage
  • the scan signal Scan is the turn-off voltage.
  • the first light emission control transistor T4 and the second light emission control transistor T5 are in an on state
  • the data write transistor T2, the compensation transistor T3, the first reset transistor T6, and the second reset transistor T7 are in an off state.
  • the first power signal ELVDD is transmitted to the first pole of the driving transistor T1 through the first light emitting control transistor T4, the gate voltage of the driving transistor T1 is maintained at Vdata+Vth, and the light emitting current I passes through the first light emitting controlling transistor T4, the driving transistor T1, and
  • the second light emission controlling transistor T5 flows into the light emitting element 20, and the light emitting element 20 emits light. That is, the first light emission controlling transistor T4 and the second light emission controlling transistor T5 receive the light emission control signal EM, and control the light emitting element 20 to emit light according to the light emission control signal EM.
  • the illuminating current I satisfies the following saturation current formula:
  • ⁇ n is the channel mobility of the driving transistor
  • Cox is the channel capacitance per unit area of the driving transistor T1
  • W and L are the channel width and the channel length of the driving transistor T1, respectively
  • Vgs is the gate and source of the driving transistor T1. The voltage difference between the poles (that is, the first pole of the driving transistor T1 in this embodiment).
  • the current flowing through the light-emitting element 20 is independent of the threshold voltage of the driving transistor T1. Therefore, the pixel circuit structure is very well compensated for the threshold voltage of the driving transistor T.
  • the reset control signal line 17 may be set as the scan line of the pixel unit of the previous row, that is, the reset control signal is served by the scan signal Scan(n-1) of the pixel unit of the previous row. , which reduces wiring and the number of signals.
  • the ratio of the duration of the illumination phase t3 to the display period of one frame can be adjusted.
  • the luminance of the light can be controlled by adjusting the length of the light-emitting phase t3 to the ratio of one frame display period.
  • the scan driver 103 in the display panel or an additionally provided driver the ratio of the length of the adjustment illumination period t3 to the display period of one frame is achieved.
  • the first stabilizing capacitor C1 can also be located between the data line 12 and other signal lines that provide a constant voltage signal.
  • the first stabilizing capacitor C1 is located between the data line 12 and the second power line 14, or the first stabilizing capacitor C1 is located between the data line 12 and the initialization signal line 16.
  • the first light-emitting control transistor T4 or the second light-emitting control transistor T5 may not be provided, or the first reset transistor T6 or the second reset transistor T7 may not be provided, that is, the embodiment of the present disclosure is not limited to FIG. 1 .
  • the particular pixel circuit shown may employ other pixel circuits that enable compensation for the drive transistor. Based on the description and teachings of the implementations of the present disclosure, other arrangements that can be easily conceived by those skilled in the art without departing from the inventive scope are within the scope of the present disclosure.
  • FIG. 4 is a schematic diagram of a display panel according to another embodiment of the present disclosure.
  • the display panel provided in this embodiment is different from the display panel in FIG. 1 in that the display panel 100 further includes a second stabilizing capacitor C2 and/or a third stabilizing capacitor C3, and the second capacitor C2 is located on the data line 12.
  • the third stabilizing capacitor C3 is located between the first power source line 13 and the first pole of the driving transistor T1. Due to the presence of the second stabilizing capacitor C2, the parasitic capacitance between the data line 12 and the gate of the driving transistor T1 interferes with the gate signal of the driving transistor T1 further. Due to the presence of the third stabilizing capacitor C3, the parasitic capacitance between the first power supply line 13 and the gate of the driving transistor T1 interferes with the gate signal of the driving transistor T1.
  • FIG. 5 is a schematic plan view (exemplary layout) of the display panel 100 of FIG. 1 .
  • the driving transistor T1, the data writing transistor T2, the compensation transistor T3, the storage capacitor Cst, and the first stabilizing capacitor C1 is shown, and the structures of other transistors are not shown.
  • Figure 6 is a cross-sectional view of the display panel of Figure 5 taken along section line I-I'
  • Figure 7 is a cross-sectional view of the display panel of Figure 5 taken along section line II-II'.
  • the display panel 100 provided by the embodiment of the present disclosure will be exemplarily described below with reference to FIGS. 5-7.
  • “same layer setting” as used in the present disclosure means that two (or two or more) material layer structures are formed by the same deposition process and patterned by the same patterning process, so both (multiple The materials are the same.
  • T1g, T1s, T1d, and T1a respectively indicate the gate, the first pole, the second pole, and the channel region of the driving transistor T1, respectively, using T2g, T2s, T2d, and T2a, respectively.
  • Representing the gate of the data write transistor T2 the first pole, the second pole, and the channel region, and the gate, the first pole, the second pole, and the channel region of the compensation transistor T3 are respectively represented by T3g, T3s, T3d, and T3a.
  • the first and second poles of the storage capacitor are respectively represented by Csa and Csb.
  • the display panel 100 includes a substrate 200 and a semiconductor pattern layer 21, a first insulating layer 22, a first conductive pattern layer 23, a second insulating layer 24, and a second conductive pattern layer 25, which are sequentially stacked on the substrate 200, The interlayer insulating layer 26 and the third conductive pattern layer 27.
  • the semiconductor pattern layer 21 includes an active layer of the driving transistor T1, an active layer of the data writing transistor T2, and an active layer of the compensation transistor T3.
  • the first conductive pattern layer 23 includes a gate line 11, a second pole Csb of the storage capacitor Cst, a gate T1g of the driving transistor T1, a gate T2g of the data writing transistor, and a gate T3g of the compensation transistor.
  • the second conductive pattern layer 25 includes a first pole Csa of the storage capacitor Cst.
  • the first pole Csa of the storage capacitor Cst and the gate T1g of the driving transistor T1 overlap each other in a direction perpendicular to the substrate 200.
  • the third conductive pattern layer 27 includes the data line 12 and the first power line 13.
  • the gate line 11 extends in the first direction D1
  • the data line 12 and the first power line 13 extend in the second direction D2 and are disposed in the same layer.
  • the first direction D1 and the second direction D2 are substantially vertical.
  • the first stabilizing capacitor C1 includes a first capacitor electrode 18 that is separately provided to be electrically connected to the first power source line 13, and the second capacitor electrode of the first stabilizing capacitor C1 is served by a portion of the data line 12 itself.
  • the second capacitor electrode may also be separately provided as an electrode connected to the data line 12.
  • the first capacitor electrode 18 is located on the side of the data line 12 close to the substrate 200 and is disposed in the same layer as the first capacitor electrode Csa of the storage capacitor Cst.
  • the first capacitor electrode 18 is electrically connected to the first power source line 13 through the first via hole 260 that passes through the interlayer insulating layer 26.
  • the first capacitor electrode 18 and the data line 12 overlap each other in a direction perpendicular to the substrate 200, thereby forming a first stabilizing capacitor C1.
  • the semiconductor pattern layer 21 is subjected to a conductor treatment using the first conductive pattern layer 23 as a mask by using a self-alignment process, for example, the semiconductor pattern layer 21 is heavily doped by ion implantation.
  • the portion of the semiconductor pattern layer 21 covered by the first conductive pattern layer 23 retains semiconductor characteristics, forming channel regions T1a, T2a, and T3a of the respective transistors.
  • the display panel 100 further includes a first connection electrode 19 configured to connect the drain region (second polar region) of the compensation transistor T3 and the gate T1g of the driving transistor T1, thereby compensating the transistor T3
  • the diode T3d is electrically connected to the gate T1g of the driving transistor T1.
  • the first capacitor electrode 18 is located near the substrate 200 by the data capacitor 12 .
  • the first capacitor electrode can function to raise the data line, and can increase the distance between the data line 12 and the first connection electrode 19 and the side surface of the second pole T3d of the compensation transistor T3, thereby Reduce this parasitic capacitance.
  • the second pole T3d of the compensation transistor T3 is directly connected to the gate of the driving transistor T1, lowering the parasitic capacitance helps to reduce the interference of the data line to the gate signal of the driving transistor T1.
  • the orthographic projection of the first connection electrode 19 on the layer where the first capacitor electrode 18 is located ie, the second conductive pattern layer 25
  • the direction in which the first capacitor electrode 18 extends perpendicular to the direction in which the data line 12 extends ie, the first The directions D1 overlap each other.
  • the orthographic projection of the first connection electrode 19 on the layer where the first capacitor electrode 18 is located (that is, the second conductive pattern layer 25) and the direction of the first capacitor electrode 18 in the direction perpendicular to the extension of the data line 12 are shown. (that is, the first direction D1) overlaps each other.
  • the first pole Csa of the storage capacitor Cst is provided with an opening 250 through which the first connection electrode 19 passes and the second via 240 penetrating the second insulating layer 24 and the interlayer insulating layer 26 and the gate of the driving transistor T1.
  • T1g (that is, the second pole Csb of the storage capacitor Cst) is electrically connected.
  • the first connection electrode 19 is electrically connected to the second pole T3d of the compensation transistor T3 through the third via 220 penetrating through the first insulating layer 22, the second insulating layer 24, and the interlayer insulating layer 26.
  • the first power source line 13 is electrically connected to the first pole Csa of the storage capacitor Cst through the fourth via hole 261 penetrating the interlayer insulating layer 26.
  • the material of the first insulating layer 22, the second insulating layer 24, and the interlayer insulating layer 26 may include an inorganic insulating material such as silicon nitride, silicon oxynitride, or the like, or aluminum oxide, titanium nitride, or the like.
  • the insulating material may further include an organic insulating material such as acrylic acid or polymethyl methacrylate (PMMA).
  • PMMA polymethyl methacrylate
  • the insulating layer may be a single layer structure or a multilayer structure.
  • materials of the first conductive pattern layer 23, the second conductive pattern layer 25, and the third conductive pattern layer 27 include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), An alloy material composed of magnesium (Mg), tungsten (W), and a combination of the above metals; or a conductive metal oxide material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc aluminum oxide (AZO) and so on.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • ZnO zinc oxide
  • AZO zinc aluminum oxide
  • the substrate 200 is a glass substrate
  • the buffer layer 28 is silicon dioxide for preventing impurities (metal ions) in the substrate 200 from diffusing into the pixel circuit structure.
  • the display panel provided by the embodiment of the present disclosure can be applied to any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display panel is an organic light emitting diode display panel.
  • Embodiments of the present disclosure also provide a display device including the above display panel.
  • the display device may be an electronic device such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator or the like that applies the display panel.
  • the display device is an organic light emitting diode display device.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of El Displays (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
PCT/CN2019/071187 2018-05-14 2019-01-10 显示面板及显示装置 Ceased WO2019218713A1 (zh)

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