WO2019024906A1 - 一种ldmos器件及其制造方法和电子装置 - Google Patents

一种ldmos器件及其制造方法和电子装置 Download PDF

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WO2019024906A1
WO2019024906A1 PCT/CN2018/098447 CN2018098447W WO2019024906A1 WO 2019024906 A1 WO2019024906 A1 WO 2019024906A1 CN 2018098447 W CN2018098447 W CN 2018098447W WO 2019024906 A1 WO2019024906 A1 WO 2019024906A1
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Prior art keywords
contact hole
layer
drain
gate structure
metal silicide
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English (en)
French (fr)
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金华俊
孙贵鹏
金宏峰
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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Priority to US16/644,856 priority Critical patent/US11158737B2/en
Priority to KR1020207006168A priority patent/KR102367270B1/ko
Publication of WO2019024906A1 publication Critical patent/WO2019024906A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
    • H10D30/0285—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs using formation of insulating sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/605—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having significant overlap between the lightly-doped extensions and the gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular to an LDMOS device, a method of fabricating the same, and an electronic device.
  • Conventional high-voltage device structures generally extend the polysilicon length to extend the polysilicon to the field plate oxide layer of the drift region to act as a field plate.
  • the field plate depletes the drift region to form a depletion layer, thereby increasing the width of the lateral depletion layer.
  • Increase the withstand voltage ie, the breakdown voltage.
  • it is necessary to select a suitable field oxide thickness between the drain and the gate in the drift region of the high voltage device and the required field oxide layer thickness is a single thickness or by parasitic oxide (for example, setting This is achieved by a shallow trench isolation structure (STI), etc. in the drift region between the drain and the gate.
  • STI shallow trench isolation structure
  • the use of STI can increase the withstand voltage of the device, but it increases the on-resistance.
  • An LDMOS device, a method of fabricating the same, and an electronic device are provided in accordance with various embodiments of the present application.
  • An LDMOS device including:
  • drift region disposed in the semiconductor substrate
  • a gate structure disposed on a portion of the surface of the semiconductor substrate and covering a portion of the surface of the drift region;
  • a metal silicide blocking layer covering at least a portion of the surface of the semiconductor substrate between the gate structure and the drain;
  • a first contact hole is disposed on a surface of at least a portion of the metal silicide blocking layer.
  • a gate structure formed on a portion of a surface of the semiconductor substrate, the gate structure covering a portion of a surface of the drift region, a source and a drain are respectively formed in the semiconductor substrate on both sides of the gate structure, wherein the drain is disposed in the drift region and has a gap between the gate structure and the gate structure;
  • metal silicide blocking layer Forming a metal silicide blocking layer, wherein the metal silicide blocking layer covers at least a portion of a surface of the semiconductor substrate between the gate structure and the drain;
  • a first contact hole is formed on a surface of at least a portion of the metal silicide blocking layer.
  • an electronic device including the aforementioned LDMOS device is also provided.
  • FIGS. 1A to 1G are schematic cross-sectional views showing a device obtained by the relevant steps of a method of fabricating an LDMOS device according to an embodiment of the present invention
  • FIG. 2 is a process flow diagram showing a method of fabricating an LDMOS device according to an embodiment of the present invention
  • FIG. 3 shows a schematic diagram of an electronic device in an embodiment of the invention.
  • the present invention provides an LDMOS device, the LDMOS device mainly comprising:
  • drift region disposed in the semiconductor substrate
  • a gate structure disposed on a portion of the surface of the semiconductor substrate and covering a portion of the surface of the drift region;
  • a metal silicide blocking layer covering at least a portion of the surface of the semiconductor substrate between the gate structure and the drain;
  • a first contact hole is disposed on a surface of at least a portion of the metal silicide blocking layer.
  • the LDMOS device of the present invention includes a metal silicide blocking layer covering at least a portion of the surface of the semiconductor substrate between the gate structure and the drain, and at least a portion of the metal silicide
  • the first contact hole on the surface of the barrier layer further enhances the depletion of the drift region to increase the breakdown voltage of the device, thereby improving the performance of the device.
  • the LDMOS device of the present invention does not need to provide shallow trench isolation in the drift region of the drain terminal. The structure, therefore, greatly reduces the on-resistance of the device.
  • the LDMOS device of the present invention includes a semiconductor substrate 100.
  • the constituent material of the semiconductor substrate 100 may be undoped single crystal silicon, monocrystalline silicon doped with impurities, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), and silicon-on-insulator (S-). SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI).
  • the constituent material of the semiconductor substrate 100 is selected from single crystal silicon.
  • the semiconductor substrate 100 may also be a P-type semiconductor substrate or an N-type semiconductor substrate.
  • an N-type high voltage device may select a P-type semiconductor substrate, and a P-type high voltage device may select an N-type semiconductor substrate.
  • the semiconductor substrate 100 is a P-type semiconductor substrate.
  • a shallow trench isolation structure is formed in the semiconductor substrate to define an active region.
  • drift region 101 is provided in the semiconductor substrate 100.
  • the drift region has different conductivity types depending on the type of the LDMOS device. For example, if the LDMOS device is an N-type LDMOS device, the drift region 101 is an N-type drift region, and if the LDMOS device is a P-type LDMOS device, the drift region 101 is a P-type drift region.
  • the doping concentration of the drift region is lower, which is lower than the doping concentration of the source and the drain, which is equivalent to forming a high resistance layer between the source and the drain, which can increase the breakdown voltage and reduce
  • the small parasitic capacitance between the source and the drain helps to improve the frequency characteristics.
  • a body region 102 may also be disposed in the semiconductor substrate 100, the body region 102 being located outside the drift region 101 and spaced apart from the drift region, wherein the body region and the drift region have opposite conductivity types. That is, when the drift region is N-type, the body region is P-type, or when the drift region is P-type, the body region is N-type.
  • a well region is further disposed in the semiconductor substrate 100, and the body region 102 and the drift region 101 are both disposed in the well region, wherein the well region has the same as the drift region 101
  • the conductivity type, and the doping concentration of the well region is lower than the doping concentration of the drift region 102, the well region and the drift region 102 outside the body region constitute a drift region having a graded doping concentration.
  • a gate structure 103 is disposed on a portion of the surface of the semiconductor substrate 100.
  • the gate structure 103 covers the channel region (for example, the surface of the partial body region 102), and further, the gate structure also covers the surface of the partial drift region 101.
  • the gate structure 103 includes a gate dielectric layer 1031 on the surface of the semiconductor substrate 100 and a gate layer 1032 on the gate dielectric layer 1031.
  • the gate dielectric layer 1031 may comprise a conventional dielectric material such as oxides, nitrides and oxynitrides of silicon having a dielectric constant from about 4 to about 20 (measured in vacuum), or a gate.
  • the dielectric layer can include a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100.
  • Such higher dielectric constant electrolyte materials may include, but are not limited to, cerium oxide, lanthanum silicate, titanium oxide, barium titanate (BSTs), and lead zirconate titanate (PZTs).
  • the gate layer 1032 is made of a polysilicon material. Generally, a metal, a metal nitride, a metal silicide or the like can be used as the material of the gate layer. In this embodiment, the material of the gate layer 1032 includes polysilicon.
  • a spacer 104 is formed on a sidewall of the gate structure 103.
  • the spacer may be one of silicon oxide, silicon nitride, silicon oxynitride or a combination thereof.
  • a source electrode 1052 and a drain electrode 1051 are respectively disposed in the semiconductor substrate 100 on both sides of the gate structure 103, wherein the drain electrode 1051 is formed in the drift region 101. And a space is formed between the gate structure 103, the source electrode 1052 is formed in the body region 102, and the source electrode 1052 and the drain electrode 1051 and the drift region 101 have the same conductivity type.
  • the drift region is an N-type drift region, and the drain and the source may be N-type source and drain, which may also be N-type dopant ion heavily doped source and drain. .
  • a body region lead-out region (not shown) having the same conductivity type as the body region is formed in the body region, for example, the body region is P-type, and the body region lead-out region may also be P-type, and The impurity doping concentration is greater than the impurity doping concentration of the body region, for example, the body region lead-out region is heavily doped with a P-type impurity.
  • the surface of the drift region, the source, the drain, and the surface of the body region are all flush with the surface of the semiconductor substrate.
  • the LDMOS device further includes a metal silicide blocking layer 106 covering at least a portion of the surface of the semiconductor substrate 100 between the gate structure 103 and the drain electrode 1051, that is, a capping gate The surface of the drift region 101 between the pole structure 103 and the drain 1051.
  • the metal silicide blocking layer 106 covers a portion of a top surface of the gate structure 103 and a surface of the semiconductor substrate 100 between the gate structure 103 and the drain electrode 1051, That is, the metal silicide blocking layer 106 covers the surface of the semiconductor substrate 100 between the gate structure 103 and the drain electrode 1051 and extends to a portion of the top surface of the gate structure 103.
  • the metal silicide blocking layer 106 also covers the spacer 104 on a sidewall of the gate structure 103 adjacent to the drain.
  • the metal silicide blocking layer 106 includes an oxide layer, a nitride layer, and an oxynitride layer stacked in this order from bottom to top, the oxide layer including, for example, silicon oxide, the nitride layer, for example A silicon nitride layer is included, and the oxynitride layer includes silicon oxynitride.
  • the thickness of the nitride layer in the metal silicide blocking layer 106 and the thickness of the oxynitride layer are all smaller than the thickness of the oxide layer, for example, the thickness of the nitride layer may be 350. ⁇ 700 ⁇ , the oxynitride layer may have a thickness of 350 to 700 angstroms, and the oxide layer may have a thickness of 1000 to 3000 angstroms, for example, 1000 angstroms, 1500 angstroms, 2000 angstroms, 2500 angstroms, 3000 angstroms, or the like.
  • the metal silicide blocking layer 106 may further include other suitable materials.
  • the metal silicide blocking layer 106 may further include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and carbon doped nitrogen. At least one of a silicon layer or the like.
  • a metal silicide layer 107 is formed on a portion of the surface of the source electrode 1052, the drain electrode 1051, and the gate structure 103, wherein the metal silicide layer 107 Materials including CoSix, NiSix, and PtSix, or combinations thereof, may be included.
  • a first contact hole 1081 is formed on a surface of at least a portion of the metal silicide blocking layer 106.
  • the first contact hole 1081 may be partially located on the surface of the metal silicide blocking layer 106 above the gate structure, partially on the surface of the metal silicide blocking layer 106 above the spacer and partially located on the surface On the surface of the metal silicide blocking layer 106 on the surface of the semiconductor substrate between the spacer and the drain, or the first contact hole 1081 may be located only at the spacer and the drain On the surface of the metal silicide blocking layer 106 on the surface of the semiconductor substrate, or the first contact hole 1081 may be partially located on the surface of the metal silicide blocking layer 106 above the spacer and partially located The surface of the metal silicide blocking layer 106 on the surface of the semiconductor substrate between the spacer and the drain.
  • the metal silicide blocking layer 106 includes an oxide layer, a nitride layer, and an oxynitride layer stacked in this order from bottom to top, and the bottom of the first contact hole 1081 is located in the nitride layer.
  • the bottom of the first contact hole 1081 is located on the surface of the nitride layer, so that the electric field of the drift region can be adjusted by adjusting the thickness of the oxide layer under the nitride layer in the metal silicide blocking layer 106. Depleted, which in turn improves device characteristics.
  • a second contact hole 1082 is disposed on a portion of the surface of the source electrode 1052, the second contact hole 1082 is electrically connected to the source electrode 1052, and further, the second contact hole 1082 is electrically A metal silicide layer 107 is connected to the surface of the source electrode 1052 to achieve electrical connection with the source electrode 1052.
  • the second contact hole 1082 and the first contact hole 1081 are electrically connected and grounded, thereby enhancing the depletion of the drift region, thereby increasing the breakdown voltage of the device.
  • the second contact hole 1082 and the first contact hole 1081 can be electrically connected to each other by electrically connecting the same metal layer or metal interconnection structure, or electrically connected in other suitable manners.
  • a third contact hole 1083 is disposed on a portion of the surface of the drain electrode 1051.
  • the third contact hole 1083 is electrically connected to the drain electrode 1051. Further, the third contact hole 1083 is electrically connected.
  • a metal silicide layer 107 is connected to the surface of the drain electrode 1051 to achieve electrical connection with the drain electrode 1051.
  • the first contact hole 1081, the second contact hole 1082, and the third contact hole 1083 are filled with a conductive material, wherein the conductive material may be any suitable conductive material well known to those skilled in the art.
  • the material includes, but is not limited to, a metal material, wherein the metal material may include one or more of Ag, Au, Cu, Pd, Pt, Cr, Mo, Ti, Ta, W, and Al.
  • the first contact hole 1081, the second contact hole 1082, and the third contact hole 1083 are filled with the same conductive material, for example, may be filled with copper metal or the like, or may be filled with different conductive materials.
  • the width of the first contact hole 1081 is greater than the width of the second contact hole 1082 and the third contact hole 1083, and the width refers to the first contact hole 1081, The diameters of the second contact hole 1082 and the third contact hole 1083 in the direction of the source and drain lines and their extension lines.
  • the LDMOS device further includes an interlayer dielectric layer 109 covering the gate structure 103, the source 1052, the drain 1051, and the metal silicide blocking a layer 106 and a surface of the exposed semiconductor substrate, the first contact hole 1081 penetrating the interlayer dielectric layer 109 above the metal silicide blocking layer 106, and the second contact hole 1082 penetrating the source
  • the interlayer dielectric layer 109 above the 1052, the third contact hole 1083 extends through the interlayer dielectric layer 109 above the drain electrode 1051.
  • the interlayer dielectric layer 109 may be a silicon oxide layer, including a material having doped or undoped silicon oxide formed by a thermal CVD fabrication process or a high density plasma (HDP) fabrication process.
  • a layer such as undoped silicon glass (USG), phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG).
  • the interlayer dielectric layer may also be boron-doped or phosphorus-doped spin-on-glass (SOG), phosphorus-doped tetraethoxysilane (PTEOS) or boron-doped. Tetraethoxysilane (BTEOS).
  • the LDMOS device of the present invention includes a metal silicide blocking layer covering at least a portion of the surface of the semiconductor substrate between the gate structure and the drain, and at least a portion of the metal silicide
  • the metal silicide blocking layer 106 includes layers stacked in order from bottom to top.
  • the depletion of the electric field in the drift region can be adjusted by adjusting the thickness of the oxide layer under the nitride layer in the metal silicide blocking layer 106, thereby improving device characteristics.
  • the LDMOS device of the present invention does not need to be in the drift region of the drain end.
  • the shallow trench isolation structure is provided, thus greatly reducing the on-resistance of the device.
  • the present invention also provides a method for fabricating an LDMOS device according to the first embodiment.
  • the method for fabricating the semiconductor device of the present invention mainly includes the following steps:
  • Step S1 providing a semiconductor substrate in which a drift region is formed, and a gate structure is formed on a part of a surface of the semiconductor substrate, the gate structure covering a portion of a surface of the drift region, Forming a source and a drain respectively in the semiconductor substrate on both sides of the gate structure, wherein the drain is disposed in the drift region and has a space between the gate structure;
  • Step S2 forming a metal silicide blocking layer, wherein the metal silicide blocking layer covers at least a portion of the surface of the semiconductor substrate between the gate structure and the drain;
  • Step S3 forming a first contact hole on at least a portion of the surface of the metal silicide blocking layer.
  • FIG. 1A to FIG. 1G show the device obtained by the relevant steps of the method for fabricating the LDMOS device according to an embodiment of the present invention.
  • FIG. 2 is a process flow diagram showing a method of fabricating an LDMOS device according to an embodiment of the present invention.
  • the method of fabricating the LDMOS device of the present invention includes the following steps:
  • step 1 is performed to provide a semiconductor substrate in which a drift region is formed, a gate structure is formed on a portion of the surface of the semiconductor substrate, and the gate structure covers a portion of the drift region a surface, a source and a drain are respectively formed in the semiconductor substrate on both sides of the gate structure, wherein the drain is disposed in the drift region and spaced apart from the gate structure.
  • a semiconductor 100 is provided.
  • the constituent material of the semiconductor substrate 100 may be undoped single crystal silicon, doped monocrystalline silicon, silicon-on-insulator (SOI), and laminated on insulator. Silicon (SSOI), silicon-on-silicon (S-SiGeOI) on insulator, silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI).
  • the constituent material of the semiconductor substrate 100 is selected from single crystal silicon.
  • the semiconductor substrate 100 may also be a P-type semiconductor substrate or an N-type semiconductor substrate.
  • an N-type high voltage device may select a P-type semiconductor substrate, and a P-type high voltage device may select an N-type semiconductor substrate.
  • the semiconductor substrate 100 is a P-type semiconductor substrate.
  • a shallow trench isolation structure is formed in the semiconductor substrate to define an active region.
  • drift region 101 is provided in the semiconductor substrate 100.
  • the drift region has different conductivity types depending on the type of the LDMOS device. For example, if the LDMOS device is an N-type LDMOS device, the drift region 101 is an N-type drift region, and if the LDMOS device is a P-type LDMOS device, the drift region 101 is a P-type drift region.
  • the doping concentration of the drift region is lower, which is lower than the doping concentration of the source and the drain, which is equivalent to forming a high resistance layer between the source and the drain, which can increase the breakdown voltage and reduce
  • the small parasitic capacitance between the source and the drain helps to improve the frequency characteristics.
  • the drift region 101 may be formed using a suitable method, such as a method of ion implantation, for example, if an N-type high voltage device is prepared, N-type ion doping is performed on a region of the semiconductor substrate 100 where the drift region 101 is predetermined to be formed, To form an N-type drift region in the substrate, if a P-type high voltage device is prepared, the semiconductor substrate 100 is doped with P-type ions to form a P-type drift region.
  • a suitable method such as a method of ion implantation
  • Doping is generally achieved by means of implantation.
  • the drift region has a low doping concentration, which is equivalent to forming a high resistance layer between the source and the drain, which can increase the breakdown voltage and reduce the parasitic capacitance between the source and the drain. Conducive to improve the frequency characteristics.
  • the implanted impurity is phosphorus
  • the implantation dose of the drift region may be 1.0 ⁇ 10 12 to 1.0 ⁇ 10 13 cm -2 .
  • a body region 102 may also be disposed in the semiconductor substrate 100, the body region 102 being located outside the drift region 101 and spaced apart from the drift region, wherein the body region and the drift region have opposite conductivity types. That is, when the drift region is N-type, the body region is P-type, or when the drift region is P-type, the body region is N-type.
  • the body region 102 may also be formed using, for example, ion implantation.
  • a P-type body region is predetermined to be formed, and a P-type dopant impurity such as boron is implanted into a region of the semiconductor substrate where a predetermined body region is formed by ion implantation.
  • a well region is formed in the semiconductor substrate 100 before forming the body region and the drift region, and the body region 102 and the drift region 101 are both disposed in the well region, wherein
  • the well region has the same conductivity type as the drift region 101, and the doping concentration of the well region is lower than the doping concentration of the drift region 102, and the well region and the drift region 102 outside the body region constitute a gradation The drift region of the doping concentration.
  • the body region may be formed first or the drift region may be formed first, and is not specifically limited herein.
  • a gate structure 103 is disposed on a portion of the surface of the semiconductor substrate 100.
  • the gate structure 103 covers the channel region (for example, the surface of the partial body region 102), and further, the gate structure also covers the surface of the partial drift region 101.
  • the gate structure 103 includes a gate dielectric layer 1031 on the surface of the semiconductor substrate 100 and a gate layer 1032 on the gate dielectric layer 1031.
  • the method of forming the gate structure 103 may include the steps of sequentially forming a gate dielectric layer and a gate layer on the semiconductor substrate 100, patterning the gate dielectric layer and the gate layer to form Gate structure 103.
  • the gate dielectric layer 1031 may comprise a conventional dielectric material such as oxides, nitrides and oxynitrides of silicon having a dielectric constant from about 4 to about 20 (measured in vacuum), or the gate dielectric layer may comprise A generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100.
  • Such higher dielectric constant electrolyte materials may include, but are not limited to, cerium oxide, lanthanum silicate, titanium oxide, barium titanate (BSTs), and lead zirconate titanate (PZTs).
  • the gate layer 1032 is made of a polysilicon material. Generally, a metal, a metal nitride, a metal silicide or the like can be used as the material of the gate layer. In this embodiment, the material of the gate layer 1032 includes polysilicon.
  • Preferred methods for forming the gate layer include chemical vapor deposition (CVD), such as low temperature chemical vapor deposition (LTCVD), low pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (LTCVD), and plasma chemical vapor deposition (PECVD).
  • CVD chemical vapor deposition
  • LTCVD low temperature chemical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • LTCVD rapid thermal chemical vapor deposition
  • PECVD plasma chemical vapor deposition
  • a similar method such as sputtering and physical vapor deposition (PVD) can also be used.
  • the thickness of the gate layer may be a suitable thickness depending on the size of the device, and is not specifically limited herein.
  • spacers 104 may also be selectively formed on the sidewalls of the gate structure 103.
  • the spacer 104 may be one of silicon oxide, silicon nitride, silicon oxynitride or a combination thereof.
  • the spacer is composed of silicon oxide and silicon nitride, and the specific process is: forming a first silicon oxide layer, a first silicon nitride layer, and a second oxide on the semiconductor substrate. The silicon layer is then etched to form spacers.
  • ion implantation may also be performed to form a body region lead-out region of the same conductivity type as the body region in the body region, for example, the body region is P-type, and the body region lead-out region may also be P-type, and
  • the impurity doping concentration is greater than the impurity doping concentration of the body region, for example, the body region lead-out region is heavily doped with a P-type impurity.
  • a source electrode 1052 and a drain electrode 1051 are respectively disposed in the semiconductor substrate 100 on both sides of the gate structure 103, wherein the drain electrode 1051 is formed in the drift region 101 and is There is a space between the gate structures 103, the source electrode 1052 is formed in the body region 102, and the source electrode 1052 and the drain and the drift region 101 have the same conductivity type, for example, the drift
  • the region is an N-type drift region, and the drain and the source may be an N-type source and drain, which may also be a source and a drain heavily doped by the N-type dopant ions.
  • the method of forming the source and the drain includes performing source-drain ion implantation on a region of the semiconductor substrate where a source and a drain are predetermined to be formed, respectively, in the semiconductor substrate 100 on both sides of the gate structure 103 a source electrode 1052 and a drain electrode 1051, wherein a patterned photoresist layer exposing a region where a source and a drain are predetermined to be formed may be first formed by using a photolithography process, and the patterned photoresist layer is The mask is subjected to source/drain ion implantation, and finally the patterned photoresist layer is removed by, for example, ashing.
  • an annealing process may also be performed.
  • the annealing may use any annealing treatment method well known to those skilled in the art including, but not limited to, rapid thermal annealing, furnace tube annealing, peak annealing, laser annealing, etc., for example, performing rapid
  • the temperature-up annealing process utilizes a high temperature of 900 to 1050 ° C to activate the dopant in the source/drain regions and simultaneously repair the lattice structure of the surface of the semiconductor substrate damaged in each ion implantation process.
  • a lightly doped drain (LDD) is formed between the source/drain regions and each gate.
  • step two is performed to form a metal silicide blocking layer, wherein the metal silicide blocking layer covers at least a portion of the surface of the semiconductor substrate between the gate structure and the drain.
  • a metal silicide blocking layer 106 covers at least a portion of the surface of the semiconductor substrate 100 between the gate structure 103 and the drain electrode 1051, that is, the gate structure 103 is covered. The surface of the drift region 101 between the drain electrode 1051.
  • the metal silicide blocking layer 106 covers a portion of a top surface of the gate structure 103 and a surface of the semiconductor substrate 100 between the gate structure 103 and the drain electrode 1051, That is, the metal silicide blocking layer 106 covers the surface of the semiconductor substrate 100 between the gate structure 103 and the drain electrode 1051 and extends to a portion of the top surface of the gate structure 103.
  • the metal silicide blocking layer 106 also covers the spacer 104 on a sidewall of the gate structure 103 adjacent to the drain.
  • the metal silicide blocking layer 106 includes an oxide layer, a nitride layer, and an oxynitride layer stacked in this order from bottom to top, the oxide layer including, for example, silicon oxide, the nitride layer, for example A silicon nitride layer is included, and the oxynitride layer includes silicon oxynitride.
  • the thickness of the nitride layer and the oxynitride layer in the metal silicide blocking layer 106 are all smaller than the thickness of the oxide layer.
  • the thickness of the nitride layer may be 350-700.
  • the oxynitride layer may have a thickness of 350 to 700 angstroms, and the oxide layer may have a thickness of 1,000 to 3,000 angstroms, for example, 1000 angstroms, 1,500 angstroms, 2000 angstroms, 2,500 angstroms, 3,000 angstroms, or the like.
  • the metal silicide blocking layer 106 may further include other suitable materials.
  • the metal silicide blocking layer 106 may further include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and carbon doped nitrogen. At least one of a silicon layer or the like.
  • the method of forming the metal silicide blocking layer 106 includes the following steps:
  • a metal silicide blocking material layer 106a is deposited to cover the gate structure 103, the spacers 104, the source electrode 1052, and the drain electrode 1051. Further, the The metal silicide blocking material layer 106a covers the entire surface of the semiconductor substrate, and the metal silicide blocking material layer 106a can be formed by conformal deposition by, for example, chemical vapor deposition, physical vapor deposition, or atomic layer deposition.
  • the metal silicide blocking material layer is patterned to form the metal silicide blocking layer 106.
  • a patterned mask layer such as a patterned photoresist layer, may be first formed on the metal silicide blocking material layer, the patterned mask layer defining a predetermined metal silicide blocking layer 106, Then, using the patterned mask layer as a mask, the metal silicide blocking material layer is etched to stop on the surface of the semiconductor substrate to form the metal silicide blocking layer 106.
  • the etching process may use dry etching. Either wet etching or the like is performed to etch the metal silicide blocking material layer, and finally the patterned mask layer is removed.
  • the finally formed metal silicide blocking layer 106 exposes a portion of the top surface of the gate structure, the drain surface, and the source surface, etc., in order to subsequently form a metal silicide.
  • a metal silicide layer is formed on the exposed surface of the source, the drain and the gate structure.
  • a metal silicide layer 107 is formed on a portion of the surface of the source electrode 1052, the drain electrode 1051, and the gate structure 103, wherein The metal silicide layer 107 may comprise materials of CoSix, NiSix, and PtSix, or a combination thereof.
  • the method of forming the metal silicide layer 107 includes the following steps: First, as shown in FIG. 1D, a metal layer 107a may be deposited, which may include nickel (nickel), cobalt ( Cobalt) and platinum (platinum) or a combination thereof. The substrate is then heated to cause silicidation of the metal layer and the underlying silicon layer, and the metal silicide layer 107 region is thus formed. An etchant that erodes the metal layer but does not attack the metal silicide layer region is then used to remove the unreacted metal layer.
  • an interlayer dielectric layer is formed to cover the gate structure 103, the source electrode 1052, the drain electrode 1051, and the metal silicide blocking layer 106.
  • an interlayer dielectric layer 109 is formed to cover the gate structure 103, the source electrode 1052, the drain electrode 1051, and the metal silicide blocking layer 106, that is, further The interlayer dielectric layer covers all surfaces exposed by the semiconductor substrate, the gate structure 103, the source electrode 1052, the spacers 104, the drain electrode 1051, and the metal silicide blocking layer 106.
  • the interlayer dielectric layer 109 may be a silicon oxide layer, including a material having doped or undoped silicon oxide formed by a thermal CVD fabrication process or a high density plasma (HDP) fabrication process.
  • a layer such as undoped silicon glass (USG), phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG).
  • the interlayer dielectric layer may also be boron-doped or phosphorus-doped spin-on-glass (SOG), phosphorus-doped tetraethoxysilane (PTEOS) or boron-doped. Tetraethoxysilane (BTEOS).
  • the deposited interlayer dielectric layer 109 may also be planarized by a planarization method such as chemical mechanical polishing such that the interlayer dielectric layer 109 has a flat surface.
  • a planarization method such as chemical mechanical polishing such that the interlayer dielectric layer 109 has a flat surface.
  • step three is performed to form a first contact hole on at least a portion of the surface of the metal silicide blocking layer.
  • a first contact hole 1081 is formed on at least a portion of the surface of the metal silicide blocking layer 106.
  • the method further includes the following steps:
  • a second contact hole 1082 is formed on a portion of the surface of the source 1052, the second contact hole 1082 is electrically connected to the source 1052;
  • a third contact hole 1083 is formed on a portion of the surface of the drain electrode 1051, and the third contact hole 1083 is electrically connected to the drain electrode 1051.
  • the method of forming the first contact hole, the second contact hole, and the third contact hole includes the following steps:
  • a patterned mask layer (eg, a patterned photoresist layer) is formed on a surface of the interlayer dielectric layer 109, the patterned mask layer defining a first contact hole and a second formed to be formed. Patterning and position of the contact hole and the third contact hole.
  • the interlayer dielectric layer is etched by using the patterned mask layer as a mask to respectively form a first contact hole, a second contact hole and a third contact hole, wherein when the first contact hole is formed by etching, It may be stopped in the nitride layer in the metal silicide blocking layer 106, that is, may be stopped on the surface of the nitride layer, since the metal silicide blocking layer 106 includes an oxide layer, a nitride layer and a layer which are sequentially stacked from bottom to top.
  • the oxynitride layer, the nitride layer and the oxynitride layer can be used as an etch barrier layer, which can ensure that the first contact hole is not etched into the semiconductor substrate during the etching process, but stops at the nitrogen On the layer. The etching of the second contact hole and the third contact hole is stopped on the surface of the semiconductor substrate.
  • the patterned mask layer is removed, and methods well known to those skilled in the art can be used.
  • the conductive material may be any suitable conductive material well known to those skilled in the art, including but not limited to a metal material, wherein the metal material may include Ag, Au, Cu, Pd, Pt, Cr, Mo, Ti. One or more of Ta, W, and Al.
  • the first contact hole 1081, the second contact hole 1082, and the third contact hole 1083 are filled with the same conductive material, for example, may be filled with copper metal or the like, or may be filled with different conductive materials.
  • a first contact hole 1081 is disposed on a surface of at least a portion of the metal silicide blocking layer 106.
  • the first contact hole 1081 may be partially located on the surface of the metal silicide blocking layer 106 above the gate structure, partially on the surface of the metal silicide blocking layer 106 above the spacer and partially located on the surface On the surface of the metal silicide blocking layer 106 on the surface of the semiconductor substrate between the spacer and the drain, or the first contact hole may be located only between the spacer and the drain On the surface of the metal silicide blocking layer 106 on the surface of the semiconductor substrate, or the first contact hole may also be partially located on the surface of the metal silicide blocking layer 106 above the spacer and partially located in the gap On the surface of the metal silicide blocking layer 106 on the surface of the semiconductor substrate between the wall and the drain.
  • the metal silicide blocking layer 106 includes an oxide layer, a nitride layer, and an oxynitride layer stacked in this order from bottom to top, and the bottom of the first contact hole 1081 is located in the nitride layer.
  • the bottom of the first contact hole 1081 is located on the surface of the nitride layer, so that the electric field of the drift region can be adjusted by adjusting the thickness of the oxide layer under the nitride layer in the metal silicide blocking layer 106. Depleted, which in turn improves device characteristics.
  • a second contact hole 1082 is disposed on a portion of the surface of the source electrode 1052, the second contact hole 1082 is electrically connected to the source electrode 1052, and further, the second contact hole 1082 is electrically A metal silicide layer 107 is connected to the surface of the source electrode 1052 to achieve electrical connection with the source electrode 1052.
  • the second contact hole 1082 and the first contact hole 1081 are electrically connected and grounded, thereby enhancing the depletion of the drift region, thereby increasing the breakdown voltage of the device.
  • the second contact hole 1082 and the first contact hole 1081 may be electrically connected to each other by electrically connecting the same metal layer or metal interconnection structure, or electrically connected together in other suitable manners.
  • a third contact hole 1083 is disposed on a portion of the surface of the drain electrode 1051.
  • the third contact hole 1083 is electrically connected to the drain electrode 1051. Further, the third contact hole 1083 is electrically connected.
  • a metal silicide layer 107 is connected to the surface of the drain electrode 1051 to achieve electrical connection with the drain electrode 1051.
  • the width of the first contact hole 1081 is greater than the width of the second contact hole 1082 and the third contact hole 1083, and the width refers to the first contact hole 1081, The diameters of the second contact hole 1082 and the third contact hole 1083 in the direction of the source and drain lines and their extension lines.
  • the first contact hole 1081 penetrates the interlayer dielectric layer 109 above the metal silicide blocking layer 106, and the second contact hole 1082 penetrates the layer above the source electrode 1052.
  • the interlayer dielectric layer 109 extends through the interlayer dielectric layer 109 above the drain electrode 1051.
  • the LDMOS device formed by the manufacturing method of the present invention includes a metal silicide blocking layer covering at least a portion of the surface of the semiconductor substrate between the gate structure and the drain, and at least partially disposed
  • the first contact hole on the surface of the metal silicide blocking layer further enhances the depletion of the drift region to increase the breakdown voltage of the device, thereby improving the performance of the device.
  • the metal silicide blocking layer 106 includes a bottom layer of the oxide layer, the nitride layer and the oxynitride layer, wherein the bottom of the first contact hole is located in the nitride layer, for example, the bottom of the first contact hole is located in the nitrogen
  • the surface of the layer so that the depletion of the electric field in the drift region can be adjusted by adjusting the thickness of the oxide layer under the nitride layer in the metal silicide blocking layer 106, thereby improving device characteristics, and the LDMOS device of the present invention is at the drain end.
  • the present invention also provides an electronic device comprising the LDMOS device of the first embodiment, the LDMOS device being prepared according to the method described in the second embodiment.
  • the electronic device of this embodiment may be any mobile phone, tablet computer, notebook computer, netbook, game machine, television, VCD, DVD, navigator, digital photo frame, camera, video camera, voice recorder, MP3, MP4, PSP, etc.
  • the product or equipment can also be any intermediate product including circuits.
  • the electronic device of the embodiment of the present invention has better performance due to the use of the above LDMOS device.
  • FIG. 3 shows an example of a mobile phone handset.
  • the mobile phone handset 300 is provided with a display portion 302 included in the housing 301, an operation button 303, an external connection port 304, a speaker 305, a microphone 306, and the like.
  • the mobile phone handset includes the LDMOS device of the first embodiment, and the LDMOS device includes:
  • drift region disposed in the semiconductor substrate
  • a gate structure disposed on a portion of the surface of the semiconductor substrate and covering a portion of the surface of the drift region;
  • a metal silicide blocking layer covering at least a portion of the surface of the semiconductor substrate between the gate structure and the drain;
  • a first contact hole is disposed on a surface of at least a portion of the metal silicide blocking layer.

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Abstract

本发明提供一种LDMOS器件及其制造方法和电子装置，包括：半导体衬底(100)；漂移区(101)，设置在半导体衬底中；栅极结构(103)，设置在半导体衬底的部分表面上，并覆盖部分漂移区的表面；源极(1052)和漏极(1051)，分别设置在栅极结构两侧的半导体衬底中，其中，漏极设置在漂移区内并与栅极结构之间存在间隔；金属硅化物阻挡层(106)，覆盖栅极结构和漏极之间的至少部分半导体衬底的表面；第一接触孔(1081)，设置在至少部分金属硅化物阻挡层的表面上。

Description

一种LDMOS器件及其制造方法和电子装置 技术领域
本发明涉及半导体技术领域，具体而言涉及一种LDMOS器件及其制造方法和电子装置。
背景技术
传统的高压器件结构通常通过调整多晶硅长度，将多晶硅扩展到漂移区的场板氧化层上面充当场板，场板对漂移区进行耗尽形成耗尽层，因此增加了横向耗尽层宽度，进而提高耐压(也即击穿电压)。同时，还需为高压器件漂移区中漏极与栅极之间选择合适的场板氧化层厚度，而所需的场板氧化层厚度皆是单一厚度或者藉由寄生的氧化物(例如，设置在漏极和栅极之间的漂移区中的浅沟槽隔离结构(STI)等)来实现。然而STI的使用虽然能够提高器件的耐压，但是其使导通电阻增大。
因此，在保证器件耐压的前提下，如何尽可能的降低导通电阻，是亟待解决的问题。
发明内容
根据本申请的各种实施例提供一种LDMOS器件及其制造方法和电子装置。
一种LDMOS器件，包括：
半导体衬底；
漂移区，设置在所述半导体衬底中；
栅极结构，设置在所述半导体衬底的部分表面上，并覆盖部分所述漂移区的表面；
源极和漏极，分别设置在所述栅极结构两侧的半导体衬底中，其中，所述漏极设置在所述漂移区内并与所述栅极结构之间存在间隔；
金属硅化物阻挡层，覆盖所述栅极结构和所述漏极之间的至少部分所述半导体衬底的表面；
第一接触孔，设置在至少部分所述金属硅化物阻挡层的表面上。
此外，还提供了一种LDMOS器件的制造方法，包括：
提供半导体衬底，在所述半导体衬底中形成有漂移区，在所述半导体衬底的部分表面上形成有栅极结构，所述栅极结构覆盖部分所述漂移区的表面，在所述栅极结构两侧的半导体衬底中分别形成有源极和漏极，其中，所述漏极设置在所述漂移区内并与所述栅极结构之间存在间隔；
形成金属硅化物阻挡层，其中，所述金属硅化物阻挡层覆盖所述栅极结构和所述漏极之间的至少部分所述半导体衬底的表面；
在至少部分所述金属硅化物阻挡层的表面上形成第一接触孔。
此外，还提供一种电子装置，所述电子装置包括前述的LDMOS器件。
本发明的一个或多个实施例的细节在下面的附图和描述中提出。本发明的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1A至图1G示出了本发明一个实施方式的LDMOS器件的制造方法的相关步骤所获得的器件的剖面示意图；
图2示出了本发明一个实施方式的LDMOS器件的制造方法的工艺流程图；
图3示出了本发明一实施例中的电子装置的示意图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技 术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
为了彻底理解本发明，将在下列的描述中提出详细步骤以及结构，以便阐释本发明提出的技术方案。本发明的较佳实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。
为了解决前述的技术问题，本发明提供一种LDMOS器件，所述LDMOS器件主要包括：
半导体衬底；
漂移区，设置在所述半导体衬底中；
栅极结构，设置在所述半导体衬底的部分表面上，并覆盖部分所述漂移区的表面；
源极和漏极，分别设置在所述栅极结构两侧的半导体衬底中，其中，所述漏极设置在所述漂移区内并与所述栅极结构之间存在间隔；
金属硅化物阻挡层，覆盖所述栅极结构和所述漏极之间的至少部分所述半导体衬底的表面；
第一接触孔，设置在至少部分所述金属硅化物阻挡层的表面上。
综上所述，本发明的LDMOS器件包括金属硅化物阻挡层，其覆盖栅极结构和所述漏极之间的至少部分所述半导体衬底的表面，以及设置在至少部分所述金属硅化物阻挡层的表面上的第一接触孔，进而增强漂移区的耗尽来提高器件的击穿电压，进而提高器件的性能，另外本发明的LDMOS器件在漏端的漂移区内无需设置浅沟槽隔离结构，因此，大大降低了器件的导通电阻。
实施例一
下面，参考图1G对本发明的LDMOS器件做详细解释和说明。
作为示例，本发明的LDMOS器件包括：半导体衬底100。半导体衬底100的构成材料可以采用未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。作为示例，在本实施 例中，半导体衬底100的构成材料选用单晶硅。
所述半导体衬底100还可以为P型半导体衬底或者N型半导体衬底，例如N型高压器件则可选择使用P型半导体衬底，而P型高压器件则可选择使用N型半导体衬底，本实施例中，所述半导体衬底100为P型半导体衬底。
示例性地，在所述半导体衬底中形成有浅沟槽隔离结构(STI)，以定义有源区。
示例性地，在所述半导体衬底100中设置有漂移区101。
根据具体的LDMOS器件的类型所述漂移区具有不同的导电类型，例如，若LDMOS器件为N型LDMOS器件，则漂移区101为N型漂移区，若LDMOS器件为P型LDMOS器件，则漂移区101为P型漂移区。
一般来说，漂移区的掺杂浓度较低，其低于源极和漏极的掺杂浓度，相当于在源极和漏极之间形成一个高阻层，能够提高击穿电压，并减小了源极和漏极之间的寄生电容，有利于提高频率特性。
在一个示例中，还可在半导体衬底100中设置有体区102，体区102位于所述漂移区101的外侧，并与漂移区间隔，其中，体区和漂移区具有相反的导电类型，也即，漂移区为N型时，体区为P型，或者，漂移区为P型时，体区为N型。
示例性地，所述半导体衬底100中还设置有阱区，所述体区102和所述漂移区101均设置在所述阱区中，其中，该阱区具有和所述漂移区101相同的导电类型，并且该阱区的掺杂浓度低于所述漂移区102的掺杂浓度，体区外侧的该阱区和漂移区102构成具有渐变的掺杂浓度的漂移区。
还可在半导体衬底100中形成其他的阱区等，在此不做赘述。
在一个示例中，在所述半导体衬底100的部分表面上设置有栅极结构103。
其中，所述栅极结构103覆盖沟道区(例如部分体区102的表面)，进一步地，栅极结构还覆盖部分漂移区101的表面。示例性地，栅极结构103包括位于半导体衬底100表面上的栅极介电层1031以及位于栅极介电层1031上的栅极层1032。
在一实施例中，栅极介电层1031可以包括传统的电介质材料诸如具有电介质常数从大约4到大约20(真空中测量)的硅的氧化物、氮化物和氮氧化物，或者，栅极介电层可以包括具有电介质常数从大约20到至少大约100的通常较高电介质常数电介质材料。这种较高电介质常数电解质材料可以包括但不 限于：氧化铪、硅酸铪、氧化钛、钛酸锶钡(BSTs)和锆钛酸铅(PZTs)。栅极层1032由多晶硅材料组成，一般也可使用金属、金属氮化物、金属硅化物或类似化合物作为栅极层的材料，本实施例中，所述栅极层1032的材料包括多晶硅。
在一个示例中，在所述栅极结构103的侧壁上形成间隙壁104。所述间隙壁可以为氧化硅、氮化硅、氮氧化硅中一种或者它们组合构成。
在一个示例中，在所述栅极结构103两侧的半导体衬底100中分别设置有源极1052和漏极1051，其中，所述漏极1051形成在所述设置在所述漂移区101内并与所述栅极结构103之间存在间隔，所述源极1052形成在所述体区102中，所述源极1052以及所述漏极1051和所述漂移区101具有相同的导电类型，例如，所述漂移区为N型漂移区，所述漏极和所述源极则可以为N型源极和漏极，其还可以为N型掺杂离子重掺杂的源极和漏极。
更进一步地，所述漏极1051与邻近该漏极的所述间隙壁104之间存在间隔。
在一个示例中，在体区中形成有与体区导电类型相同的体区引出区(未示出)，例如，体区为P型，则体区引出区则也可以为P型，且其杂质掺杂浓度大于体区的杂质掺杂浓度，例如体区引出区为P型杂质重掺杂。
示例性地，所述漂移区的表面、所述源极、所述漏极、所述体区的表面均和所述半导体衬底的表面齐平。
在一个示例中，所述LDMOS器件还包括金属硅化物阻挡层106，其覆盖所述栅极结构103和所述漏极1051之间的至少部分所述半导体衬底100的表面，也即覆盖栅极结构103和漏极1051之间的漂移区101的表面。
在一个示例中，所述金属硅化物阻挡层106覆盖部分所述栅极结构103的顶面以及所述栅极结构103和所述漏极1051之间的所述半导体衬底100的表面，也即，所述金属硅化物阻挡层106覆盖所述栅极结构103和所述漏极1051之间的所述半导体衬底100的表面并延伸到部分所述栅极结构103的顶面上，在所述栅极结构103的侧壁上形成有间隙壁104时，所述金属硅化物阻挡层106还覆盖与所述漏极邻近的栅极结构103一侧壁上的间隙壁104。
在一个示例中，所述金属硅化物阻挡层106包括自下而上依次层叠的氧化物层、氮化物层和氮氧化物层，所述氧化物层例如包括氧化硅、所述氮化物层例如包括氮化硅、所述氮氧化物层包括氮氧化硅。
示例性地，金属硅化物阻挡层106中的所述氮化物层的厚度、所述氮氧 化物层的厚度均小于所述氧化物层的厚度，例如，所述氮化物层的厚度可以为350～700埃，所述氮氧化物层的厚度可以为350～700埃，所述氧化物层的厚度可以包括1000～3000埃，例如1000埃、1500埃、2000埃、2500埃、3000埃等。
值得一提的是，所述金属硅化物阻挡层106还可以包括其他适合的材料，例如金属硅化物阻挡层106还可以包括氧化硅层、氮化硅层、氮氧化硅层和掺碳的氮化硅层等中的至少一种。
在一个示例中，为了降低接触电阻，在所述源极1052、所述漏极1051和所述栅极结构103的部分表面上形成有金属硅化物层107，其中，所述金属硅化物层107可以包括CoSix、NiSix及PtSix或其组合的材料。
在一个示例中，在至少部分所述金属硅化物阻挡层106的表面上有第一接触孔1081。其中，所述第一接触孔1081可以部分位于所述栅极结构上方的金属硅化物阻挡层106的表面上，部分位于所述间隙壁上方的金属硅化物阻挡层106的表面上以及部分位于所述间隙壁和所述漏极之间的半导体衬底表面上的金属硅化物阻挡层106的表面上，或者，所述第一接触孔1081还可以仅位于所述间隙壁和所述漏极之间的半导体衬底表面上的金属硅化物阻挡层106的表面上，或者，所述第一接触孔1081还可以部分位于所述间隙壁上方的金属硅化物阻挡层106的表面上以及部分位于所述间隙壁和所述漏极之间的半导体衬底表面上的金属硅化物阻挡层106的表面上。
在一个示例中，所述金属硅化物阻挡层106包括自下而上依次层叠的氧化物层、氮化物层和氮氧化物层，则所述第一接触孔1081的底部位于所述氮化物层中，例如，所述第一接触孔1081的底部位于所述氮化物层的表面，这样可以通过调整金属硅化物阻挡层106中的氮化物层下方的氧化物层的厚度来调节漂移区电场的耗尽，进而改善器件特性。
在一个示例中，在所述源极1052的部分表面上设置有第二接触孔1082，所述第二接触孔1082电连接所述源极1052，更进一步地，所述第二接触孔1082电连接所述源极1052表面的金属硅化物层107，以实现和所述源极1052的电连接。
进一步地，所述第二接触孔1082和所述第一接触孔1081电连接在一起并接地，进而可以增强对漂移区的耗尽，进而提升器件的击穿电压。
其中，第二接触孔1082和第一接触孔1081可以通过电连接相同的金属层或者金属互连结构的方式实现两者之间的电连接，或者其他适合的方式电 连接在一起。
在一个示例中，在所述漏极1051的部分表面上设置有第三接触孔1083，所述第三接触孔1083电连接所述漏极1051，更进一步地，所述第三接触孔1083电连接所述漏极1051表面的金属硅化物层107，以实现和所述漏极1051的电连接。
在一个示例中，所述第一接触孔1081、第二接触孔1082和第三接触孔1083中填充有导电材料，其中，所述导电材料可以为本领域技术人员熟知的任何适合的导电材料，包括但不限于金属材料，其中，所述金属材料可以包括Ag、Au、Cu、Pd、Pt、Cr、Mo、Ti、Ta、W和Al中的一种或几种。
其中，所述第一接触孔1081、第二接触孔1082和第三接触孔1083中填充有相同的导电材料，例如可均填充有铜金属等，也可以填充有不同的导电材料。
在一个示例中，为了增强漂移区的耗尽，第一接触孔1081的宽度大于所述第二接触孔1082和所述第三接触孔1083的宽度，该宽度是指第一接触孔1081、所述第二接触孔1082和所述第三接触孔1083在源极和漏极连线及其延长线方向上的直径。
在一个示例中，LDMOS器件还包括层间介电层109，所述层间介电层109覆盖所述栅极结构103、所述源极1052、所述漏极1051以及所述金属硅化物阻挡层106以及露出的半导体衬底的表面，所述第一接触孔1081贯穿所述金属硅化物阻挡层106上方的所述层间介电层109，所述第二接触孔1082贯穿所述源极1052上方的所述层间介电层109，所述第三接触孔1083贯穿所述漏极1051上方的所述层间介电层109。
所述层间介电层109可为氧化硅层，包括利用热化学气相沉积(thermal CVD)制造工艺或高密度等离子体(HDP)制造工艺形成的有掺杂或未掺杂的氧化硅的材料层，例如未经掺杂的硅玻璃(USG)、磷硅玻璃(PSG)或硼磷硅玻璃(BPSG)。此外，层间介电层也可以是掺杂硼或掺杂磷的自旋涂布式玻璃(spin-on-glass，SOG)、掺杂磷的四乙氧基硅烷(PTEOS)或掺杂硼的四乙氧基硅烷(BTEOS)。
至此完成了对本发明的LDMOS器件的关键结构的说明，对于完整的器件结构还包括其他的部件，在此不做一一赘述。
综上所述，本发明的LDMOS器件包括金属硅化物阻挡层，其覆盖栅极结构和所述漏极之间的至少部分所述半导体衬底的表面，以及设置在至少部 分所述金属硅化物阻挡层的表面上的第一接触孔，进而增强漂移区的耗尽来提高器件的击穿电压，进而提高器件的性能，进一步地，所述金属硅化物阻挡层106包括自下而上依次层叠的氧化物层、氮化物层和氮氧化物层，则所述第一接触孔的底部位于所述氮化物层中，例如，所述第一接触孔的底部位于所述氮化物层的表面，这样可以通过调整金属硅化物阻挡层106中的氮化物层下方的氧化物层的厚度来调节漂移区电场的耗尽，进而改善器件特性，另外，本发明的LDMOS器件在漏端的漂移区内无需设置浅沟槽隔离结构，因此，大大降低了器件的导通电阻。
实施例二
本发明还提供一种前述实施例一中的LDMOS器件的制造方法，作为示例，如图2所示，本发明的半导体器件的制造方法主要包括以下步骤：
步骤S1，提供半导体衬底，在所述半导体衬底中形成有漂移区，在所述半导体衬底的部分表面上形成有栅极结构，所述栅极结构覆盖部分所述漂移区的表面，在所述栅极结构两侧的半导体衬底中分别形成有源极和漏极，其中，所述漏极设置在所述漂移区内并与所述栅极结构之间存在间隔；
步骤S2，形成金属硅化物阻挡层，其中，所述金属硅化物阻挡层覆盖所述栅极结构和所述漏极之间的至少部分所述半导体衬底的表面；
步骤S3，在至少部分所述金属硅化物阻挡层的表面上形成第一接触孔。
下面参考图1A至图1G、图2对本发明的LDMOS器件的制造方法做详细描述，其中，图1A至图1G示出了本发明一个实施方式的LDMOS器件的制造方法的相关步骤所获得的器件的剖面示意图；图2示出了本发明一个实施方式的LDMOS器件的制造方法的工艺流程图。
具体地，本发明的LDMOS器件的制造方法包括以下步骤：
首先，执行步骤一，提供半导体衬底，在所述半导体衬底中形成有漂移区，在所述半导体衬底的部分表面上形成有栅极结构，所述栅极结构覆盖部分所述漂移区的表面，在所述栅极结构两侧的半导体衬底中分别形成有源极和漏极，其中，所述漏极设置在所述漂移区内并与所述栅极结构之间存在间隔。
示例性地，如图1A所示，提供半导体100，半导体衬底100的构成材料可以采用未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅 (SiGeOI)以及绝缘体上锗(GeOI)等。作为示例，在本实施例中，半导体衬底100的构成材料选用单晶硅。
所述半导体衬底100还可以为P型半导体衬底或者N型半导体衬底，例如N型高压器件则可选择使用P型半导体衬底，而P型高压器件则可选择使用N型半导体衬底，本实施例中，所述半导体衬底100为P型半导体衬底。
示例性地，在所述半导体衬底中形成有浅沟槽隔离结构(STI)，以定义有源区。
示例性地，在所述半导体衬底100中设置有漂移区101。
根据具体的LDMOS器件的类型所述漂移区具有不同的导电类型，例如，若LDMOS器件为N型LDMOS器件，则漂移区101为N型漂移区，若LDMOS器件为P型LDMOS器件，则漂移区101为P型漂移区。
一般来说，漂移区的掺杂浓度较低，其低于源极和漏极的掺杂浓度，相当于在源极和漏极之间形成一个高阻层，能够提高击穿电压，并减小了源极和漏极之间的寄生电容，有利于提高频率特性。
可以使用合适的方法形成所述漂移区101，例如离子注入的方法，例如，若制备N型高压器件，则对所述半导体衬底100中预定形成漂移区101的区域进行N型离子掺杂，以在衬底内形成N型漂移区，若制备P型高压器件，则对半导体衬底100进行P型离子掺杂，形成P型漂移区。
掺杂一般是通过注入的方法实现。所需要的掺杂浓度越高，则注入过程中的注入剂量相应地也应该越高。一般来说，漂移区的掺杂浓度较低，相当于在源极和漏极之间形成一个高阻层，能够提高击穿电压，并减小了源极和漏极之间的寄生电容，有利于提高频率特性。例如，在根据本发明的一个实施例中，注入杂质为磷，漂移区的注入剂量可以为1.0×10 12～1.0×10 13cm -2。
在一个示例中，还可在半导体衬底100中设置有体区102，体区102位于所述漂移区101的外侧，并与漂移区间隔，其中，体区和漂移区具有相反的导电类型，也即，漂移区为N型时，体区为P型，或者，漂移区为P型时，体区为N型。也可以使用例如离子注入的方法形成所述体区102，例如，预定形成P型体区，则通过离子注入向半导体衬底的预定形成体区的区域注入P型掺杂杂质例如硼。
示例性地，在形成所述体区和所述漂移区之前，在所述半导体衬底100中形成阱区，所述体区102和所述漂移区101均设置在所述阱区中，其中，该阱区具有和所述漂移区101相同的导电类型，并且该阱区的掺杂浓度低于 所述漂移区102的掺杂浓度，体区外侧的该阱区和漂移区102构成具有渐变的掺杂浓度的漂移区。
还可在半导体衬底100中形成其他的阱区等，在此不做赘述。
值得一提的是，可以先形成所述体区也可以先形成所述漂移区，在此不作具体限定。
在一个示例中，在所述半导体衬底100的部分表面上设置有栅极结构103。
其中，所述栅极结构103覆盖沟道区(例如部分体区102的表面)，进一步地，栅极结构还覆盖部分漂移区101的表面。示例性地，栅极结构103包括位于半导体衬底100表面上的栅极介电层1031以及位于栅极介电层1031上的栅极层1032。
在一个示例中，形成栅极结构103的方法可以包括以下步骤：在半导体衬底100上依次形成栅极介电层和栅极层，图案化栅极介电层和所述栅极层以形成栅极结构103。栅极介电层1031可以包括传统的电介质材料诸如具有电介质常数从大约4到大约20(真空中测量)的硅的氧化物、氮化物和氮氧化物，或者，栅极介电层可以包括具有电介质常数从大约20到至少大约100的通常较高电介质常数电介质材料。这种较高电介质常数电解质材料可以包括但不限于：氧化铪、硅酸铪、氧化钛、钛酸锶钡(BSTs)和锆钛酸铅(PZTs)。栅极层1032由多晶硅材料组成，一般也可使用金属、金属氮化物、金属硅化物或类似化合物作为栅极层的材料，本实施例中，所述栅极层1032的材料包括多晶硅。
栅极层优选的形成方法包括化学气相沉积法(CVD)，如低温化学气相沉积(LTCVD)、低压化学气相沉积(LPCVD)、快热化学气相沉积(LTCVD)、等离子体化学气相沉积(PECVD)，也可使用例如溅镀及物理气相沉积(PVD)等一般相似方法。栅极层的厚度可以根据器件的尺寸使用适合的厚度，在此不做具体限制。
在一个示例中，在形成栅极结构之后，还可选择性地，在所述栅极结构103的侧壁上形成间隙壁104。所述间隙壁104可以为氧化硅、氮化硅、氮氧化硅中一种或者它们组合构成。作为本实施例的一中实施方式，所述间隙壁为氧化硅、氮化硅共同组成，具体工艺为：在半导体衬底上形成第一氧化硅层、第一氮化硅层以及第二氧化硅层，然后采用蚀刻方法形成间隙壁。
示例性地，随后，还可以进行离子注入，在体区中形成与体区导电类型 相同的体区引出区，例如，体区为P型，则体区引出区则也可以为P型，且其杂质掺杂浓度大于体区的杂质掺杂浓度，例如体区引出区为P型杂质重掺杂。
在一个示例中，在所述栅极结构103两侧的半导体衬底100中分别设置有源极1052和漏极1051，其中，所述漏极1051形成在所述漂移区101内并与所述栅极结构103之间存在间隔，所述源极1052形成在所述体区102中，所述源极1052以及所述漏极和所述漂移区101具有相同的导电类型，例如，所述漂移区为N型漂移区，所述漏极和所述源极则可以为N型源极和漏极，其还可以为N型掺杂离子重掺杂的源极和漏极。
更进一步地，所述漏极1051与邻近该漏极的所述间隙壁104之间存在间隔。
其中，形成所述源极和漏极的方法包括对半导体衬底中预定形成源极和漏极的区域执行源漏离子注入，在所述栅极结构103两侧的半导体衬底100中分别设置有源极1052和漏极1051，其中，可以通过利用光刻工艺首先形成暴露出预定形成源极和漏极的区域的图案化的光刻胶层，再以该图案化的光刻胶层为掩膜，进行源漏离子注入，最后利用例如灰化的方法去除所述图案化的光刻胶层。
随后，还可以进行退火工艺，示例性地，退火可以使用本领域技术人员熟知的任何的退火处理方法，包括但不限于快速热退火、炉管退火、峰值退火、激光退火等，例如，进行快速升温退火工艺，利用900至1050℃的高温来活化源极/漏极区域内的掺杂质，并同时修补在各离子注入工艺中受损的半导体衬底表面的晶格结构。此外，亦可视产品需求及功能性考量，另于源极/漏极区域与各栅极之间分别形成轻掺杂漏极(LDD)。
接着，执行步骤二，形成金属硅化物阻挡层，其中，所述金属硅化物阻挡层覆盖所述栅极结构和所述漏极之间的至少部分所述半导体衬底的表面。
示例性地，如图1C所示，金属硅化物阻挡层106覆盖所述栅极结构103和所述漏极1051之间的至少部分所述半导体衬底100的表面，也即覆盖栅极结构103和漏极1051之间的漂移区101的表面。
在一个示例中，所述金属硅化物阻挡层106覆盖部分所述栅极结构103的顶面以及所述栅极结构103和所述漏极1051之间的所述半导体衬底100的表面，也即，所述金属硅化物阻挡层106覆盖所述栅极结构103和所述漏极 1051之间的所述半导体衬底100的表面并延伸到部分所述栅极结构103的顶面上，在所述栅极结构103的侧壁上形成有间隙壁104时，所述金属硅化物阻挡层106还覆盖与所述漏极邻近的栅极结构103一侧壁上的间隙壁104。
在一个示例中，所述金属硅化物阻挡层106包括自下而上依次层叠的氧化物层、氮化物层和氮氧化物层，所述氧化物层例如包括氧化硅、所述氮化物层例如包括氮化硅、所述氮氧化物层包括氮氧化硅。
示例性地，金属硅化物阻挡层106中的所述氮化物层、所述氮氧化物层的厚度均小于所述氧化物层的厚度，例如，所述氮化物层的厚度可以为350～700埃，所述氮氧化物层的厚度可以为350～700埃，所述氧化物层的厚度可以包括1000～3000埃，例如1000埃、1500埃、2000埃、2500埃、3000埃等。
值得一提的是，所述金属硅化物阻挡层106还可以包括其他适合的材料，例如金属硅化物阻挡层106还可以包括氧化硅层、氮化硅层、氮氧化硅层和掺碳的氮化硅层等中的至少一种。
在一个示例中，如图1B和图1C所示，形成所述金属硅化物阻挡层106的方法包括以下步骤：
首先，如图1B所示，沉积形成金属硅化物阻挡材料层106a，以覆盖所述栅极结构103、所述间隙壁104、所述源极1052和所述漏极1051，进一步地，所述金属硅化物阻挡材料层106a覆盖整个半导体衬底的表面，可通过例如化学气相沉积、物理气相沉积或原子层沉积的方法共形沉积形成所述金属硅化物阻挡材料层106a。
接着，如图1C所示，图案化所述金属硅化物阻挡材料层，以形成所述金属硅化物阻挡层106。
具体地，可首先在所述金属硅化物阻挡材料层上形成图案化的掩膜层，例如图案化的光刻胶层，该图案化的掩膜层定义预定形成的金属硅化物阻挡层106，然后以图案化的掩膜层为掩膜，蚀刻所述金属硅化物阻挡材料层停止于所述半导体衬底的表面，以形成所述金属硅化物阻挡层106，该蚀刻工艺可以使用干法蚀刻或者湿法蚀刻等方法实现对金属硅化物阻挡材料层的蚀刻，最后去除图案化的掩膜层。
其中，最终形成的金属硅化物阻挡层106露出了部分栅极结构顶面、漏极表面以及源极表面等，以便于后续形成金属硅化物。
随后，在所述源极、所述漏极和所述栅极结构露出的表面上形成金属硅 化物层。
在一个示例中，如图1D所示，为了降低接触电阻，在所述源极1052、所述漏极1051和所述栅极结构103的部分表面上形成有金属硅化物层107，其中，所述金属硅化物层107可以包括CoSix、NiSix及PtSix或其组合的材料。
在一个示例中，如图1D至1E所示，形成所述金属硅化物层107的方法包括以下步骤：首先，如图1D所示，沉积金属层107a，其可包含镍(nickel)、钴(cobalt)及铂(platinum)或其组合的材料。接着加热衬底，造成金属层与其下的硅层发生硅化作用，金属硅化物层107区域因而形成。接着使用可侵蚀金属层，但不致侵蚀金属硅化层区域的蚀刻剂，以将未反应的金属层除去。
随后，形成层间介电层，以覆盖所述栅极结构103、所述源极1052、所述漏极1051以及所述金属硅化物阻挡层106。
具体地，如图1F所示，形成层间介电层109，以覆盖所述栅极结构103、所述源极1052、所述漏极1051以及所述金属硅化物阻挡层106，也即进一步地，层间介电层覆盖半导体衬底露出的所有表面、所述栅极结构103、所述源极1052、间隙壁104、所述漏极1051以及所述金属硅化物阻挡层106。
所述层间介电层109可为氧化硅层，包括利用热化学气相沉积(thermal CVD)制造工艺或高密度等离子体(HDP)制造工艺形成的有掺杂或未掺杂的氧化硅的材料层，例如未经掺杂的硅玻璃(USG)、磷硅玻璃(PSG)或硼磷硅玻璃(BPSG)。此外，层间介电层也可以是掺杂硼或掺杂磷的自旋涂布式玻璃(spin-on-glass，SOG)、掺杂磷的四乙氧基硅烷(PTEOS)或掺杂硼的四乙氧基硅烷(BTEOS)。
示例性地，还可以通过平坦化的方法(例如化学机械研磨)对沉积的层间介电层109进行平坦化，以使层间介电层109具有平坦的表面。
接着，执行步骤三，在至少部分所述金属硅化物阻挡层的表面上形成第一接触孔。
具体地，如图1G所示，在至少部分所述金属硅化物阻挡层106的表面上形成第一接触孔1081。
在一个示例中，在形成所述第一接触孔的步骤中，还包括以下步骤：
在所述源极1052的部分表面上形成第二接触孔1082，所述第二接触孔1082电连接所述源极1052；
在所述漏极1051的部分表面上形成第三接触孔1083，所述第三接触孔1083电连接所述漏极1051。
在一个示例中，形成所述第一接触孔、所述第二接触孔和所述第三接触孔的方法包括以下步骤：
首先，在所述层间介电层109的表面上形成图案化的掩膜层(例如图案化的光刻胶层)，该图案化的掩膜层定义预定形成的第一接触孔、第二接触孔和第三接触孔的图案化以及位置等。
接着，以图案化的掩膜层为掩膜，蚀刻所述层间介电层，以分别形成第一接触孔、第二接触孔和第三接触孔，其中，蚀刻形成第一接触孔时，可停止在金属硅化物阻挡层106中的氮化物层中，也即可以停止在氮化物层的表面，由于金属硅化物阻挡层106包括自下而上依次层叠的氧化物层、氮化物层和氮氧化物层，氮化物层和氮氧化物层可以用作刻蚀阻挡层，这样能够保证在第一接触孔的刻蚀过程中不会被刻蚀到半导体衬底中，而是停止在氮化物层上。其中第二接触孔和第三接触孔的刻蚀停止在半导体衬底的表面上。
随后，去除图案化的掩膜层，可以使用本领域技术人员熟知的方法。
随后，形成导电材料填充所述第一接触孔、第二接触孔和第三接触孔，以形成最终的第一接触孔1081、第二接触孔1082和第三接触孔1083。其中，所述导电材料可以为本领域技术人员熟知的任何适合的导电材料，包括但不限于金属材料，其中，所述金属材料可以包括Ag、Au、Cu、Pd、Pt、Cr、Mo、Ti、Ta、W和Al中的一种或几种。
其中，所述第一接触孔1081、第二接触孔1082和第三接触孔1083中填充有相同的导电材料，例如可均填充有铜金属等，也可以填充有不同的导电材料。
在一个示例中，在至少部分所述金属硅化物阻挡层106的表面上设置有第一接触孔1081。其中，所述第一接触孔1081可以部分位于所述栅极结构上方的金属硅化物阻挡层106的表面上，部分位于所述间隙壁上方的金属硅化物阻挡层106的表面上以及部分位于所述间隙壁和所述漏极之间的半导体衬底表面上的金属硅化物阻挡层106的表面上，或者，所述第一接触孔还可以仅位于所述间隙壁和所述漏极之间的半导体衬底表面上的金属硅化物阻挡层106的表面上，或者，所述第一接触孔还可以部分位于所述间隙壁上方的金属硅化物阻挡层106的表面上以及部分位于所述间隙壁和所述漏极之间的半导体衬底表面上的金属硅化物阻挡层106的表面上。
在一个示例中，所述金属硅化物阻挡层106包括自下而上依次层叠的氧化物层、氮化物层和氮氧化物层，则所述第一接触孔1081的底部位于所述氮化物层中，例如，所述第一接触孔1081的底部位于所述氮化物层的表面，这样可以通过调整金属硅化物阻挡层106中的氮化物层下方的氧化物层的厚度来调节漂移区电场的耗尽，进而改善器件特性。
在一个示例中，在所述源极1052的部分表面上设置有第二接触孔1082，所述第二接触孔1082电连接所述源极1052，更进一步地，所述第二接触孔1082电连接所述源极1052表面的金属硅化物层107，以实现和所述源极1052的电连接。
进一步地，所述第二接触孔1082和所述第一接触孔1081电连接在一起并接地，进而可以增强对漂移区的耗尽，进而提升器件的击穿电压。
其中，第二接触孔1082和第一接触孔1081可以通过电连接相同的金属层或者金属互连结构的方式实现两者之间的电连接，或者其他适合的方式电连接在一起。
在一个示例中，在所述漏极1051的部分表面上设置有第三接触孔1083，所述第三接触孔1083电连接所述漏极1051，更进一步地，所述第三接触孔1083电连接所述漏极1051表面的金属硅化物层107，以实现和所述漏极1051的电连接。
在一个示例中，为了增强漂移区的耗尽，第一接触孔1081的宽度大于所述第二接触孔1082和所述第三接触孔1083的宽度，该宽度是指第一接触孔1081、所述第二接触孔1082和所述第三接触孔1083在源极和漏极连线及其延长线方向上的直径。
在一个示例中，所述第一接触孔1081贯穿所述金属硅化物阻挡层106上方的所述层间介电层109，所述第二接触孔1082贯穿所述源极1052上方的所述层间介电层109，所述第三接触孔1083贯穿所述漏极1051上方的所述层间介电层109。
至此完成了对本发明的LDMOS器件的制造方法的关键步骤的说明，对于完整的器件结构制备还可能需要其他的步骤，在此不做一一赘述。
综上所述，通过本发明的制造方法形成的LDMOS器件包括金属硅化物阻挡层，其覆盖栅极结构和所述漏极之间的至少部分所述半导体衬底的表面，以及设置在至少部分所述金属硅化物阻挡层的表面上的第一接触孔，进而增强漂移区的耗尽来提高器件的击穿电压，进而提高器件的性能，进一步地， 所述金属硅化物阻挡层106包括自下而上依次层叠的氧化物层、氮化物层和氮氧化物层，则所述第一接触孔的底部位于所述氮化物层中，例如，所述第一接触孔的底部位于所述氮化物层的表面，这样可以通过调整金属硅化物阻挡层106中的氮化物层下方的氧化物层的厚度来调节漂移区电场的耗尽，进而改善器件特性，另外本发明的LDMOS器件在漏端的漂移区内无需设置浅沟槽隔离结构，因此，大大降低了器件的导通电阻，并且本发明的方法无需增加光刻版，也不用重复利用光刻版来增加工艺步骤，工艺简单，容易控制。
实施例三
本发明还提供了一种电子装置，包括实施例一所述的LDMOS器件，所述LDMOS器件根据实施例二所述方法制备得到。
本实施例的电子装置，可以是手机、平板电脑、笔记本电脑、上网本、游戏机、电视机、VCD、DVD、导航仪、数码相框、照相机、摄像机、录音笔、MP3、MP4、PSP等任何电子产品或设备，也可为任何包括电路的中间产品。本发明实施例的电子装置，由于使用了上述的LDMOS器件，因而具有更好的性能。
其中，图3示出移动电话手机的示例。移动电话手机300被设置有包括在外壳301中的显示部分302、操作按钮303、外部连接端口304、扬声器305、话筒306等。
其中所述移动电话手机包括实施例一所述的LDMOS器件，所述LDMOS器件包括：
半导体衬底；
漂移区，设置在所述半导体衬底中；
栅极结构，设置在所述半导体衬底的部分表面上，并覆盖部分所述漂移区的表面；
源极和漏极，分别设置在所述栅极结构两侧的半导体衬底中，其中，所述漏极设置在所述漂移区内并与所述栅极结构之间存在间隔；
金属硅化物阻挡层，覆盖所述栅极结构和所述漏极之间的至少部分所述半导体衬底的表面；
第一接触孔，设置在至少部分所述金属硅化物阻挡层的表面上。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未 对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种LDMOS器件，包括：
    半导体衬底；
    漂移区，设置在所述半导体衬底中；
    栅极结构，设置在所述半导体衬底的部分表面上，并覆盖部分所述漂移区的表面；
    源极和漏极，分别设置在所述栅极结构两侧的半导体衬底中，其中，所述漏极设置在所述漂移区内并与所述栅极结构之间存在间隔；
    金属硅化物阻挡层，覆盖所述栅极结构和所述漏极之间的至少部分所述半导体衬底的表面；
    第一接触孔，设置在至少部分所述金属硅化物阻挡层的表面上。
  2. 如权利要求1所述的LDMOS器件，其中，所述金属硅化物阻挡层覆盖部分所述栅极结构的顶面以及所述栅极结构和所述漏极之间的所述半导体衬底的表面。
  3. 如权利要求1所述的LDMOS器件，其中，所述金属硅化物阻挡层包括自下而上依次层叠的氧化物层、氮化物层和氮氧化物层，所述第一接触孔的底部位于所述氮化物层中。
  4. 如权利要求3所述的LDMOS器件，其中，所述氮化物层和所述氮氧化物层的厚度均小于所述氧化物层的厚度。
  5. 如权利要求1所述的LDMOS器件，其中，
    在所述源极的部分表面上设置有第二接触孔，所述第二接触孔电连接所述源极；
    在所述漏极的部分表面上设置有第三接触孔，所述第三接触孔电连接所述漏极。
  6. 如权利要5所述的LDMOS器件，其中，所述第一接触孔的宽度大于所述第二接触孔和所述第三接触孔的宽度。
  7. 如权利要求5所述的LDMOS器件，其中，所述第一接触孔和所述第二接触孔电连接并均接地。
  8. 如权利要求5所述的LDMOS器件，其中，还包括层间介电层，所述层间介电层覆盖所述栅极结构、所述源极、所述漏极以及所述金属硅化物阻 挡层，所述第一接触孔贯穿所述金属硅化物层上方的所述层间介电层，所述第二接触孔贯穿所述源极上方的所述层间介电层，所述第三接触孔贯穿所述漏极上方的所述层间介电层。
  9. 如权利要求1所述的LDMOS器件，其中，还包括间隙壁，所述间隙壁设置在所述栅极结构的侧壁上，所述漏极与所述间隙壁之间存在间隔。
  10. 一种LDMOS器件的制造方法，包括：
    提供半导体衬底，在所述半导体衬底中形成有漂移区，在所述半导体衬底的部分表面上形成有栅极结构，所述栅极结构覆盖部分所述漂移区的表面，在所述栅极结构两侧的半导体衬底中分别形成有源极和漏极，其中，所述漏极设置在所述漂移区内并与所述栅极结构之间存在间隔；
    形成金属硅化物阻挡层，其中，所述金属硅化物阻挡层覆盖所述栅极结构和所述漏极之间的至少部分所述半导体衬底的表面；
    在至少部分所述金属硅化物阻挡层的表面上形成第一接触孔。
  11. 如权利要求10所述的制造方法，其中，所述金属硅化物阻挡层覆盖部分所述栅极结构的顶面以及所述栅极结构和所述漏极之间的所述半导体衬底的表面。
  12. 如权利要求10所述的制造方法，其中，所述金属硅化物阻挡层包括自下而上依次层叠的氧化物层、氮化物层和氮氧化物层，所述第一接触孔的底部位于所述氮化物层中。
  13. 如权利要求12所述的制造方法，其中，所述氮化物层和所述氮氧化物层的厚度均小于所述氧化物层的厚度。
  14. 如权利要求10所述的制造方法，其中，形成所述金属硅化物阻挡层的方法包括以下步骤：
    沉积形成金属硅化物阻挡材料层，以覆盖所述栅极结构、所述源极和所述漏极；
    图案化所述金属硅化物阻挡材料层，以形成所述金属硅化物阻挡层。
  15. 如权利要求10所述的制造方法，其中，在形成所述第一接触孔的步骤中，还包括以下步骤：
    在所述源极的部分表面上形成第二接触孔，通过所述第二接触孔可电连接所述源极；
    在所述漏极的部分表面上形成第三接触孔，通过所述第三接触孔可电连接所述漏极。
  16. 如权利要求15所述的制造方法，其中，所述第一接触孔的宽度大于所述第二接触孔和所述第三接触孔的宽度。
  17. 如权利要求15所述的制造方法，其中，所述第一接触孔和所述第二接触孔电连接并均接地。
  18. 如权利要求15所述的制造方法，其中，在形成所述金属硅化物阻挡层之后，形成所述第一接触孔之前，还包括以下步骤：
    形成层间介电层，以覆盖所述栅极结构、所述源极、所述漏极以及所述金属硅化物阻挡层，其中，所述第一接触孔贯穿所述金属硅化物阻挡层上方的所述层间介电层，所述第二接触孔贯穿所述源极上方的所述层间介电层，所述第三接触孔贯穿所述漏极上方的所述层间介电层。
  19. 如权利要求10所述的制造方法，其中，在所述半导体衬底的部分表面上形成有栅极结构之后，还包括，在所述栅极结构的侧壁上形成间隙壁，所述漏极与所属间隙壁之间存在间隔。
  20. 一种电子装置，所述电子装置包括如权利要求1至9之一所述的LDMOS器件。
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