WO2020024967A1 - 横向扩散金属氧化物半导体器件及其制造方法 - Google Patents

横向扩散金属氧化物半导体器件及其制造方法 Download PDF

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WO2020024967A1
WO2020024967A1 PCT/CN2019/098528 CN2019098528W WO2020024967A1 WO 2020024967 A1 WO2020024967 A1 WO 2020024967A1 CN 2019098528 W CN2019098528 W CN 2019098528W WO 2020024967 A1 WO2020024967 A1 WO 2020024967A1
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gate
layer
region
semiconductor device
oxide semiconductor
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PCT/CN2019/098528
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French (fr)
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高桦
孙贵鹏
罗泽煌
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无锡华润上华科技有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like

Definitions

  • the invention relates to the field of semiconductor manufacturing, in particular to a laterally diffused metal oxide semiconductor device, and also relates to a method for manufacturing the laterally diffused metal oxide semiconductor device.
  • LDMOS laterally diffused metal oxide semiconductor
  • HAI hot carrier injection
  • a laterally diffused metal oxide semiconductor device includes: a substrate; a drift region disposed in the substrate; a gate structure disposed on the substrate, including a gate dielectric layer and a gate dielectric layer An upper gate layer; a drain region disposed in a substrate on one side of the gate structure and in contact with the drift region; a source region disposed on a liner on the other side of the gate structure And a gate-like structure, which is disposed above the drift region between the gate structure and the drain region, the material of the gate-like structure is the same as that of the gate layer, and the gate-like structure It is insulated from the gate layer.
  • the laterally diffused metal oxide semiconductor device can improve the HCI characteristics of the device by providing a gate-like structure insulated from the gate layer above the drift region between the gate layer and the drain region.
  • a method for manufacturing a laterally diffused metal oxide semiconductor device includes: obtaining a substrate, wherein a drift region is formed in the substrate; forming a gate dielectric layer on the substrate; and forming a gate dielectric layer on the substrate A gate material is formed thereon; photolithography is performed using a first photoresist and the gate material is etched to form a gate layer and a gate-like structure separated from the gate layer, and the gate-like structure is provided at Above the drift region, the first photoresist includes a gate layer pattern and a gate-like structure pattern; a drain region and a source region are formed, and the drain region is formed on a substrate on one side of the gate layer And in contact with the drift region, the source region is formed in a substrate on the other side of the gate layer, and the gate-like structure is located between the gate layer and the drain region.
  • the above method for manufacturing a laterally diffused metal oxide semiconductor device can be improved by rationally designing the pattern of the first lithographic plate, and setting a gate-like structure separated from the gate layer above the drift region between the gate layer and the drain region. HCI characteristics of the device.
  • This method does not require the addition of a lithographic plate, nor does it impose strict requirements on the in-line process. And only by adjusting the pattern of the first lithographic plate, and accordingly changing the characteristics of the gate-like structure, such as the size, number, and pitch, the device characteristics can be fine-tuned, so that the HCI characteristics of the device can be adjusted more reasonably to meet the reliability of the device Sexual requirements.
  • FIG. 1 is a schematic structural diagram of a laterally diffused metal oxide semiconductor device according to an embodiment
  • FIG. 2 is a flowchart of a method of manufacturing a laterally diffused metal oxide semiconductor device according to an embodiment
  • 3a to 3h are schematic cross-sectional views of a laterally diffused metal oxide semiconductor device in a manufacturing process according to an embodiment.
  • Spatial relation terms such as “below”, “below”, “below”, “below”, “above”, “above”, etc., in It may be used here for convenience of description to describe the relationship between one element or feature and other elements or features shown in the figure. It should be understood that in addition to the orientations shown in the figures, the spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the figures is turned over, then the element or feature described as “below” or “beneath” other elements or features would then be oriented “above” the other element or feature. Thus, the exemplary terms “below” and “below” can include both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptors used herein are interpreted accordingly.
  • Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown can be expected due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present invention should not be limited to the specific shape of the region shown here, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle generally has round or curved features and / or implanted concentration gradients at its edges, rather than a binary change from the implanted region to the non-implanted region. Likewise, a buried area formed by implantation may result in some implantation in the area between the buried area and the surface through which the implantation proceeds. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.
  • P + type is simply referred to as P-type with heavy doping concentration.
  • P-type doping concentration P-type represents lightly doped P-type
  • N + type represents heavily doped N-type
  • N-type represents medium-doped N-type
  • N-type represents lightly-doped N type.
  • FIG. 1 is a schematic structural diagram of a laterally diffused metal oxide semiconductor device according to an embodiment, including a substrate 10, a drift region 20, a gate structure, a drain region 40, a source region 50, and a gate-like structure 66.
  • the drift region 20 is disposed in the substrate.
  • a gate structure is disposed on the substrate 10.
  • the gate structure includes a gate dielectric layer 62 and a gate layer 64 on the gate dielectric layer 62.
  • the drain region 40 is disposed in the substrate 10 on one side of the gate structure (in FIG. 1, the substrate 10 is disposed on the right side of the gate structure), and is in contact with the drift region 20; in one embodiment, it is disposed In the drift region 20.
  • the source region 50 is provided in the substrate 10 on the other side of the gate structure (in FIG. 1, the substrate 10 is provided on the left side of the gate structure).
  • the gate-like structure 66 is disposed above the drift region 20 and between the gate structure and the drain region 40.
  • the material of the gate-like structure 66 is the same as that of the gate layer 64.
  • the gate layer 64 is a polysilicon gate, and the material of the gate-like structure 66 is polysilicon.
  • the number of gate-like structures 66 is two. In other embodiments, different numbers of gate-like structures 66 may be set according to the specific conditions of the device and electrical parameter requirements, such as one, three, 4 etc.
  • the insulation between the gate-like structure 66 and the gate layer 64 can be achieved by filling an insulating medium between the gate-like structure 66 and the gate layer 64.
  • an insulating medium between the gate-like structure 66 and the gate layer 64.
  • the gate-like structures 66 are also filled with an insulating medium.
  • the gate-like structure 66 structure can be used as a field plate, and its shape is not limited. Generally, the shape that can be easily manufactured can be selected according to the difficulty of the process.
  • the above-mentioned laterally diffused metal oxide semiconductor device can improve the HCI characteristics of the device by providing a gate-like structure 66 insulated from the gate layer 64 above the drift region 20 between the gate layer 64 and the drain region 40.
  • this structure can correspondingly optimize the surface electric field strength of the device to a certain extent, and also help reduce the on-resistance of the device to a certain extent.
  • the substrate 10 is a semiconductor substrate, and the material thereof may be undoped single crystal silicon, impurity-doped single crystal silicon, silicon on insulator (SOI), silicon on insulator (SSOI), Silicon germanium (S-SiGeOI), silicon germanium (SiGeOI) on insulator and germanium on insulator (GeOI) are laminated on the insulator.
  • the constituent material of the substrate 10 is single-crystal silicon.
  • the substrate 10 has a second conductivity type
  • the drift region 20 has a first conductivity type
  • the drain region 40 and the source region 50 have a first conductivity type.
  • the first conductivity type is N-type and the second conductivity type is P-type; in another embodiment, the first conductivity type is P-type and the second conductivity type is N-type.
  • the substrate 10 may be a P-type semiconductor substrate or an N-type semiconductor substrate.
  • an N-type high-voltage device may select a P-type semiconductor substrate
  • a P-type high-voltage device may select an N-type semiconductor substrate.
  • the substrate 10 is a P-type semiconductor substrate.
  • the drift region 20 has different conductivity types according to the specific type of LDMOS device. For example, if the LDMOS device is an N-type LDMOS device, the drift region 20 is an N-type drift region; if the LDMOS device is a P-type LDMOS device, the drift region 20 is a P-type drift region. In the embodiment shown in FIG. 1, the drift region 20 is an N-type drift region. Generally, the doping concentration of the drift region 20 is lower, which is lower than that of the drain region 40 and the source region 50.
  • the gate dielectric layer 62 may include conventional dielectric materials such as oxides, nitrides, and oxynitrides of silicon having a dielectric constant from about 4 to about 20 (measured in vacuum), or the gate The dielectric layer 62 may include a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100.
  • Such higher dielectric constant dielectric materials may include, but are not limited to: hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs).
  • the gate layer 64 is a polysilicon material. In other embodiments, a metal, a metal nitride, a metal silicide, or a similar compound may be used as the material of the gate layer 64.
  • the minimum distance between the gate-like structure 66 and the gate layer 64 is between 0.15 microns and 0.2 microns.
  • the drain region 40 and the source region 50 are a drain and a source heavily doped with N-type doped ions.
  • the LDMOS device further includes a metal silicide barrier (SAB) layer 72.
  • the metal silicide barrier layer 72 covers the gate-like structure 66 and also covers the surface of the drift region 20 between the gate-like structure 66 and the drain region 40.
  • a metal silicide 42 is formed on the surface of the drain region 40
  • a metal silicide 65 is formed on the surface of the gate layer 64
  • a metal silicide 52 is formed on the surface of the source region surface 50. Setting the metal silicide can reduce the contact resistance.
  • Self-aligned metal silicide is a fairly simple and convenient contact metallization process, but during the fabrication of semiconductor devices, some areas require a salicide process, and some areas require non-self-aligned metal silicide (non -salicide) process.
  • non-salicide metal silicide
  • SAB self-aligned silicide area blocking film
  • the material of the metal silicide may be CoSix, NiSix, PtSix, or a combination of these compounds.
  • the metal silicide barrier layer 72 includes an oxide layer, such as silicon oxide. Further, the metal silicide barrier layer 72 may also have a multilayer structure, for example, it includes an oxide layer, a nitride layer, and an oxynitride layer that are sequentially stacked from bottom to top.
  • the nitride layer is silicon nitride. In one embodiment, the oxynitride layer is silicon oxynitride.
  • the LDMOS device further includes an insulating layer 74 and a metal field plate 80.
  • the insulating layer 74 is disposed on the gate layer 64, the metal silicide blocking layer 72, the drain region 40 and the source region 50, and the metal field plate 80 is disposed on the insulating layer 74.
  • the thickness of the insulating layer 74 can be adjusted according to the characteristics of the device. For example, reducing the thickness of the insulating layer 74 can increase the depletion of the drift region, and increasing the thickness can reduce the depletion of the drift region.
  • the material of the insulating layer 74 is silicon oxide.
  • the structure of the metal field plate 80 on the insulating layer 74 can improve the surface electric field of the device, enhance the depletion of the drift region of the device, and improve the withstand voltage (BV) of the device. It can be understood that, in other embodiments, other field plate structures known in the art may be adopted or cooperated with other field plate structures known in the art to improve the surface electric field of the device, such as an electrode field plate structure (such as a polysilicon electrode). Field plate structure).
  • a structure with a wider contact hole (named a contact hole in this specification) is used instead of the structure in which the metal field plate 80 is provided on the insulating layer 74.
  • the metal silicide barrier layer 72 includes an oxide layer and an oxide etch barrier layer on the oxide layer. Setting the oxide etch barrier layer can ensure that the bottom of the hole stays when the nail is etched. In the oxide etching barrier layer (so that it will not be etched into the oxide layer), then the depletion of the electric field in the drift region can be accurately adjusted by adjusting the thickness of the oxide layer, thereby improving device characteristics.
  • the material of the oxide layer is silicon oxide
  • the material of the oxide etch stop layer is nitride, such as silicon nitride.
  • the metal silicide blocking layer 72 includes a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer, which are sequentially stacked from bottom to top. That is, the gate-like structure 66 is suitable for various field plate structures (such as the aforementioned insulating layer 74 + metal field plate 80, electrode field plate structure, nail contact hole structure, etc.).
  • the LDMOS device further includes a first contact hole 92.
  • the first contact hole 92 is in contact with the metal field plate 80 to lead the metal field plate 80 out.
  • the first contact hole 92 leads the metal field plate 80 to ground.
  • the LDMOS device further includes a second contact hole 94.
  • the second contact hole 94 is electrically connected to the gate layer 64. Further, the second contact hole 94 is electrically connected to the metal silicide 65 to achieve electrical connection with the gate layer 64 and lead the gate out.
  • the LDMOS device further includes a third contact hole 96 and a fourth contact hole 98.
  • the third contact hole 96 is electrically connected to the drain region 40. Further, the third contact hole 96 is electrically connected to the metal silicide 42 to achieve electrical connection with the drain region 40.
  • the fourth contact hole 98 is electrically connected to the source region 50. Further, the fourth contact hole 98 is electrically connected to the metal silicide 52 to achieve electrical connection with the source region 50.
  • the first contact hole 92, the second contact hole 94, the third contact hole 96, the fourth contact hole 98, and the nail contact hole are filled with a conductive material, wherein the conductive material may be any suitable material known to those skilled in the art.
  • the conductive material includes, but is not limited to, a metal material; wherein, the metal material may include one or more of Ag, Au, Cu, Pd, Pt, Cr, Mo, Ti, Ta, W, and Al.
  • the first contact hole 92, the second contact hole 94, the third contact hole 96, the fourth contact hole 98, and the nail contact hole can be filled with the same conductive material, for example, all of them can be filled with tungsten metal or the like. Different conductive materials.
  • the insulating layer 74 and the metal field plate 80 are not required to be provided, and therefore, the first contact hole 92 is not required to be provided.
  • the LDMOS device further includes a body region 30.
  • the body region 30 is located on a side of the gate layer 64 away from the drift region 20 and is spaced from the drift region 20.
  • a source region 50 is formed in the body region 30.
  • the body region 30 has a conductivity type opposite to the drift region 20, that is, the body region 30 has a second conductivity type.
  • the body region 30 is a P-shaped body region.
  • a body region lead-out region (not shown in 1) having the same conductivity type as the body region 30 may be provided in the body region 30.
  • the body region lead-out region may also be a P-type and its impurity doping concentration is greater than the impurity doping concentration of the body region.
  • the body region lead-out region is heavily doped with P-type impurities.
  • the LDMOS device further includes a sidewall 76.
  • the side wall 76 is disposed on the gate structure side away from the gate-like structure 66, and is also disposed on the gate-like structure 66 side away from the gate structure (for the embodiment of the gate-like structure 66, it is the gate-like structure provided on the outermost side). Outside of structure 66).
  • the sidewall 76 may be one of silicon oxide, silicon nitride, and silicon oxynitride, or a combination thereof.
  • a nail contact hole is provided on the surface of at least part of the metal silicide barrier layer 72.
  • the A contact hole may be partially located on the surface of the metal silicide barrier layer 72 above the gate layer 64, partially located on the surface of the metal silicide barrier layer 72 above the sidewall 76, and partially located on the sidewall 76 and the drain.
  • the nail contact hole On the surface of the metal silicide blocking layer 72 on the surface of the substrate 10 between the polar regions 40; or, the nail contact hole may be located only on the surface of the substrate 10 between the sidewall 76 and the drain region 40 On the surface of the metal silicide barrier layer 72; or, the nail contact hole may be partially located on the surface of the metal silicide barrier layer 72 above the sidewall 76 and partially on the surface of the sidewall 76 and the drain region 40 between the surfaces of the substrate 10 on the surface of the metal silicide barrier layer 72.
  • the fourth contact hole 98 of the source electrode is electrically connected to the ground contact hole and grounded, so as to enhance the depletion of the drift region and further increase the breakdown voltage of the device.
  • the fourth contact hole 98 and the first contact hole may be electrically connected to each other by electrically connecting the same metal layer or a metal interconnection structure, or may be electrically connected together by other suitable methods.
  • the width of the first contact hole is larger than the width of the first contact hole 92, the second contact hole 94, the third contact hole 96, and the fourth contact hole 98.
  • the width refers to the contact The diameter of the hole in the direction of the line connecting the source region 50 and the drain region 40 and its extension line.
  • the drain region 40 is not provided with a shallow trench isolation (STI) structure.
  • STI shallow trench isolation
  • FIG. 2 is a flowchart of a method for manufacturing a laterally diffused metal oxide semiconductor device according to an embodiment, including the following steps:
  • the substrate 10 is a semiconductor substrate, and its material can be undoped single crystal silicon, doped single crystal silicon, silicon on insulator (SOI), and silicon on insulator (SSOI), silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI).
  • the constituent material of the substrate 10 is single-crystal silicon.
  • the substrate 10 has a second conductivity type
  • the drift region 20 has a first conductivity type
  • the drain region 40 and the source region 50 have a first conductivity type.
  • the first conductivity type is N-type and the second conductivity type is P-type; in another embodiment, the first conductivity type is P-type and the second conductivity type is N-type.
  • the substrate 10 may be a P-type semiconductor substrate or an N-type semiconductor substrate.
  • an N-type high-voltage device may select a P-type semiconductor substrate
  • a P-type high-voltage device may select an N-type semiconductor substrate.
  • the substrate 10 is a P-type semiconductor substrate.
  • the drift region 20 has different conductivity types according to the specific type of LDMOS device. For example, if the LDMOS device is an N-type LDMOS device, the drift region 20 is an N-type drift region; if the LDMOS device is a P-type LDMOS device, the drift region 20 is a P-type drift region. In the embodiment shown in FIG. 1, the drift region 20 is an N-type drift region. Generally, the doping concentration of the drift region 20 is lower, which is lower than that of the drain region 40 and the source region 50.
  • the drift region 20 may be formed using a suitable method, such as a doping process. Doping is generally achieved by ion implantation. For example, if an N-type high-voltage device is prepared, N-type ion doping is performed on a region in the substrate 10 where the drift region 20 is to be formed to form an N-type drift region in the substrate; The bottom 10 is doped with P-type ions to form a P-type drift region. The higher the required doping concentration, the higher the implantation dose during the implantation process.
  • a gate dielectric layer is formed on the substrate.
  • the gate dielectric layer 62 may include conventional dielectric materials such as oxides, nitrides, and oxynitrides of silicon having a dielectric constant from about 4 to about 20 (measured in a vacuum), Alternatively, the gate dielectric layer 62 may include a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant dielectric materials may include, but are not limited to: hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs).
  • the gate dielectric layer 62 may be formed using a process known in the art, such as a thermal oxidation process.
  • a gate material is formed on the gate dielectric layer.
  • the gate material is a polysilicon material.
  • a metal, a metal nitride, a metal silicide, or a similar compound may be used as the gate material.
  • the method for forming the gate material may use a chemical vapor deposition (CVD) method, such as low temperature chemical vapor deposition (LTCVD), low pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (LTCVD), and plasma.
  • CVD chemical vapor deposition
  • LTCVD low temperature chemical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • LTCVD fast thermal chemical vapor deposition
  • PECVD can also use methods such as sputtering and physical vapor deposition (PVD).
  • the thickness of the gate material may be a suitable thickness according to the size of the device, and is not specifically limited herein.
  • step S230 may be any one of the deposition processes.
  • S240, photolithography and etching of the gate material are performed by using the first photoresist to form a gate layer and a gate-like structure.
  • the first photoresist includes a gate layer pattern and a gate-like structure pattern.
  • the photoresist on the gate material is used to define the gate layer pattern and the gate-like structure pattern as an etching barrier layer by photolithography, and then the gate is etched.
  • the material forms the gate layer 64 and the gate-like structure 66. Referring to FIG. 3 c, a gate-like structure 66 is formed above the drift region 20 and is separated from the gate layer 64.
  • a body region 30 may also be formed in the substrate 10 before the gate-like structure 66 is formed.
  • the body region 30 is located on a side of the gate layer 64 away from the drift region 20 and is spaced from the drift region 20.
  • the body region 30 has a conductivity type opposite to that of the drift region 20.
  • the body region 30 is a P-shaped body region.
  • the body region 30 may be formed using, for example, ion implantation.
  • the body region is lithographically and etched to remove the gate material at a position where the body region is to be formed.
  • a region where the body region is to be formed is implanted with a P-type doped impurity such as boron, and the body region 30 may be formed by thermal diffusion after the implantation.
  • the drain region 40 is disposed in the substrate 10 on one side of the gate layer 64 (in FIG. 3d, the substrate 10 is disposed on the right side of the gate layer 64), and is in contact with the drift region 20; in one embodiment Is provided in the drift region 20.
  • the source region 50 is provided in the substrate 10 on the other side of the gate layer 64 (in FIG. 3d, the substrate 10 is provided on the left side of the gate layer 64).
  • the drain region 40 and the source region 50 have a first conductivity type.
  • the drain region 40 and the source region 50 are N-type, which may also be a source and a drain heavily doped with N-type doped ions.
  • the method for forming the source and drain includes performing source-drain ion implantation on a region in the semiconductor substrate where the source and drain are to be formed, and forming drains in the substrate 10 on both sides of the gate layer 64, respectively.
  • the polar region 40 and the source region 50 By using a photolithography process, a patterned photoresist layer that first exposes a predetermined formation of the drain region 40 and the source region 50 may be formed first, and then the patterned photoresist layer is used as a mask to perform source and drain ion implantation. Finally, the patterned photoresist layer is removed by a method such as ashing.
  • an annealing process may be performed.
  • the annealing may be performed by any annealing treatment method known to those skilled in the art, including but not limited to rapid thermal annealing, furnace tube annealing, peak annealing, laser annealing, etc., for example, performing rapid annealing
  • the heating annealing process utilizes a high temperature of 900 to 1050 ° C to activate the dopants in the source / drain regions, and simultaneously repairs the lattice structure on the surface of the semiconductor substrate damaged during each ion implantation process.
  • a lightly doped drain (LDD) is formed between the source / drain region and each gate.
  • the gate structure 66 can improve the HCI characteristics of the device. This method does not require the addition of a lithographic plate, nor does it impose strict requirements on the in-line process. Moreover, only by adjusting the pattern of the first lithographic plate, and accordingly changing the characteristics such as the size, number, and pitch of the gate-like structure 66, the characteristics of the device can be fine-tuned, so that the HCI characteristics of the device can be adjusted more reasonably to meet Device reliability requirements.
  • the step S240 further includes a step of forming the side wall 76.
  • the side wall 76 is disposed on the gate structure side away from the gate-like structure 66, and is also disposed on the gate-like structure 66 side away from the gate structure (for the embodiment of the gate-like structure 66, it is the gate-like structure provided on the outermost side). Outside of structure 66).
  • the sidewall 76 may be one of silicon oxide, silicon nitride, and silicon oxynitride, or a combination thereof. In one embodiment, the sidewall 76 is formed by etching after deposition.
  • the method further includes S260: forming a metal silicide barrier layer.
  • the metal silicide blocking layer 72 covers the gate-like structure 66, and also covers the surface of the drift region 20 between the gate-like structure 66 and the drain region 40.
  • the metal silicide barrier layer 72 includes an oxide layer, a nitride layer, and an oxynitride layer sequentially stacked from bottom to top.
  • the oxide layer includes, for example, silicon oxide and the nitride layer.
  • silicon nitride is included, and the oxynitride layer includes silicon oxynitride.
  • the metal silicide barrier layer 72 may further include other suitable materials.
  • the metal silicide barrier layer 72 may further include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a carbon-doped silicon nitride layer, or the like. At least one.
  • the method for forming the metal silicide barrier layer 72 is as follows:
  • a metal silicide barrier material layer is deposited to cover the gate layer 64, the sidewall 76, the source region 50 and the drain region 40.
  • the deposited metal silicide barrier material layer can cover the entire surface of the substrate 10, and the metal silicide barrier material layer can be formed by, for example, chemical vapor deposition, physical vapor deposition, or atomic layer deposition.
  • a metal silicide barrier material layer is patterned to form a metal silicide barrier layer 72.
  • a patterned masking layer such as a patterned photoresist layer, may be first formed on the metal silicide blocking material layer, and the patterned masking layer defines a predetermined metal silicide blocking layer 72, Then, using the patterned mask layer as a mask, the metal silicide barrier material layer is etched to form the metal silicide barrier layer 72.
  • the etching process can be performed by using dry etching or wet etching. The silicide blocks the etching of the material layer and finally removes the patterned mask layer.
  • the finally formed metal silicide blocking layer 72 exposes part of the top surface of the gate layer 64, the surface of the drain region 40, and the surface of the source region 50, so as to facilitate subsequent formation of the metal silicide.
  • the metal silicide barrier layer 72 also fills the gap between the gate-like structure 66 and the gate layer 64 (for a plurality of gate-like structures 66, the metal silicide barrier layer 72 also fills the gap between adjacent gate-like structures 66), we need insulation between the gate layer 64 and the gate-like structures 66, so it is possible to fill in the insulating metal silicide barrier layer 72.
  • the gap between the gate-like structure 66 and the gate layer 64 may also be filled with other insulating materials.
  • the gate layer 64 and the gate-like structure 66 form a hollow structure, although they can also maintain insulation, they are not easy to implement.
  • the method further includes S270: forming a metal silicide on the surface of the drain region, the surface of the gate layer, and the surface of the source region not covered by the metal silicide barrier layer.
  • a metal silicide layer is formed on a part of the surface of the source region 50, a part of the surface of the drain region 40, and a part of the surface of the gate layer 64.
  • the metal silicide layer may include CoSix, NiSix, and PtSix or Its combination of materials.
  • the method for forming a metal silicide layer includes the following steps. First, as shown in FIG. 3f, a metal or other metal substitute is deposited, which may include nickel, cobalt, and platinum. Or a combination thereof, forming the metal layer 81. The substrate is then heated to cause silicidation between the metal layer 81 and the silicon layer below it to form a metal silicide 42, a metal silicide 52, and a metal silicide 65. Then, an etching that can erode the metal layer 81 without eroding the metal silicide is used. Agent to remove the unreacted metal layer, as shown in Figure 3g.
  • the method further includes step S280: forming an insulating layer on the gate layer, the metal silicide barrier layer, the drain region, and the source region.
  • the material of the insulating layer 74 is silicon oxide.
  • the thickness of the insulating layer 74 can be adjusted according to the characteristics of the device. For example, reducing the thickness of the insulating layer 74 can enhance the depletion of the drift region, and increasing the thickness can reduce the depletion of the drift region.
  • the method further includes step S290: forming a metal field plate on the insulating layer.
  • a layer of metal is deposited on the insulating layer 74, and the metal used as the metal field plate 80 is retained by photolithography and etching processes.
  • the metal silicide barrier layer 72 includes an oxide layer and an oxide etch barrier layer on the oxide layer. After step S270, a step of forming a nail contact hole is further included, and the bottom of the nail contact hole is located in the oxide etching barrier layer. The provision of an oxide etch barrier layer can ensure that the bottom of the hole stays in the oxide etch barrier layer when the nail is etched.
  • the step S290 further includes a step of forming a contact hole.
  • the contact hole may include a first contact hole 92, a second contact hole 94, a third contact hole 96, and a fourth contact hole 98, or may include a second contact hole 94, a third contact hole 96, a fourth contact hole 98, and a nail contact. hole.
  • the first contact hole 92 is in contact with the metal field plate 80 to lead the metal field plate 80 out. In one embodiment, the first contact hole 92 leads the metal field plate 80 to ground.
  • the second contact hole 94 is electrically connected to the gate layer 64. Further, the second contact hole 94 is electrically connected to the metal silicide 65 to achieve an electrical connection with the gate layer 64 and lead the gate out.
  • the third contact hole 96 is electrically connected to the drain region 40. Further, the third contact hole 96 is electrically connected to the metal silicide 42 to achieve electrical connection with the drain region 40.
  • the fourth contact hole 98 is electrically connected to the source region 50. Further, the fourth contact hole 98 is electrically connected to the metal silicide 52 to achieve electrical connection with the source region 50.
  • the first contact hole 92, the second contact hole 94, the third contact hole 96, and the fourth contact hole 98 are filled with a conductive material.
  • the conductive material may be any suitable conductive material well known to those skilled in the art, including But it is not limited to metal materials; wherein, the metal materials may include one or more of Ag, Au, Cu, Pd, Pt, Cr, Mo, Ti, Ta, W, and Al.
  • the first contact hole 92, the second contact hole 94, the third contact hole 96, and the fourth contact hole 98 can be filled with the same conductive material, such as tungsten metal, etc., or different conductive materials. .
  • a step of forming an interlayer dielectric is further included. Subsequently, the interlayer dielectric covers the insulating layer 74 and the metal field plate 80.
  • the interlayer dielectric may be a silicon oxide layer, including a layer of a doped or undoped silicon oxide material formed using a thermal chemical vapor deposition (CVD) manufacturing process or a high-density plasma (HDP) manufacturing process, such as Undoped silica glass (USG), phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG).
  • the interlayer dielectric may also be boron or phosphorus-doped spin-on-glass (SOG), phosphorus-doped tetraethoxysilane (PTEOS), or boron-doped tetra-ethoxysilane (PTEOS). Ethoxysilane (BTEOS).
  • the deposited interlayer dielectric may also be planarized by a planarization method, such as chemical mechanical polishing (CMP), so that the interlayer dielectric has a flat surface.
  • CMP chemical mechanical polishing
  • a method of forming a contact hole includes the following steps:
  • a patterned mask layer (for example, a patterned photoresist layer) is formed on the surface of the interlayer dielectric.
  • the patterned mask layer defines a first contact hole 92, a second contact hole 94, The patterns and positions of the third contact hole 96 and the fourth contact hole 98.
  • the interlayer dielectric is etched to form a first contact hole, a second contact hole, a third contact hole, and a fourth contact hole, respectively.
  • the patterned mask layer is subsequently removed, using methods known to those skilled in the art.
  • first contact hole, the second contact hole, the third contact hole, and the fourth contact hole are filled with a conductive material to form a final first contact hole 92, a second contact hole 94, a third contact hole 96, and a fourth contact hole.
  • the contact hole 98 is shown in FIG. 1.

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Abstract

一种横向扩散金属氧化物半导体器件及其制造方法。所述横向扩散金属氧化物半导体器件包括：衬底(10)；漂移区(20)，设置在所述衬底(10)中；栅极结构，设置在所述衬底(10)上，包括栅极介电层(62)和栅极介电层(62)上的栅极层(64)；漏极区(40)，设置在所述栅极结构的一侧的衬底(10)中，与所述漂移区(20)相接触；源极区(50)，设置在所述栅极结构的另一侧的衬底(10)中；及类栅结构(66)，设置在所述漂移区(20)上方、所述栅极结构与所述漏极区(40)之间，所述类栅结构(66)的材质与所述栅极层(64)相同，所述类栅结构(66)与所述栅极层(64)之间绝缘。

Description

横向扩散金属氧化物半导体器件及其制造方法 技术领域
本发明涉及半导体制造领域，特别是涉及一种横向扩散金属氧化物半导体器件，还涉及一种横向扩散金属氧化物半导体器件的制造方法。
背景技术
横向扩散金属氧化物半导体(LDMOS)器件由于工作在较高的电压下，易形成较高的沟道横向电场和氧化层纵向电场，使得载流子在输送过程中发生碰撞电离，产生额外的电子空穴对。部分热载流子进入栅氧化层，使得器件的阈值电压上升，饱和电流和载流子迁移率下降，称为热载流子注入(HCI)效应。
因此，在保证器件其他参数(例如击穿电压、导通电阻等)的条件下，HCI效应通常越小越好。
发明内容
基于此，有必要提供一种能够改善HCI特性的横向扩散金属氧化物半导体器件及其制造方法。
一种横向扩散金属氧化物半导体器件，包括：衬底；漂移区，设置在所述衬底中；栅极结构，设置在所述衬底上，包括栅极介电层和栅极介电层上的栅极层；漏极区，设置在所述栅极结构的一侧的衬底中，与所述漂移区相接触；源极区，设置在所述栅极结构的另一侧的衬底中；及类栅结构，设置在所述漂移区上方、所述栅极结构与所述漏极区之间，所述类栅结构的材质与所述栅极层相同，所述类栅结构与所述栅极层之间绝缘。
上述横向扩散金属氧化物半导体器件，通过在栅极层与漏极区之间的漂 移区上方设置与栅极层之间绝缘的类栅结构，能够改善器件的HCI特性。
还有必要提供一种横向扩散金属氧化物半导体器件的制造方法。
一种横向扩散金属氧化物半导体器件的制造方法，包括：获取衬底，所述衬底中形成有漂移区；在所述衬底上形成栅极介电层；在所述栅极介电层上形成栅极材质；使用第一光刻版光刻并对所述栅极材质进行刻蚀，形成栅极层和与所述栅极层分离的类栅结构，所述类栅结构设置在所述漂移区上方，所述第一光刻版包括栅极层图案和类栅结构图案；形成漏极区和源极区，所述漏极区形成于所述栅极层的一侧的衬底中，且与所述漂移区相接触，所述源极区形成于所述栅极层的另一侧的衬底中，所述类栅结构位于所述栅极层和漏极区之间。
上述横向扩散金属氧化物半导体器件的制造方法，通过合理设计第一光刻版的图案，在栅极层与漏极区之间的漂移区上方设置与栅极层分离的类栅结构，能够改善器件的HCI特性。该方法既不需要增加光刻版，也不会对在线工艺有严苛的要求。而且只需要通过调整第一光刻版的图案，从而相应改变类栅结构大小、数量、间距等特性，就能够对器件的特性进行微调，从而更合理地调整器件的HCI特性，来满足器件可靠性的要求。
附图说明
图1是一实施例中横向扩散金属氧化物半导体器件的结构示意图；
图2是一实施例中横向扩散金属氧化物半导体器件的制造方法的流程图；
图3a至图3h是一实施例中横向扩散金属氧化物半导体器件在制造过程中的剖面示意图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来 实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数 形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例。这样，可以预期由于例如制造技术和/或容差导致的从所示形状的变化。因此，本发明的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本发明的范围。
本文所使用的半导体领域词汇为本领域技术人员常用的技术词汇，例如对于P型和N型杂质，为区分掺杂浓度，简易的将P+型代表重掺杂浓度的P型，P型代表中掺杂浓度的P型，P-型代表轻掺杂浓度的P型，N+型代表重掺杂浓度的N型，N型代表中掺杂浓度的N型，N-型代表轻掺杂浓度的N型。
图1是一实施例中横向扩散金属氧化物半导体器件的结构示意图，包括衬底10、漂移区20、栅极结构、漏极区40、源极区50及类栅结构66。其中，漂移区20设置在衬底中。栅极结构设置在衬底10上，栅极结构包括栅极介电层62和栅极介电层62上的栅极层64。漏极区40设置在栅极结构的一侧的衬底10中(图1中为设置在栅极结构右侧的衬底10中)，与漂移区20相接触；在一个实施例中为设置在漂移区20中。源极区50设置在栅极结构的另一侧的衬底10中(图1中为设置在栅极结构左侧的衬底10中)。类栅结构66设置在漂移区20上方、栅极结构与漏极区40之间。类栅结构66的材质与栅极层64相同，在图1所示实施例中，栅极层64为多晶硅栅，类栅结构 66的材质为多晶硅。在图1所示的实施例中，类栅结构66的数量为2，在其他实施例中可以根据器件的具体情况和电参数需求设置不同数量的类栅结构66，例如1个、3个、4个等。类栅结构66与栅极层64之间绝缘，具体可以通过在类栅结构66与栅极层64之间填充绝缘介质来实现，对于类栅结构66为多个的实施例，可以在相邻的类栅结构66之间也填充绝缘介质。类栅结构66结构可以作为场板使用，其形状不限，一般可以根据工艺的实现难度来选择容易制作的形状。
上述横向扩散金属氧化物半导体器件，通过在栅极层64与漏极区40之间的漂移区20上方，设置与栅极层64之间绝缘的类栅结构66，能够改善器件的HCI特性。同时，该结构相应的能够在一定程度上优化器件表面电场强度，同时也对降低器件的导通电阻有一定的帮助。
在一个实施例中，衬底10为半导体衬底，其材料可以采用未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。在图1所示的实施例中，衬底10的构成材料选用单晶硅。
在一个实施例中，衬底10具有第二导电类型，漂移区20具有第一导电类型，漏极区40和源极区50具有第一导电类型。在一个实施例中，第一导电类型是N型，第二导电类型是P型；在另一个实施例中，第一导电类型是P型，第二导电类型是N型。
衬底10可以为P型半导体衬底或者N型半导体衬底，例如N型高压器件则可选择使用P型半导体衬底，而P型高压器件则可选择使用N型半导体衬底。在图1所示的实施例中，衬底10为P型半导体衬底。
根据具体的LDMOS器件的类型，漂移区20具有不同的导电类型。例如，若LDMOS器件为N型LDMOS器件，则漂移区20为N型漂移区；若LDMOS器件为P型LDMOS器件，则漂移区20为P型漂移区。在图1所示的实施例中，漂移区20为N型漂移区。一般来说，漂移区20的掺杂浓度较低，其低于漏极区40和源极区50的掺杂浓度。
在一个实施例中，栅极介电层62可以包括传统的电介质材料诸如具有电介质常数从大约4到大约20(真空中测量)的硅的氧化物、氮化物和氮氧化物，或者，栅极介电层62可以包括具有电介质常数从大约20到至少大约100的通常较高电介质常数电介质材料。这种较高电介质常数电介质材料可以包括但不限于：氧化铪、硅酸铪、氧化钛、钛酸锶钡(BSTs)和锆钛酸铅(PZTs)。
在一个实施例中，栅极层64为多晶硅材料，在其他实施例中也可使用金属、金属氮化物、金属硅化物或类似化合物作为栅极层64的材料。
在一个实施例中，类栅结构66和栅极层64之间的最小距离(即类栅结构66到栅极层64最近的直线距离)介于0.15微米到0.2微米之间。
在本实施例中，漏极区40和源极区50为N型掺杂离子重掺杂的漏极和源极。
在图1所示的实施例中，LDMOS器件还包括金属硅化物阻挡(Silicide Area Block,SAB)层72。金属硅化物阻挡层72覆盖类栅结构66，还覆盖漂移区20位于类栅结构66和漏极区40之间的表面。漏极区40的表面形成有金属硅化物42，栅极层64的表面形成有金属硅化物65，源极区表面50的表面形成有金属硅化物52。设置金属硅化物可以降低接触电阻。自对准金属硅化物(salicide)是一种相当简单方便的接触金属化程序，但是在半导体器件的制作过程中，有一些区域需要salicide过程，而有些区域需要非自对准金属硅化物(non-salicide)过程，对于需要non-salicide过程的器件，就要利用上述salicide的特性，用不会与金属反应的材料把需要non-salicide的区域覆盖起来。这种用于覆盖non-salicide器件的材料就称为自对准硅化物区域阻挡膜(SAB)。
在一个实施例中，金属硅化物(包括金属硅化物42、金属硅化物52、金属硅化物65)的材质可以为CoSix、NiSix、PtSix或这些化合物的组合。
在一个实施例中，金属硅化物阻挡层72包括氧化物层，例如氧化硅。进一步地，金属硅化物阻挡层72还可以为多层结构，例如包括自下而上依次层叠的氧化物层、氮化物层和氮氧化物层。在一个实施例中，氮化物层是氮化 硅。在一个实施例中，氮氧化物层是氮氧化硅。
在图1所示的实施例中，LDMOS器件还包括绝缘层74和金属场板80。绝缘层74设置在栅极层64、金属硅化物阻挡层72、漏极区40及源极区50上，金属场板80设置在绝缘层74上。绝缘层74的厚度可根据器件的特性进行调整，比如减薄绝缘层74的厚度可增强漂移区的耗尽，增加厚度则可减弱漂移区的耗尽。在一个实施例中，绝缘层74的材质为氧化硅。绝缘层74上设置金属场板80的结构，能够改善器件表面电场，增强器件漂移区的耗尽，从而提高器件耐压(BV)。可以理解的，在其他实施例中，也可以采用本领域习知的其他场板结构，或者与本领域习知的其他场板结构配合来改善器件表面电场，例如电极场板结构(比如多晶硅电极场板结构)。
在一个实施例中，采用一种宽度较大的接触孔(在本说明书中命名为甲接触孔)结构，来替代在绝缘层74上设置金属场板80的结构。在该实施例中，金属硅化物阻挡层72包括氧化物层和氧化物层上的氧化物刻蚀阻挡层，设置氧化物刻蚀阻挡层可以保证该甲接触孔刻蚀时，孔的底部停留在氧化物刻蚀阻挡层中(这样就不会刻蚀到氧化物层中)，那么就可以通过调整该氧化物层的厚度来准确调节漂移区电场的耗尽，进而改善器件特性。在一个实施例中，该氧化物层的材质为氧化硅，氧化物刻蚀阻挡层的材质为氮化物，例如氮化硅。在一个实施例中，金属硅化物阻挡层72包括自下而上依次层叠的氧化硅层、氮化硅层和氮氧化硅层。也就是说，类栅结构66适用于各种场板结构(例如前述的绝缘层74+金属场板80，电极场板结构、甲接触孔结构等)。
在图1所示的实施例中，LDMOS器件还包括第一接触孔92。第一接触孔92与金属场板80接触，以将金属场板80引出。在一个实施例中，第一接触孔92将金属场板80引出后接地。
在图1所示的实施例中，LDMOS器件还包括第二接触孔94。第二接触孔94电连接栅极层64，进一步地，第二接触孔94电连接金属硅化物65，以实现和栅极层64的电连接，将栅极引出。在图1所示的实施例中，LDMOS器件还包括第三接触孔96和第四接触孔98。第三接触孔96电连接漏极区40，进 一步地，第三接触孔96电连接金属硅化物42，以实现和漏极区40的电连接。第四接触孔98电连接源极区50，进一步地，第四接触孔98电连接金属硅化物52，以实现和源极区50的电连接。
第一接触孔92、第二接触孔94、第三接触孔96、第四接触孔98及甲接触孔中填充有导电材料，其中，所述导电材料可以为本领域技术人员熟知的任何适合的导电材料，包括但不限于金属材料；其中，所述金属材料可以包括Ag、Au、Cu、Pd、Pt、Cr、Mo、Ti、Ta、W和Al中的一种或几种。
在一个实施例中，第一接触孔92、第二接触孔94、第三接触孔96、第四接触孔98及甲接触孔可以填充相同的导电材料，例如均填充钨金属等，也可以填充不同的导电材料。
可以理解的，在设置甲接触孔的实施例中，就不需要再设置绝缘层74和金属场板80，因此也就不需要设置第一接触孔92。
在图1所示的实施例中，LDMOS器件还包括体区30。体区30位于栅极层64远离漂移区20的一侧，并与漂移区20间隔。源极区50形成在体区30中。体区30具有和漂移区20相反的导电类型，即体区30具有第二导电类型。在图1所示实施例中，体区30为P形体区。
在一个实施例中，可以在体区30中设置与体区30导电类型相同的体区引出区(未1中未示)。例如，体区30为P型，则体区引出区则也可以为P型，且其杂质掺杂浓度大于体区的杂质掺杂浓度，例如体区引出区为P型杂质重掺杂。
在图1所示的实施例中，LDMOS器件还包括侧墙76。侧墙76设置在栅极结构远离类栅结构66的一侧，还设置在类栅结构66远离栅极结构的一侧(对于类栅结构66的实施例，是设置在最外的一个类栅结构66的外侧)。侧墙76可以为氧化硅、氮化硅、氮氧化硅中的一种或者它们组合构成。
在一个实施例中，在至少部分金属硅化物阻挡层72的表面上设置有甲接触孔。其中，所述甲接触孔可以部分位于栅极层64上方的金属硅化物阻挡层72的表面上，部分位于侧墙76上方的金属硅化物阻挡层72的表面上以及部 分位于侧墙76和漏极区40之间的衬底10表面上的金属硅化物阻挡层72的表面上；或者，所述甲接触孔还可以仅位于侧墙76和漏极区40之间的衬底10表面上的金属硅化物阻挡层72的表面上；又或者，所述甲接触孔还可以部分位于所述侧墙76上方的金属硅化物阻挡层72的表面上以及部分位于侧墙76和所述漏极区40之间的衬底10表面上的金属硅化物阻挡层72的表面上。
在一个实施例中，源极的第四接触孔98和所述甲接触孔电连接在一起并接地，进而可以增强对漂移区的耗尽，进而提升器件的击穿电压。
第四接触孔98和甲接触孔可以通过电连接相同的金属层或者金属互连结构的方式实现两者之间的电连接，或者其他适合的方式电连接在一起。
在一个示例中，为了增强漂移区的耗尽，甲接触孔的宽度大于第一接触孔92、第二接触孔94、第三接触孔96及第四接触孔98的宽度，该宽度是指接触孔在源极区50和漏极区40连线及其延长线方向上的直径。
在图1所示的实施例中，漏极区40不设置浅沟槽隔离(STI)结构，相对于设置STI结构来改善多晶硅处的HCI的技术，可以大大降低器件的导通电阻。
本申请还提供一种横向扩散金属氧化物半导体器件的制造方法，图2是一实施例中横向扩散金属氧化物半导体器件的制造方法的流程图，包括下列步骤：
S210，获取衬底。
衬底中形成有漂移区。参见图3a，在一个实施例中，衬底10为半导体衬底，其材料可以采用未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。在图1所示的实施例中，衬底10的构成材料选用单晶硅。
在一个实施例中，衬底10具有第二导电类型，漂移区20具有第一导电类型，漏极区40和源极区50具有第一导电类型。在一个实施例中，第一导 电类型是N型，第二导电类型是P型；在另一个实施例中，第一导电类型是P型，第二导电类型是N型。
衬底10可以为P型半导体衬底或者N型半导体衬底，例如N型高压器件则可选择使用P型半导体衬底，而P型高压器件则可选择使用N型半导体衬底。在图1所示的实施例中，衬底10为P型半导体衬底。
根据具体的LDMOS器件的类型，漂移区20具有不同的导电类型。例如，若LDMOS器件为N型LDMOS器件，则漂移区20为N型漂移区；若LDMOS器件为P型LDMOS器件，则漂移区20为P型漂移区。在图1所示的实施例中，漂移区20为N型漂移区。一般来说，漂移区20的掺杂浓度较低，其低于漏极区40和源极区50的掺杂浓度。
可以使用合适的方法形成漂移区20，例如掺杂工艺。掺杂一般是通过离子注入的方法实现。例如，若制备N型高压器件，则对衬底10中预定形成漂移区20的区域进行N型离子掺杂，以在衬底内形成N型漂移区；若制备P型高压器件，则对衬底10进行P型离子掺杂，形成P型漂移区。所需要的掺杂浓度越高，则注入过程中的注入剂量相应地也应该越高。
S220，在衬底上形成栅极介电层。
参见图3b，在一个实施例中，栅极介电层62可以包括传统的电介质材料诸如具有电介质常数从大约4到大约20(真空中测量)的硅的氧化物、氮化物和氮氧化物，或者，栅极介电层62可以包括具有电介质常数从大约20到至少大约100的通常较高电介质常数电介质材料。这种较高电介质常数电介质材料可以包括但不限于：氧化铪、硅酸铪、氧化钛、钛酸锶钡(BSTs)和锆钛酸铅(PZTs)。
栅极介电层62可以用本领域习知的工艺形成，例如热氧化工艺。
S230，在栅极介电层上形成栅极材质。
在一个实施例中，栅极材质为多晶硅材料，在其他实施例中也可使用金属、金属氮化物、金属硅化物或类似化合物作为栅极材质。
在一个实施例中，栅极材质的形成方法可以采用化学气相沉积法(CVD)， 如低温化学气相沉积(LTCVD)、低压化学气相沉积(LPCVD)、快热化学气相沉积(LTCVD)、等离子体化学气相沉积(PECVD)，也可使用例如溅镀及物理气相沉积(PVD)等方法。栅极材质的厚度可以根据器件的尺寸使用适合的厚度，在此不做具体限制。
在一个实施例中，LDMOS器件的制造过程中可以有两次栅极材质的淀积工艺，步骤S230可以为其中的任一次淀积工艺。
S240，使用第一光刻版光刻并对栅极材质进行刻蚀，形成栅极层和类栅结构。
第一光刻版包括栅极层图案和类栅结构图案，通过光刻将栅极材质上的光刻胶定义出栅极层图案和类栅结构图案作为刻蚀阻挡层，然后刻蚀栅极材质形成栅极层64和类栅结构66。参见图3c，形成的类栅结构66位于漂移区20上方，且与栅极层64相分离。
参见图3c，在一个实施例中，还可在形成类栅结构66之前，于衬底10中形成体区30。体区30位于栅极层64远离漂移区20的一侧，并与漂移区20间隔。体区30具有和漂移区20相反的导电类型，在图3c所示实施例中，体区30为P形体区。可以使用例如离子注入的方法形成体区30，例如，在步骤S230之后、S240之前进行体区光刻及刻蚀，去除预定形成体区位置的栅极材质，然后通过离子注入向衬底10内预定形成体区的区域注入P型掺杂杂质例如硼，注入之后可以通过热扩散形成体区30。
S250，形成漏极区和源极区。
漏极区40设置在栅极层64的一侧的衬底10中(图3d中为设置在栅极层64右侧的衬底10中)，与漂移区20相接触；在一个实施例中为设置在漂移区20中。源极区50设置在栅极层64的另一侧的衬底10中(图3d中为设置在栅极层64左侧的衬底10中)。在一个实施例中，漏极区40和源极区50具有第一导电类型。例如，漏极区40和源极区50为N型，其还可以为N型掺杂离子重掺杂的源极和漏极。
在一个实施例中，形成源极和漏极的方法包括对半导体衬底中预定形成 源极和漏极的区域执行源漏离子注入，在栅极层64两侧的衬底10中分别形成漏极区40和源极区50。可以通过利用光刻工艺首先形成暴露出预定形成漏极区40和源极区50的图案化的光刻胶层，再以该图案化的光刻胶层为掩膜，进行源漏离子注入，最后利用例如灰化的方法去除图案化的光刻胶层。
随后，还可以进行退火工艺，示例性地，退火可以使用本领域技术人员熟知的任何的退火处理方法，包括但不限于快速热退火、炉管退火、峰值退火、激光退火等，例如，进行快速升温退火工艺，利用900至1050℃的高温来活化源极/漏极区域内的掺杂质，并同时修补在各离子注入工艺中受损的半导体衬底表面的晶格结构。此外，亦可视产品需求及功能性考量，另于源极/漏极区域与各栅极之间分别形成轻掺杂漏极(LDD)。
上述横向扩散金属氧化物半导体器件的制造方法，通过合理设计第一光刻版的图案，在栅极层64与漏极区40之间的漂移区20上方，设置与栅极层64分离的类栅结构66，能够改善器件的HCI特性。该方法既不需要增加光刻版，也不会对在线工艺有严苛的要求。而且只需要通过调整第一光刻版的图案，从而相应改变类栅结构66的大小、数量、间距等特性，就能够对器件的特性进行微调，从而更合理地调整器件的HCI特性，来满足器件可靠性的要求。
在一个实施例中，步骤S240之后还包括形成侧墙76的步骤。侧墙76设置在栅极结构远离类栅结构66的一侧，还设置在类栅结构66远离栅极结构的一侧(对于类栅结构66的实施例，是设置在最外的一个类栅结构66的外侧)。侧墙76可以为氧化硅、氮化硅、氮氧化硅中的一种或者它们组合构成。在一个实施例中，侧墙76是淀积后通过刻蚀形成。
在一个实施例中，步骤S250之后还包括S260：形成金属硅化物阻挡层。参见图3e，金属硅化物阻挡层72覆盖类栅结构66，还覆盖漂移区20位于类栅结构66和漏极区40之间的表面。
在一个实施例中，所述金属硅化物阻挡层72包括自下而上依次层叠的氧化物层、氮化物层和氮氧化物层，所述氧化物层例如包括氧化硅、所述氮化 物层例如包括氮化硅、所述氮氧化物层包括氮氧化硅。所述金属硅化物阻挡层72还可以包括其他适合的材料，例如金属硅化物阻挡层72还可以包括氧化硅层、氮化硅层、氮氧化硅层和掺碳的氮化硅层等中的至少一种。
在一个实施例中，形成金属硅化物阻挡层72的方法如下：
首先沉积形成金属硅化物阻挡材料层，以覆盖栅极层64、侧墙76、源极区50和漏极区40。为了简化工艺，沉积的金属硅化物阻挡材料层可以覆盖整个衬底10的表面，可通过例如化学气相沉积、物理气相沉积或原子层沉积的方法沉积形成金属硅化物阻挡材料层。
接着，如图3e所示，图案化金属硅化物阻挡材料层，以形成金属硅化物阻挡层72。具体地，可首先在所述金属硅化物阻挡材料层上形成图案化的掩膜层，例如图案化的光刻胶层，该图案化的掩膜层定义预定形成的金属硅化物阻挡层72，然后以图案化的掩膜层为掩膜，蚀刻所述金属硅化物阻挡材料层，以形成所述金属硅化物阻挡层72，该蚀刻工艺可以使用干法蚀刻或者湿法蚀刻等方法实现对金属硅化物阻挡材料层的蚀刻，最后去除图案化的掩膜层。
在图3e所示的实施例中，最终形成的金属硅化物阻挡层72露出了部分栅极层64顶面、漏极区40表面以及源极区50表面等，以便于后续形成金属硅化物。
可以理解的，在一个实施例中，金属硅化物阻挡层72也填入类栅结构66与栅极层64之间的空隙中(对于类栅结构66为多个的情况，金属硅化物阻挡层72还填入相邻的类栅结构66之间的空隙中)，我们需要栅极层64和类栅结构66之间绝缘，所以填入绝缘的金属硅化物阻挡层72是可以的。在其他实施例中，类栅结构66与栅极层64之间的空隙也可以填入其他绝缘材质。栅极层64和类栅结构66形成中空结构虽然也能保持绝缘，但工艺上不好实现。
步骤S260之后还包括S270：在未被金属硅化物阻挡层覆盖的漏极区表面、栅极层表面及源极区表面形成金属硅化物。
为了降低接触电阻，在源极区50的部分表面、漏极区40的部分表面及栅极层64的部分表面上形成金属硅化物层，其中，金属硅化物层可以包括CoSix、NiSix及PtSix或其组合的材料。
在一个实施例中，形成金属硅化物层的方法包括以下步骤：首先，如图3f所示，沉积金属或其他金属替代物，其可包含镍(nickel)、钴(cobalt)及铂(platinum)或其组合的材料，形成金属层81。接着加热衬底，造成金属层81与其下的硅层发生硅化作用，形成金属硅化物42、金属硅化物52、金属硅化物65，接着使用可侵蚀金属层81、但不致侵蚀金属硅化物的蚀刻剂，以将未反应的金属层除去，如图3g所示。
在一个实施例中，步骤S270之后还包括步骤S280：在栅极层、金属硅化物阻挡层、漏极区及源极区上形成绝缘层。
参见图3h，在一个实施例中，绝缘层74的材质为氧化硅。可以根据器件的特性来调整绝缘层74的厚度，比如减薄绝缘层74的厚度可增强漂移区的耗尽，增加厚度则可减弱漂移区的耗尽。
在一个实施例中，步骤S280之后还包括步骤S290：在绝缘层上形成金属场板。在绝缘层74上淀积一层金属，再利用光刻和刻蚀工艺将作为金属场板80的金属保留下来。
在一个实施例中，金属硅化物阻挡层72包括氧化物层和氧化物层上的氧化物刻蚀阻挡层。步骤S270之后还包括形成甲接触孔的步骤，所述甲接触孔的底部位于所述氧化物刻蚀阻挡层内。设置氧化物刻蚀阻挡层可以保证该甲接触孔刻蚀时，孔的底部停留在氧化物刻蚀阻挡层中。
在一个实施例中，步骤S290之后还包括形成接触孔的步骤。接触孔可以包括第一接触孔92、第二接触孔94、第三接触孔96及第四接触孔98，或者包括第二接触孔94、第三接触孔96、第四接触孔98及甲接触孔。
第一接触孔92与金属场板80接触，以将金属场板80引出。在一个实施例中，第一接触孔92将金属场板80引出后接地。
第二接触孔94电连接栅极层64，进一步地，第二接触孔94电连接金属 硅化物65，以实现和栅极层64的电连接，将栅极引出。第三接触孔96电连接漏极区40，进一步地，第三接触孔96电连接金属硅化物42，以实现和漏极区40的电连接。第四接触孔98电连接源极区50，进一步地，第四接触孔98电连接金属硅化物52，以实现和源极区50的电连接。
第一接触孔92、第二接触孔94、第三接触孔96及第四接触孔98中填充有导电材料，其中，所述导电材料可以为本领域技术人员熟知的任何适合的导电材料，包括但不限于金属材料；其中，所述金属材料可以包括Ag、Au、Cu、Pd、Pt、Cr、Mo、Ti、Ta、W和Al中的一种或几种。
在一个实施例中，第一接触孔92、第二接触孔94、第三接触孔96及第四接触孔98可以填充相同的导电材料，例如均填充钨金属等，也可以填充不同的导电材料。
在一个实施例中，在步骤S290之后、形成接触孔的步骤之前，还包括形成层间介质(ILD)的步骤。随后，层间介质覆盖绝缘层74和金属场板80。
所述层间介质可为氧化硅层，包括利用热化学气相沉积(thermal CVD)制造工艺或高密度等离子体(HDP)制造工艺形成的有掺杂或未掺杂的氧化硅的材料层，例如未经掺杂的硅玻璃(USG)、磷硅玻璃(PSG)或硼磷硅玻璃(BPSG)。此外，层间介质也可以是掺杂硼或掺杂磷的自旋涂布式玻璃(spin-on-glass，SOG)、掺杂磷的四乙氧基硅烷(PTEOS)或掺杂硼的四乙氧基硅烷(BTEOS)。
在一个实施例中，还可以通过平坦化的方法(例如化学机械研磨CMP)对沉积的层间介质进行平坦化，以使层间介质具有平坦的表面。
在一个实施例中，形成接触孔的方法包括以下步骤：
首先，在层间介质的表面上形成图案化的掩膜层(例如图案化的光刻胶层)，该图案化的掩膜层定义预定形成的第一接触孔92、第二接触孔94、第三接触孔96及第四接触孔98的图案以及位置等。
接着，以图案化的掩膜层为掩膜，蚀刻层间介质，以分别形成第一接触孔、第二接触孔、第三接触孔及第四接触孔。随后去除图案化的掩膜层，可 以使用本领域技术人员习知的方法。
最后，使用导电材料填充第一接触孔、第二接触孔、第三接触孔及第四接触孔，以形成最终的第一接触孔92、第二接触孔94、第三接触孔96及第四接触孔98，如图1所示。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种横向扩散金属氧化物半导体器件，包括：
    衬底；
    漂移区，设置在所述衬底中；
    栅极结构，设置在所述衬底上，包括栅极介电层和栅极介电层上的栅极层；
    漏极区，设置在所述栅极结构的一侧的衬底中，与所述漂移区相接触；
    源极区，设置在所述栅极结构的另一侧的衬底中；及
    类栅结构，设置在所述漂移区上方、所述栅极结构与所述漏极区之间，所述类栅结构的材质与所述栅极层相同，所述类栅结构与所述栅极层之间绝缘。
  2. 根据权利要求1所述的横向扩散金属氧化物半导体器件，其中，还包括：
    金属硅化物阻挡层，覆盖所述类栅结构、覆盖所述漂移区位于所述类栅结构和漏极区之间的表面；及
    金属硅化物，形成于未被金属硅化物阻挡层覆盖的漏极区表面、栅极层表面及源极区表面。
  3. 根据权利要求2所述的横向扩散金属氧化物半导体器件，其中，还包括：
    绝缘层，设置在所述栅极层、金属硅化物阻挡层、漏极区及源极区上；
    金属场板，设置在所述绝缘层上；及
    第一接触孔，与所述金属场板接触以将所述金属场板引出。
  4. 根据权利要求2所述的横向扩散金属氧化物半导体器件，其中，
    所述金属硅化物阻挡层包括氧化物层和氧化物层上的氧化物刻蚀阻挡层，所述横向扩散金属氧化物半导体器件还包括甲接触孔，所述甲接触孔的底部位于所述氧化物刻蚀阻挡层内。
  5. 根据权利要求4所述的横向扩散金属氧化物半导体器件，其中，所述金属硅化物阻挡层包括自下而上依次层叠的氧化硅层、氮化硅层和氮氧化硅层。
  6. 根据权利要求4所述的横向扩散金属氧化物半导体器件，其中，电连接源极区的接触孔与所述甲接触孔电连接在一起并接地。
  7. 根据权利要求1所述的横向扩散金属氧化物半导体器件，其中，所述类栅结构和栅极层之间的最小距离介于0.15微米到0.2微米之间。
  8. 根据权利要求1所述的横向扩散金属氧化物半导体器件，其中，还包括体区，所述体区位于栅极层远离漂移区的一侧，并与所述漂移区间隔，所述源极区形成在体区中，所述体区具有和漂移区相反的导电类型。
  9. 根据权利要求1所述的横向扩散金属氧化物半导体器件，其中，还包括侧墙，所述侧墙设置在栅极结构远离类栅结构的一侧，还设置在类栅结构远离栅极结构的一侧。
  10. 一种横向扩散金属氧化物半导体器件的制造方法，包括：
    获取衬底，所述衬底中形成有漂移区；
    在所述衬底上形成栅极介电层；
    在所述栅极介电层上形成栅极材质；
    使用第一光刻版光刻并对所述栅极材质进行刻蚀，形成栅极层和与所述栅极层分离的类栅结构，所述类栅结构设置在所述漂移区上方，所述第一光刻版包括栅极层图案和类栅结构图案；及
    形成漏极区和源极区，所述漏极区形成于所述栅极层的一侧的衬底中，且与所述漂移区相接触，所述源极区形成于所述栅极层的另一侧的衬底中，所述类栅结构位于所述栅极层和漏极区之间。
  11. 根据权利要求10所述的横向扩散金属氧化物半导体器件的制造方法，其中，所述形成漏极区和源极区的步骤之后，还包括以下步骤：
    形成金属硅化物阻挡层，所述金属硅化物阻挡层覆盖所述类栅结构，还覆盖所述漂移区位于所述类栅结构和漏极区之间的表面；及
    在未被金属硅化物阻挡层覆盖的漏极区表面、栅极层表面及源极区表面形成金属硅化物。
  12. 根据权利要求10所述的横向扩散金属氧化物半导体器件的制造方法，其中，还包括以下步骤：
    在所述栅极层、金属硅化物阻挡层、漏极区及源极区上形成绝缘层；及
    在所述绝缘层上形成金属场板。
  13. 根据权利要求12所述的横向扩散金属氧化物半导体器件的制造方法，其中，还包括形成与所述金属场板接触的第一接触孔，将所述金属场板引出的步骤。
  14. 根据权利要求11所述的横向扩散金属氧化物半导体器件的制造方法，其中，所述金属硅化物阻挡层包括氧化物层和氧化物层上的氧化物刻蚀阻挡层，所述在未被金属硅化物阻挡层覆盖的漏极区表面、栅极层表面及源极区表面形成金属硅化物的步骤之后，还包括形成甲接触孔的步骤，所述甲接触孔的底部位于所述氧化物刻蚀阻挡层内。
  15. 根据权利要求10所述的横向扩散金属氧化物半导体器件的制造方法，其中，所述在所述栅极介电层上形成栅极材质的步骤，是淀积多晶硅。
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