WO2022061737A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2022061737A1
WO2022061737A1 PCT/CN2020/117829 CN2020117829W WO2022061737A1 WO 2022061737 A1 WO2022061737 A1 WO 2022061737A1 CN 2020117829 W CN2020117829 W CN 2020117829W WO 2022061737 A1 WO2022061737 A1 WO 2022061737A1
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Prior art keywords
source
dielectric layer
drain
forming
layer
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PCT/CN2020/117829
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English (en)
French (fr)
Inventor
苏博
吴汉洙
郑春生
郑二虎
张海洋
Original Assignee
中芯国际集成电路制造(上海)有限公司
中芯国际集成电路制造(北京)有限公司
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Application filed by 中芯国际集成电路制造(上海)有限公司, 中芯国际集成电路制造(北京)有限公司 filed Critical 中芯国际集成电路制造(上海)有限公司
Priority to PCT/CN2020/117829 priority Critical patent/WO2022061737A1/zh
Priority to CN202080103614.6A priority patent/CN115997275A/zh
Priority to TW110128226A priority patent/TWI791256B/zh
Publication of WO2022061737A1 publication Critical patent/WO2022061737A1/zh
Priority to US18/124,058 priority patent/US20230223452A1/en

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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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Definitions

  • Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
  • the interconnect structure includes interconnect lines and contact hole plugs formed in the contact openings.
  • the contact hole plug is connected with the semiconductor device, and the interconnection wire realizes the connection between the contact hole plugs, thereby forming a circuit.
  • the contact hole plugs in the transistor structure include gate contact hole plugs located on the surface of the gate structure, which are used to realize the connection between the gate structure and external circuits, and also include source-drain contact hole plugs located on the surface of the source and drain doped regions. , used to connect the source and drain doped regions with external circuits.
  • the problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.
  • an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate on which a gate structure is formed, a sidewall of the gate structure is formed with a dummy spacer, and the dummy A contact hole etch stop layer is formed on the sidewall of the sidewall, and source and drain doped regions are formed in the substrate on both sides of the gate structure; a sacrificial dielectric is formed over the source and drain doped regions and the top of the gate structure forming a source-drain plug, penetrating the sacrificial dielectric layer above the top of the source-drain doped region, and in contact with the source-drain doped region; after forming the source-drain plug, etching the sacrificing the dielectric layer until the top of the dummy spacer is exposed; after exposing the top of the dummy spacer, remove the dummy spacer, and form a gap between the contact hole etch stop layer and the sidewall of the gate structure ; form
  • an embodiment of the present invention further provides a semiconductor structure, including: a substrate; a gate structure, located on the substrate; source and drain doped regions, located in the substrate on both sides of the gate structure; and contact hole etching a stop layer, located on the substrate between the source and drain doped regions and the gate structure and disposed opposite to the sidewall of the gate structure, the contact hole is etched between the stop layer and the sidewall of the gate structure There is a gap; source and drain plugs are located on the top of the source and drain doped regions and are in contact with the source and drain doped regions; a top dielectric layer is filled between the source and drain plugs, and the top dielectric layer layer is also filled in the gap, and the top dielectric layer located in the gap serves as a sidewall, or the top dielectric layer seals the top of the gap to form an air gap.
  • the material of the top dielectric layer It is a low-k dielectric material or an ultra-low-k dielectric material.
  • the technical solution of the embodiment of the present invention has the following advantages: in the formation method provided by the embodiment of the present invention, a dummy spacer is formed on the sidewall of the gate structure, and the source-drain doped region and the gate are formed. A sacrificial dielectric layer is formed over the top of the structure, and a source-drain plug penetrating the sacrificial dielectric layer above the top of the source-drain doped region and in contact with the source-drain doped region is formed.
  • the sacrificial dielectric layer is etched Until the top of the dummy spacer is exposed, and the dummy spacer is removed, a gap is formed between the contact hole etch stop layer and the sidewall of the gate structure, and then a top dielectric layer filled between the source and drain plugs is formed, and the top dielectric Layers also fill in gaps, forming sidewalls that sit in gaps, or seal the tops of gaps, creating air gaps.
  • the material dielectric constant of the top dielectric layer is smaller than the material dielectric constant of the dummy spacer; wherein, the material dielectric constant is formed by removing the dummy spacer and forming a top dielectric layer with a lower material dielectric constant Lower spacers or air gaps, thereby reducing the effective capacitance between the gate structure and the source-drain plug, thereby improving the performance of the semiconductor structure.
  • the material of the dummy spacer can be flexibly selected, so that the material of the dummy spacer is compatible with the subsequent process, which is beneficial to improve the performance of the semiconductor structure accordingly.
  • 1 to 4 are schematic structural diagrams corresponding to each step in a method for forming a semiconductor structure.
  • 5 to 16 are schematic structural diagrams corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.
  • the performance of the current semiconductor structure needs to be improved. Now combined with a method for forming a semiconductor structure, the reasons for its performance to be improved are analyzed.
  • 1 to 4 are schematic structural diagrams corresponding to each step in a method for forming a semiconductor structure.
  • a substrate 10 is provided, a dummy gate structure 20 is formed on the substrate 10, sidewalls 22 are formed on the sidewalls of the dummy gate structure 20, and source and drain doped regions 11 are formed in the substrate 10 on both sides of the dummy gate structure 20, A bottom dielectric layer 12 covering the source and drain doped regions 11 is formed on the substrate 10 at the side of the dummy gate structure 20 .
  • the dummy gate structure 20 is removed, and a gate opening 25 is formed in the bottom dielectric layer 12 .
  • a gate structure 30 is formed in the gate opening 25 (shown in FIG. 2).
  • a top dielectric layer 40 is formed over the top of the source-drain doped region 11 and the gate structure 30 ; a source-drain plug 50 is formed to penetrate the top dielectric layer 40 and the bottom dielectric layer above the top of the source-drain doped region 11 12, and is in contact with the source and drain doped regions 11.
  • the step of forming the source-drain doped region 11 usually includes: using the spacer 22 as a mask, etching the substrate 10 on both sides of the dummy gate structure 20, and forming a groove in the substrate 10 (not shown in the figure).
  • the groove is pre-cleaned; after the pre-cleaning treatment, an epitaxial layer is formed in the groove, and in the process of forming the epitaxial layer, ions are self-doped in situ and doped with ions
  • the epitaxial layer is used as the source-drain doped region 11 .
  • the process of removing the dummy gate structure 20 usually includes a wet etching process.
  • the etching resistance of the sidewall spacers 20 is also proposed. request.
  • the dielectric constant of the material of the spacer 20 is usually high (for example, the material of the spacer 20 is silicon nitride), so that the gap between the gate structure 30 and the source-drain plug 50 is caused.
  • the effective capacitance between them is large.
  • an embodiment of the present invention provides a method for forming a semiconductor structure, including: forming a contact hole etch stop layer on the sidewall of the dummy spacer, and forming an active electrode in the substrate on both sides of the gate structure A drain doped region; a sacrificial dielectric layer is formed over the top of the source and drain doped regions and the gate structure; a source-drain plug is formed, penetrating the sacrificial dielectric layer above the top of the source and drain doped regions, and is connected with the source and drain doped regions are in contact; after the source and drain plugs are formed, the sacrificial dielectric layer is etched until the top of the dummy spacer is exposed; after the top of the dummy spacer is exposed, the dummy is removed sidewalls, forming a gap between the contact hole etch stop layer and the sidewall of the gate structure; forming a top dielectric layer filled between the source and drain plugs, and the top dielectric layer is also
  • a spacer or an air gap with a lower dielectric constant is formed, thereby reducing the gate structure and the size of the air gap. Effective capacitance between source and drain plugs, thereby improving the performance of the semiconductor structure.
  • the material of the dummy sidewall can be flexibly selected, so that the material of the dummy sidewall is compatible with the subsequent process, which is beneficial to improve the performance of the semiconductor structure accordingly.
  • 5 to 16 are schematic structural diagrams corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.
  • a substrate 100 is provided, a gate structure 400 is formed on the substrate 100 , a dummy spacer 220 is formed on a sidewall of the gate structure 400 , and a contact is formed on the sidewall of the dummy spacer 220
  • the hole etch stop layer 300 is formed, and the source and drain doped regions 110 are formed in the substrate 100 on both sides of the gate structure 400 .
  • the substrate 100 is used to provide a process platform for subsequent processes.
  • the substrate 100 is a planar substrate.
  • the substrate is used to form a fin field effect transistor (FinFET), and accordingly, the substrate includes a substrate and a fin protruding from the substrate.
  • FinFET fin field effect transistor
  • the base 100 is a silicon substrate.
  • the substrate may also be a substrate of other material types.
  • the material of the substrate can be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate or other materials. type of substrate.
  • the substrate 100 includes a device region 100b and an isolation region 100a, the device region 100b is used to form a transistor, and the remaining region outside the device region 100b is Quarantine 100a.
  • the device area 100b is an active area (Active Area, AA), and an active gate contact hole plug (Contact Over Active Gate, COAG) is subsequently formed on the top of the gate structure 400 in the active area ), thereby saving chip area.
  • the gate structure 400 is formed by a process of forming a high-k gate dielectric layer and then forming a gate electrode layer (high k last metal gate last). Therefore, referring to FIG. 5 and FIG. 6 , after forming the gate electrode Before the structure 400 , the forming method further includes: forming a dummy gate structure (dummy gate) 200 on the substrate 100 .
  • FIG. 5 is a top view, and for convenience of illustration, only the substrate 100 , the dummy gate structure 200 and the source-drain doped region 110 are shown, and FIG. 6 is a cross-sectional view of FIG. 5 along the secant line A1A2 .
  • the dummy gate structure 200 is formed on the substrate 100 of the device region 100b.
  • the dummy gate structure 200 is used to occupy a space for the formation of the subsequent gate structure 400 .
  • the dummy gate structure 200 is a polysilicon gate structure, that is, the dummy gate structure 200 includes a dummy gate layer, and the material of the dummy gate layer is polysilicon.
  • the material of the dummy gate layer may further include other materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or amorphous carbon.
  • the dummy gate structure 200 is a single-layer structure, and the dummy gate structure 200 only includes a dummy gate layer.
  • the dummy gate structure may also be a stacked structure, correspondingly including a dummy gate oxide layer and a dummy gate layer on the dummy gate oxide layer, wherein the material of the dummy gate oxide layer may be silicon oxide.
  • dummy spacers 220 are formed on the sidewalls of the dummy gate structure 200 .
  • the dummy sidewall spacers 220 are used to protect the sidewalls of the dummy gate structure 200 and also used to define the formation positions of the source and drain doped regions 110 .
  • the dummy spacers 220 and the source-drain doped regions 110 are located in the device region 100b.
  • the subsequent steps further include: removing the dummy spacer 220 and forming a gap at the position of the dummy spacer 220. Therefore, the dummy spacer 220 is used to occupy space for forming the gap.
  • a top dielectric layer with a smaller dielectric constant will be formed. In order to enable the material of the top dielectric layer to have a lower dielectric constant, the material of the top dielectric layer is usually loose in structure and low in density.
  • the material of the dummy spacer 220 can be selected flexibly, so that the material of the dummy spacer 220 is compatible with the subsequent process, and there are corresponding It is beneficial to improve the performance of the semiconductor structure.
  • the etch resistance of the dummy spacer 220 is relatively high, and the probability of damage to the dummy spacer 220 is low in the subsequent process of removing the dummy gate structure 200 , or the source-drain doped region 110 is formed. During the process, the probability of the dummy sidewall 220 being damaged is low.
  • the material of the dummy spacer 220 is selected as follows: during the process of removing the dummy spacer 220, the dummy spacer 220 and other film layers (for example, , gate structure or contact hole etch stop layer 300, etc.), the etching selection is relatively high, so that the process of removing the dummy spacer 220 causes less damage to other film layers.
  • the dummy spacer 220 may be a single-layer structure or a laminated structure, and the material of the dummy spacer 220 may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, boron nitride, aluminum oxide and aluminum nitride one or more of.
  • the dummy spacer 220 is a single-layer structure, and the material of the dummy spacer 220 is silicon oxide.
  • the hardness and density of silicon oxide are relatively high, therefore, the damage to the dummy spacers 220 is small in the subsequent process, so that the dummy spacers 220 can be compatible with the subsequent processes, and silicon oxide is a material that can be easily removed, This facilitates subsequent removal of the dummy sidewall spacers 220 .
  • a gap is formed at the position of the dummy spacer 220, and a spacer is formed in the gap.
  • the width of the dummy spacer 220 is too small, It is difficult for the material of the spacer to fill the gap, resulting in an ineffective reduction of the effective capacitance between the gate structure and the source-drain plug; when the width of the dummy spacer 220 is too large, the source The distance between the drain doped region 110 and the subsequent gate structure is too large, so that the channel length is too large, which in turn causes the device size to be too large, and it is difficult to meet the development requirements of device miniaturization.
  • the width of the dummy sidewall spacers 220 is 2 nm to 12 nm.
  • the width of the dummy spacer 220 is 5 nanometers, 7 nanometers or 10 nanometers.
  • the steps of forming the dummy spacers 220 include: forming a dummy spacer material layer (not shown) conformally covering the dummy gate structure 200 and the substrate 100 ; removing the dummy spacer material layers on both sides of the dummy gate structure 200 to expose Parts of the substrate 100 on both sides of the dummy gate structure 200 and the remaining dummy spacer material layers serve as the dummy spacers 220 .
  • the dummy spacer 220 also covers the top of the dummy gate structure 200 .
  • the forming method further includes: forming an offset spacer 210 conformally covering the dummy gate structure 200 and the substrate 100 .
  • the offset spacers 210 are used to increase the channel length of the formed transistor, thereby improving the short channel effect and the hot carrier effect caused by the short channel effect.
  • the offset spacers 210 exposed by the dummy spacers 220 are also removed. Therefore, the remaining offset spacers 210 are located between the dummy spacers 220 and the dummy gates. between the structures 200 and between the dummy spacers 220 and the substrate 100 .
  • the material of the offset spacers 210 is silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon oxynitride or silicon oxynitride. In this embodiment, the material of the offset spacers 210 is silicon nitride.
  • source and drain doped regions 110 are formed in the substrate 100 on both sides of the dummy gate structure 200 . Specifically, the source and drain doped regions 110 are located in the device region 100b (as shown in FIG. 5 ). The source and drain doped regions 110 serve as source or drain regions of the formed transistor.
  • the source and drain doped regions 110 are formed by an epitaxy process.
  • the step of forming the source-drain doped region 110 includes: using the dummy spacer 220 as a mask, etching the substrate 100 on both sides of the dummy gate structure 200 to form a groove; using an epitaxial process to form a groove in the groove.
  • the epitaxial layer, and in the process of forming the epitaxial layer, self-doping ions in-situ, the epitaxial layer doped with ions is used as the source-drain doping region 110 .
  • the material of the epitaxial layer is Si or SiC, and the epitaxial layer provides tensile stress to the channel region of the NMOS transistor, thereby helping to improve the carrier mobility of the NMOS transistor, wherein the doping in the epitaxial layer
  • the ions are N-type ions, and the N-type ions include P ions, As ions or Sb ions.
  • the material of the epitaxial layer is Si or SiGe, and the epitaxial layer provides compressive stress to the channel region of the PMOS transistor, thereby helping to improve the carrier mobility of the PMOS transistor.
  • the doping in the epitaxial layer The ions are P-type ions, and the P-type ions include B ions, Ga ions or In ions.
  • a contact etch stop layer is formed to conformally cover the dummy spacers 220 , the dummy gate structures 200 and the substrate 100 . stop layer, CESL) 300.
  • the step of etching the bottom dielectric layer is included.
  • the contact hole etching stop layer 300 is used to define the etching process. stop position, so as to avoid over-etching of the source and drain doped regions 110 .
  • the materials of the contact hole etch stop layer 300 include low-k dielectric materials (low-k dielectric materials refer to dielectric materials with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9), ultra-low-k dielectric materials (ultra-low-k dielectric materials).
  • the dielectric material refers to a dielectric material with a relative dielectric constant less than 2.6) or silicon nitride.
  • the contact hole etch stop layer 300 is also located between the source-drain plug and the gate structure. Therefore, the contact hole etch stop layer 300 It also affects the effective capacitance between the source-drain plug and the gate structure.
  • an anti-diffusion layer 310 is further formed between the dummy spacer 220 and the contact hole etch stop layer 300 .
  • the anti-diffusion layer 310 is used to prevent easily diffusible ions in the dummy spacers 220 from diffusing into the contact hole etch stop layer 300 , thereby preventing the problem of increasing the dielectric constant of the contact hole etch stop layer 300 due to ion diffusion. .
  • the material of the contact hole etch stop layer 300 is a low-k dielectric material or an ultra-low-k dielectric material
  • the material of the dummy spacer 220 is an oxygen-containing material (eg, silicon oxide). Diffusion into the contact hole etch stop layer 300 will cause the dielectric constant of the contact hole etch stop layer 300 to increase.
  • the anti-diffusion layer 310 is formed therebetween, which can reduce the probability that the dielectric constant of the material of the contact hole etch stop layer 300 increases. Therefore, the density of the anti-diffusion layer 310 is high.
  • the anti-diffusion layer 310 is subsequently retained, therefore, the material of the anti-diffusion layer 310 is an insulating material.
  • the material of the anti-diffusion layer 310 includes silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, boron carbonitride, aluminum oxide, and aluminum nitride.
  • the material of the anti-diffusion layer 310 is silicon nitride.
  • the anti-diffusion layer 310 is also located between the source-drain plug and the gate structure, and the anti-diffusion layer 310 also affects the effective capacitance between the source-drain plug and the gate structure.
  • the dielectric constant of the material of the anti-diffusion layer 310 is relatively large, therefore, when the thickness of the anti-diffusion layer 310 is too large, the effective capacitance between the source-drain plug and the gate structure is likely to be too large, and, Also, the distance between the source-drain doped region 110 and the gate structure is too large, so that the channel length is too large, and thus the device size is too large, and it is difficult to meet the development requirements of device miniaturization. Therefore, while ensuring the anti-diffusion effect of the anti-diffusion layer 310 on ions, and considering the above effects comprehensively, the thickness of the anti-diffusion layer 310 is less than or equal to 30 ⁇ .
  • the thickness of the anti-diffusion layer 310 is less than or equal to 15 ⁇ , so that the effective capacitance between the source-drain plug and the gate structure is small while ensuring the effect of the anti-diffusion layer 310 to prevent ion diffusion.
  • the thickness of the anti-diffusion layer 310 is 5 ⁇ to 15 ⁇ .
  • the thickness of the anti-diffusion layer 310 is 10 ⁇ .
  • the contact hole etch stop layer 300 is correspondingly formed on the anti-diffusion layer 310 .
  • the process of forming the anti-diffusion layer 310 includes an atomic layer deposition process, a chemical vapor deposition process, or a plasma enhanced chemical vapor deposition process.
  • the anti-diffusion layer 310 is formed by an atomic layer deposition process.
  • the thickness of the anti-diffusion layer 310 is relatively small. By using the atomic layer deposition process, it is easy to form the anti-diffusion layer 310 with a small thickness, and the thickness uniformity of the anti-diffusion layer 310 is good. In addition, the anti-diffusion layer 310 has good steps coverage capability.
  • a bottom dielectric layer 101 is formed on the substrate 100 on the side of the dummy gate structure 200 .
  • the bottom dielectric layer 101 is used to isolate adjacent devices.
  • the bottom dielectric layer 101 is an interlayer dielectric layer (Inter Layer Dielectric, ILD).
  • the material of the bottom dielectric layer 101 is an insulating material, and the material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.
  • the material of the bottom dielectric layer 101 is silicon oxide.
  • the bottom dielectric layer 101 is formed through a deposition and planarization process (eg, chemical mechanical polishing process), so that the top of the dummy gate structure 200 is exposed from the bottom dielectric layer 101 .
  • the top of the bottom dielectric layer 101 is flush with the top of the dummy gate structure 200 .
  • the contact hole etch stop layer 300 , the anti-diffusion layer 310 , the dummy spacer 220 and the offset above the tops of the dummy spacers 220 and the dummy gate structures 200 are removed Side wall 210.
  • the dummy gate structure 200 is removed, a gate opening 102 is formed in the bottom dielectric layer 101 (as shown in FIG. 9 ); a gate structure 400 is formed in the gate opening 102 (as shown in FIG. 10 ) ).
  • the gate structure 400 is located in the device region 100 b (as shown in FIG. 5 ), and a bottom dielectric layer 101 is formed on the substrate 100 exposed by the gate structure 400 , and the bottom dielectric layer 101 covers Source and drain doped regions 110 .
  • the gate structure 400 is used to control the on or off of the conductive channel.
  • the gate structure 400 is a metal gate structure, and the gate structure 400 includes a high-k gate dielectric layer (not shown) that conformally covers the bottom and sidewalls of the gate opening 102 , and a high-k gate dielectric layer (not shown) on the high-k gate dielectric layer.
  • a work function layer (not shown in the figure), and a gate electrode layer (not shown in the figure) on the work function layer.
  • the material of the high-k gate dielectric layer is a high-k dielectric material, wherein the high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide.
  • the material of the high-k gate dielectric layer may be selected from HfO 2 , ZrO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al 2 O 3 and the like.
  • the material of the high-k gate dielectric layer is HfO 2 .
  • the work function layer is used to adjust the threshold voltage of the formed transistor.
  • the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN and TiAlN;
  • the work function layer It is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN and TiAlC.
  • the gate electrode layer is used to extract the electrical properties of the gate structure 200 .
  • the material of the gate electrode layer is Al, Cu, Ag, Au, Pt, Ni, Ti or W.
  • the density and hardness of the dummy spacers 220 are relatively high, and therefore, the process of removing the dummy gate structure 200 causes less damage to the dummy spacers 220 .
  • the forming method further includes: in the device region 100 b (as shown in FIG. 5 ), forming a bottom dielectric layer penetrating the top of the source-drain doped region 110 101 and the bottom source-drain plug 120 in contact with the source-drain doped region 110 , and the source-drain capping layer 130 located on the top surface of the bottom source-drain plug 120 .
  • a top source-drain plug contacting the bottom source-drain plug 120 is subsequently formed on the bottom source-drain plug 120 , and the top source-drain plug and the bottom source-drain plug 120 constitute a source-drain plug.
  • the material of the bottom source-drain plug 120 is copper.
  • the lower resistivity of copper is beneficial to improving the signal delay of the RC in the latter stage, increasing the processing speed of the chip, and also helping to reduce the resistance of the bottom source-drain plug 120, thereby reducing power consumption accordingly.
  • the material of the bottom source-drain plug may also be a conductive material such as tungsten or cobalt.
  • the sacrificial dielectric layer on the top of the gate structure 400 in the Active Area (AA) region is formed in contact with the gate structure 400 .
  • the gate plug, the source-drain cap layer 130 is located on the top surface of the bottom source-drain plug 120, and is used to protect the bottom source-drain plug 120 during the process of forming the gate plug, which is beneficial to reduce the bottom
  • the source-drain plug 120 is damaged and the probability that the gate plug and the bottom source-drain plug 120 are shorted.
  • the source-drain capping layer 130 is selected from materials with higher etching selectivity than the gate capping layer, the dummy sidewall spacers 220 , the bottom dielectric layer 101 and the sacrificial dielectric layer formed subsequently, which is beneficial to ensure that the source-drain capping layer 130 can be responsive to the bottom.
  • the source-drain plug 120 plays a protective role.
  • the material of the source-drain capping layer 130 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride and boron carbonitride.
  • the materials of the source-drain capping layer 130 and the gate capping layer are different, and the materials of the source-drain capping layer 130 and the dummy spacers 220 are different.
  • the material of the source-drain capping layer 130 is silicon carbide.
  • the top surface of the source-drain cap layer 130 and the bottom dielectric layer 101 are flush with each other.
  • 11 is a cross-sectional view at the position of the device region 100b, therefore, the bottom dielectric layer 101 located in the isolation region 100a (as shown in FIG. 5) is not shown.
  • the forming method further includes: forming a gate capping layer 410 on the top surface of the gate structure 400 .
  • the gate capping layer 410 is used to protect the gate structure 400, so as to reduce the damage to the gate structure 400 and the reduction of the top source-drain plug during the formation of the top source-drain plug. The probability that the drain plug is shorted to the gate structure 400 .
  • the gate structure 400 is etched back to remove a partial thickness of the gate structure 400 ; after the partial thickness of the gate structure 400 is removed, a gate is formed on the top of the remaining gate structure 400 Pole cap layer 410 .
  • the top surfaces of the gate capping layer 410 and the bottom dielectric layer 101 are flush.
  • the gate capping layer 410 is selected from a material having etching selectivity with the source-drain capping layer 130 , the bottom dielectric layer 101 and the sacrificial dielectric layer formed subsequently, so as to help ensure that the gate capping layer 410 can effectively protect the gate structure 400 . to protection.
  • the material of the gate capping layer 410 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride and boron carbonitride kind.
  • the material of the gate capping layer 410 is silicon nitride.
  • a sacrificial dielectric layer 140 is formed over the top of the source and drain doped regions 110 and the gate structure 400 .
  • the sacrificial dielectric layer 140 is formed on the bottom dielectric layer 101 .
  • the sacrificial dielectric layer 140 is used to provide a process basis for the subsequent formation of top source-drain plugs and gate plugs.
  • the material of the sacrificial dielectric layer 140 is an insulating material. Moreover, the sacrificial dielectric layer 140 will be etched later, therefore, the sacrificial dielectric layer 140 is selected from a material that is easy to be etched.
  • the material of the sacrificial dielectric layer 140 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, boron nitride, aluminum oxide, and aluminum nitride.
  • the material of the sacrificial dielectric layer 140 is the same as the material of the dummy spacer 220 , which facilitates the subsequent etching of the sacrificial dielectric layer 140 and the dummy spacer 220 in the same etching step.
  • the material of the sacrificial dielectric layer 140 is silicon oxide.
  • a source-drain plug 180 (as shown in FIG. 14 ) is formed, penetrating the sacrificial dielectric layer 140 above the top of the source-drain doped region 110 , and being in phase with the source-drain doped region 110 touch.
  • the source-drain plugs 180 are used to achieve electrical connection between the source-drain doped regions 110 and external circuits or other interconnect structures.
  • the steps of forming the source-drain plugs 180 include: forming the top source-drain plugs 122 and the top source-drain plugs 125 penetrating the sacrificial dielectric layer 140 and the source-drain capping layer 130 above the top of the source-drain doped region 110 Contact with the bottom source-drain plug 120 , and the top source-drain plug 122 and the bottom source-drain plug 120 constitute a source-drain plug 180 .
  • the sacrificial dielectric layer 140 and the source-drain capping layer 130 above the top of the source-drain doped region 110 are sequentially etched to form source-drain contact holes 160 exposing the bottom source-drain plugs 120 ; as shown in FIG. 14 As shown, the top source-drain plug 122 is formed in the source-drain contact hole 160 .
  • the material of the top source-drain plug 122 reference may be made to the foregoing description of the bottom source-drain plug 120, and details are not repeated here.
  • the forming method further includes: forming a gate plug 170 (as shown in FIG. 14 ), penetrating the sacrificial dielectric layer 140 and the gate capping layer 410 above the top of the gate structure 400 (as shown in FIG. 12 ) ) and in contact with the gate structure 400 .
  • the gate plug 170 is used to make electrical connection between the gate structure 400 and external circuits or other interconnect structures.
  • the gate plug 170 is formed above the gate structure 400 in the active region, and the gate plug 170 is an active gate contact hole plug (Contact Over Active Gate, COAG), compared with the scheme in which the gate plug is in contact with the gate structure located in the isolation region, this embodiment omits the part of the gate structure 400 located in the isolation region, which is beneficial to save the area of the chip and realize the Further reduction in chip size.
  • COAG Active Gate
  • the sacrificial dielectric layer 140 and the gate capping layer 410 above the top of the gate structure 400 are sequentially etched to form the gate contact hole 150 exposing the top of the gate structure 400 ; as shown in FIG. 14 , A gate plug 170 is formed in the gate contact hole 150 .
  • the top source-drain plug 125 and the gate plug 170 are formed in the same step. It should be noted that, in this embodiment, the gate plug 170 is formed before the sacrificial dielectric layer 140 is etched, so as to reduce changes to the current process and improve the process compatibility of the formation method.
  • the sacrificial dielectric layer 140 is etched until the top of the dummy spacer 220 (as shown in FIG. 13 ) is exposed; after the top of the dummy spacer 220 is exposed, the dummy spacer 220 is removed, and the A gap 190 is formed between the contact hole etch stop layer 300 and the sidewall of the gate structure 400 .
  • the gap 190 is used to provide a space for the subsequent formation of sidewalls.
  • the step of etching the sacrificial dielectric layer 140 until the top of the dummy spacer 220 is exposed includes: removing the sacrificial dielectric layer 140 located in the device region 100 b (as shown in FIG. 5 ). By removing only the sacrificial dielectric layer 140 of the device region 100b, the impact on the isolation region 100a (as shown in FIG. 5) is reduced.
  • the top dielectric layer filled between the source and drain plugs 180 is subsequently formed.
  • only the sacrificial dielectric layer 140 is etched, and the bottom dielectric layer 101 is not etched.
  • the top dielectric layer is filled in the top source and drain plugs. Between 125, the aspect ratio of the space filled by the top dielectric layer is small, which reduces the technological difficulty of forming the top dielectric layer, and is beneficial to improve the formation quality of the top dielectric layer.
  • an isotropic etching process is used to remove the sacrificial dielectric layer 140 and the dummy sidewall spacers 220 in the device region 100b.
  • an isotropic etching process By using an isotropic etching process, the sacrificial dielectric layer 140 and the dummy sidewall spacers 220 in the device region 100b can be removed cleanly, and the etching rate is relatively fast.
  • the isotropic etching process is a remote plasma etching process.
  • the remote plasma etching process has isotropic etching characteristics, and the remote plasma etching process also has good etching selectivity, thereby reducing the loss of other film layers during the etching process.
  • the principle of the remote plasma etching process is to form plasma outside the etching chamber (for example, plasma generated by a remote plasma generator), and then introduce it into the etching chamber and use the plasma to interact with the layer to be etched.
  • the chemical reaction is used for etching, so an isotropic etching effect can be achieved, and because there is no ion bombardment, other film layers will not be damaged.
  • the isotropic etching process may also be a wet etching process.
  • the materials of the sacrificial dielectric layer 140 and the dummy spacers 220 are the same. Therefore, the sacrificial dielectric layer 140 and the dummy spacers 220 in the device region 100b can be removed in the same etching step, which simplifies the process steps.
  • a top dielectric layer 500 filled between the source and drain plugs 180 is formed, and the top dielectric layer 500 is also filled in the gap 190 to form a spacer 510 located in the gap 190 .
  • the dielectric constant of the material of the top dielectric layer 500 The dielectric constant of the material is smaller than that of the dummy spacer 220 (shown in FIG. 14 ).
  • the top dielectric layer 500 is filled between the source-drain plug 180 and the gate plug 170 .
  • the spacers 510 with a lower dielectric constant are formed, thereby reducing the gate structure 400 and the source-drain plugs 180 (specifically, the bottom effective capacitance between the source-drain plugs 120), thereby improving the performance of the semiconductor structure.
  • the material of the top dielectric layer 500 includes a low-k dielectric material or an ultra-low-k dielectric material. Therefore, the dielectric constant of the material of the sidewall spacer 510 is small, so that the gate structure 400 and the source and drain can be reduced. Effective capacitance between plugs 180. Moreover, in this embodiment, in order to further reduce the transistor area, an active gate contact hole plug (Contact Over Active Gate, COAG) process, the distance between the gate plugs 170 and the source-drain plugs 180 is correspondingly small, and the top dielectric layer 500 is filled between the source-drain plugs 180.
  • COAG Contact Over Active Gate
  • the top dielectric layer 500 is also beneficial to reduce the parasitic capacitance between the gate plug 170 and the source-drain plug 180 .
  • the top dielectric layer seals the top of the gap to form an air gap.
  • the dielectric constant of air is relatively small, which can correspondingly reduce the effective capacitance between the gate structure and the source-drain plug.
  • the top dielectric layer 500 is formed by a spin coating process.
  • the process temperature of the spin coating process is relatively low, so as to avoid the problem of channel degradation caused by high temperature, which is beneficial to improve the performance of the semiconductor structure.
  • the top dielectric layer may also be formed by chemical vapor deposition, fluid chemical vapor deposition, or atomic layer deposition.
  • the top dielectric layer 500 covers the top of the source-drain plug 180 .
  • the subsequent process further includes: forming a metal interconnection line electrically connected to the source-drain plug 180 on the top of the source-drain plug 180 , and the metal interconnection line is formed in an inter metal dielectric (IMD) layer.
  • IMD inter metal dielectric
  • the dielectric layer 500 covers the tops of the source-drain plugs 180 , so that the top dielectric layer 500 higher than the tops of the source-drain plugs 180 serves as an inter-metal dielectric layer, thereby simplifying the process steps of the back-end-of-line (BEOL) process.
  • BEOL back-end-of-line
  • the top of the top dielectric layer is flush with the top of the source-drain plug, or the top of the top dielectric layer is lower than the top of the source-drain plug, so that the inter-metal dielectric can be selected flexibly layer materials to meet the performance requirements of the semiconductor structure.
  • the COAG process is used as an example for description.
  • the method can still achieve the effect of reducing the effective capacitance between the source-drain plug and the gate structure.
  • the present invention also provides a semiconductor structure.
  • a schematic structural diagram of an embodiment of the semiconductor structure of the present invention is shown.
  • the semiconductor structure includes: a substrate 100; a gate structure 400, located on the substrate 100; a source-drain doped region 110, located in the substrate 100 on both sides of the gate structure 400; a contact hole etching stop layer 300, located on the source-drain doped region 110
  • a gap 190 between the contact hole etch stop layer 300 and the sidewall of the gate structure 400 (as shown in FIG. 14 ).
  • the source-drain plug 180 is located on top of the source-drain doped region 110 and is in contact with the source-drain doped region 110; the top dielectric layer 500 is filled between the source-drain plugs 180, and the top dielectric layer 500 It is also filled in the gap 190, and the top dielectric layer 500 located in the gap 190 serves as the sidewall 510, or the top dielectric layer 500 seals the top of the gap 190 to form an air gap, and the material of the top dielectric layer 500 is low-k dielectric. Electrical materials or ultra-low-k dielectric materials.
  • the base 100 is a planar substrate. In other embodiments, the base includes a substrate and fins protruding from the substrate. In this embodiment, the base 100 is a silicon substrate. In other embodiments, the substrate may also be a substrate of other material types.
  • the material of the base can be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the base can also be other types of substrates, such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. .
  • the substrate 100 includes a device region 100b and an isolation region 100a, the device region 100b is used to form a transistor, and the remaining region outside the device region 100b is Quarantine 100a.
  • the device region 100b is an active region.
  • FIG. 16 is a cross-sectional view at the position of the A1A2 secant line based on FIG. 5 .
  • the gate structure 400 is located on the substrate 100 of the device region 100b, and the gate structure 400 is used to control the turn-on or turn-off of the conductive channel.
  • the gate structure 400 is a metal gate structure, including a high-k gate dielectric layer (not shown), a work function layer (not shown) on the high-k gate dielectric layer, and a gate on the work function layer electrode layer (not shown).
  • the specific description of the gate structure 400 can be combined with the corresponding descriptions of the foregoing embodiments, and will not be repeated here.
  • the semiconductor structure further includes: offset sidewall spacers 210 located on the sidewalls of the gate structure 400 exposed by the gap 190 .
  • the offset spacers 210 are used to increase the channel length of the formed transistor, thereby improving the short channel effect and the hot carrier effect caused by the short channel effect.
  • the material of the offset spacers 210 is silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon oxynitride or silicon oxynitride. In this embodiment, the material of the offset spacers 210 is silicon nitride.
  • the gap 190 is formed by removing the dummy spacers, and the offset spacers 210 are formed before the dummy spacers are formed. Therefore, the offset spacers 210 are also The extension covers the bottom of gap 190 .
  • the source and drain doped regions 110 are located in the device region 100b, and the source and drain doped regions 110 serve as source or drain regions of the formed transistor.
  • the source-drain doped region 110 is formed by an epitaxial process, and the source-drain doped region 110 includes an epitaxial layer doped with ions.
  • the semiconductor structure is an NMOS transistor
  • the material of the epitaxial layer is Si or SiC
  • the doping ions in the epitaxial layer are N-type ions
  • the N-type ions include P ions, As ions or Sb ions.
  • the material of the epitaxial layer is Si or SiGe
  • the dopant ions in the epitaxial layer are P-type ions
  • the P-type ions include B ions, Ga ions or In ions.
  • the semiconductor structure further includes: a bottom dielectric layer 101 (as shown in FIG. 9 ) located on the substrate 100 at the side of the gate structure 400 , and the bottom dielectric layer 101 covers the source and drain doped regions 110 .
  • the bottom dielectric layer 101 is used to isolate adjacent devices.
  • the bottom dielectric layer 110 is an interlayer dielectric layer.
  • the material of the bottom dielectric layer 101 is an insulating material, and the material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.
  • the material of the bottom dielectric layer 101 is silicon oxide.
  • the contact hole etch stop layer 300 covers the sidewall of the dummy spacer, and the gap 190 is formed by removing the dummy spacer. Therefore, the contact hole etch stop layer 300 is located in the source-drain doped region 110 and the gate structure 400 are disposed on the substrate 100 and opposite to the sidewall of the gate structure 400 , and there is a gap 190 between the contact hole etch stop layer 300 and the sidewall of the gate structure 400 .
  • the step of etching the bottom dielectric layer 101 is included.
  • the drain doped region 110 is over-etched.
  • the material of the contact hole etch stop layer 300 includes low-k dielectric material, ultra-low-k dielectric material or silicon nitride.
  • the contact hole etch stop layer 300 is also located between the source-drain plug 180 and the gate structure 400 . Therefore, the contact hole etch stop layer 300 also affects the relationship between the source-drain plug 180 and the gate structure 400 .
  • the semiconductor structure further includes: an anti-diffusion layer 310 , and a sidewall of the etch stop layer 300 of the contact hole exposed in the gap 190 .
  • the anti-diffusion layer 310 is used to prevent easily diffusible ions in the dummy spacers from diffusing into the contact hole etch stop layer 300 , thereby preventing the problem of increasing the dielectric constant of the contact hole etch stop layer 300 due to ion diffusion.
  • the material of the contact hole etch stop layer 300 is a low-k dielectric material or an ultra-low-k dielectric material
  • the material of the dummy spacer is usually an oxygen-containing material (eg, silicon oxide).
  • the anti-diffusion layer 310 can reduce the probability that the material of the contact hole etching stop layer 300 will increase the dielectric constant.
  • the density of the anti-diffusion layer 310 is high, and the material of the anti-diffusion layer 310 is an insulating material.
  • the material of the anti-diffusion layer 310 includes one of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, boron carbonitride, aluminum oxide, and aluminum nitride variety.
  • the material of the anti-diffusion layer 310 is silicon nitride.
  • the anti-diffusion layer 310 is also located between the source-drain plug 180 and the gate structure 400 , and the anti-diffusion layer 310 also affects the effective capacitance between the source-drain plug 180 and the gate structure 400 .
  • the dielectric constant of the material of the diffusion layer 310 is relatively large. Therefore, when the thickness of the anti-diffusion layer 310 is too large, the effective capacitance between the source-drain plug 180 and the gate structure 400 is likely to be too large. As a result, the distance between the source-drain doped region 110 and the gate structure 400 is too large, resulting in an excessively large channel length, which in turn results in an excessively large device size, making it difficult to meet the development requirements of device miniaturization. Therefore, while ensuring the anti-diffusion effect of the anti-diffusion layer 310 on ions, considering the above effects comprehensively, the thickness of the anti-diffusion layer 310 is less than or equal to 30 ⁇ .
  • the thickness of the anti-diffusion layer 310 is less than or equal to 15 ⁇ , so that the effective capacitance between the source-drain plug 180 and the gate structure 400 is smaller while ensuring the effect of the anti-diffusion layer 310 to prevent ion diffusion. .
  • the thickness of the anti-diffusion layer 310 is 5 ⁇ to 15 ⁇ .
  • the width of the gap 190 should not be too small or too large.
  • the width of the gap 190 is 2 nm to 12 nm.
  • the anti-diffusion layer 310 is formed. Therefore, the anti-diffusion layer 310 is also located in the contact hole etch. between the bottom of the etch stop layer 300 and the substrate 100 .
  • the source-drain plugs 180 are used to achieve electrical connection between the source-drain doped regions 110 and external circuits or other interconnect structures.
  • the material of the source-drain plug 180 is copper.
  • the material of the source-drain plug may also be a conductive material such as tungsten or cobalt.
  • the gate plugs in the semiconductor structure are contact over active gate (COAG) plugs. Therefore, the source-drain plugs 180 include: bottom source-drain plugs 120 , The bottom dielectric layer 101 above the source and drain doped regions 110 is penetrated and in contact with the source and drain doped regions 110 ; the top source and drain plugs 122 are located on and in contact with the bottom source and drain plugs 120 .
  • the semiconductor structure further includes: a source-drain capping layer 130 located between the top of the bottom source-drain plug 120 and the top dielectric layer 500 .
  • the semiconductor structure typically further includes a gate plug located in and in contact with the top dielectric layer 500 on top of the gate structure 400 in the active region, and a source-drain capping layer 130 located at the bottom of the source-drain plug 120
  • the top surface is used to protect the bottom source-drain plug 120 in the process of forming the gate plug, which is beneficial to reduce the damage to the bottom source-drain plug 120, as well as the gate plug and the bottom source-drain plug. The probability that the plug 120 will be shorted.
  • the source-drain capping layer 130 is selected from materials with higher etch selectivity than the gate capping layer, the dummy sidewall spacers 220 , the bottom dielectric layer 101 and the top dielectric layer 500 , so as to help ensure that the source-drain capping layer 130 can be used for the bottom.
  • the source-drain plug 120 plays a protective role.
  • the material of the source-drain capping layer 130 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride and boron carbonitride.
  • the material of the source-drain capping layer 130 is silicon carbide.
  • the top surface of the source-drain cap layer 130 and the bottom dielectric layer 101 are flush with each other.
  • the semiconductor structure further includes: a gate plug 170 located on top of the gate structure 400 and in contact with the gate structure 400 .
  • the gate plug 170 is used to make electrical connection between the gate structure 400 and external circuits or other interconnect structures.
  • the gate plug 170 is located above the gate structure 400 in the active region, that is to say, the gate plug 170 is an active gate contact hole plug, and the gate plug and the gate plug located in the isolation region Compared with the solution in which the gate structures are in contact, the present embodiment omits the portion of the gate structure 400 located in the isolation region, which is beneficial to saving the area of the chip and further reducing the size of the chip.
  • the semiconductor structure further includes: a gate capping layer 410 (as shown in FIG. 12 ) located between the top of the gate structure 400 and the top dielectric layer 500 .
  • the gate capping layer 410 is used to protect the gate structure 400 , so as to reduce damage to the gate structure 400 during the process of forming the top source-drain plug 122 , and The probability that the top source-drain plug 122 is shorted to the gate structure 400 .
  • the gate capping layer 410 is selected from materials with etching selectivity to the source-drain capping layer 130 , the bottom dielectric layer 101 and the top dielectric layer 500 , so as to help ensure that the gate capping layer 410 can protect the gate structure 400 effect.
  • the material of the gate capping layer 410 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride and boron carbonitride kind.
  • the material of the gate capping layer 410 is silicon nitride.
  • the top surfaces of the gate capping layer 410 and the bottom dielectric layer 101 are flush.
  • the semiconductor structure further includes: a sacrificial dielectric layer 101 (as shown in FIG. 10 ) located on the substrate 100 of the isolation region 100 a (as shown in FIG. 5 ), the sacrificial dielectric layer 101 and the top of the source-drain plug 180 are flush.
  • the sacrificial dielectric layer 140 is located on the bottom dielectric layer 101 .
  • the sacrificial dielectric layer 140 is used to provide a process basis for forming the top source-drain plugs 122 and the gate plugs 170 .
  • the material of the sacrificial dielectric layer 140 is an insulating material. Moreover, during the formation of the semiconductor structure, the bottom dielectric layer 101 is etched to provide a space for the formation of the top dielectric layer 500 . Therefore, the sacrificial dielectric layer 140 is made of materials that are easy to be etched.
  • the material of the sacrificial dielectric layer 140 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, boron nitride, aluminum oxide, and aluminum nitride. In this embodiment, the material of the sacrificial dielectric layer 140 is silicon oxide.
  • the top dielectric layer 500 is located in the device region 100 . Therefore, during the formation of the semiconductor structure, only the sacrificial dielectric layer 140 of the device region 100b is removed, thereby reducing the influence on the isolation region 100a (as shown in FIG. 5 ).
  • the top dielectric layer 500 is filled between the source-drain plug 180 and the gate plug 170 . Specifically, the top dielectric layer 500 is also filled in the gap 190 , and the top dielectric layer 500 located in the gap 190 serves as the sidewall 510 .
  • the material of the top dielectric layer 500 includes a low-k dielectric material or an ultra-low-k dielectric material. Therefore, the dielectric constant of the material of the sidewall spacer 510 is small, so that the gate structure 400 and the source-drain plug 180 (specifically, the bottom effective capacitance between the source-drain plugs 120), thereby improving the performance of the semiconductor structure.
  • the semiconductor structure adopts source-gate contact hole plugs (Contact Over Active Gate (COAG), the distance between the gate plug 170 and the source-drain plug 180 is correspondingly smaller, and the top dielectric layer 500 is filled between the source-drain plugs 180, therefore, by using a material with a lower dielectric constant
  • the top dielectric layer 500 is also beneficial to reduce the parasitic capacitance between the gate plug 170 and the source-drain plug 180 .
  • the RC delay of the interconnect structure in the integrated circuit can also be reduced.
  • the top dielectric layer seals the top of the gap to form an air gap.
  • the dielectric constant of air is relatively small, which can correspondingly reduce the effective capacitance between the gate structure and the source-drain plug.
  • the top dielectric layer 500 covers the top of the source-drain plug 180 .
  • the subsequent process further includes: forming a metal interconnection line electrically connected to the source-drain plug 180 on the top of the source-drain plug 180 , the metal interconnection line is formed in the inter-metal dielectric layer, and the source-drain plug is covered by the top dielectric layer 500 .
  • the top of the plug 180 makes the top dielectric layer 500 higher than the top of the source-drain plug 180 serve as an inter-metal dielectric layer, thereby simplifying the process steps of the back-end process.
  • the top of the top dielectric layer is flush with the top of the source-drain plug, or the top of the top dielectric layer is lower than the top of the source-drain plug, so that the inter-metal dielectric can be selected flexibly layer materials to meet the performance requirements of the semiconductor structure.
  • the semiconductor structure may be formed by the formation method described in the foregoing embodiments, or may be formed by other formation methods.
  • the specific description of the semiconductor structure in this embodiment reference may be made to the corresponding descriptions in the foregoing embodiments, which will not be repeated in this embodiment.

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Abstract

一种半导体结构及其形成方法，方法包括：提供基底，基底上形成有栅极结构，栅极结构侧壁形成有伪侧墙，伪侧墙侧壁形成有接触孔刻蚀停止层，栅极结构两侧基底内形成有源漏掺杂区；在源漏掺杂区和栅极结构的顶部上方形成牺牲介质层；形成源漏插塞，贯穿源漏掺杂区顶部上方的牺牲介质层并与源漏掺杂区相接触；刻蚀牺牲介质层直至露出伪侧墙的顶部；露出伪侧墙的顶部后，去除伪侧墙，在接触孔刻蚀停止层和栅极结构的侧壁之间形成间隙；形成填充于源漏插塞之间的顶部介质层，顶部介质层还填充于间隙中，或者，顶部介质层密封间隙的顶部，顶部介质层的材料介电常数小于伪侧墙的材料介电常数。本发明能够降低栅极结构和源漏插塞之间的有效电容。

Description

半导体结构及其形成方法 技术领域
本发明实施例涉及半导体制造领域，尤其涉及一种半导体结构及其形成方法。
 背景技术
随着集成电路制造技术的不断发展，人们对集成电路的集成度和性能的要求变得越来越高。为了提高集成度，降低成本，元器件的关键尺寸不断变小，集成电路内部的电路密度越来越大，这种发展使得晶圆表面无法提供足够的面积来制作所需要的互连线。
为了满足关键尺寸缩小过后的互连线所需，目前不同金属层或者金属层与基底的导通是通过互连结构实现的。互连结构包括互连线和形成于接触开口内的接触孔插塞。接触孔插塞与半导体器件相连接，互连线实现接触孔插塞之间的连接，从而构成电路。
晶体管结构内的接触孔插塞包括位于栅极结构表面的栅极接触孔插塞，用于实现栅极结构与外部电路的连接，还包括位于源漏掺杂区表面的源漏接触孔插塞，用于实现源漏掺杂区与外部电路的连接。
 技术问题
本发明实施例解决的问题是提供一种半导体结构及其形成方法，提高半导体结构的性能。
 技术解决方案
为解决上述问题，本发明实施例提供一种半导体结构的形成方法，包括：提供基底，所述基底上形成有栅极结构，所述栅极结构的侧壁形成有伪侧墙，所述伪侧墙的侧壁形成有接触孔刻蚀停止层，所述栅极结构两侧的基底内形成有源漏掺杂区；在所述源漏掺杂区和栅极结构的顶部上方形成牺牲介质层；形成源漏插塞，贯穿所述源漏掺杂区顶部上方的所述牺牲介质层，并与所述源漏掺杂区相接触；形成所述源漏插塞后，刻蚀所述牺牲介质层直至露出所述伪侧墙的顶部；露出所述伪侧墙的顶部后，去除所述伪侧墙，在所述接触孔刻蚀停止层和栅极结构的侧壁之间形成间隙；形成填充于所述源漏插塞之间的顶部介质层，所述顶部介质层还填充于所述间隙中，形成位于所述间隙中的侧墙，或者，所述顶部介质层密封所述间隙的顶部，形成空气隙，所述顶部介质层的材料介电常数小于所述伪侧墙的材料介电常数。
相应的，本发明实施例还提供一种半导体结构，包括：基底；栅极结构，位于所述基底上；源漏掺杂区，位于所述栅极结构两侧的基底内；接触孔刻蚀停止层，位于所述源漏掺杂区和栅极结构之间的基底上且与所述栅极结构的侧壁相对设置，所述接触孔刻蚀停止层和栅极结构的侧壁之间具有间隙；源漏插塞，位于所述源漏掺杂区的顶部，且与所述源漏掺杂区相接触；顶部介质层，填充于所述源漏插塞之间，所述顶部介质层还填充于所述间隙中，位于所述间隙中的所述顶部介质层作为侧墙，或者，所述顶部介质层密封所述间隙的顶部，围成空气隙，所述顶部介质层的材料为低k介电材料或超低k介电材料。
 有益效果
与现有技术相比，本发明实施例的技术方案具有以下优点：本发明实施例提供的形成方法中，形成位于栅极结构侧壁的伪侧墙，并在源漏掺杂区和栅极结构的顶部上方形成牺牲介质层、以及贯穿源漏掺杂区顶部上方的牺牲介质层且与源漏掺杂区相接触的源漏插塞，在形成源漏插塞后，刻蚀牺牲介质层直至露出伪侧墙的顶部，并去除伪侧墙，在接触孔刻蚀停止层和栅极结构的侧壁之间形成间隙，接着形成填充于源漏插塞之间的顶部介质层，顶部介质层还填充于间隙中，形成位于间隙中的侧墙，或者密封间隙的顶部，形成空气隙（air gap），所述顶部介质层的材料介电常数小于伪侧墙的材料介电常数；其中，通过去除伪侧墙，并形成材料介电常数更低的顶部介质层，以形成材料介电常数更低的侧墙或者空气隙，从而降低栅极结构和源漏插塞之间的有效电容，进而提高半导体结构的性能。而且，由于后续会去除伪侧墙，因此，这能够灵活选择所述伪侧墙的材料，使得所述伪侧墙的材料与后续工艺制程相兼容，相应有利于提高半导体结构的性能。
 附图说明
图1至图4是一种半导体结构的形成方法中各步骤对应的结构示意图。
图5至图16是本发明半导体结构的形成方法一实施例中各步骤对应的结构示意图。
 本发明的实施方式
目前半导体结构的性能有待提高。现结合一种半导体结构的形成方法分析其性能有待提高的原因。
图1至图4是一种半导体结构的形成方法中各步骤对应的结构示意图。
参考图1，提供基底10，基底10上形成有伪栅结构20，伪栅结构20的侧壁形成有侧墙22，伪栅结构20两侧的基底10内形成有源漏掺杂区11，伪栅结构20侧部的基底10上形成有覆盖源漏掺杂区11的底部介质层12。
参考图2，去除所述伪栅结构20，在底部介质层12中形成栅极开口25。
参考图3，在所述栅极开口25（如图2所示）中形成栅极结构30。
参考图4，在源漏掺杂区11和栅极结构30的顶部上方形成顶部介质层40；形成源漏插塞50，贯穿源漏掺杂区11顶部上方的顶部介质层40和底部介质层12，并与源漏掺杂区11相接触。
在半导体结构的形成过程中，形成源漏掺杂区11的步骤通常包括：以侧墙22为掩膜，刻蚀伪栅结构20两侧的基底10，在基底10内形成凹槽（图未示）；对凹槽进行预清洗（pre-clean）处理；在预清洗处理后，在凹槽中形成外延层，且在形成外延层的过程中，原位自掺杂离子，掺杂有离子的外延层作为源漏掺杂区11。其中，为了降低预清洗处理对侧墙22的损伤，侧墙22的硬度和致密度较高，使得侧墙22的耐刻蚀度较高。而且，去除伪栅结构20的工艺通常包括湿法刻蚀工艺，同理，为了降低侧墙22在去除伪栅结构20的过程中受损的概率，也对侧墙20的耐刻蚀度提出了要求。因此，在目前的半导体结构的形成过程中，侧墙20的材料介电常数通常较高（例如，侧墙20的材料为氮化硅），从而导致栅极结构30和源漏插塞50之间的有效电容较大。
为了解决所述技术问题，本发明实施例提供一种半导体结构的形成方法，包括：伪侧墙的侧壁形成有接触孔刻蚀停止层，所述栅极结构两侧的基底内形成有源漏掺杂区；在所述源漏掺杂区和栅极结构的顶部上方形成牺牲介质层；形成源漏插塞，贯穿所述源漏掺杂区顶部上方的所述牺牲介质层，并与所述源漏掺杂区相接触；形成所述源漏插塞后，刻蚀所述牺牲介质层直至露出所述伪侧墙的顶部；露出所述伪侧墙的顶部后，去除所述伪侧墙，在所述接触孔刻蚀停止层和栅极结构的侧壁之间形成间隙；形成填充于所述源漏插塞之间的顶部介质层，所述顶部介质层还填充于所述间隙中，形成位于所述间隙中的侧墙，或者，所述顶部介质层密封所述间隙的顶部，形成空气隙，所述顶部介质层的材料介电常数小于所述伪侧墙的材料介电常数。
本发明实施例提供的形成方法中，通过去除伪侧墙，并形成材料介电常数更低的顶部介质层，以形成材料介电常数更低的侧墙或者空气隙，从而降低栅极结构和源漏插塞之间的有效电容，进而提高半导体结构的性能。而且，由于后续会去除伪侧墙，因此，这能够灵活选择伪侧墙的材料，使得伪侧墙的材料与后续工艺制程相兼容，相应有利于提高半导体结构的性能。
为使本发明实施例的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图5至图16是本发明半导体结构的形成方法一实施例中各步骤对应的结构示意图。
结合参考图5至图10，提供基底100，基底100上形成有栅极结构400，所述栅极结构400的侧壁形成有伪侧墙220，所述伪侧墙220的侧壁形成有接触孔刻蚀停止层300，所述栅极结构400两侧的基底100内形成有源漏掺杂区110。
所述基底100用于为后续工艺制程提供工艺平台。本实施例中，以所述基底100用于形成平面型场效应晶体管为例，所述基底100为平面型衬底。在其他实施例中，所述基底用于形成鳍式场效应晶体管（FinFET），相应的，所述基底包括衬底以及凸出于衬底的鳍部。
本实施例中，所述基底100为硅衬底。在另一些实施例中，所述基底还可以为其他材料类型的衬底。例如，所述基底的材料可以为锗、锗化硅、碳化硅、砷化镓或镓化铟等其他材料，所述基底还能够为绝缘体上的硅衬底或者绝缘体上的锗衬底等其他类型的衬底。
如图5所示，图5为俯视图，本实施例中，所述基底100包括器件区100b和隔离区100a，所述器件区100b用于形成晶体管，所述器件区100b之外的剩余区域为隔离区100a。本实施例中，所述器件区100b为有源区（Active Area，AA），后续在所述有源区的栅极结构400顶部形成有源栅极接触孔插塞（Contact Over Active Gate，COAG），从而节省芯片的面积。
本实施例中，所述栅极结构400采用后形成高k栅介质层后形成栅电极层（high k last metal gate last）的工艺形成，因此，结合参考图5和图6，在形成栅极结构400之前，所述形成方法还包括：在所述基底100上形成伪栅结构（dummy gate）200。
其中，图5为俯视图，且为了便于图示，仅示出了基底100、伪栅结构200和源漏掺杂区110，图6是图5沿A1A2割线的剖面图。具体地，所述伪栅结构200形成于器件区100b的基底100上。所述伪栅结构200用于为后续栅极结构400的形成占据空间位置。
本实施例中，伪栅结构200为多晶硅栅结构，即伪栅结构200包括伪栅层，伪栅层的材料为多晶硅。在其他实施例中，伪栅层的材料还可以包括氧化硅、氮化硅、氮氧化硅、碳化硅、碳氮化硅、碳氮氧化硅或非晶碳等其他材料。作为一种示例，伪栅结构200为单层结构，伪栅结构200仅包括伪栅层。在其他实施例中，所述伪栅结构还可以为叠层结构，相应包括伪栅氧化层以及位于伪栅氧化层上的伪栅层，其中，伪栅氧化层的材料可以为氧化硅。
继续参考图6，在所述伪栅结构200的侧壁形成伪侧墙220。伪侧墙220用于保护伪栅结构200的侧壁，还用于定义源漏掺杂区110的形成位置。伪侧墙220和源漏掺杂区110位于所述器件区100b。
需要说明的是，后续步骤还包括：去除伪侧墙220，在伪侧墙220的位置处形成间隙，因此，伪侧墙220用于为形成间隙占据空间。后续形成间隙后，会形成材料介电常数更小的顶部介质层，为了使顶部介质层的材料能够具有较低的介电常数，顶部介质层的材料通常为结构较为疏松、致密度较低的材料，因此，通过先形成用于为间隙占据空间的伪侧墙220，这能够灵活选择所述伪侧墙220的材料，使得所述伪侧墙220的材料与后续工艺制程相兼容，相应有利于提高半导体结构的性能。例如，所述伪侧墙220的耐刻蚀度较高，在后续去除伪栅结构200的过程中，所述伪侧墙220受损的概率较低，或者，形成源漏掺杂区110的过程中，所述伪侧墙220受损的概率较低。此外，由于后续还会去除所述伪侧墙220，因此，所述伪侧墙220的材料选取为：去除所述伪侧墙220的过程中，所述伪侧墙220和其他膜层（例如，栅极结构或接触孔刻蚀停止层300等）之间的刻蚀选择比较高，从而使得去除所述伪侧墙220的工艺对其他膜层的损伤较小。
所述伪侧墙220可以为单层结构或叠层结构，所述伪侧墙220的材料可以包括氧化硅、氮化硅、碳化硅、氮氧化硅、氮化硼、氧化铝和氮化铝中的一种或多种。本实施例中，所述伪侧墙220为单层结构，所述伪侧墙220的材料为氧化硅。氧化硅的硬度和致密度较高，因此，后续制程对所述伪侧墙220的损伤较小，使得所述伪侧墙220能够与后续制程相兼容，且氧化硅为易于被去除的材料，便于后续去除所述伪侧墙220。
需要说明的是，后续去除所述伪侧墙220后，在所述伪侧墙220的位置处形成间隙，并在所述间隙中形成侧墙，当所述伪侧墙220的宽度过小时，侧墙的材料难以填充于所述间隙中，从而导致降低栅极结构与源漏插塞之间的有效电容的效果不佳；当所述伪侧墙220的宽度过大时，则相应导致源漏掺杂区110与后续栅极结构之间的距离过大，从而导致沟道长度过大，进而导致器件尺寸过大，难以满足器件小型化的发展需求。为此，本实施例中，在平行于所述基底100表面且垂直于伪栅结构200侧壁的方向上，所述伪侧墙220的宽度为2纳米至12纳米。例如，所述伪侧墙220的宽度为5纳米、7纳米或10纳米。
具体地，形成伪侧墙220的步骤包括：形成保形覆盖伪栅结构200和基底100的伪侧墙材料层（图未示）；去除伪栅结构200两侧的伪侧墙材料层，露出伪栅结构200两侧的部分基底100，剩余的伪侧墙材料层作为伪侧墙220。通过去除伪栅结构200两侧的伪侧墙材料层，露出伪栅结构200两侧的部分基底100，从而为后续形成源漏掺杂区110做准备。相应的，本实施例中，所述伪侧墙220还覆盖伪栅结构200的顶部。
还需要说明的是，在形成伪侧墙材料层之前，所述形成方法还包括：形成保形覆盖伪栅结构200和基底100的偏移侧墙（offset spacer）210。偏移侧墙210用于增大所形成晶体管的沟道长度，从而改善短沟道效应以及由短沟道效应引起的热载流子效应。相应的，为了形成源漏掺杂区，在形成伪侧墙220后，还去除伪侧墙220露出的偏移侧墙210，因此，剩余的偏移侧墙210位于伪侧墙220和伪栅结构200之间、以及伪侧墙220和基底100之间。
偏移侧墙210的材料为氧化硅、氮化硅、氮氧化硅、氮碳氧化硅、氮硼氧化硅或氮碳硼氧硅。本实施例中，所述偏移侧墙210的材料为氮化硅。
继续参考图6，形成伪侧墙220后，在伪栅结构200两侧的基底100中形成源漏掺杂区110。具体地，所述源漏掺杂区110位于所述器件区100b（如图5所示）中。所述源漏掺杂区110作为所形成晶体管的源区或漏区。
本实施例中，采用外延工艺，形成所述源漏掺杂区110。具体地，形成源漏掺杂区110的步骤包括：以所述伪侧墙220为掩膜，刻蚀伪栅结构200两侧的基底100，形成凹槽；采用外延工艺，在凹槽中形成外延层，并在形成所述外延层的过程中，原位自掺杂离子，掺杂有离子的外延层作为源漏掺杂区110。当形成NMOS晶体管时，外延层的材料为Si或SiC，外延层为NMOS晶体管的沟道区提供拉应力作用，从而有利于提高NMOS晶体管的载流子迁移率，其中，外延层中的掺杂离子为N型离子，N型离子包括P离子、As离子或Sb离子。当形成PMOS晶体管时，外延层的材料为Si或SiGe，外延层为PMOS晶体管的沟道区提供压应力作用，从而有利于提高PMOS晶体管的载流子迁移率，其中，外延层中的掺杂离子为P型离子，P型离子包括B离子、Ga离子或In离子。
参考图7，在形成源漏掺杂区110之后，形成保形覆盖伪侧墙220、伪栅结构200和基底100的接触孔刻蚀停止层（contact etch stop layer，CESL）300。
后续形成与源漏掺杂区110相接触的源漏插塞的过程中，包括刻蚀底部介质层的步骤，在刻蚀底部介质层的过程中，利用接触孔刻蚀停止层300定义刻蚀停止的位置，从而避免源漏掺杂区110被过刻蚀。相应的，接触孔刻蚀停止层300和后续形成的底部介质层之间具有较高的刻蚀选择比。所述接触孔刻蚀停止层300的材料包括低k介电材料（低k介质材料指相对介电常数大于或等于2.6且小于等于3.9的介质材料）、超低k介电材料（超低k介质材料指相对介电常数小于2.6的介质材料）或氮化硅。
需要说明的是，后续在源漏掺杂区110上形成源漏插塞后，接触孔刻蚀停止层300也位于源漏插塞和栅极结构之间，因此，接触孔刻蚀停止层300也会影响源漏插塞和栅极结构之间的有效电容，所述接触孔刻蚀停止层300的材料介电常数越小，源漏插塞和栅极结构之间的有效电容越小。因此，本实施例中，为了使得所述接触孔刻蚀停止层300的材料介电常数较小，所述接触孔刻蚀停止层300的材料为低k介电材料或超低k介电材料。
本实施例中，伪侧墙220和接触孔刻蚀停止层300之间还形成有防扩散层310。防扩散层310用于防止伪侧墙220中的易扩散离子扩散至接触孔刻蚀停止层300中，从而防止因离子扩散而引起接触孔刻蚀停止层300的材料介电常数增大的问题。
具体地，所述接触孔刻蚀停止层300的材料为低k介电材料或超低k介电材料，所述伪侧墙220的材料为含氧材料（例如：氧化硅），当氧离子扩散至接触孔刻蚀停止层300中时，会导致所述接触孔刻蚀停止层300的材料介电常数变大，因此，通过在所述伪侧墙220和接触孔刻蚀停止层300之间形成防扩散层310，能够降低接触孔刻蚀停止层300材料介电常数变大的概率。因此，防扩散层310的致密度较高。而且，后续保留防扩散层310，因此，防扩散层310的材料为绝缘材料。具体地，所述防扩散层310的材料包括氮化硅、碳化硅、碳氮化硅、碳氮氧化硅、氮氧化硅、氮化硼、碳氮化硼、氧化铝和氮化铝中的一种多种。作为一种示例，所述防扩散层310的材料为氮化硅。
需要说明的是，所述防扩散层310也位于源漏插塞和栅极结构之间，所述防扩散层310也会影响源漏插塞和栅极结构之间的有效电容。所述防扩散层310的材料的介电常数较大，因此，当所述防扩散层310的厚度过大时，容易导致源漏插塞和栅极结构之间的有效电容过大，而且，还会导致源漏掺杂区110与栅极结构之间的距离过大，从而导致沟道长度过大，进而导致器件尺寸过大，难以满足器件小型化的发展需求。因此，在保证所述防扩散层310对离子的防扩散作用的同时，综合考虑上述影响，所述防扩散层310的厚度小于或等于30Å。
本实施例中，防扩散层310的厚度小于或等于15Å，从而在保证防扩散层310的防止离子扩散的作用的同时，使得源漏插塞和栅极结构之间的有效电容较小。其中，当防扩散层310的厚度过小时，容易导致防扩散层310的防止离子扩散的作用变差，因此，本实施例中，防扩散层310的厚度为5Å至15Å。例如，防扩散层310的厚度为10Å。
本实施例中，在形成所述源漏掺杂区110之后，形成所述接触孔刻蚀停止层300之前，形成保形覆盖所述伪侧墙220、伪栅结构200和基底100的防扩散层310，所述接触孔刻蚀停止层300相应形成在防扩散层310上。
形成防扩散层310的工艺包括原子层沉积工艺、化学气相沉积工艺或等离子体增强化学气相沉积工艺。本实施例中，采用原子层沉积工艺形成防扩散层310。防扩散层310的厚度较小，通过采用原子层沉积工艺，易于形成厚度较小的防扩散层310，且使得防扩散层310的厚度均匀性好，此外，使得防扩散层310具有良好的台阶覆盖能力。
参考图8，形成所述接触孔刻蚀停止层300后，在所述伪栅结构200侧部的基底100上形成底部介质层101。
所述底部介质层101用于隔离相邻器件。本实施例中，所述底部介质层101为层间介质层（Inter Layer Dielectric，ILD）。底部介质层101的材料为绝缘材料，其材料包括氧化硅、氮化硅、氮氧化硅、碳氧化硅、碳氮化硅和碳氮氧化硅中的一种或多种。作为一种示例，底部介质层101的材料为氧化硅。
具体地，通过沉积以及平坦化工艺（例如，化学机械研磨工艺）形成所述底部介质层101，使得所述底部介质层101露出伪栅结构200的顶部。本实施例中，所述底部介质层101的顶部和伪栅结构200的顶部相齐平。其中，在形成所述底部介质层101的过程中，去除高于所述伪侧墙220和伪栅结构200顶部的接触孔刻蚀停止层300、防扩散层310、伪侧墙220和偏移侧墙210。
结合参考图9和图10，去除伪栅结构200，在底部介质层101中形成栅极开口102（如图9所示）；在栅极开口102中形成栅极结构400（如图10所示）。
相应的，所述栅极结构400位于所述器件区100b（如图5所示）中，且所述栅极结构400露出的基底100上形成有底部介质层101，所述底部介质层101覆盖源漏掺杂区110。
在晶体管工作时，栅极结构400用于控制导电沟道的开启或关断。具体地，栅极结构400为金属栅极结构，栅极结构400包括保形覆盖栅极开口102的底部和侧壁的高k栅介质层（图未示）、位于高k栅介质层上的功函数层（图未示）、以及位于功函数层上的栅电极层（图未示）。
高k栅介质层的材料为高k介质材料，其中，高k介质材料是指相对介电常数大于氧化硅相对介电常数的介电材料。具体地，所述高k栅介质层的材料可以选自HfO 2、ZrO 2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO或Al 2O 3等。作为一种示例，所述高k栅介质层的材料为HfO 2。
功函数层用于调节所形成晶体管的阈值电压。当形成PMOS晶体管时，功函数层为P型功函数层，P型功函数层的材料包括TiN、TaN、TaSiN、TaAlN和TiAlN中的一种或几种；当形成NMOS晶体管时，功函数层为N型功函数层，N型功函数层的材料包括TiAl、Mo、MoN、AlN和TiAlC中的一种或几种。
栅电极层用于将栅极结构200的电性引出。本实施例中，栅电极层的材料为Al、Cu、Ag、Au、Pt、Ni、Ti或W。
需要说明的是，伪侧墙220的致密度和硬度较高，因此，去除伪栅结构200的工艺对伪侧墙220的损伤较小。
参考图11，形成所述栅极结构400后，所述形成方法还包括：在所述器件区100b（如图5所示）中，形成贯穿所述源漏掺杂区110上方的底部介质层101且与源漏掺杂区110相接触的底部源漏插塞120、以及位于底部源漏插塞120顶面的源漏盖帽层130。
本实施例中，后续在底部源漏插塞120上形成与底部源漏插塞120相接触的顶部源漏插塞，顶部源漏插塞和底部源漏插塞120构成源漏插塞。
本实施例中，底部源漏插塞120的材料为铜。铜的电阻率较低，有利于改善后段RC的信号延迟，提高芯片的处理速度，同时还有利于降低底部源漏插塞120的电阻，相应降低了功耗。在其他实施例中，底部源漏插塞的材料还可以为钨或钴等导电材料。
后续在底部介质层101（如图10所示）上形成牺牲介质层后，在有源（Active Area，AA）区的栅极结构400顶部的牺牲介质层中形成与栅极结构400相接触的栅极插塞，源漏盖帽层130位于底部源漏插塞120的顶面，用于在形成栅极插塞的过程中，对底部源漏插塞120起到保护的作用，有利于降低底部源漏插塞120受损、以及栅极插塞与底部源漏插塞120发生短接的概率。
源漏盖帽层130选用与栅极盖帽层、伪侧墙220、底部介质层101以及后续形成的牺牲介质层具有较高刻蚀选择性的材料，从而有利于保证源漏盖帽层130能够对底部源漏插塞120起到保护的作用。本实施例中，源漏盖帽层130的材料包括氮化硅、碳化硅、碳氮化硅、碳氮氧化硅、氮氧化硅、氮化硼和碳氮化硼中的一种或多种。具体地，源漏盖帽层130和栅极盖帽层的材料不同，源漏盖帽层130和伪侧墙220的材料不同。作为一种示例，源漏盖帽层130的材料为碳化硅。
本实施例中，源漏盖帽层130和底部介质层101的顶面相齐平。其中，图11是在所述器件区100b位置处的剖视图，因此，未示意出位于所述隔离区100a（如图5所示）的底部介质层101。
本实施例中，所述形成方法还包括：形成位于栅极结构400顶面的栅极盖帽层410。后续形成顶部源漏插塞时，栅极盖帽层410用于对栅极结构400起到保护的作用，从而在形成顶部源漏插塞的过程中，降低栅极结构400受损、以及顶部源漏插塞与栅极结构400发生短接的概率。具体地，回刻蚀所述栅极结构400，去除部分厚度的所述栅极结构400；去除部分厚度的所述栅极结构400后，在剩余的所述栅极结构400的顶部上形成栅极盖帽层410。本实施例中，栅极盖帽层410和底部介质层101的顶面相齐平。
栅极盖帽层410选用与源漏盖帽层130、底部介质层101以及后续形成的牺牲介质层具有刻蚀选择性的材料，从而有利于保证所述栅极盖帽层410能够对栅极结构400起到保护的作用。本实施例中，所述栅极盖帽层410的材料包括氮化硅、碳化硅、碳氮化硅、碳氮氧化硅、氮氧化硅、氮化硼和碳氮化硼中的一种或多种。作为一种示例，所述栅极盖帽层410的材料为氮化硅。
参考图12，在所述源漏掺杂区110和栅极结构400的顶部上方形成牺牲介质层140。
具体地，所述牺牲介质层140形成于底部介质层101上。所述牺牲介质层140用于为后续形成顶部源漏插塞和栅极插塞提供工艺基础。
牺牲介质层140的材料为绝缘材料。而且，后续会对牺牲介质层140进行刻蚀，因此，牺牲介质层140选用易于被刻蚀的材料。牺牲介质层140的材料包括氧化硅、氮化硅、碳化硅、氮氧化硅、氮化硼、氧化铝和氮化铝中的一种或多种。本实施例中，所述牺牲介质层140的材料和所述伪侧墙220的材料相同，便于后续在同一刻蚀步骤中，刻蚀所述牺牲介质层140和伪侧墙220。相应的，本实施例中，所述牺牲介质层140的材料为氧化硅。
结合参考图13和图14，形成源漏插塞180（如图14所示），贯穿所述源漏掺杂区110顶部上方的牺牲介质层140，并与所述源漏掺杂区110相接触。
源漏插塞180用于实现源漏掺杂区110与外部电路或其他互连结构之间的电连接。本实施例中，形成源漏插塞180的步骤包括：形成贯穿源漏掺杂区110顶部上方的牺牲介质层140和源漏盖帽层130的顶部源漏插塞122，顶部源漏插塞125与底部源漏插塞120相接触，且顶部源漏插塞122和底部源漏插塞120构成源漏插塞180。
具体地，如图13所示，依次刻蚀源漏掺杂区110顶部上方的牺牲介质层140和源漏盖帽层130，形成露出底部源漏插塞120的源漏接触孔160；如图14所示，在源漏接触孔160中形成顶部源漏插塞122。对顶部源漏插塞122的材料的具体描述，可结合参考前述对底部源漏插塞120的描述，在此不再赘述。
本实施例中，所述形成方法还包括：形成栅极插塞170（如图14所示），贯穿栅极结构400顶部上方的牺牲介质层140和栅极盖帽层410（如图12所示），并与栅极结构400相接触。
栅极插塞170用于实现栅极结构400与外部电路或其他互连结构之间的电连接。本实施例中，栅极插塞170形成于有源区的栅极结构400上方，栅极插塞170为有源栅极接触孔插塞（Contact Over Active Gate，COAG），与栅极插塞与位于隔离区的栅极结构相接触的方案相比，本实施例省去了栅极结构400位于隔离区的部分，有利于节省芯片的面积，实现芯片尺寸的进一步缩小。对栅极插塞170的材料的具体描述，可结合参考前述对底部源漏插塞120的描述，在此不再赘述。
具体地，如图13所示，依次刻蚀栅极结构400顶部上方的牺牲介质层140和栅极盖帽层410，形成露出栅极结构400顶部的栅极接触孔150；如图14所示，在栅极接触孔150中形成栅极插塞170。
本实施例中，在形成源漏接触孔160和栅极接触孔150后，在同一步骤中，形成顶部源漏插塞125和栅极插塞170。需要说明的是，本实施例中，在刻蚀牺牲介质层140之前，形成栅极插塞170，从而减小对目前工艺制程的改动，提高所述形成方法的工艺兼容性。
参考图15，形成源漏插塞180后，刻蚀牺牲介质层140直至露出伪侧墙220（如图13所示）的顶部；露出伪侧墙220的顶部后，去除伪侧墙220，在接触孔刻蚀停止层300和栅极结构400的侧壁之间形成间隙190。
所述间隙190用于为后续形成侧墙提供空间位置。
本实施例中，刻蚀牺牲介质层140直至露出伪侧墙220的顶部的步骤包括：去除位于所述器件区100b（如图5所示）的牺牲介质层140。通过仅去除所述器件区100b的牺牲介质层140，从而减小对隔离区100a（如图5所示）的影响。其中，后续形成填充于源漏插塞180之间的顶部介质层，本实施例仅刻蚀牺牲介质层140，未刻蚀底部介质层101，相应的，顶部介质层填充于顶部源漏插塞125之间，顶部介质层所填充的空间的深宽比较小，这降低了形成顶部介质层的工艺难度，有利于提高顶部介质层的形成质量。
本实施例中，采用各向同性的刻蚀工艺，去除所述器件区100b的牺牲介质层140和伪侧墙220。通过采用各向同性的刻蚀工艺，以便于能够将所述器件区100b的牺牲介质层140和伪侧墙220去除干净，而且，刻蚀速率较快。
本实施例中，所述各向同性的刻蚀工艺为远程等离子体（remote plasma）刻蚀工艺。远程等离子体蚀刻工艺具有各向同性的刻蚀特性，而且，远程等离子体刻蚀工艺也具有较好的刻蚀选择性，从而在刻蚀的过程中，减小对其他膜层的损耗。其中，远程等离子体蚀刻工艺的原理是在刻蚀腔室外部形成等离子体（例如，通过远程等离子体发生器产生等离子体），然后引入刻蚀腔室中并利用等离子体与被刻蚀层的化学反应进行蚀刻，因而可以实现各向同性的刻蚀效果，且因为没有离子轰击，因而不会损伤其他膜层。在其他实施例中，所述各向同性的刻蚀工艺也可以为湿法刻蚀工艺。
需要说明的是，牺牲介质层140和伪侧墙220的材料相同，因此，能够在同一刻蚀步骤中，去除所述器件区100b的牺牲介质层140和伪侧墙220，简化了工艺步骤。
参考图16，形成填充于源漏插塞180之间的顶部介质层500，顶部介质层500还填充于间隙190中，形成位于间隙190中的侧墙510，顶部介质层500的材料介电常数小于伪侧墙220（如图14所示）的材料介电常数。具体地，顶部介质层500填充于源漏插塞180和栅极插塞170之间。
通过去除伪侧墙220，并形成材料介电常数更低的顶部介质层500，以形成材料介电常数更低的侧墙510，从而降低栅极结构400和源漏插塞180（具体为底部源漏插塞120）之间的有效电容，进而提高半导体结构的性能。
本实施例中，所述顶部介质层500的材料包括低k介电材料或超低k介电材料，因此，侧墙510的材料介电常数较小，从而能够降低栅极结构400和源漏插塞180之间的有效电容。而且，本实施例中，为实现晶体管面积的进一步缩小，引入了有源栅极接触孔插塞（Contact Over Active Gate，COAG）工艺，栅极插塞170和源漏插塞180之间的距离相应较小，顶部介质层500填充于源漏插塞180之间，因此，通过形成材料介电常数较低的顶部介质层500，还有利于减小栅极插塞170和源漏插塞180之间的寄生电容。此外，通过形成材料介电常数较低的顶部介质层500，还有利于降低集成电路中互连结构的RC延迟。
在其他实施例中，当所述间隙的深宽比（aspect ratio，AR）较大时，所述顶部介质层密封所述间隙的顶部，形成空气隙。空气的介电常数较小，相应也能够降低栅极结构和源漏插塞之间的有效电容。
本实施例中，采用旋涂工艺形成顶部介质层500。旋涂工艺的工艺温度较低，从而避免高温所引起的沟道退化问题，有利于提高半导体结构的性能。在其他实施例中，还可以采用化学气相沉积、流体化学气相沉积工艺或原子层沉积工艺，形成顶部介质层。
本实施例中，顶部介质层500覆盖源漏插塞180的顶部。后续制程还包括：在源漏插塞180的顶部形成电连接源漏插塞180的金属互连线，金属互连线形成于金属层间介质（inter metal dielectric，IMD）层中，通过使顶部介质层500覆盖源漏插塞180的顶部，使得高于源漏插塞180顶部的顶部介质层500作为金属层间介质层，从而简化后段（BEOL）制程的工艺步骤。在其他实施例中，所述顶部介质层的顶部与源漏插塞的顶部相齐平，或者，所述顶部介质层的顶部低于源漏插塞的顶部，从而能够灵活选取金属层间介质层的材料，以满足半导体结构的性能需求。
需要说明的是，本实施例中，以COAG工艺为例进行说明。在其他实施例中，当栅极插塞位于隔离区的栅极结构顶部时，通过所述方法，仍能够起到降低源漏插塞和栅极结构之间的有效电容的效果。
相应的，本发明还提供一种半导体结构。继续参考图16，示出了本发明半导体结构一实施例的结构示意图。
所述半导体结构包括：基底100；栅极结构400，位于基底100上；源漏掺杂区110，位于栅极结构400两侧的基底100内；接触孔刻蚀停止层300，位于源漏掺杂区110和栅极结构400之间的基底100上且与栅极结构400的侧壁相对设置，接触孔刻蚀停止层300和栅极结构400的侧壁之间具有间隙190（如图14所示）；源漏插塞180，位于源漏掺杂区110的顶部，且与源漏掺杂区110相接触；顶部介质层500，填充于源漏插塞180之间，顶部介质层500还填充于间隙190中，位于间隙190中的顶部介质层500作为侧墙510，或者，顶部介质层500密封间隙190的顶部，围成空气隙，所述顶部介质层500的材料为低k介电材料或超低k介电材料。
本实施例中，基底100为平面型衬底。在其他实施例中，所述基底包括衬底以及凸出于衬底的鳍部。本实施例中，基底100为硅衬底。在另一些实施例中，基底还可以为其他材料类型的衬底。例如，基底的材料可以为锗、锗化硅、碳化硅、砷化镓或镓化铟等其他材料，基底还能够为绝缘体上的硅衬底或者绝缘体上的锗衬底等其他类型的衬底。
如图5所示，图5为俯视图，本实施例中，所述基底100包括器件区100b和隔离区100a，所述器件区100b用于形成晶体管，所述器件区100b之外的剩余区域为隔离区100a。本实施例中，所述器件区100b为有源区。
其中，图16是基于图5在A1A2割线位置处的剖视图。
所述栅极结构400位于所述器件区100b的基底100上，栅极结构400用于控制导电沟道的开启或关断。具体地，栅极结构400为金属栅极结构，包括高k栅介质层（图未示）、位于高k栅介质层上的功函数层（图未示）、以及位于功函数层上的栅电极层（图未示）。对栅极结构400的具体描述，可结合参考前述实施例的相应描述，在此不再赘述。
需要说明的是，所述半导体结构还包括：偏移侧墙210，位于间隙190露出的栅极结构400的侧壁。偏移侧墙210用于增大所形成晶体管的沟道长度，从而改善短沟道效应以及由短沟道效应引起的热载流子效应。偏移侧墙210的材料为氧化硅、氮化硅、氮氧化硅、氮碳氧化硅、氮硼氧化硅或氮碳硼氧硅。本实施例中，所述偏移侧墙210的材料为氮化硅。
本实施例中，在所述半导体结构的形成方法中，通过去除伪侧墙，以形成所述间隙190，且偏移侧墙210在形成伪侧墙之前形成，因此，偏移侧墙210还延伸覆盖间隙190底部。
源漏掺杂区110位于器件区100b中，源漏掺杂区110作为所形成晶体管的源区或漏区。源漏掺杂区110通过外延工艺形成，源漏掺杂区110包括掺杂有离子的外延层。当所述半导体结构为NMOS晶体管时，外延层的材料为Si或SiC，外延层中的掺杂离子为N型离子，N型离子包括P离子、As离子或Sb离子。当所述半导体结构为PMOS晶体管时，外延层的材料为Si或SiGe，外延层中的掺杂离子为P型离子，P型离子包括B离子、Ga离子或In离子。
本实施例中，所述半导体结构还包括：底部介质层101（如图9所示），位于栅极结构400侧部的基底100上，底部介质层101覆盖源漏掺杂区110。
底部介质层101用于隔离相邻器件。本实施例中，底部介质层110为层间介质层。底部介质层101的材料为绝缘材料，其材料包括氧化硅、氮化硅、氮氧化硅、碳氧化硅、碳氮化硅和碳氮氧化硅中的一种或多种。作为一种示例，底部介质层101的材料为氧化硅。
在半导体结构的形成过程中，接触孔刻蚀停止层300覆盖伪侧墙的侧壁，而间隙190通过去除伪侧墙的方式形成，因此，接触孔刻蚀停止层300位于源漏掺杂区110和栅极结构400之间的基底100上且与栅极结构400的侧壁相对设置，接触孔刻蚀停止层300和栅极结构400的侧壁之间具有间隙190。
在形成源漏插塞180的过程中，包括刻蚀底部介质层101的步骤，在刻蚀底部介质层101的过程中，利用接触孔刻蚀停止层300定义刻蚀停止的位置，从而避免源漏掺杂区110被过刻蚀。相应的，接触孔刻蚀停止层300和底部介质层101之间具有较高的刻蚀选择比。接触孔刻蚀停止层300的材料包括低k介电材料、超低k介电材料或氮化硅。
需要说明的是，接触孔刻蚀停止层300也位于源漏插塞180和栅极结构400之间，因此，接触孔刻蚀停止层300也会影响源漏插塞180和栅极结构400之间的有效电容，接触孔刻蚀停止层300的材料介电常数越小，源漏插塞180和栅极结构400之间的有效电容越小。因此，本实施例中，为了使得接触孔刻蚀停止层300的材料介电常数越小，接触孔刻蚀停止层300的材料为低k介电材料或超低k介电材料。
因此，本实施例中，所述半导体结构还包括：防扩散层310，位于间隙190露出的接触孔刻蚀停止层300的侧壁。防扩散层310用于防止伪侧墙中的易扩散离子扩散至接触孔刻蚀停止层300中，从而防止因离子扩散而引起接触孔刻蚀停止层300的材料介电常数增大的问题。具体地，接触孔刻蚀停止层300的材料为低k介电材料或超低k介电材料，伪侧墙的材料通常为含氧材料（例如：氧化硅），当氧离子扩散至接触孔刻蚀停止层300中时，会导致接触孔刻蚀停止层300的材料介电常数变大，因此，通过防扩散层310，能够降低接触孔刻蚀停止层300材料介电常数变大的概率。
因此，防扩散层310的致密度较高，且防扩散层310的材料为绝缘材料。具体地，防扩散层310的材料包括氮化硅、碳化硅、碳氮化硅、碳氮氧化硅、氮氧化硅、氮化硼、碳氮化硼、氧化铝和氮化铝中的一种多种。作为一种示例，所述防扩散层310的材料为氮化硅。
需要说明的是，防扩散层310也位于源漏插塞180和栅极结构400之间，防扩散层310也会影响源漏插塞180和栅极结构400之间的有效电容，所述防扩散层310的材料的介电常数较大，因此，当所述防扩散层310的厚度过大时，容易导致源漏插塞180和栅极结构400之间的有效电容过大，而且，还会导致源漏掺杂区110与栅极结构400之间的距离过大，从而导致沟道长度过大，进而导致器件尺寸过大，难以满足器件小型化的发展需求。因此，在保证防扩散层310对离子的防扩散作用的同时，综合考虑上述影响，防扩散层310的厚度小于或等于30Å。
本实施例中，防扩散层310的厚度小于或等于15Å，从而在保证防扩散层310的防止离子扩散的作用的同时，使得源漏插塞180和栅极结构400之间的有效电容较小。其中，当防扩散层310的厚度过小时，容易导致防扩散层310的防止离子扩散的作用变差，因此，防扩散层310的厚度为5Å至15Å。
本实施例中，平行于基底100表面且垂直于栅极结构400侧壁的方向上，所述间隙190的宽度不宜过小，也不宜过大。当所述间隙190的宽度过小时，顶部介质层500的材料难以填充于间隙190中，从而导致降低栅极结构400与源漏插塞180之间的寄生电容的效果不佳；当所述间隙190的宽度过大时，则相应导致源漏掺杂区110与栅极结构400之间的距离过大，从而导致沟道长度过大，进而导致器件尺寸过大，难以满足器件小型化的发展需求。为此，本实施例中，所述间隙190的宽度为2纳米至12纳米。
本实施例中，在半导体结构的形成过程中，在形成源漏掺杂区110之后，形成接触孔刻蚀停止层300之前，形成防扩散层310，因此，防扩散层310还位于接触孔刻蚀停止层300的底部和基底100之间。
源漏插塞180用于实现源漏掺杂区110与外部电路或其他互连结构之间的电连接。本实施例中，源漏插塞180的材料为铜。在其他实施例中，源漏插塞的材料还可以为钨或钴等导电材料。
本实施例中，所述半导体结构中的栅极插塞为源栅极接触孔插塞（Contact Over Active Gate，COAG），因此，所述源漏插塞180包括：底部源漏插塞120，贯穿源漏掺杂区110上方的底部介质层101且与源漏掺杂区110相接触；顶部源漏插塞122，位于底部源漏插塞120上且与底部源漏插塞120相接触。
相应的，所述半导体结构还包括：源漏盖帽层130，位于底部源漏插塞120的顶部与顶部介质层500之间。所述半导体结构通常还包括：栅极插塞，位于有源区的栅极结构400顶部的顶部介质层500中且与栅极结构400相接触，源漏盖帽层130位于底部源漏插塞120的顶面，用于在形成栅极插塞的过程中，对底部源漏插塞120起到保护的作用，有利于降低底部源漏插塞120受损、以及栅极插塞与底部源漏插塞120发生短接的概率。
所述源漏盖帽层130选用与栅极盖帽层、伪侧墙220、底部介质层101以及顶部介质层500具有较高刻蚀选择性的材料，从而有利于保证源漏盖帽层130能够对底部源漏插塞120起到保护的作用。本实施例中，源漏盖帽层130的材料包括氮化硅、碳化硅、碳氮化硅、碳氮氧化硅、氮氧化硅、氮化硼和碳氮化硼中的一种或多种。作为一种示例，源漏盖帽层130的材料为碳化硅。
本实施例中，源漏盖帽层130和底部介质层101的顶面相齐平。
本实施例中，所述半导体结构还包括：栅极插塞170，位于栅极结构400的顶部，并与栅极结构400相接触。栅极插塞170用于实现栅极结构400与外部电路或其他互连结构之间的电连接。本实施例中，栅极插塞170位于有源区的栅极结构400上方，也就是说，栅极插塞170为有源栅极接触孔插塞，与栅极插塞与位于隔离区的栅极结构相接触的方案相比，本实施例省去了栅极结构400位于隔离区的部分，有利于节省芯片的面积，实现芯片尺寸的进一步缩小。
相应的，所述半导体结构还包括：栅极盖帽层410（如图12所示），位于栅极结构400的顶部与顶部介质层500之间。在形成顶部源漏插塞122时，栅极盖帽层410用于对栅极结构400起到保护的作用，从而在形成顶部源漏插塞122的过程中，降低栅极结构400受损、以及顶部源漏插塞122与栅极结构400发生短接的概率。
栅极盖帽层410选用与源漏盖帽层130、底部介质层101以及顶部介质层500具有刻蚀选择性的材料，从而有利于保证所述栅极盖帽层410能够对栅极结构400起到保护的作用。本实施例中，所述栅极盖帽层410的材料包括氮化硅、碳化硅、碳氮化硅、碳氮氧化硅、氮氧化硅、氮化硼和碳氮化硼中的一种或多种。作为一种示例，所述栅极盖帽层410的材料为氮化硅。
本实施例中，栅极盖帽层410和底部介质层101的顶面相齐平。
本实施例中，所述半导体结构还包括：牺牲介质层101（如图10所示），位于所述隔离区100a（如图5所示）的所述基底100上，所述牺牲介质层101的顶部和所述源漏插塞180的顶部相齐平。
其中，图16是在所述器件区100b位置处的剖视图，因此，未示意出位于所述隔离区100a的底部介质层101。具体地，所述牺牲介质层140位于底部介质层101上。所述牺牲介质层140用于为形成顶部源漏插塞122和栅极插塞170提供工艺基础。
牺牲介质层140的材料为绝缘材料。而且，在所述半导体结构的形成过程中，通过刻蚀底部介质层101，从而为顶部介质层500的形成提供空间位置，因此，牺牲介质层140选用易于被刻蚀的材料。牺牲介质层140的材料包括氧化硅、氮化硅、碳化硅、氮氧化硅、氮化硼、氧化铝和氮化铝中的一种或多种。本实施例中，所述牺牲介质层140的材料为氧化硅。
相应的，本实施例中，顶部介质层500位于所述器件区100中。因此，在所述半导体结构的形成过程中，仅去除所述器件区100b的牺牲介质层140，从而减小对隔离区100a（如图5所示）的影响。
本实施例中，顶部介质层500填充于源漏插塞180和栅极插塞170之间。具体地，顶部介质层500还填充于间隙190中，且位于间隙190中的顶部介质层500作为侧墙510。
顶部介质层500的材料包括低k介电材料或超低k介电材料，因此，侧墙510的材料介电常数较小，从而能够降低栅极结构400和源漏插塞180（具体为底部源漏插塞120）之间的有效电容，进而提高半导体结构的性能。而且，本实施例中，所述半导体结构采用源栅极接触孔插塞（Contact Over Active Gate，COAG），栅极插塞170和源漏插塞180之间的距离相应较小，顶部介质层500填充于源漏插塞180之间，因此，通过采用材料介电常数较低的顶部介质层500，还有利于减小栅极插塞170和源漏插塞180之间的寄生电容。此外，通过采用材料介电常数较低的顶部介质层500，还能够降低集成电路中互连结构的RC延迟。
在其他实施例中，当间隙的深宽比较大时，顶部介质层密封间隙的顶部，形成空气隙。空气的介电常数较小，相应也能够降低栅极结构和源漏插塞之间的有效电容。
本实施例中，所述顶部介质层500覆盖源漏插塞180的顶部。后续制程还包括：在源漏插塞180的顶部形成电连接源漏插塞180的金属互连线，金属互连线形成于金属层间介质层中，通过使顶部介质层500覆盖源漏插塞180的顶部，使得高于源漏插塞180顶部的顶部介质层500作为金属层间介质层，从而简化后段制程的工艺步骤。在其他实施例中，所述顶部介质层的顶部与源漏插塞的顶部相齐平，或者，所述顶部介质层的顶部低于源漏插塞的顶部，从而能够灵活选取金属层间介质层的材料，以满足半导体结构的性能需求。
所述半导体结构可以采用前述实施例所述的形成方法所形成，也可以采用其他形成方法所形成。对本实施例所述半导体结构的具体描述，可参考前述实施例中的相应描述，本实施例在此不再赘述。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (24)

  1. 一种半导体结构，其特征在于，包括：
    基底；
    栅极结构，位于所述基底上；
    源漏掺杂区，位于所述栅极结构两侧的基底内；
    接触孔刻蚀停止层，位于所述源漏掺杂区和栅极结构之间的基底上且与所述栅极结构的侧壁相对设置，所述接触孔刻蚀停止层和栅极结构的侧壁之间具有间隙；
    源漏插塞，位于所述源漏掺杂区的顶部，且与所述源漏掺杂区相接触；
    顶部介质层，填充于所述源漏插塞之间，所述顶部介质层还填充于所述间隙中，位于所述间隙中的所述顶部介质层作为侧墙，或者，所述顶部介质层密封所述间隙的顶部，围成空气隙，所述顶部介质层的材料为低k介电材料或超低k介电材料。
  2. 如权利要求1所述的半导体结构，其特征在于，所述半导体结构还包括：防扩散层，位于所述间隙露出的所述接触孔刻蚀停止层的侧壁。
  3. 如权利要求1所述的半导体结构，其特征在于，所述基底包括器件区和隔离区；
    所述栅极结构、源漏掺杂区和顶部介质层均位于所述器件区中；
    所述半导体结构还包括：牺牲介质层，位于所述隔离区的所述基底上，所述牺牲介质层的顶部和所述源漏插塞的顶部相齐平。
  4. 如权利要求1所述的半导体结构，其特征在于，所述半导体结构还包括：底部介质层，位于所述栅极结构侧部的基底上，所述底部介质层覆盖所述源漏掺杂区；
    所述源漏插塞包括：底部源漏插塞，贯穿所述源漏掺杂区上方的底部介质层且与所述源漏掺杂区相接触；顶部源漏插塞，位于所述底部源漏插塞上且与所述底部源漏插塞相接触；
    所述半导体结构还包括：源漏盖帽层，位于所述底部源漏插塞的顶部与所述顶部介质层之间；栅极插塞，位于所述栅极结构的顶部，并与所述栅极结构相接触；栅极盖帽层，位于所述栅极结构的顶部与所述顶部介质层之间；
    所述顶部介质层填充于所述源漏插塞和栅极插塞之间。
  5. 如权利要求1所述的半导体结构，其特征在于，所述顶部介质层覆盖所述源漏插塞的顶部；
    或者，所述顶部介质层的顶部与所述源漏插塞的顶部相齐平；
    或者，所述顶部介质层的顶部低于所述源漏插塞的顶部。
  6. 如权利要求1所述的半导体结构，其特征在于，在平行于所述基底表面且垂直于所述栅极结构侧壁的方向上，所述间隙的宽度为2纳米至12纳米。
  7. 如权利要求1所述的半导体结构，其特征在于，所述接触孔刻蚀停止层的材料为低k介电材料、超低k介电材料或氮化硅。
  8. 如权利要求2所述的半导体结构，其特征在于，所述防扩散层的材料包括氮化硅、碳化硅、碳氮化硅、碳氮氧化硅、氮氧化硅、氮化硼、碳氮化硼、氧化铝和氮化铝中的一种多种。
  9. 如权利要求2所述的半导体结构，其特征在于，所述防扩散层的厚度小于或等于30Å。
  10. 如权利要求9所述的半导体结构，其特征在于，所述防扩散层的厚度为5Å至15Å。
  11. 一种半导体结构的形成方法，其特征在于，包括：
    提供基底，所述基底上形成有栅极结构，所述栅极结构的侧壁形成有伪侧墙，所述伪侧墙的侧壁形成有接触孔刻蚀停止层，所述栅极结构两侧的基底内形成有源漏掺杂区；
    在所述源漏掺杂区和栅极结构的顶部上方形成牺牲介质层；
    形成源漏插塞，贯穿所述源漏掺杂区顶部上方的所述牺牲介质层，并与所述源漏掺杂区相接触；
    形成所述源漏插塞后，刻蚀所述牺牲介质层直至露出所述伪侧墙的顶部；
    露出所述伪侧墙的顶部后，去除所述伪侧墙，在所述接触孔刻蚀停止层和栅极结构的侧壁之间形成间隙；
    形成填充于所述源漏插塞之间的顶部介质层，所述顶部介质层还填充于所述间隙中，形成位于所述间隙中的侧墙，或者，所述顶部介质层密封所述间隙的顶部，形成空气隙，所述顶部介质层的材料介电常数小于所述伪侧墙的材料介电常数。
  12. 如权利要求11所述的半导体结构的形成方法，其特征在于，所述提供基底的步骤中，所述伪侧墙和接触孔刻蚀停止层之间还形成有防扩散层。
  13. 如权利要求11所述的半导体结构的形成方法，其特征在于，所述基底包括器件区和隔离区，所述栅极结构、伪侧墙和源漏掺杂区位于所述器件区；
    刻蚀所述牺牲介质层直至露出所述伪侧墙的顶部的步骤中，去除位于所述器件区的所述牺牲介质层。
  14. 如权利要求11所述的半导体结构的形成方法，其特征在于，所述提供基底的步骤中，所述栅极结构露出的基底上形成有底部介质层，所述底部介质层覆盖所述源漏掺杂区；
    形成所述牺牲介质层之前，所述形成方法还包括：形成贯穿所述源漏掺杂区上方的底部介质层且与所述源漏掺杂区相接触的底部源漏插塞、以及位于所述底部源漏插塞顶面的源漏盖帽层；去除部分厚度的所述栅极结构，在剩余的所述栅极结构的顶部上形成栅极盖帽层；
    形成所述源漏插塞的步骤包括：形成贯穿所述源漏掺杂区顶部上方的所述牺牲介质层和源漏盖帽层的顶部源漏插塞，所述顶部源漏插塞与所述底部源漏插塞相接触，且所述顶部源漏插塞和底部源漏插塞构成源漏插塞；
    形成所述牺牲介质层之后，刻蚀所述牺牲介质层直至露出所述伪侧墙的顶部之前，所述形成方法还包括：形成栅极插塞，贯穿所述栅极结构顶部上方的所述牺牲介质层和栅极盖帽层，并与所述栅极结构相接触；
    形成所述顶部介质层的步骤中，所述顶部介质层填充于所述源漏插塞和栅极插塞之间。
  15. 如权利要求11所述的半导体结构的形成方法，其特征在于，所述提供基底的步骤中，所述栅极结构露出的基底上形成有底部介质层，所述底部介质层覆盖所述源漏掺杂区；
    在形成所述栅极结构之前，所述形成方法还包括：在所述基底上形成伪栅结构；
    形成所述伪侧墙的步骤中，所述伪侧墙形成于所述伪栅结构的侧壁；
    形成所述栅极结构的步骤包括：去除所述伪栅结构，在所述底部介质层中形成栅极开口；在所述栅极开口中形成栅极结构。
  16. 如权利要求11所述的半导体结构的形成方法，其特征在于，所述牺牲介质层的材料和所述伪侧墙的材料相同。
  17. 如权利要求11所述的半导体结构的形成方法，其特征在于，所述伪侧墙的材料包括氧化硅、氮化硅、碳化硅、氮氧化硅、氮化硼、氧化铝和氮化铝中的一种或多种。
  18. 如权利要求11所述的半导体结构的形成方法，其特征在于，所述接触孔刻蚀停止层的材料为低k介电材料、超低k介电材料或氮化硅。
  19. 如权利要求11所述的半导体结构的形成方法，其特征在于，所述牺牲介质层的材料包括氧化硅、氮化硅、碳化硅、氮氧化硅、氮化硼、氧化铝和氮化铝中的一种或多种。
  20. 如权利要求11所述的半导体结构的形成方法，其特征在于，采用各向同性的刻蚀工艺，刻蚀所述牺牲介质层直至露出所述伪侧墙的顶部、以及去除所述伪侧墙，所述各向同性的刻蚀工艺包括远程等离子体刻蚀工艺或湿法刻蚀工艺。
  21. 如权利要求11所述的半导体结构的形成方法，其特征在于，采用旋涂工艺、化学气相沉积、流体化学气相沉积工艺或原子层沉积工艺，形成所述顶部介质层。
  22. 如权利要求11所述的半导体结构的形成方法，其特征在于，所述顶部介质层的材料包括低k介电材料或超低k介电材料。
  23. 如权利要求12所述的半导体结构的形成方法，其特征在于，形成所述防扩散层的工艺包括原子层沉积工艺、化学气相沉积工艺或等离子体增强化学气相沉积工艺。
  24. 如权利要求12所述的半导体结构的形成方法，其特征在于，所述防扩散层的材料包括氮化硅、碳化硅、碳氮化硅、碳氮氧化硅、氮氧化硅、氮化硼、碳氮化硼、氧化铝和氮化铝中的一种多种。
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