WO2018225822A1 - 薄膜トランジスタの製造方法 - Google Patents
薄膜トランジスタの製造方法 Download PDFInfo
- Publication number
- WO2018225822A1 WO2018225822A1 PCT/JP2018/021876 JP2018021876W WO2018225822A1 WO 2018225822 A1 WO2018225822 A1 WO 2018225822A1 JP 2018021876 W JP2018021876 W JP 2018021876W WO 2018225822 A1 WO2018225822 A1 WO 2018225822A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- semiconductor layer
- sputtering
- target
- gas
- oxide semiconductor
- Prior art date
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 51
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 claims abstract description 132
- 239000010408 film Substances 0.000 claims abstract description 124
- 238000004544 sputter deposition Methods 0.000 claims abstract description 97
- 239000007789 gas Substances 0.000 claims abstract description 90
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims abstract description 62
- 239000000758 substrate Substances 0.000 claims abstract description 62
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 53
- 229910052786 argon Inorganic materials 0.000 claims abstract description 31
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910001882 dioxygen Inorganic materials 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims description 19
- 230000008569 process Effects 0.000 claims description 9
- 239000010410 layer Substances 0.000 description 140
- 229910052751 metal Inorganic materials 0.000 description 50
- 239000002184 metal Substances 0.000 description 50
- 229910052760 oxygen Inorganic materials 0.000 description 32
- 239000001301 oxygen Substances 0.000 description 31
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 29
- 239000003990 capacitor Substances 0.000 description 18
- 239000002826 coolant Substances 0.000 description 13
- 239000000463 material Substances 0.000 description 13
- 239000000110 cooling liquid Substances 0.000 description 11
- 238000000151 deposition Methods 0.000 description 10
- 230000008021 deposition Effects 0.000 description 10
- 230000001681 protective effect Effects 0.000 description 10
- 230000001965 increasing effect Effects 0.000 description 9
- 238000009616 inductively coupled plasma Methods 0.000 description 8
- 238000010438 heat treatment Methods 0.000 description 7
- 239000002356 single layer Substances 0.000 description 7
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- 238000012360 testing method Methods 0.000 description 6
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 6
- 206010021143 Hypoxia Diseases 0.000 description 5
- 238000000026 X-ray photoelectron spectrum Methods 0.000 description 5
- 230000007547 defect Effects 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 230000007246 mechanism Effects 0.000 description 5
- 229910044991 metal oxide Inorganic materials 0.000 description 5
- 150000004706 metal oxides Chemical class 0.000 description 5
- 239000002245 particle Substances 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 5
- 239000004696 Poly ether ether ketone Substances 0.000 description 4
- 239000004734 Polyphenylene sulfide Substances 0.000 description 4
- 229910007541 Zn O Inorganic materials 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 238000011156 evaluation Methods 0.000 description 4
- 238000001755 magnetron sputter deposition Methods 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 229920002530 polyetherether ketone Polymers 0.000 description 4
- 229920000069 polyphenylene sulfide Polymers 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 238000012856 packing Methods 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical class N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 230000009466 transformation Effects 0.000 description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- 239000004698 Polyethylene Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000012809 cooling fluid Substances 0.000 description 2
- 238000003795 desorption Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000010891 electric arc Methods 0.000 description 2
- 229920006351 engineering plastic Polymers 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 229920000573 polyethylene Polymers 0.000 description 2
- -1 polyethylene terephthalate Polymers 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000010935 stainless steel Substances 0.000 description 2
- 229910001220 stainless steel Inorganic materials 0.000 description 2
- 239000013077 target material Substances 0.000 description 2
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 2
- 229910001316 Ag alloy Inorganic materials 0.000 description 1
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910019092 Mg-O Inorganic materials 0.000 description 1
- 229910019395 Mg—O Inorganic materials 0.000 description 1
- 229910052779 Neodymium Inorganic materials 0.000 description 1
- 229920012266 Poly(ether sulfone) PES Polymers 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 230000037237 body shape Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000000498 cooling water Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 230000005596 ionic collisions Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000000696 magnetic material Substances 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000011112 polyethylene naphthalate Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 239000003507 refrigerant Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 239000000057 synthetic resin Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/0021—Reactive sputtering or evaporation
- C23C14/0036—Reactive sputtering
- C23C14/0073—Reactive sputtering by exposing the substrates to reactive gases intermittently
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/02—Pretreatment of the material to be coated
- C23C14/024—Deposition of sublayers, e.g. to promote adhesion of the coating
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
- C23C14/08—Oxides
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/34—Sputtering
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/34—Sputtering
- C23C14/3485—Sputtering using pulsed power to the target
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32192—Microwave generated discharge
- H01J37/32211—Means for coupling power to the plasma
- H01J37/3222—Antennas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
Definitions
- the present invention relates to a method for manufacturing a thin film transistor having an oxide semiconductor layer.
- the present invention relates to a method for manufacturing a thin film transistor in which an oxide semiconductor layer is formed by sputtering a target using plasma.
- Patent Document 1 discloses that an oxygen-excess oxide semiconductor layer is formed by sputtering a target metal oxide with a ratio of an oxygen flow rate to a total flow rate of a sputtering gas of 90% to 100%, A method of obtaining a thin film transistor having an oxygen-excess oxide semiconductor layer with high reproducibility by covering the oxide semiconductor layer with a dense metal oxide is disclosed.
- Patent Document 1 uses a high-concentration oxygen gas as a sputtering gas, the density of plasma generated near the surface of the target is reduced. Therefore, the sputtering rate is reduced and the deposition rate of the oxide semiconductor layer is reduced.
- a high-concentration oxygen gas as a sputtering gas as disclosed in Patent Document 1 it is necessary to increase the bias voltage applied to the target.
- the energy of ions that collide with the target increases, and oxygen is desorbed from the metal oxide that is the target during the collision. For this reason, the material composition of the target and the composition of the film formed on the substrate are different, and the film quality may be deteriorated.
- the present invention has been made in view of the above-described problems, and prevents oxygen deficiency in an oxide semiconductor layer, forms an oxide semiconductor layer with excellent film quality, and further provides an oxide semiconductor layer at a high deposition rate.
- the main object is to provide a method for manufacturing a thin film transistor that can improve productivity by forming a thin film.
- a method for manufacturing a thin film transistor having an oxide semiconductor layer according to the present invention includes a gate electrode, a gate insulating layer, an oxide semiconductor layer, a source electrode, and a drain electrode on a substrate.
- a step of forming an oxide semiconductor layer on the gate insulating layer by sputtering a target using plasma, and the step of forming the oxide semiconductor layer includes only argon gas as a sputtering gas.
- a second film forming process for performing sputtering by supplying a mixed gas of argon gas and oxygen gas as a sputtering gas, and the bias voltage applied to the target is ⁇ It is a negative voltage of 1 kV or more.
- the bias voltage applied to the target is smaller than the conventional one (for example, ⁇ 1 to ⁇ 2 kV), the generation of sputtered particles from which oxygen has been released can be suppressed. As a result, a film that maintains the same oxide state as the target material is formed on the substrate, and a high-quality film can be formed.
- the bias voltage applied to the target is small, sputtered particles from which oxygen is not desorbed reach the substrate.
- sputtering can be performed by supplying only argon gas as the sputtering gas, the deposition rate can be increased compared to the case of supplying oxygen gas in addition to argon gas.
- an oxide semiconductor layer having a large amount of oxygen in the film can be formed by including the second film formation step of supplying a mixed gas of argon gas and oxygen gas as a sputtering gas.
- oxygen deficiency in the oxide semiconductor layer can be prevented, and a thin film transistor with excellent electrical characteristics can be manufactured.
- supplying only argon gas as sputtering gas means that the concentration of argon gas in the supplied sputtering gas is 99.9999% or more.
- the oxygen gas concentration in the mixed gas is preferably 5% or less.
- the oxygen gas concentration in the sputtering gas in the second film formation step is reduced, the density of plasma generated near the surface of the target can be increased, and the film formation rate is further improved. can do.
- the film thickness of the first semiconductor layer formed by the first film forming process is larger than the film thickness of the second semiconductor layer formed by the second film forming process.
- the bias voltage applied to the target during sputtering is preferably a negative voltage of ⁇ 600 V or more. With such a configuration, since the bias voltage applied to the target is smaller, the energy of ions colliding with the target becomes smaller. As a result, at the time of ion collision, the amount of released oxygen from the target metal oxide can be further reduced, and an oxide semiconductor layer with better film quality can be formed.
- the second film formation step may be performed after the first film formation step.
- the second semiconductor layer having a large amount of oxygen in the film can be provided on the first semiconductor layer. Therefore, desorption of oxygen from the first semiconductor layer can be suppressed in a heat treatment step that is a subsequent step. As a result, oxygen deficiency in the first semiconductor layer can be suppressed, and a thin film transistor with more excellent electrical characteristics can be manufactured.
- a second film formation step may be performed first, followed by a first film formation step, and then a second film formation step.
- the first semiconductor layer can be disposed between the second semiconductor layers having a large amount of oxygen in the film. Therefore, desorption of oxygen from the first semiconductor layer can be suppressed in a heat treatment step that is a subsequent step.
- the second semiconductor layer can supply oxygen to the first semiconductor layer from both the upper surface side and the lower surface side of the first semiconductor layer. As a result, oxygen depletion of the first semiconductor layer can be suppressed, and a thin film transistor with more excellent electrical characteristics can be manufactured.
- Sputtering in the first film forming step and the second film forming step is preferably performed under a pressure of 0.5 Pa to 3.1 Pa.
- the deposition rate can be further improved. Since the mean free process becomes longer by lowering the pressure during sputtering, the sputtered particles adhere to the substrate without being diffused during transportation, and the film formation rate can be further improved. Therefore, sputtering is preferably performed under a pressure of 3.1 Pa or less. On the other hand, if the pressure is less than 0.5 Pa, plasma may not be generated and maintained. Therefore, the above range is appropriate.
- Sputtering in the first film-forming process and the second film-forming process is performed in such a manner that a vacuum container that is evacuated and gas is introduced, a substrate holding unit that holds the substrate in the vacuum container, and the substrate in the vacuum container.
- a sputtering apparatus that includes a target holding unit that holds a target and a plurality of antennas that are arranged along the surface of the substrate held by the substrate holding unit and generate plasma.
- the oxide semiconductor layer can be prevented from oxygen deficiency, and an oxide semiconductor layer with excellent film quality can be formed.
- a layer can be formed to improve productivity.
- FIG. 6 is a diagram schematically illustrating the band structure of thin film transistors of Samples 2 to 4 created by a negative bias stress test.
- the thin film transistor 1 of the present embodiment is a so-called bottom gate thin film transistor.
- the substrate 2, the gate electrode 3, the gate insulating layer 4, the oxide semiconductor layer 5, the source electrode 6, and It has a drain electrode 7 and a protective film 8 and is provided in this order from the substrate 2 side.
- the substrate 2 is made of a material that can transmit light.
- plastic synthetic resin
- PET polyethylene terephthalate
- PEN polyethylene naphthalate
- PES polyethersulfone
- acrylic polyimide
- It may be composed of glass or the like.
- a gate electrode 3 is provided on the substrate 2.
- the gate electrode 3 is made of a material having high conductivity.
- a metal such as Si, Al, Mo, Cr, Ta, Ti, Pt, Au, Ag, Al—Nd, Ag alloy, tin oxide
- It can be formed using a conductive film of a metal oxide such as zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), or In—Ga—Zn—O (IGZO).
- the gate electrode 3 may have a single layer structure or a stacked structure of two or more layers of these conductive films.
- a gate insulating layer 4 is provided on the gate electrode 3.
- the gate insulating layer 4 is made of a highly insulating material, for example, an insulating film such as SiO 2 , SiN x , SiON, Al 2 O 3 , Y 2 O 3 , Ta 2 O 5 , Hf 2 , or the like It may be an insulating film containing at least two of these compounds.
- the gate insulating layer 4 may have a single layer structure or a laminated structure of two or more layers of these conductive films.
- the oxide semiconductor layer 5 is provided on the gate insulating layer 4.
- the oxide semiconductor layer 5 is composed of an oxide semiconductor layer containing In and O, and includes, for example, In—Ga—Zn—O, In—Al—Mg—O, In—Al—Zn—O, and In—Hf—Zn. It is preferably composed of —O and the like.
- the oxide semiconductor layer 5 of the present embodiment includes a first semiconductor layer 5a formed by sputtering with only argon gas supplied as a sputtering gas, and a mixed gas of argon gas and oxygen gas as sputtering gas. And the formed second semiconductor layer 5b. From the substrate 2 side, the first semiconductor layer 5a and the second semiconductor layer 5b are stacked in this order.
- the first semiconductor layer 5a is an amorphous oxide semiconductor (a-IGZO) such as InGaZnO
- the second semiconductor layer 5b is a crystalline oxide semiconductor such as InGaZnO (nc-IGZO).
- the thickness of the first semiconductor layer 5a relative to the thickness of the entire oxide semiconductor layer 5 is configured to be 50% or more. That is, the thickness of the first semiconductor layer 5a is configured to be larger than the thickness of the second semiconductor layer 5b.
- a source electrode 6 and a drain electrode 7 are provided on the oxide semiconductor layer 5.
- the source electrode 6 and the drain electrode 7 are each made of a material having high conductivity so as to function as an electrode, and may be made of the same material as the gate electrode 2.
- a protective film 8 is provided on the oxide semiconductor 5, the source electrode 6, and the drain electrode 7.
- the protective film 8 may be composed of a silicon oxide film (SiO 2 ) or a fluorinated silicon nitride film (SiN: F) containing fluorine in the silicon nitride film.
- a substrate 2 made of, for example, a glass substrate is prepared, and a gate electrode 3 is formed on the surface of the substrate 2.
- the gate electrode 3 may be formed by a general sputtering method such as DC sputtering, for example.
- a gate insulating layer 4 is formed so as to cover the surface of the substrate 2 and the gate electrode 3.
- a gate insulating layer 3 can be formed by, for example, an evaporation method such as a plasma CVD method.
- the oxide semiconductor layer 5 of the present embodiment includes a vacuum vessel 20 that is evacuated and into which a gas is introduced, a substrate holding unit 30 that holds a substrate in the vacuum vessel 20, and a vacuum vessel 20.
- a sputtering apparatus 100 comprising: a target holding unit 40 that holds a target facing the substrate therein; and a plurality of antennas 50 that are arranged along the surface of the substrate held by the substrate holding unit 30 and generate plasma. Can be formed.
- the step of forming the oxide semiconductor layer 5 of the present embodiment includes a first film forming step of performing sputtering by supplying only argon gas as a sputtering gas, and supplying a mixed gas of argon gas and oxygen gas as a sputtering gas. And a second film forming step for performing sputtering.
- a target prepared by using a conductive oxide sintered body such as InGaZnO, which is a raw material of the oxide semiconductor 5 is arranged in the target holding unit 40.
- the substrate 2 is placed on the substrate holding unit 30.
- the first semiconductor layer 5 a is formed on the gate insulating layer 4. Specifically, after the vacuum vessel 20 is evacuated to 3 ⁇ 10 ⁇ 6 Torr or lower, an argon gas of 50 to 200 sccm is introduced as a sputtering gas, and the pressure in the vacuum vessel 2 is set to 0.5 to 3.1 Pa. Adjust so that Then, high frequency power of 1 to 10 kW is supplied to the plurality of antennas 50 to generate and maintain inductively coupled plasma. A DC voltage pulse is applied to the target to perform sputtering of the target. The voltage applied to the target is a negative voltage of ⁇ 1 kV or higher, preferably a negative voltage of ⁇ 600 V or higher. Thereby, as shown in FIG. 2C, the first semiconductor layer 5 a is formed on the gate insulating layer 4.
- the second semiconductor layer 5b is formed on the first semiconductor layer 5a.
- the pressure in the vacuum chamber 2 is set to 0.5 to 3.3 while introducing a mixed gas of argon gas and oxygen gas of 50 to 200 sccm as a sputtering gas. Adjust to 1 Pa.
- high frequency power of 1 to 10 kW is supplied to the plurality of antennas 50 to generate and maintain inductively coupled plasma.
- a DC voltage pulse is applied to the target to perform sputtering of the target.
- the voltage applied to the target is a negative voltage of ⁇ 1 kV or higher, preferably a negative voltage of ⁇ 600 V or higher.
- the oxygen gas concentration in the mixed gas is preferably 5% or less. When the oxygen gas concentration is in such a range, the film formation rate can be further improved.
- the film thickness of the first semiconductor layer 5a formed by the first film formation process is larger than the film thickness of the second semiconductor layer 5b formed by the second film formation process.
- the first film forming step and the second film forming step are preferably performed.
- the film thickness of the first semiconductor layer 5a and the film thickness of the second semiconductor layer 5b can be increased by changing the film formation time, the high frequency power of the antenna, and the direct current voltage of the target.
- the source electrode 6 and the drain electrode 7 are formed on the oxide semiconductor layer 5.
- the source electrode 6 and the drain electrode 7 can be formed by, for example, DC sputtering. Specifically, first, a resist is applied, exposed, and developed on the oxide semiconductor layer 5, and then the source electrode 5 and the drain made of a metal layer are formed on the oxide semiconductor layer 5 on which the resist is not formed by a DC sputtering method. The electrode 6 is formed. Then, the resist on the oxide semiconductor layer 5 is peeled to form the source electrode 6 and the drain electrode 7 as shown in FIG.
- a protective film is formed using a plasma CVD method so as to cover the upper surfaces of the formed oxide semiconductor layer 5, the source electrode 6, and the drain electrode 7. Form.
- Heat treatment Finally, heat treatment is performed in an atmosphere containing oxygen at atmospheric pressure.
- the furnace temperature in the heat treatment is preferably 150 to 300 ° C.
- the heat treatment time is preferably 1 to 3 hours. As described above, the thin film transistor 1 of the present embodiment can be obtained.
- the sputtering apparatus 100 used in “formation of the oxide semiconductor layer 5” in the manufacturing method described above will be described.
- the high-frequency voltage supplied to the antenna and the target bias voltage can be set independently. Therefore, the bias voltage can be set to a low voltage such that ions in the plasma are attracted to the target and sputtered independently of the generation of the plasma. Therefore, the negative bias voltage applied to the target during sputtering is set to ⁇ 1 kV. It becomes possible to set to such a small value.
- the structure of the sputtering apparatus 100 is demonstrated.
- the sputtering apparatus 100 forms a film on the substrate W by sputtering the target T using the inductively coupled plasma P.
- substrate W is a board
- FPD flat panel displays
- the sputtering apparatus 100 includes a vacuum container 20 that is evacuated and into which a gas is introduced, a substrate holding unit 30 that holds the substrate W in the vacuum container 20, and a vacuum container. 20, a target holding unit 40 for holding the target T, a plurality of linear antennas 50 arranged in the vacuum vessel 20, and a high frequency for generating inductively coupled plasma P in the vacuum vessel 20. And a high-frequency power source 60 that is applied to the plurality of antennas 50. When a high frequency is applied to the plurality of antennas 50 from the high frequency power supply 60, a high frequency current IR flows through the plurality of antennas 50, and an induction electric field is generated in the vacuum vessel 20 to generate inductively coupled plasma P.
- the vacuum vessel 20 is, for example, a metal vessel, and the inside thereof is evacuated by the evacuation device 70.
- the vacuum vessel 20 is electrically grounded.
- a sputtering gas 90 is introduced into the vacuum container 20 via, for example, a sputtering gas supply mechanism 80 having a flow rate controller (not shown) and the gas introduction port 21.
- the sputtering gas 90 is, for example, an inert gas such as argon (Ar), or a mixed gas of an inert gas such as argon and oxygen gas.
- the sputtering gas supply mechanism 80 of this embodiment selectively supplies argon gas and a mixed gas of argon gas and oxygen gas into the vacuum vessel 20.
- the substrate holding unit 30 is a holder that holds the flat substrate W in the vacuum container 20 so as to be in a horizontal state, for example.
- This holder is electrically grounded in this example.
- the target holding unit 40 holds the target T so as to face the substrate W held by the substrate holding unit 30.
- the target T of the present embodiment is a flat plate having a rectangular shape in plan view, and is an oxide semiconductor material such as InGaZnO, for example.
- the target holding unit 40 is provided on a side wall 20a (for example, an upper side wall) that forms the vacuum vessel 20.
- An insulating unit 10 having a vacuum sealing function is provided between the target holding unit 40 and the upper side wall 20a of the vacuum vessel 20.
- a target bias power supply 11 that applies a target bias voltage thereto is connected to the target T via a target holding unit 40 in this example.
- the target bias voltage is a voltage at which ions (Ar + ) in the plasma P are drawn into the target T and sputtered.
- the target bias voltage in the present embodiment is a negative voltage of ⁇ 1 kV or more, preferably ⁇ 200 to ⁇ 600 V.
- a plurality of target holding units 40 are provided.
- the plurality of target holding portions 40 are arranged in parallel on the same plane on the front surface side of the substrate W in the vacuum container 20 so as to be along the front surface of the substrate W (for example, substantially parallel to the back surface of the substrate W). ing.
- the plurality of target holding portions 40 are arranged at equal intervals so that their longitudinal directions are parallel to each other.
- the plurality of targets T arranged in the vacuum container 20 are substantially parallel to the surface of the substrate W and are equally spaced so that the longitudinal directions thereof are parallel to each other. Will be placed.
- Each target holding unit 40 has the same configuration.
- the plurality of antennas 50 are arranged in parallel on the same plane on the surface side of the substrate W in the vacuum container 20 so as to be along the surface of the substrate W (for example, substantially parallel to the surface of the substrate W). .
- the plurality of antennas 50 are arranged at equal intervals so that their longitudinal directions are parallel to each other.
- Each antenna 50 is linear and has the same configuration in plan view, and its length is several tens of centimeters or more.
- the antenna 50 of the present embodiment is disposed on each side of the target T held by each target holding unit 40 as shown in FIG. That is, the antennas 50 and the targets T are alternately arranged, and one target T is sandwiched between the two antennas 50.
- the longitudinal direction of each antenna 50 and the longitudinal direction of the target T held by each target holding portion 40 are the same direction.
- each antenna 50 is, for example, copper, aluminum, alloys thereof, stainless steel, etc., but is not limited thereto.
- the antenna 50 may be hollow, and a coolant such as cooling water may be flowed therein to cool the antenna 50.
- Insulating members 12 are respectively provided at portions where both ends of the antenna 50 penetrate outside the vacuum vessel 20.
- Each insulating member 12 has both end portions of the antenna 50 penetrating, and the penetrating portions are vacuum-sealed by packing, for example.
- Each insulating member 12 and the vacuum container 20 are also vacuum-sealed by packing, for example.
- the material of the insulating member 12 is, for example, ceramics such as alumina, quartz, or engineering plastics such as polyphenylene sulfide (PPS) or polyether ether ketone (PEEK).
- each antenna 50 located in the vacuum vessel 20 is covered with a straight tubular insulating cover 13 made of an insulating material. It is not necessary to seal between the both ends of the insulating cover 13 and the vacuum vessel 20. This is because even if the gas 90 enters the space in the insulating cover 13, the space is small and the moving distance of electrons is short, so that plasma P is not normally generated in the space.
- the material of the insulating cover 13 is, for example, quartz, alumina, fluororesin, silicon nitride, silicon carbide, silicon or the like, but is not limited thereto.
- a high-frequency power source 60 is connected to a feeding end portion 50a that is one end portion of the antenna 50 via a matching circuit 61, and a termination portion 50b that is the other end portion is directly grounded.
- an impedance adjustment circuit such as a variable capacitor or a variable reactor may be provided at the feeding end portion 50a or the termination portion 50b to adjust the impedance of each antenna 50.
- a high-frequency current IR can be passed from the high-frequency power supply 60 to the antenna 50 via the matching circuit 61.
- the high frequency is, for example, a general 13.56 MHz, but is not limited thereto.
- the antenna 50 of this embodiment has a hollow structure having a flow path through which the coolant CL flows.
- the antenna 50 is provided between at least two tubular metal conductor elements 51 (hereinafter referred to as “metal pipes 51”) and adjacent metal pipes 51.
- metal pipes 51 tubular metal conductor elements 51
- adjacent metal pipes 51 adjacent metal pipes 51.
- insulating pipe 52 tubular insulating element 52 that insulates the metal pipes 51
- capacitor 53 that is a capacitive element electrically connected in series with the adjacent metal pipes 51 are provided. ing.
- the number of metal pipes 51 is two, and the number of insulating pipes 52 and capacitors 53 is one each.
- one metal pipe 51 is also referred to as “first metal pipe 51A”, and the other metal pipe is also referred to as “second metal pipe 51B”.
- the antenna 50 may have a configuration including three or more metal pipes 51. In this case, the number of the insulating pipes 52 and the capacitors 53 is one less than the number of the metal pipes 51. Become.
- the coolant CL circulates through the antenna 50 through a circulation channel 14 provided outside the vacuum vessel 20, and the circulation channel 14 has heat for adjusting the coolant CL to a constant temperature.
- a temperature control mechanism 141 such as an exchanger and a circulation mechanism 142 such as a pump for circulating the coolant CL in the circulation flow path 14 are provided.
- the cooling liquid CL high resistance water is preferable from the viewpoint of electrical insulation, for example, pure water or water close thereto is preferable.
- a liquid refrigerant other than water such as a fluorine-based inert liquid, may be used.
- the metal pipe 51 has a straight tube shape in which a linear flow path 51x in which the cooling liquid CL flows is formed.
- a male thread 51a is formed on the outer peripheral portion of at least one longitudinal end of the metal pipe 51.
- the metal pipe 51 of this embodiment forms the edge part in which the external thread part 51a was formed, and other members by separate parts, they may be joined, but you may form from a single member.
- male screw parts 51a be formed at both ends in the longitudinal direction of the metal pipe 51 so as to be compatible.
- the material of the metal pipe 51 is, for example, copper, aluminum, alloys thereof, stainless steel, or the like.
- the insulating pipe 52 has a straight tube shape in which a linear flow path 52x in which the cooling liquid CL flows is formed. Then, on the side peripheral walls at both ends in the axial direction of the insulating pipe 52, female screw portions 52 a that are screwed and connected to the male screw portion 51 a of the metal pipe 51 are formed. Moreover, the recessed part 52b for fitting each electrode 53A, 53B of the capacitor
- PE polyethylene
- PPS
- the capacitor 53 is provided inside the insulating pipe 52, and specifically, provided in the flow path 52x through which the coolant CL of the insulating pipe 52 flows.
- the capacitor 53 includes a first electrode 53A electrically connected to one of the adjacent metal pipes 51 (first metal pipe 51A) and the other of the adjacent metal pipes 51 (second metal).
- Each electrode 53A, 53B has a substantially rotating body shape, and a main flow path 53x is formed at the center along the central axis.
- each of the electrodes 53A and 53B includes a flange portion 531 that electrically contacts an end portion of the metal pipe 51 on the insulating pipe 52 side, and an extending portion 532 that extends from the flange portion 531 toward the insulating pipe 52 side. have.
- the flange portion 531 and the extension portion 532 may be formed from a single member, or may be formed by separate parts and joined together.
- the materials of the electrodes 53A and 53B are, for example, aluminum, copper, and alloys thereof.
- the flange portion 531 is in contact with the end portion of the metal pipe 51 on the insulating pipe 52 side over the entire circumferential direction. Specifically, the axial end surface of the flange portion 531 contacts the tip end surface of a cylindrical contact portion 511 formed at the end portion of the metal pipe 51 over the entire circumferential direction, and the contact portion of the metal pipe 51. Electrical contact is made with the end face of the metal pipe 51 via a ring-shaped multi-face contact 15 provided on the outer periphery of 511. Note that the flange portion 531 may be in electrical contact with the metal pipe 51 by any one of them.
- a plurality of through holes 531h are formed in the flange portion 531 in the thickness direction.
- the extending portion 532 has a cylindrical shape, and a main flow path 53x is formed therein.
- the extension part 532 of the first electrode 53A and the extension part 532 of the second electrode 53B are arranged coaxially with each other. That is, the extended portion 532 of the second electrode 53B is provided in the extended portion 532 of the first electrode 53A. Thereby, a cylindrical space along the flow path direction is formed between the extending portion 532 of the first electrode 53A and the extending portion 532 of the second electrode 53B.
- the electrodes 53A and 53B configured in this way are fitted in a recess 52b formed on the side peripheral wall of the insulating pipe 52.
- the first electrode 53A is fitted in a recess 52b formed on one end side in the axial direction of the insulating pipe 52
- the second electrode is inserted in the recess 52b formed on the other end side in the axial direction of the insulating pipe 52.
- 53B is fitted.
- the electrodes 53A and 53B are fitted into the concave portions 52b of the insulating pipe 52, and the male screw portion 51a of the metal pipe 51 is screwed into the female screw portion 52a of the insulating pipe 52, whereby the contact portion of the metal pipe 51 is contacted.
- the distal end surface of 511 contacts the flange portion 531 of the electrodes 53A and 53B, and the electrodes 53A and 53B are sandwiched and fixed between the insulating pipe 52 and the metal pipe 51.
- the antenna 50 of the present embodiment has a structure in which the metal pipe 51, the insulating pipe 52, the first electrode 53A, and the second electrode 53B are coaxially arranged.
- connection part of the metal pipe 51 and the insulation pipe 52 has a seal structure with respect to the vacuum and the coolant CL.
- the seal structure of the present embodiment is realized by a seal member 16 such as packing provided at the proximal end portion of the male screw portion 51a.
- the seal between the metal pipe 51 and the insulating pipe 52 and the electrical contact between the metal pipe 51 and each of the electrodes 53A and 53B are performed together with the fastening of the male screw portion 51a and the female screw portion 52a. Is very simple.
- the coolant CL flows from the first metal pipe 51A
- the coolant CL flows to the second electrode 53B side through the main channel 53x and the through hole 531h of the first electrode 53A.
- the coolant CL that has flowed to the second electrode 53B side flows to the second metal pipe 51B through the main channel 53x and the through hole 531h of the second electrode 53B.
- the cylindrical space between the extending portion 532 of the first electrode 53A and the extending portion 532 of the second electrode 53B is filled with the cooling liquid CL, and the cooling liquid CL becomes a dielectric and becomes a capacitor. 53 is configured.
- the capacitor 53 is electrically connected in series to the metal pipes 51 adjacent to each other via the insulating pipe 52, the combined reactance of the antenna 50 is simple. In other words, the capacitive reactance is subtracted from the inductive reactance, and the impedance of the antenna 50 can be reduced. As a result, even when the antenna 50 is lengthened, an increase in impedance can be suppressed, a high-frequency current can easily flow through the antenna 50, and the plasma P can be generated efficiently. Thereby, the density of plasma P can be raised and the film-forming speed
- the gap between the electrodes 53A and 53B constituting the capacitor 53 and the dielectric is used. It is possible to eliminate the gap generated in the. As a result, the uniformity of the plasma P can be improved, and the uniformity of the film formation can be improved. Further, by using the cooling liquid CL as a dielectric, it is not necessary to prepare a liquid dielectric different from the cooling liquid CL, and the first electrode 53A and the second electrode 53B can be cooled. .
- the cooling liquid CL is adjusted to a constant temperature by a temperature control mechanism.
- this cooling liquid CL as a dielectric, it is possible to suppress a change in the dielectric constant due to a temperature change, thereby suppressing a change in capacitance value. This also improves the uniformity of the plasma P. Further, when water is used as the cooling liquid CL, the relative dielectric constant of water is about 80 (20 ° C.), which is larger than the dielectric sheet made of resin, so that the capacitor 53 that can withstand high voltage is formed. Can do.
- the high frequency voltage supplied to the antenna 50 and the bias voltage of the target T can be set independently, so that the bias voltage can be set independently from the generation of the plasma P.
- the voltage can be set to a low voltage so that ions therein are attracted to the target T and sputtered.
- the target T can be sputtered at a low voltage, the change in the material composition of the target T and the composition of the film formed on the substrate W can be reduced.
- the plasma P for sputtering is generated using the antenna 50, the target T can be consumed uniformly and the use efficiency of the target T can be improved as compared with the magnetron sputtering apparatus.
- the present embodiment has a configuration that does not have a DC magnetic field near the target surface, and can be easily applied to a magnetic material.
- the capacitance value can be accurately set from the distance between the first electrode 53A and the second electrode 53B, the facing area, and the relative dielectric constant of the coolant CL without considering the gap.
- the structure for pressing the electrodes 53A and 53B and the dielectric for filling the gaps can be eliminated, and the structure around the antenna due to the pressing structure and the deterioration of the uniformity of the plasma P caused thereby can be prevented. be able to.
- the relationship between the target bias voltage (V) and the film formation rate (nm / min) was evaluated.
- the target T used is IGZO1114, and the size is 150 ⁇ 1000 mm.
- the distance between antennas (pitch width) is 200 mm.
- the target-substrate distance is 125 mm.
- the size of the substrate W is 320 ⁇ 400 mm.
- the pressure inside the vacuum vessel 20 was adjusted to 1.3 Pa while introducing a sputtering gas (Ar gas) of 100 sccm.
- a sputtering gas Ar gas
- High frequency power 5 kW, 7 kW, or 8 kW was supplied to the plurality of antennas 50 to generate and maintain inductively coupled plasma P.
- a DC voltage pulse 50 kHz, Duty 97%) was applied to the target T, the target T was sputtered, and the film formation rate was measured.
- each target bias voltage at each high frequency power is shown in FIG.
- the target bias voltage is ⁇ 665 V when the high frequency power is 5 kW
- the target bias voltage is ⁇ 440 V when the high frequency power is 7 kW
- the high frequency power is 8 kW.
- the target bias voltage may be -344V.
- the film formation rate was evaluated when oxygen gas was supplied together with argon gas into the vacuum vessel.
- the target T used is IGZO1114, and the size is 150 ⁇ 1000 mm.
- the distance between antennas (pitch width) is 200 mm.
- the target-substrate distance is 125 mm.
- the size of the substrate W is 320 ⁇ 400 mm.
- the pressure in the vacuum vessel 20 was adjusted to 0.9 Pa while introducing a mixed gas (argon gas + oxygen gas) of 100 sccm.
- High frequency power of 7 kW or 8 kW was supplied to the plurality of antennas 50 to generate and maintain inductively coupled plasma P.
- a DC voltage pulse of ⁇ 400 V (50 kHz, Duty 97%) was applied to the target T, the target T was sputtered, and the film formation rate was measured.
- FIG. 7 shows the film formation rate when the concentration of oxygen gas is changed at each high-frequency power. As can be seen from FIG. 7, the deposition rate decreases as the oxygen gas concentration increases, and the deposition rate is highest when only argon gas is supplied.
- the oxygen bonding state of the IGZO film (IGZO film according to the present invention) formed using the sputtering apparatus 100 of the present embodiment is measured using an X-ray photoelectron spectrometer (XPS analyzer (Shimadzu Corporation KRATOS AXIS-ULTRA)). analyzed. Further, as a comparative example, an oxygen binding state of an IGZO film (IGZO film according to a conventional example) formed using a conventional RF magnetron sputtering apparatus (Eiko ESS-300 Co., Ltd.) was analyzed using the XPS analyzer. .
- IGZO film After evacuating the vacuum vessel 20 to 3 ⁇ 10 ⁇ 6 Torr or less, the pressure in the vacuum vessel 20 was adjusted to 1.3 Pa while introducing a 100 sccm sputtering gas (Ar gas only). High frequency power of 7 kW was supplied to the plurality of antennas 50 to generate and maintain inductively coupled plasma P. A DC voltage pulse of ⁇ 400 V (50 kHz, Duty 97%) was applied to the target T, and the target T (IGZO1114) was sputtered to form a film.
- IGZO film After evacuating the vacuum vessel to 3 ⁇ 10 ⁇ 6 Torr or less, vacuum was introduced while introducing 19.1 sccm of sputtering gas (Ar gas) and 0.9 sccm of oxygen gas (mixed gas with an oxygen concentration of 4.5%). The pressure in the container was adjusted to 0.6 Pa. A high frequency power of 100 W was supplied to the cathode, and the target T (IGZO1114) was sputtered to form a film.
- Ar gas sputtering gas
- oxygen gas mixed gas with an oxygen concentration of 4.5%
- FIG. 8 shows an XPS spectrum of Ga2p 3/2 obtained by an XPS analyzer.
- FIG. 9 is a diagram showing the ratio of each component obtained by peak-separating the XPS spectrum of Ga2p 3/2 , the XPS spectrum of In3d 5/2 , and the XPS spectrum of Zn2p 3/2 .
- a film in which 60% or more of the metal element is combined with oxygen without adding a reactive gas (oxygen gas). can be formed.
- Example creation Four bottom gate thin film transistors using a low-resistance silicon substrate as a gate electrode were prepared (Samples 1 to 4).
- a gate insulating layer made of SiO 2 and having a thickness of 100 nm is provided on a gate electrode of a low-resistance silicon substrate, and an oxide semiconductor layer made of an IGZO film (IGZO 1114) is provided on the gate insulating layer.
- an oxide semiconductor layer having a thickness of 50 nm was formed as a single layer using a conventional high-frequency magnetron sputtering apparatus, and finally heat-treated in an oxygen atmosphere at 300 ° C. for 2 hours.
- an oxide semiconductor layer was formed using the sputtering apparatus 100 described above.
- a DC pulse voltage of ⁇ 350 V was applied to the target, plasma was generated using a high frequency antenna, only argon gas was supplied as a sputtering gas, sputtering was performed at room temperature, and a 50 nm thick oxide A semiconductor layer was formed as a single layer and finally heat-treated in an oxygen atmosphere at 300 ° C. for 2 hours.
- an oxide semiconductor layer was formed as a single layer under the same conditions as Sample 2, and was finally heat-treated in an oxygen atmosphere at 250 ° C. for 2 hours.
- a DC pulse voltage of ⁇ 350 V was first applied to the target, plasma was generated using a high frequency antenna, only argon gas was supplied as a sputtering gas, and sputtering was performed at room temperature. One semiconductor layer was formed. Thereafter, a mixed gas of argon gas and oxygen gas (concentration: 5%) was supplied as a sputtering gas, and sputtering was performed at room temperature to form a second semiconductor layer having a thickness of 5 nm on the first semiconductor layer. Thereafter, heat treatment was finally performed in an oxygen atmosphere at 250 ° C. for 2 hours.
- the sample 4 with the oxide semiconductor layer having a two-layer structure manufactured by the manufacturing method of the present embodiment has a very small threshold voltage shift amount ⁇ V th , and the electrical stress was found to be more stable. This is a better result than the sample 1 in which the oxide semiconductor layer is formed by the conventional magnetron sputtering apparatus and the samples 2 and 3 in which the oxide semiconductor layer is formed as a single layer by the sputtering apparatus 100 of the present embodiment. I understand.
- the oxide semiconductor layer is formed at the interface between the oxide semiconductor layer (a-IGZO) and the protective film (SiO 2 ). It is thought that defects are likely to occur. For this reason, carriers are generated in the channel layer even when the gate voltage V gs is zero, current flows, and a thin film transistor is required unless a negative voltage that cancels fixed charges due to defects generated at the interface is applied as the gate voltage V gs. It is thought that cannot be shut off.
- the second semiconductor layer formed by sputtering using a mixed gas of argon gas and oxygen gas as the sputtering gas is a crystalline oxide semiconductor (nc). -IGZO).
- nc crystalline oxide semiconductor
- -IGZO crystalline oxide semiconductor
- ⁇ Effect of this embodiment> since the bias voltage applied to the target is smaller than the conventional one (for example, ⁇ 1 to ⁇ 2 kV), the generation of sputtered particles from which oxygen is desorbed is suppressed. be able to. As a result, a film that maintains the same oxide state as the target material is formed on the substrate, and a high-quality film can be formed. In addition, since the bias voltage applied to the target is small, sputtered particles from which oxygen is not desorbed reach the substrate.
- the bias voltage applied to the target is small, sputtered particles from which oxygen is not desorbed reach the substrate.
- the deposition rate can be increased compared to the case of supplying oxygen gas in addition to argon gas.
- an oxide semiconductor layer having a large amount of oxygen in the film can be formed by including the second film formation step of supplying a mixed gas of argon gas and oxygen gas as a sputtering gas. As a result, oxygen deficiency in the oxide semiconductor layer can be prevented, and a thin film transistor with excellent electrical characteristics can be manufactured.
- the thin film transistor 1 of the above embodiment has a bottom gate structure, but is not limited thereto, and may have a top gate structure.
- the second semiconductor layer 5b is provided on the first semiconductor layer 5a.
- the first semiconductor layer 5a is provided on the second semiconductor layer 5b. Good.
- the second film formation step may be performed first, and then the first film formation step may be performed.
- the oxide semiconductor layer 5 of the thin film transistor 1 of the above embodiment has a two-layer structure in which the second semiconductor layer 5b is provided on the first semiconductor layer 5a. However, as shown in FIG. It may have a three-layer structure in which the first semiconductor layer 5a is provided between the two second semiconductor layers 5b.
- the second film formation step may be performed first, then the first film formation step, and then the second film formation step.
- the antenna has a linear shape, but may have a curved or bent shape.
- the metal pipe may be curved or bent, or the insulating pipe may be curved or bent.
- the extending portion of the electrode is cylindrical, but may be another rectangular tube shape, a flat plate shape, a curved plate shape, or a bent plate shape.
- the capacitor 53 has a two-cylinder structure composed of two cylindrical extending portions.
- three or more cylindrical extending portions 532 are coaxially arranged. It may be placed on top.
- the extending portions 532 of the first electrodes 53A and the extending portions 532 of the second electrodes 53B are arranged alternately.
- the inner and outer two are the extending portions 532 of the first electrode 53A, and the middle one is the extending portion 532 of the second electrode 53B.
- the electrodes 53A and 53B and the metal pipe 51 are contacted by providing contact terminals 533 on the electrodes 53A and 53B, as shown in FIG. You may comprise so that 533 may contact the metal pipe 51.
- FIG. The configuration of FIG. 14 is provided with a contact terminal 533 protruding outward in the axial direction from the flange portion 531 of the electrodes 53A, 53B, and the contact terminal 533 is in press contact with the outer peripheral surface of the contact portion 511 of the metal pipe 51. is there.
- the relative positions of the electrodes 53A and 53B are defined by the surface facing the axially outer side of the recess 52b of the insulating pipe 52.
- the metal element 51 on one side of the insulating element 52 may be used as the first electrode 53A.
- the second electrode 53B electrically connected to the metal element 51 on the other side of the insulating element 52 passes through the inside of the insulating element 52 and into the metal element 51 on one side of the insulating element 52. It can be considered that the configuration extends.
- the conductor element and the insulating element have a tubular shape having one internal flow path, but may have two or more internal flow paths or have a branched internal flow path. good.
- the sputtering apparatus 100 of the above embodiment has a configuration having a plurality of target holding units, but may have a configuration having one target holding unit. Even in this case, a configuration having a plurality of antennas is desirable, but a configuration having one antenna may also be used.
- an oxygen semiconductor layer is prevented from being oxygen deficient, an oxide semiconductor layer having excellent film quality is formed, and further, an oxide semiconductor layer is formed at a high film formation rate. Productivity can be improved.
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Plasma & Fusion (AREA)
- Optics & Photonics (AREA)
- Analytical Chemistry (AREA)
- Thin Film Transistor (AREA)
- Physical Vapour Deposition (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Abstract
Description
特許文献1に開示されるような、スパッタリングガスとして高濃度の酸素ガスを用いるスパッタ法においてスパッタ率を向上させるためには、ターゲットに印加するバイアス電圧を大きくする必要がある。しかしその場合には、ターゲットに衝突するイオンのエネルギーが大きくなり、衝突時にターゲットである金属酸化物から酸素が脱離する。そのため、ターゲットの材料組成と基板に形成される膜の組成とが異なってしまい、膜質が悪化するおそれがある。
またターゲットに印加するバイアス電圧が小さいので、酸素が脱離していないスパッタ粒子が基板に到達することになる。その結果、スパッタリングガスとしてアルゴンガスのみを供給してスパッタリングを行うことができるので、アルゴンガスに加えて酸素ガスを供給する場合に比べて成膜速度を速くすることができる。
さらに、スパッタリングガスとしてアルゴンガスと酸素ガスの混合ガスを供給する第2成膜工程を有することにより、膜中酸素量が大きい酸化物半導体層を形成することができる。その結果、酸化物半導体層の酸素欠乏を防止することができ、電気的特性に優れた薄膜トランジスタを製造することができる。
このような構成であれば、第2成膜工程におけるスパッタリングガス中の酸素ガス濃度が小さくなり、ターゲットの表面近傍に生成されるプラズマの密度をより大きくすることができ、成膜速度をさらに向上することができる。
このような構成であれば、酸化物半導体層を形成する工程において、成膜速度が大きい第1成膜工程を実施する割合を高くすることができ、酸化物半導体層全体の平均成膜速度を大きくすることができ、生産性がさらに向上することができる。
このような構成であれば、ターゲットに印加するバイアス電圧がより小さいので、ターゲットに衝突するイオンのエネルギーがより小さくなる。その結果、イオンの衝突時に、ターゲットである金属酸化物からの酸素の脱離量をより低減することができ、より優れた膜質の酸化物半導体層を形成することができる。
このような構成であれば、第1半導体層の上に、膜中酸素量が大きい第2半導体層を設けることができる。そのため、後工程である熱処理工程等において、第1半導体層からの酸素の脱離を抑制することができる。その結果、第1半導体層の酸素欠乏を抑制することができ、より電気的特性に優れた薄膜トランジスタを製造することができる。
このような構成であれば、膜中酸素量が大きい第2半導体層の間に第1半導体層を配置することができる。そのため、後工程である熱処理工程等において、第1半導体層からの酸素の脱離を抑制することができる。さらには、第2半導体層は、第1半導体層の上面側および下面側の両方から、第1半導体層に酸素を供給することができる。その結果、その結果、第1半導体層の酸素欠乏を抑制することができ、より電気的特性に優れた薄膜トランジスタを製造することができる。
このような構成であれば、成膜速度をより向上することができる。スパッタリング時の圧力をより低くすることで平均自由工程が長くなるため、スパッタ粒子が輸送中に拡散されずに基板に付着し、成膜速度をより向上することができる。そのためスパッタリングは3.1Pa以下の圧力下で行うことが好ましい。一方で圧力が0.5Pa未満であると、プラズマを生成維持できないおそれがある。よって、上記範囲が適切となる。
このようなスパッタリング装置を用いることにより、アンテナに供給する高周波電圧とターゲットのバイアス電圧との設定を独立して行うことができるので、バイアス電圧をプラズマの生成とは独立してプラズマ中のイオンをターゲットに引き込んでスパッタさせる程度の低電圧に設定することができる。そのため、スパッタリング時にターゲットに印加する負のバイアス電圧を-1kV以上の小さな値に設定することが可能になる。
2 ・・・基板
3 ・・・ゲート電極
4 ・・・ゲート絶縁層
5 ・・・酸化物半導体層
5a ・・・第1半導体層
5b ・・・第2半導体層
6 ・・・ソース電極
7 ・・・ドレイン電極
8 ・・・保護膜
100・・・スパッタリング装置
W ・・・基板
P ・・・プラズマ
T ・・・ターゲット
20 ・・・真空容器
30 ・・・基板保持部
40 ・・・ターゲット保持部
50 ・・・アンテナ
51 ・・・導体要素
52 ・・・絶縁要素
53 ・・・容量素子
まず、本発明の実施形態の製造方法により得られる薄膜トランジスタ1の構成について説明する。
本実施形態の薄膜トランジスタ1は、所謂ボトムゲート構造の薄膜トランジスタであり、図1に示すように、基板2と、ゲート電極3と、ゲート絶縁層4と、酸化物半導体層5と、ソース電極6およびドレイン電極7と、保護膜8とを有し、基板2側からこの順に設けられている。
本実施形態では、酸化物半導体層5全体の膜厚に対する第1半導体層5aの膜厚が、50%以上になるように構成されている。すなわち、第1半導体層5aの膜厚が第2半導体層5bの膜厚よりも大きくなるように構成されている。
次に、図2を用いて、図1の薄膜トランジスタ1の製造方法について説明する。
まず、図2(a)に示すように、例えばガラス基板からなる基板2を準備し、該基板2の表面上に、ゲート電極3を形成する。ゲート電極3の形成は、例えば、DCスパッタリング等の一般的なスパッタリング法によって行ってよい。
次に、図2(b)に示すように、基板2の表面およびゲート電極3を覆うようにゲート絶縁層4を形成する。このようなゲート絶縁層3は、たとえば、プラズマCVD法等の蒸着法により形成することができる。
次に、図2(c)および(d)に示すように、ゲート絶縁層4上にチャネル層としての酸化物半導体層5を形成する。本実施形態の酸化物半導体層5は、図3に示すような、真空排気され且つガスが導入される真空容器20と、真空容器20内において基板を保持する基板保持部30と、真空容器20内において基板と対向してターゲットを保持するターゲット保持部40と、基板保持部30に保持された基板の表面に沿って配列され、プラズマを発生させる複数のアンテナ50と、を備えるスパッタリング装置100を用いて形成することができる。
本実施形態の酸化物半導体層5を形成する工程は、スパッタリングガスとしてアルゴンガスのみを供給してスパッタリングを行う第1成膜工程と、スパッタリングガスとしてアルゴンガスと酸素ガスの混合ガスを供給してスパッタリングを行う第2成膜工程とを含むことを特徴としている。第1成膜工程と第2成膜工程では、共通して、酸化物半導体5の原料となるInGaZnO等の導電性酸化物焼結体をターゲットとし、ターゲット保持部40に準備したターゲットを配置し、基板保持部30に基板2を配置する。
まず、ゲート絶縁層4上に第1半導体層5aを形成する。
具体的には、真空容器20を3×10-6Torr以下に真空排気した後、50~200sccmのアルゴンガスをスパッタリングガスとして導入しつつ、真空容器内2の圧力を0.5~3.1Paとなるように調整する。そして複数のアンテナ50に1~10kWの高周波電力を供給し、誘導結合型のプラズマを生成・維持する。ターゲットに直流電圧パルスを印加して、ターゲットのスパッタリングを行う。ターゲットに印加する電圧は-1kV以上の負電圧とし、好ましくは-600V以上の負電圧とする。
これにより、図2(c)に示すように、ゲート絶縁層4上に第1半導体層5aを形成する。
第1半導体層5aを形成した後、図2(d)に示すように、第1半導体層5a上に第2半導体層5bを形成する。
具体的には、第1半導体層の成膜を完了した後、50~200sccmのアルゴンガスと酸素ガスの混合ガスをスパッタリングガスとして導入しつつ、真空容器内2の圧力を0.5~3.1Paとなるように調整する。そして複数のアンテナ50に1~10kWの高周波電力を供給し、誘導結合型のプラズマを生成・維持する。ターゲットに直流電圧パルスを印加して、ターゲットのスパッタリングを行う。ターゲットに印加する電圧は-1kV以上の負電圧とし、好ましくは-600V以上の負電圧とする。
第2成膜工程においては、混合ガスにおける酸素ガスの濃度が5%以下であることが好ましい。酸素ガス濃度がこのような範囲であれば、成膜速度をより向上することができる。
次に、図2(e)に示すように、酸化物半導体層5上にソース電極6およびドレイン電極7を形成する。ソース電極6およびドレイン電極7の形成は、例えば、DCスパッタリングにより形成することができる。具体的には、まず、酸化物半導体層5上にレジストを塗布、露光、現像した後、レジストが形成されていない酸化物半導体層5上にDCスパッタリング法によって金属層からなるソース電極5およびドレイン電極6を形成する。そして、酸化物半導体層5上のレジストを剥離することによって、図2(e)に示すように、ソース電極6およびドレイン電極7が形成される。
次に、必要に応じて、図2(f)に示すように、形成された酸化物半導体層5、ソース電極6およびドレイン電極7の上面を覆うように、例えばプラズマCVD法を用いて保護膜を形成する。
最後に、酸素を含む大気圧下の雰囲気中で熱処理を行う。熱処理における炉内温度は150~300℃が好ましい。また熱処理時間は1~3時間が好ましい。
以上により、本実施形態の薄膜トランジスタ1を得ることができる。
次に、上述した製造方法における“酸化物半導体層5の形成”で使用するスパッタリング装置100について説明する。
上述した“酸化物半導体層5の形成”の工程ではスパッタリング装置100を使用することにより、アンテナに供給する高周波電圧とターゲットのバイアス電圧との設定を独立して行うことができる。そのため、バイアス電圧をプラズマの生成とは独立してプラズマ中のイオンをターゲットに引き込んでスパッタさせる程度の低電圧に設定することができ、そのため、スパッタリング時にターゲットに印加する負のバイアス電圧を-1kV以上の小さな値に設定することが可能になる。
以下に、スパッタリング装置100の構成について説明する。
このように、金属パイプ51及び絶縁パイプ52の間のシール、及び、金属パイプ51と各電極53A、53Bとの電気的接触が、雄ねじ部51a及び雌ねじ部52aの締結と共に行われるので、組み立て作業が非常に簡便となる。
本実施形態のスパッタリング装置100において、ターゲットバイアス電圧(V)と成膜速度(nm/min)との関係を評価した。なお、使用したターゲットTは、IGZO1114であり、サイズは、150×1000mmである。アンテナ間距離(ピッチ幅)は、200mmである。ターゲット-基板間距離は、125mmである。基板Wのサイズは、320×400mmである。
本実施形態のスパッタリング装置100を用いて、真空容器内にアルゴンガスとともに酸素ガスを供給した場合の成膜速度を評価した。なお、使用したターゲットTは、IGZO1114であり、サイズは、150×1000mmである。アンテナ間距離(ピッチ幅)は、200mmである。ターゲット-基板間距離は、125mmである。基板Wのサイズは、320×400mmである。
本実施形態のスパッタリング装置100を用いて形成したIGZO膜(本発明によるIGZO膜)の酸素結合状態をX線光電子分光分析装置(XPS分析装置(株式会社島津製作所 KRATOS AXIS‐ULTRA))を用いて分析した。また、比較例として、従来方式のRFマグネトロンスパッタ装置(株式会社エイコー ESS‐300)を用いて形成したIGZO膜(従来例によるIGZO膜)の酸素結合状態を、前記XPS分析装置を用いて分析した。
真空容器20を3×10-6Torr以下に真空排気した後に、100sccmのスパッタ用ガス(Arガスのみ)を導入しつつ真空容器20内の圧力を1.3Paとなるように調整した。複数のアンテナ50に7kWの高周波電力を供給して、誘導結合型のプラズマPを生成・維持した。ターゲットTに-400Vの直流電圧パルス(50kHz、Duty97%)を印加して、ターゲットT(IGZO1114)をスパッタリングして成膜した。
従来例によるIGZO膜:
真空容器を3×10-6Torr以下に真空排気した後に、19.1sccmのスパッタ用ガス(Arガス)及び0.9sccmの酸素ガス(酸素濃度4.5%の混合ガス)を導入しつつ真空容器内の圧力を0.6Paとなるように調整した。カソードに100Wの高周波電力を供給してターゲットT(IGZO1114)をスパッタリングして成膜した。
本実施形態に係る製造方法により作られた薄膜トランジスタの電気的特性を確認するため、以下の要領で負バイアスストレス試験を行った。
低抵抗シリコン基板をゲート電極として使用したボトムゲート構造の薄膜トランジスタを4つ準備した(サンプル1~4)。いずれのサンプルも、低抵抗シリコン基板のゲート電極の上に、SiO2からなる膜厚100nmのゲート絶縁層を設け、その上にIGZO膜(IGZO1114)からなる酸化物半導体層を設け、その上に、ソース電極、ドレイン電極(Pt:20nm、Mo:80nm)及び保護膜(SiO2)を設けた。
サンプル2~4では、上述したスパッタリング装置100を用いて酸化物半導体層を形成した。
サンプル2は、ターゲットに-350Vの直流パルス電圧を印加して、高周波アンテナを用いてプラズマ生成を行い、スパッタリングガスとしてアルゴンガスのみを供給して、室温でスパッタリングを行い、厚さ50nmの酸化物半導体層を単層で形成し、最終的に酸素雰囲気で300℃、2時間で熱処理を行った。
サンプル3は、サンプル2と同じ条件により酸化物半導体層を単層で形成し、最終的に酸素雰囲気で250℃、2時間で熱処理を行った。
作製したサンプル1~4に対して、次の条件により負バイアスストレス試験を行い、ストレス時間(秒)に対する閾値電圧のシフト量(ΔVth(V))を測定した。試験結果を図10に示す。
・ゲート印加電圧:-20V
・ストレス時間:1~10000s
・ドレイン-ソース間電圧:5.0V
このように構成した本実施形態の薄膜トランジスタの製造方法によれば、ターゲットに印加するバイアス電圧が従来(例えば-1~-2kV)よりも小さいので、酸素が脱離したスパッタ粒子の生成を抑制することができる。その結果、基板には、ターゲット材料と同じ酸化物状態を維持した膜が形成され、高品質の膜を形成することができる。
またターゲットに印加するバイアス電圧が小さいので、酸素が脱離していないスパッタ粒子が基板に到達することになる。その結果、スパッタリングガスとしてアルゴンガスのみを供給してスパッタリングを行うことができるので、アルゴンガスに加えて酸素ガスを供給する場合に比べて成膜速度を速くすることができる。
さらに、スパッタリングガスとしてアルゴンガスと酸素ガスの混合ガスを供給する第2成膜工程を有することにより、膜中酸素量が大きい酸化物半導体層を形成することができる。その結果、酸化物半導体層の酸素欠乏を防止することができ、電気的特性に優れた薄膜トランジスタを製造することができる。
なお、本発明は前記実施形態に限られるものではない。
Claims (8)
- 基板上に、ゲート電極と、ゲート絶縁層と、酸化物半導体層と、ソース電極と、ドレイン電極とを有する薄膜トランジスタの製造方法であって、
プラズマを用いてターゲットをスパッタリングすることにより、前記ゲート絶縁層の上に酸化物半導体層を形成する工程を含み、
前記酸化物半導体層を形成する工程は、
スパッタリングガスとしてアルゴンガスのみを供給してスパッタリングを行う第1成膜工程と、
スパッタリングガスとしてアルゴンガスと酸素ガスの混合ガスを供給してスパッタリングを行う第2成膜工程とを含み、
前記ターゲットに印加するバイアス電圧が-1kV以上の負電圧である、薄膜トランジスタの製造方法。 - 前記第2成膜工程において、前記混合ガスにおける前記酸素ガスの濃度が5%以下である、請求項1に記載の薄膜トランジスタの製造方法。
- 前記第1成膜工程により形成される第1半導体層の膜厚が、前記第2成膜工程により形成される第2半導体層の膜厚よりも大きい、請求項1又は2に記載の薄膜トランジスタの製造方法。
- 前記バイアス電圧が-600V以上の負電圧である、請求項1乃至3のいずれか1項に記載の薄膜トランジスタの製造方法。
- 前記酸化物半導体層を形成する工程において、前記第1成膜工程を行った後に前記第2成膜工程を行う、請求項1乃至4のいずれか1項に記載の薄膜トランジスタの製造方法。
- 前記酸化物半導体層を形成する工程において、前記第2成膜工程を行った後に前記第1成膜工程行い、その後さらに前記第2成膜工程を行う、請求項1乃至4のいずれか1項に記載の薄膜トランジスタの製造方法。
- 前記第1成膜工程および前記第2成膜工程は、0.5Pa以上3.1Pa以下の圧力下で行われる、請求項1乃至6のいずれか1項に記載の薄膜トランジスタの製造方法。
- 前記第1成膜工程および前記第2成膜工程は、真空排気され且つガスが導入される真空容器と、前記真空容器内において基板を保持する基板保持部と、前記真空容器内において前記基板と対向して前記ターゲットを保持するターゲット保持部と、前記基板保持部に保持された前記基板の表面に沿って配列され、前記プラズマを発生させる複数のアンテナと、を備えるスパッタリング装置を用いてスパッタリングを行うものである、請求項1乃至7のいずれか1項に記載の薄膜トランジスタの製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019523971A JP6928884B2 (ja) | 2017-06-07 | 2018-06-07 | 薄膜トランジスタの製造方法 |
KR1020197035759A KR102322393B1 (ko) | 2017-06-07 | 2018-06-07 | 박막 트랜지스터의 제조 방법 |
CN201880037318.3A CN110709968B (zh) | 2017-06-07 | 2018-06-07 | 薄膜晶体管的制造方法 |
US16/619,943 US11417752B2 (en) | 2017-06-07 | 2018-06-07 | Method for producing thin film transistor |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017-113014 | 2017-06-07 | ||
JP2017113014 | 2017-06-07 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2018225822A1 true WO2018225822A1 (ja) | 2018-12-13 |
Family
ID=64565949
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2018/021876 WO2018225822A1 (ja) | 2017-06-07 | 2018-06-07 | 薄膜トランジスタの製造方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US11417752B2 (ja) |
JP (1) | JP6928884B2 (ja) |
KR (1) | KR102322393B1 (ja) |
CN (1) | CN110709968B (ja) |
TW (1) | TWI684283B (ja) |
WO (1) | WO2018225822A1 (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2020088152A (ja) * | 2018-11-26 | 2020-06-04 | 日新電機株式会社 | 薄膜トランジスタの製造方法 |
WO2021015149A1 (ja) * | 2019-07-19 | 2021-01-28 | 日新電機株式会社 | 薄膜トランジスタの製造方法 |
KR20220003603A (ko) | 2019-06-25 | 2022-01-10 | 닛신덴키 가부시키 가이샤 | 산화물 반도체의 가공 방법 및 박막 트랜지스터의 제조 방법 |
JP7483883B2 (ja) | 2019-11-15 | 2024-05-15 | ダイソン・テクノロジー・リミテッド | スパッタ堆積装置及び方法 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102511735B1 (ko) * | 2021-07-14 | 2023-03-17 | 성균관대학교산학협력단 | 전계 효과 트랜지스터 및 이의 제조 방법 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010226101A (ja) * | 2009-02-27 | 2010-10-07 | Semiconductor Energy Lab Co Ltd | 半導体装置及びその作製方法 |
JP2011142174A (ja) * | 2010-01-06 | 2011-07-21 | Fujifilm Corp | 成膜方法および半導体装置 |
WO2012031962A1 (en) * | 2010-09-10 | 2012-03-15 | Applied Materials, Inc. | Method and system for depositing a thin-film transistor |
JP2013211544A (ja) * | 2012-03-02 | 2013-10-10 | Semiconductor Energy Lab Co Ltd | 半導体装置及び半導体装置の作製方法、並びに酸化膜の作製方法 |
JP2015179839A (ja) * | 2014-02-28 | 2015-10-08 | 株式会社半導体エネルギー研究所 | 半導体装置、該半導体装置を有する表示装置、該表示装置を有する表示モジュール、並びに該半導体装置、該表示装置、及び該表示モジュールを有する電子機器 |
JP2016056446A (ja) * | 2014-05-02 | 2016-04-21 | 株式会社半導体エネルギー研究所 | 酸化物の作製方法 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002094057A (ja) * | 2000-09-20 | 2002-03-29 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
US20070012557A1 (en) * | 2005-07-13 | 2007-01-18 | Applied Materials, Inc | Low voltage sputtering for large area substrates |
KR20080064269A (ko) | 2007-01-04 | 2008-07-09 | 주식회사 엘지화학 | 스퍼터링에 의한 산화아연계 박막의 제조방법 및 이에 의해제조된 산화아연계 박막 |
WO2011055668A1 (en) * | 2009-11-06 | 2011-05-12 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
JP5362112B2 (ja) | 2010-06-17 | 2013-12-11 | 株式会社アルバック | スパッタ成膜装置及び防着部材 |
US20120064665A1 (en) * | 2010-09-13 | 2012-03-15 | Semiconductor Energy Laboratory Co., Ltd. | Deposition apparatus, apparatus for successive deposition, and method for manufacturing semiconductor device |
JP5886491B2 (ja) | 2010-11-12 | 2016-03-16 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
TWI416737B (zh) * | 2010-12-30 | 2013-11-21 | Au Optronics Corp | 薄膜電晶體及其製造方法 |
JP5984354B2 (ja) * | 2011-10-07 | 2016-09-06 | 住友電気工業株式会社 | 半導体素子 |
JP5795551B2 (ja) | 2012-05-14 | 2015-10-14 | 富士フイルム株式会社 | 電界効果型トランジスタの製造方法 |
JP6264248B2 (ja) * | 2014-09-26 | 2018-01-24 | 日新電機株式会社 | 成膜方法およびスパッタリング装置 |
-
2018
- 2018-06-06 TW TW107119544A patent/TWI684283B/zh active
- 2018-06-07 CN CN201880037318.3A patent/CN110709968B/zh active Active
- 2018-06-07 JP JP2019523971A patent/JP6928884B2/ja active Active
- 2018-06-07 WO PCT/JP2018/021876 patent/WO2018225822A1/ja active Application Filing
- 2018-06-07 US US16/619,943 patent/US11417752B2/en active Active
- 2018-06-07 KR KR1020197035759A patent/KR102322393B1/ko active IP Right Grant
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010226101A (ja) * | 2009-02-27 | 2010-10-07 | Semiconductor Energy Lab Co Ltd | 半導体装置及びその作製方法 |
JP2011142174A (ja) * | 2010-01-06 | 2011-07-21 | Fujifilm Corp | 成膜方法および半導体装置 |
WO2012031962A1 (en) * | 2010-09-10 | 2012-03-15 | Applied Materials, Inc. | Method and system for depositing a thin-film transistor |
JP2013211544A (ja) * | 2012-03-02 | 2013-10-10 | Semiconductor Energy Lab Co Ltd | 半導体装置及び半導体装置の作製方法、並びに酸化膜の作製方法 |
JP2015179839A (ja) * | 2014-02-28 | 2015-10-08 | 株式会社半導体エネルギー研究所 | 半導体装置、該半導体装置を有する表示装置、該表示装置を有する表示モジュール、並びに該半導体装置、該表示装置、及び該表示モジュールを有する電子機器 |
JP2016056446A (ja) * | 2014-05-02 | 2016-04-21 | 株式会社半導体エネルギー研究所 | 酸化物の作製方法 |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2020088152A (ja) * | 2018-11-26 | 2020-06-04 | 日新電機株式会社 | 薄膜トランジスタの製造方法 |
JP7247546B2 (ja) | 2018-11-26 | 2023-03-29 | 日新電機株式会社 | 薄膜トランジスタの製造方法 |
KR20220003603A (ko) | 2019-06-25 | 2022-01-10 | 닛신덴키 가부시키 가이샤 | 산화물 반도체의 가공 방법 및 박막 트랜지스터의 제조 방법 |
WO2021015149A1 (ja) * | 2019-07-19 | 2021-01-28 | 日新電機株式会社 | 薄膜トランジスタの製造方法 |
JP2021019102A (ja) * | 2019-07-19 | 2021-02-15 | 日新電機株式会社 | 薄膜トランジスタの製造方法 |
CN114127956A (zh) * | 2019-07-19 | 2022-03-01 | 日新电机株式会社 | 薄膜晶体管的制造方法 |
JP7317282B2 (ja) | 2019-07-19 | 2023-07-31 | 日新電機株式会社 | 薄膜トランジスタの製造方法 |
CN114127956B (zh) * | 2019-07-19 | 2024-04-05 | 日新电机株式会社 | 薄膜晶体管的制造方法 |
JP7483883B2 (ja) | 2019-11-15 | 2024-05-15 | ダイソン・テクノロジー・リミテッド | スパッタ堆積装置及び方法 |
Also Published As
Publication number | Publication date |
---|---|
TW201904074A (zh) | 2019-01-16 |
US20210151585A1 (en) | 2021-05-20 |
JP6928884B2 (ja) | 2021-09-01 |
KR20200003171A (ko) | 2020-01-08 |
TWI684283B (zh) | 2020-02-01 |
US11417752B2 (en) | 2022-08-16 |
JPWO2018225822A1 (ja) | 2020-05-21 |
CN110709968A (zh) | 2020-01-17 |
KR102322393B1 (ko) | 2021-11-05 |
CN110709968B (zh) | 2023-03-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2018225822A1 (ja) | 薄膜トランジスタの製造方法 | |
CN110709533B (zh) | 溅射装置 | |
WO2019181095A1 (ja) | 成膜方法、薄膜トランジスタの製造方法および薄膜トランジスタ | |
US8704267B2 (en) | Light-emitting display device | |
US10121898B2 (en) | Thin-film transistor substrate and method of manufacturing the same | |
TWI541900B (zh) | 絕緣膜及其製造方法 | |
JP6550514B2 (ja) | ディスプレイ用酸化物半導体薄膜、ディスプレイ用薄膜トランジスタ及びディスプレイ用スパッタリングターゲット | |
JP2011142174A (ja) | 成膜方法および半導体装置 | |
CN115735268A (zh) | 通过电感耦合等离子体进行溅射成膜的成膜装置 | |
WO2020116499A1 (ja) | 薄膜トランジスタ及びその製造方法 | |
TWI835033B (zh) | 氧化物半導體的成膜方法及薄膜電晶體的製造方法 | |
JP2021190590A (ja) | 酸化物半導体の成膜方法及び薄膜トランジスタの製造方法 | |
US20240088301A1 (en) | Process to reduce plasma induced damage | |
WO2020262322A1 (ja) | 酸化物半導体の加工方法及び薄膜トランジスタの製造方法 | |
JP2019165177A (ja) | 成膜方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 18813180 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 2019523971 Country of ref document: JP Kind code of ref document: A |
|
ENP | Entry into the national phase |
Ref document number: 20197035759 Country of ref document: KR Kind code of ref document: A |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 18813180 Country of ref document: EP Kind code of ref document: A1 |