WO2018120303A1 - 一种igzo薄膜晶体管的goa电路及显示装置 - Google Patents

一种igzo薄膜晶体管的goa电路及显示装置 Download PDF

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Publication number
WO2018120303A1
WO2018120303A1 PCT/CN2017/071156 CN2017071156W WO2018120303A1 WO 2018120303 A1 WO2018120303 A1 WO 2018120303A1 CN 2017071156 W CN2017071156 W CN 2017071156W WO 2018120303 A1 WO2018120303 A1 WO 2018120303A1
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Prior art keywords
thin film
film transistor
drain
gate
constant voltage
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PCT/CN2017/071156
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English (en)
French (fr)
Inventor
石龙强
陈书志
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深圳市华星光电技术有限公司
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Priority to EP17885663.9A priority Critical patent/EP3564943B1/en
Priority to JP2019528070A priority patent/JP6874261B2/ja
Priority to US15/329,251 priority patent/US10109251B2/en
Priority to KR1020197021131A priority patent/KR102323913B1/ko
Publication of WO2018120303A1 publication Critical patent/WO2018120303A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO

Definitions

  • the present invention relates to the field of liquid crystal panels, and in particular to a GOA circuit and a display device for an IGZO thin film transistor.
  • gate driver Gate Driver On
  • the Array, GOA technology prepares a display substrate, and the GOA circuit refers to a scanning line driving circuit directly prepared on an array substrate.
  • the GOA circuit includes a plurality of shift registers sequentially connected, each shift register drives a scan line, and provides an enable signal for the next stage shift register, so that the GOA circuit as a whole can realize the purpose of turning the scan lines on line by line.
  • the GOA technology not only saves cost, but also saves the binding process in the gate direction, which is extremely advantageous for improving the productivity, and improves the integration degree of the liquid crystal display panel.
  • the GOA circuit is mainly composed of a pull-up part and a pull-up control (Pull-up control). Part), transfer part, pull-down part, pull-down maintenance circuit (Pull-down Holding) Part), and the rising part responsible for the potential rise (Boost Part), the rising part is generally composed of a bootstrap capacitor.
  • the pull-up portion is mainly responsible for outputting an input clock signal (Clock) to the gate of the thin film transistor as a driving signal of the liquid crystal display.
  • the pull-up control part is mainly responsible for controlling the opening of the pull-up part, which is generally a signal transmitted by the upper-level GOA circuit.
  • the pull-down portion is mainly responsible for quickly scanning the signal (that is, the potential of the gate of the thin film transistor) after outputting the scan signal. Pull low to low.
  • the pull-down sustain circuit portion is mainly responsible for keeping the scan signal and the signal of the pull-up portion in a closed state (ie, a set negative potential).
  • the rising portion is mainly responsible for the secondary rise of the potential of the pull-up portion to ensure the normal output of the pull-up portion.
  • IGZO materials have high mobility and good device stability. These advantages can reduce the complexity of the GOA circuit. Due to the high mobility, the size of the TFT in the GOA can be made smaller than that of the a-Si, which is advantageous for the production of a narrow bezel display.
  • the stability of the device can reduce the number of power supplies and TFTs used to stabilize the performance of the TFT, thereby making relatively simple circuits and reducing power consumption.
  • Vth ie, the threshold voltage of the transistor
  • PBTS DC forward bias temperature stress test
  • Stress stress causes the threshold voltage (Vth) of IGZO thin film transistor to move very positively. This leads to circuit failure.
  • a GOA circuit of an IGZO thin film transistor comprising a plurality of cascaded GOA units, wherein N is a positive integer, and the GO stage unit of the Nth stage comprises:
  • a pull-up control unit for controlling the scan driving signal of the scanning line of the current level to be in a high state
  • a pull-up unit for pulling up the scan driving signal of the scanning line of the current level
  • a pull-down unit for pulling down the scan driving signal of the scanning line of the current level
  • a pull-down maintaining unit for generating a low-level scan driving signal of the scanning line of the current level
  • the next transmission unit is used to output the level transmission signal of the current level
  • a bootstrap capacitor for generating a low level or high level scan drive signal of the scan line of the current stage
  • a first constant voltage negative level power supply for providing a first constant voltage negative level signal
  • a second constant voltage negative level power supply for providing a second constant voltage negative level signal
  • the first constant voltage negative level power supply is respectively connected to the pull-down maintaining unit and the pull-down unit, and the second constant voltage negative level power supply is connected to the pull-down maintaining unit.
  • the potential of the second constant voltage negative level power supply output level is less than the potential of the first constant voltage negative level power supply output level.
  • the potentials of the first constant voltage negative level signal and the second constant voltage negative level signal are both smaller than a threshold potential of the IGZO thin film transistor.
  • the pull-up control unit includes a first thin film transistor, a second thin film transistor, and a third thin film transistor;
  • the source of the first thin film transistor is connected to the stage signal input terminal ST(n-4) or the turn-on signal input end of the n-4th stage, and the drain thereof is respectively connected to the second thin film transistor and the third a source of the thin film transistor is connected, and a gate thereof is connected to a gate of the third thin film transistor;
  • a drain of the second thin film transistor is connected to a scan driving signal output end of the current stage, and a gate thereof is connected to the first node;
  • the drain of the third thin film transistor is connected to the first node, and the gate input thereof is connected to the stage signal input terminal ST(n-4) or the turn-on signal input end of the n-4th stage.
  • the downlink unit includes a fourth thin film transistor, a source of the fourth thin film transistor is input to a clock signal of the current stage, a drain thereof is connected to a level signal output end of the current stage, and a gate thereof is The first node is connected.
  • the pull-up unit includes a fifth thin film transistor, a source of the fifth thin film transistor is input to a clock signal of the current stage, a drain thereof is connected to a scan driving signal output end of the current stage, and a gate thereof is The first node is connected.
  • the pull-down unit includes a sixth thin film transistor, a seventh thin film transistor, an eighth thin film transistor, a ninth thin film transistor, a tenth thin film transistor, and an eleventh thin film transistor, wherein
  • a gate of the sixth thin film transistor is connected to the first node, a drain thereof is connected to a scan driving signal output end of the current stage, and a source thereof is respectively connected to a source of the seventh thin film transistor and the eighth a drain connection of the thin film transistor;
  • a drain of the seventh thin film transistor is connected to a scan driving signal output end of the current stage, a source thereof is connected to a drain of the eighth thin film transistor, and a gate thereof is connected to a gate of the eighth thin film transistor;
  • the source of the eighth thin film transistor is connected to the first constant voltage negative level power supply, and the gate thereof is connected to the output driving end of the N+4th stage;
  • a drain of the ninth thin film transistor is connected to the first node, a source thereof is connected to a drain of the tenth thin film transistor, and a gate thereof is connected to a gate of the third thin film transistor;
  • a gate of the tenth thin film transistor is connected to a scan driving signal output end of the N+4th stage, and a source thereof is connected to the first constant voltage negative level power supply;
  • the gate of the eleventh thin film transistor is connected to the first node, the drain thereof is connected to the scan driving signal output end of the current stage, and the source thereof is connected to the drain of the tenth thin film transistor.
  • the pull-down maintaining unit includes a twelfth thin film transistor, a thirteenth thin film transistor, a fourteenth thin film transistor, a fifteenth thin film transistor, a sixteenth thin film transistor, a seventeenth thin film transistor, and an eighteenth thin film transistor ,among them,
  • the source of the twelfth thin film transistor is connected to the first constant voltage negative level power supply, the drain thereof is connected to the level signal output end of the current stage, and the gate thereof is connected to the second node;
  • the source of the thirteenth thin film transistor is connected to the first constant voltage negative level power supply, the drain thereof is connected to the level signal output end of the current stage, and the gate thereof is connected to the second node;
  • the source of the fourteenth thin film transistor is connected to the second node, and the drain thereof is connected to the constant voltage high level power input terminal or the clock signal input end of the current stage, and the gate thereof and the seventeenth portion respectively a source of the thin film transistor is connected to a drain of the sixteenth thin film transistor;
  • a drain of the fifteenth thin film transistor is connected to the second node, a source thereof is connected to a second constant voltage negative level power supply, and a gate thereof is connected to the first node;
  • a source of the sixteenth thin film transistor is connected to the second constant voltage negative level power supply, a drain thereof is connected to a source of the seventeenth thin film transistor, and a gate thereof is connected to the first node;
  • a drain of the seventeenth thin film transistor is connected to a drain of the fourteenth thin film transistor, and a gate thereof is connected to the constant voltage high level power input terminal or the clock signal input end of the current stage;
  • the eighteenth thin film transistor has a gate connected to the second node, a source connected to the first constant voltage negative level power supply, and a drain connected to the first node.
  • one end of the bootstrap capacitor is connected to the first node, and the other end is connected to the scan driving signal output end of the current stage.
  • a display device comprising a GOA circuit of an IGZO thin film transistor, the GOA circuit of the IGZO thin film transistor comprising:
  • N a positive integer
  • the GOA unit of the Nth level includes:
  • a pull-up control unit for controlling the scan driving signal of the scanning line of the current level to be in a high state
  • a pull-up unit for pulling up the scan driving signal of the scanning line of the current level
  • a pull-down unit for pulling down the scan driving signal of the scanning line of the current level
  • a pull-down maintaining unit for generating a low-level scan driving signal of the scanning line of the current level
  • the next transmission unit is used to output the level transmission signal of the current level
  • a bootstrap capacitor for generating a low level or high level scan drive signal of the scan line of the current stage
  • a first constant voltage negative level power supply for providing a first constant voltage negative level signal
  • a second constant voltage negative level power supply for providing a second constant voltage negative level signal
  • the first constant voltage negative level power supply is respectively connected to the pull-down maintaining unit and the pull-down unit, and the second constant voltage negative level power supply is connected to the pull-down maintaining unit.
  • the potential of the second constant voltage negative level power supply output level is smaller than the potential of the first constant voltage negative level power supply output level.
  • the potentials of the first constant voltage negative level signal and the second constant voltage negative level signal are both smaller than a threshold potential of the IGZO thin film transistor.
  • the pull-up control unit includes a first thin film transistor, a second thin film transistor, and a third thin film transistor;
  • the source of the first thin film transistor is connected to the stage signal input terminal ST(n-4) or the turn-on signal input end of the n-4th stage, and the drain thereof is respectively connected to the second thin film transistor and the third a source of the thin film transistor is connected, and a gate thereof is connected to a gate of the third thin film transistor;
  • a drain of the second thin film transistor is connected to a scan driving signal output end of the current stage, and a gate thereof is connected to the first node;
  • the drain of the third thin film transistor is connected to the first node, and the gate input thereof is connected to the stage signal input terminal ST(n-4) or the turn-on signal input end of the n-4th stage.
  • the downlink unit comprises a fourth thin film transistor, wherein a source of the fourth thin film transistor is input to a clock signal of the current stage, and a drain thereof is connected to a level signal output end of the current stage, and a gate and a gate thereof are connected The first node is connected.
  • the pull-up unit includes a fifth thin film transistor, a source of the fifth thin film transistor is input to a clock signal of the current stage, and a drain thereof is connected to a scan driving signal output end of the current stage, and a gate and a gate thereof are connected The first node is connected.
  • the pull-down unit includes a sixth thin film transistor, a seventh thin film transistor, an eighth thin film transistor, a ninth thin film transistor, a tenth thin film transistor, and an eleventh thin film transistor, wherein
  • a gate of the sixth thin film transistor is connected to the first node, a drain thereof is connected to a scan driving signal output end of the current stage, and a source thereof is respectively connected to a source of the seventh thin film transistor and the eighth a drain connection of the thin film transistor;
  • a drain of the seventh thin film transistor is connected to a scan driving signal output end of the current stage, a source thereof is connected to a drain of the eighth thin film transistor, and a gate thereof is connected to a gate of the eighth thin film transistor;
  • the source of the eighth thin film transistor is connected to the first constant voltage negative level power supply, and the gate thereof is connected to the output driving end of the N+4th stage;
  • a drain of the ninth thin film transistor is connected to the first node, a source thereof is connected to a drain of the tenth thin film transistor, and a gate thereof is connected to a gate of the third thin film transistor;
  • a gate of the tenth thin film transistor is connected to a scan driving signal output end of the N+4th stage, and a source thereof is connected to the first constant voltage negative level power supply;
  • the gate of the eleventh thin film transistor is connected to the first node, the drain thereof is connected to the scan driving signal output end of the current stage, and the source thereof is connected to the drain of the tenth thin film transistor.
  • the pull-down maintaining unit comprises a twelfth thin film transistor, a thirteenth thin film transistor, a fourteenth thin film transistor, a fifteenth thin film transistor, a sixteenth thin film transistor, a seventeenth thin film transistor and an eighteenth thin film. Transistor, among them,
  • the source of the twelfth thin film transistor is connected to the first constant voltage negative level power supply, the drain thereof is connected to the level signal output end of the current stage, and the gate thereof is connected to the second node;
  • the source of the thirteenth thin film transistor is connected to the first constant voltage negative level power supply, the drain thereof is connected to the level signal output end of the current stage, and the gate thereof is connected to the second node;
  • the source of the fourteenth thin film transistor is connected to the second node, and the drain thereof is connected to the constant voltage high level power input terminal or the clock signal input end of the current stage, and the gate thereof and the seventeenth portion respectively a source of the thin film transistor is connected to a drain of the sixteenth thin film transistor;
  • a drain of the fifteenth thin film transistor is connected to the second node, a source thereof is connected to a second constant voltage negative level power supply, and a gate thereof is connected to the first node;
  • a source of the sixteenth thin film transistor is connected to the second constant voltage negative level power supply, a drain thereof is connected to a source of the seventeenth thin film transistor, and a gate thereof is connected to the first node;
  • a drain of the seventeenth thin film transistor is connected to a drain of the fourteenth thin film transistor, and a gate thereof is connected to the constant voltage high level power input terminal or the clock signal input end of the current stage;
  • the eighteenth thin film transistor has a gate connected to the second node, a source connected to the first constant voltage negative level power supply, and a drain connected to the first node.
  • one end of the bootstrap capacitor is connected to the first node, and the other end is connected to a scan driving signal output end of the current stage.
  • a GOA circuit and a display device for an IGZO thin film transistor of the present invention wherein a first constant voltage negative level power supply and a second constant voltage negative level power supply are provided in a GOA circuit, and the first constant voltage negative level power supply is separately provided
  • the pull-down maintaining unit is connected to the pull-down unit, and the second constant-voltage negative-level power supply is connected to the pull-down maintaining unit, which solves the problem that the threshold voltage of the IGZO thin film transistor is easily negative, resulting in failure of the GOA circuit.
  • FIG. 1 is a schematic overall structural diagram of a GOA circuit of an IGZO thin film transistor according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram showing relationship between signal waveforms and potentials of a GOA circuit of an IGZO thin film transistor according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram showing the waveform of the GOA circuit of the IGZO thin film transistor according to the 32th stage GOA as an example.
  • IGZO Indium Gallium Zinc Oxide
  • indium gallium zinc oxide a thin film transistor technology that is coated with a layer of metal oxide on top of the TFT-LCD active layer.
  • IGZO materials have high mobility and good device stability.
  • FIG. 1 is a schematic diagram showing the overall structure of a GOA circuit of an IGZO thin film transistor according to an embodiment of the present invention.
  • the GOA circuit of an IGZO thin film transistor of the present invention includes a plurality of cascaded GOA units, wherein N is a positive integer, and the GO level unit of the Nth stage includes:
  • a pull-up control unit 100 is configured to control the scan driving signal of the scan line of the current stage to be in a high state.
  • a pull-up unit 200 is configured to pull up a scan driving signal of the scan line of the current stage.
  • a pull-down unit 500 is configured to pull down the scan driving signal of the scan line of the current stage.
  • a pull-down maintaining unit 400 is configured to generate a low-level scan driving signal of the scanning line of the current stage.
  • the next transmission unit 300 is used to output the level transmission signal of the current level.
  • a bootstrap capacitor Cb is used to generate a low level or high level scan drive signal of the scan line of the current stage.
  • the first constant voltage negative level power supply VSS1 is for providing a first constant voltage negative level signal, which is a negative DC direct current power supply.
  • the second constant voltage negative level power supply VSS2 is for providing a second constant voltage negative level signal, which is a negative DC direct current power supply.
  • the first constant voltage negative level power supply VSS1 is connected to the pull-down maintaining unit 400 and the pull-down unit 500, respectively, and the second constant voltage negative level power supply VSS2 is connected to the pull-down maintaining unit 400.
  • the potential of the output level of the second constant voltage negative level power supply VSS2 is smaller than the potential of the output level of the first constant voltage negative level power supply VSS1.
  • the potentials of the first constant voltage negative level signal and the second constant voltage negative level signal are both smaller than the threshold potential of the IGZO thin film transistor.
  • the pull-up control unit 100 includes a first thin film transistor T1, a second thin film transistor T2, and a third thin film transistor T3;
  • the source of the first thin film transistor T1 is connected to the stage signal input terminal ST(n-4) or the turn-on signal input terminal STV of the n-4th stage, and the drain thereof is respectively connected to the second thin film transistor T2 and the a source of the third thin film transistor T3 is connected, and a gate thereof is connected to a gate of the third thin film transistor T3;
  • the drain of the second thin film transistor T2 is connected to the scan drive signal output terminal G(n) of the current stage, and the gate thereof is connected to the first node Q(n);
  • the drain of the third thin film transistor T3 is connected to the first node Q(n), and the gate input thereof is input to the stage signal input terminal ST(n-4) of the n-4th stage or the input signal input terminal STV. connection.
  • the downlink unit 300 includes a fourth thin film transistor T4, and the source of the fourth thin film transistor T4 inputs a clock signal of the current stage, and the drain thereof and the level signal output terminal ST of the current stage ( n) connected, the gate of which is connected to the first node Q(n).
  • the pull-up unit 200 includes a fifth thin film transistor T5.
  • the source of the fifth thin film transistor T5 inputs a clock signal of the current stage, and the drain thereof and the scan driving signal output end G of the current stage ( n) connected, the gate of which is connected to the first node Q(n).
  • the pull-down unit 500 includes a sixth thin film transistor T6, a seventh thin film transistor T7, an eighth thin film transistor T8, a ninth thin film transistor T9, a tenth thin film transistor T10, and an eleventh thin film transistor T11, wherein ,
  • a gate of the sixth thin film transistor T6 is connected to the first node Q(n), a drain thereof is connected to a scan driving signal output terminal G(n) of the current stage, and a source thereof is respectively connected to the seventh film.
  • a source of the transistor T7 is connected to a drain of the eighth thin film transistor T8;
  • the drain of the seventh thin film transistor T7 is connected to the scan driving signal output terminal G(n) of the current stage, the source thereof is connected to the drain of the eighth thin film transistor T8, and the gate thereof and the eighth film The gate of the transistor T8 is connected;
  • the source of the eighth thin film transistor T8 is connected to the first constant voltage negative level power supply VSS1, and the gate thereof is connected to the output driving end of the N+4th stage;
  • a drain of the ninth thin film transistor T9 is connected to the first node Q(n), a source thereof is connected to a drain of the tenth thin film transistor T10, and a gate thereof is opposite to the third thin film transistor T3.
  • a gate of the tenth thin film transistor T10 is connected to a scan driving signal output end of the N+4th stage, and a source thereof is connected to the first constant voltage negative level power supply VSS1;
  • a gate of the eleventh thin film transistor T11 is connected to the first node Q(n), a drain thereof is connected to a scan driving signal output terminal G(n) of the current stage, and a source thereof and the tenth film are connected The drain of the transistor T10 is connected.
  • the pull-down maintaining unit 400 includes a twelfth thin film transistor T12, a thirteenth thin film transistor T13, a fourteenth thin film transistor T14, a fifteenth thin film transistor T15, a sixteenth thin film transistor T16, and a tenth. Seven thin film transistors T17 and eighteenth thin film transistors T18, wherein
  • the source of the twelfth thin film transistor T12 is connected to the first constant voltage negative level power supply VSS1, and the drain thereof is connected to the level signal output terminal ST(n) of the current stage, and the gate thereof and the second node P (n) connected;
  • the source of the thirteenth thin film transistor T13 is connected to the first constant voltage negative level power supply VSS1, the drain thereof is connected to the level signal output terminal ST(n) of the current stage, and the gate and the second node P are connected. (n) connected;
  • the source of the fourteenth thin film transistor T14 is connected to the second node P(n), and the drain thereof is connected to the constant voltage high level power input terminal or the clock signal input end of the current stage, and the gate thereof is respectively a source of the seventeenth thin film transistor T17 is connected to a drain of the sixteenth thin film transistor T16;
  • the drain of the fifteenth thin film transistor T15 is connected to the second node P(n), the source thereof is connected to the second constant voltage negative level power source VSS2, and the gate thereof is connected to the first node Q(n) connection;
  • a source of the sixteenth thin film transistor T16 is connected to the second constant voltage negative level power supply VSS2, a drain thereof is connected to a source of the seventeenth thin film transistor T17, and a gate thereof and the first node Q(n) connection;
  • the drain of the seventeenth thin film transistor T17 is connected to the drain of the fourteenth thin film transistor T14, and the gate thereof is connected to the constant voltage high level power input terminal or the clock signal input end of the current stage. ;
  • a gate of the eighteenth thin film transistor T18 is connected to the second node P(n), a source thereof is connected to the first constant voltage negative level power supply VSS1, and a drain thereof is connected to the first node Q ( n) Connection.
  • one end of the bootstrap capacitor Cb is connected to the first node Q(n), and the other end is connected to the scan driving signal output terminal G(n) of the current stage.
  • FIG. 2 is a schematic diagram showing the relationship between the signal waveform and the potential of the GOA circuit of an IGZO thin film transistor according to the embodiment.
  • the invention is based on the 8K4K display and introduces the patent.
  • the present invention uses eight CK (clock) signals, and the time of overlap between the CK signal and the CK signal is called CDT, and the length of overlap is 3.75us.
  • the STV of the present invention is a start pulse (start Pulse) Trigger signal, one pulse per frame.
  • the pulse width is 8*CDT, and the overlap time between STV and CK is CDT.
  • STV is a high-frequency AC signal, which appears once every frame, and CK is also a high-frequency AC signal.
  • FIG. 3 is a schematic diagram showing the waveform of the GOA circuit of the IGZO thin film transistor according to the 32th stage GOA as an example. As you can see from Figure 3:
  • the second node P (32) is low, and the thirteenth thin film transistor T13, the eighteenth thin film transistor T18, and the twelfth thin film transistor T12 are all turned off, and the low potential of the first constant voltage negative level power supply VSS1 does not affect.
  • ST (28) turns to a low potential
  • the first thin film transistor T1, and the third thin film transistor T3 are turned off.
  • CK8 is at a high potential
  • G (32) is at a high potential
  • the first node Q (32) is capacitively coupled. The effect is raised to a higher potential and the second node P (32) continues to remain low.
  • the threshold voltages of the sixth thin film transistor T6, the seventh thin film transistor T7, and the eighth thin film transistor T8 are excessively negative, the high potential of G(32) is leaked, and the G(32) waveform is pulled down at a high potential, and the waveform cannot be normally output.
  • the nine thin film transistor T9, the tenth thin film transistor T10 and the eleventh thin film transistor T11 adopt a structure composed of three thin film transistors.
  • the first thin film transistor T1, the second thin film transistor T2, and the third thin film The breakdown voltages of the transistor T3, the ninth thin film transistor T9, the tenth thin film transistor T10, and the eleventh thin film transistor T11 are much smaller than 0, which can well prevent the threshold voltage of the IGZO thin film transistor from being too negative, and ensure the G(N) waveform.
  • the normal output The normal output.
  • G(36) is at a high potential
  • the seventh thin film transistor T7, the eighth thin film transistor T8, the ninth thin film transistor T9, and the tenth thin film transistor T10 are turned on, and the first nodes Q(32), G(32) are pulled.
  • the second node P (32) is high potential
  • the ninth thin film transistor T9, the tenth thin film transistor T10 and the eleventh thin film transistor T11, the twelfth thin film transistor T12, the thirteenth thin film transistor T13, and the eighteenth thin film transistor T18 Open, the first node Q (32), G (32) remains low.
  • the pull-down maintaining unit 400 adopts CK(n) as a DC power source instead of the conventional VDD, the fourteenth thin film transistor T14 and the seventeenth thin film transistor T17 can be effectively prevented from being subjected to severe PBTS (Positive). Bias temperature stress, the effect of the test, causes the threshold voltage of the IGZO thin film transistor to move very positively, resulting in circuit failure.
  • a GOA circuit and a display device for an IGZO thin film transistor of the present invention wherein a first constant voltage negative level power supply VSS1 and a second constant voltage negative level power supply VSS2 are provided in a GOA circuit, and the first constant voltage negative level power supply VSS1 is provided Connected to the pull-down maintaining unit 400 and the pull-down unit 500, respectively, the second constant-voltage negative-level power source VSS2 is connected to the pull-down maintaining unit 400, and the first constant-voltage negative-level signal and the second The potential of the constant voltage negative level signal is smaller than the threshold potential of the IGZO thin film transistor, which solves the problem that the threshold voltage of the IGZO thin film transistor is easily negative, resulting in failure of the GOA circuit.
  • the present embodiment provides a display device including a GOA circuit of an IGZO thin film transistor according to the first embodiment.
  • the GOA circuit of the IGZO thin film transistor has been described in detail in the first embodiment, and is no longer described herein. Repeat the discussion.

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Abstract

一种IGZO薄膜晶体管的GOA电路及显示装置，该GOA电路包括多个级联的GOA单元，第N级GOA单元包括一上拉控制单元(100)、一上拉单元(200)、一下拉单元(500)、一下拉维持单元(400)、一下传单元(300)、一自举电容(Cb)、第一恒压负电平电源(VSS1)与第二恒压负电平电源(VSS2)。解决了由IGZO薄膜晶体管组成的GOA电路容易失效的问题。

Description

一种IGZO薄膜晶体管的GOA电路及显示装置 技术领域
本发明涉及液晶面板技术领域，特别涉及一种IGZO薄膜晶体管的GOA电路及显示装置。
 背景技术
目前，一般采用在阵列基板上制备栅极驱动(Gate Driver On Array，GOA)技术制备显示基板，GOA电路是指直接制备在阵列基板上的扫描线驱动电路。GOA电路包括多级依次连接的移位寄存器，每个移位寄存器驱动一条扫描线，并为下一级移位寄存器提供开启信号，从而GOA电路整体上可实现使扫描线逐行开启的目的。GOA技术相比传统工艺，不仅节省了成本，同时由于可以省去栅极方向上的绑定工艺，对提升产能极为有利，并提高了液晶显示面板的集成度。
通常，GOA电路主要由上拉部分(Pull-up part)、上拉控制部分(Pull-up control part)、下传部分(Transfer part)、下拉部分(Pull-down part)、下拉维持电路部分(Pull-down Holding part)、以及负责电位抬升的上升部分(Boost part)组成，上升部分一般由一自举电容构成。上拉部分主要负责将输入的时钟信号(Clock)输出至薄膜晶体管的栅极，作为液晶显示器的驱动信号。上拉控制部分主要负责控制上拉部分的打开，一般是由上级GOA电路传递来的信号作用。下拉部分主要负责在输出扫描信号后，快速地将扫描信号(亦即薄膜晶体管的栅极的电位) 拉低为低电平。下拉维持电路部分则主要负责将扫描信号和上拉部分的信号保持在关闭状态(即设定的负电位)。上升部分则主要负责对上拉部分的电位进行二次抬升，确保上拉部分的正常输出。IGZO材料具有较高的迁移率，和良好的器件稳定性。这些优点，可减少GOA电路的复杂程度。由于高迁移率，GOA中TFT的尺寸相对a-Si可以做小，有利于窄边框显示器的制作。器件的稳定，可以减少用来稳定TFT的性能的电源和TFT的个数，从而可以做相对简单的电路，并且降低功耗。然而，由于IGZO-TFT Vth（即晶体管的阈值电压）容易为负值，会导致GOA电路失效。另外，IGZO-TFT对DC的正向偏压温度应力测试（PBTS）非常敏感，长期的应力测试（Stress）会导致IGZO薄膜晶体管的阈值电压（Vth）正向的移动非常严重。从而导致电路失效。
 技术问题
本发明的目的在于提供一种IGZO薄膜晶体管的GOA电路及显示装置，以解决现有技术中，IGZO薄膜晶体管的阈值电压容易为负值，导致GOA电路失效的问题。
 技术解决方案
本发明的技术方案如下：
一种IGZO薄膜晶体管的GOA电路，其包括多个级联的GOA单元，设N为正整数，第N级所述GOA单元包括：
一上拉控制单元，用于控制本级扫描线的扫描驱动信号处于高电平状态；
一上拉单元，用于拉升本级扫描线的扫描驱动信号；
一下拉单元，用于拉低本级扫描线的扫描驱动信号；
一下拉维持单元，用于生成本级扫描线的低电平的扫描驱动信号；
一下传单元，用于输出本级的级传信号；
一自举电容，用于生成本级扫描线的低电平或高电平的扫描驱动信号；
第一恒压负电平电源，用于提供第一恒压负电平信号；
第二恒压负电平电源，用于提供第二恒压负电平信号；
其中，所述第一恒压负电平电源分别与所述下拉维持单元和所述下拉单元连接，所述第二恒压负电平电源与所述下拉维持单元连接。
优选地，所述第二恒压负电平电源输出电平的电位小于所述第一恒压负电平电源输出电平的电位。
优选地，所述第一恒压负电平信号与所述第二恒压负电平信号的电位均小于所述IGZO薄膜晶体管的阈值电位。
优选地，所述上拉控制单元包括第一薄膜晶体管、第二薄膜晶体管及第三薄膜晶体管；其中，
所述第一薄膜晶体管的源极与第n-4级的级传信号输入端ST（n-4）或开启信号输入端连接，其漏极分别与所述第二薄膜晶体管和所述第三薄膜晶体管的源极连接，其栅极与所述第三薄膜晶体管的栅极连接；
所述第二薄膜晶体管的的漏极与本级的扫描驱动信号输出端连接，其栅极连接第一节点；
所述第三薄膜晶体管的漏极与所述第一节点连接，其栅极输入与第n-4级的级传信号输入端ST（n-4）或开启信号输入端连接。
优选地，所述下传单元包括第四薄膜晶体管，所述第四薄膜晶体管的源极输入本级的时钟信号，其漏极与本级的级传信号输出端连接，其栅极与所述第一节点连接。
优选地，所述上拉单元包括第五薄膜晶体管，所述第五薄膜晶体管的源极输入本级的时钟信号，其漏极与本级的扫描驱动信号输出端连接，其栅极与所述第一节点连接。
优选地，所述下拉单元包括第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管与第十一薄膜晶体管，其中，
所述第六薄膜晶体管的栅极与所述第一节点连接，其漏极与本级的扫描驱动信号输出端连接，其源极分别与所述第七薄膜晶体管的源极和所述第八薄膜晶体管的漏极连接；
所述第七薄膜晶体管的漏极与本级的扫描驱动信号输出端连接，其源极与所述第八薄膜晶体管的漏极连接，其栅极与所述第八薄膜晶体管的栅极连接；
所述第八薄膜晶体管的源极与所述第一恒压负电平电源连接，其栅极与第N+4级的扫描驱动信号输出端连接；
所述第九薄膜晶体管的漏极与所述第一节点连接，其源极与所述第十薄膜晶体管的漏极连接，其栅极与所述第三薄膜晶体管的的栅极连接；
所述第十薄膜晶体管的栅极与第N+4级的扫描驱动信号输出端连接，其源极与所述第一恒压负电平电源连接；
所述第十一薄膜晶体管的栅极与所述第一节点连接，其漏极与本级的扫描驱动信号输出端连接，其源极与所述第十薄膜晶体管的漏极连接。
优选地，所述下拉维持单元包括第十二薄膜晶体管、第十三薄膜晶体管、第十四薄膜晶体管、第十五薄膜晶体管、第十六薄膜晶体管、第十七薄膜晶体管与第十八薄膜晶体管，其中，
所述第十二薄膜晶体管的源极与所述第一恒压负电平电源连接，其漏极与本级的级传信号输出端连接，其栅极与第二节点连接；
所述第十三薄膜晶体管的源极与所述第一恒压负电平电源连接，其漏极与本级的级传信号输出端连接，其栅极与第二节点连接；
所述第十四薄膜晶体管的源极与所述第二节点连接，其漏极与恒压高电平电源输入端或本级的时钟信号输入端连接，其栅极分别与所述第十七薄膜晶体管的源极和所述第十六薄膜晶体管的漏极连接；
所述第十五薄膜晶体管的漏极与所述第二节点连接，其源极与第二恒压负电平电源连接，其栅极与所述第一节点连接；
所述第十六薄膜晶体管的源极与所述第二恒压负电平电源连接，其漏极与所述第十七薄膜晶体管的源极连接，其栅极与所述第一节点连接；
所述第十七薄膜晶体管的漏极与所述第十四薄膜晶体管的漏极连接，其栅极与所述恒压高电平电源输入端或本级的所述时钟信号输入端连接；
所述第十八薄膜晶体管的栅极与所述第二节点连接，其源极与所述第一恒压负电平电源连接，其漏极与所述第一节点连接。
优选地，所述自举电容的一端连接所述第一节点，另一端连接本级的扫描驱动信号输出端。
一种显示装置，其包括一IGZO薄膜晶体管的GOA电路，该IGZO薄膜晶体管的GOA电路包括：
多个级联的GOA单元，设N为正整数，第N级所述GOA单元包括：
一上拉控制单元，用于控制本级扫描线的扫描驱动信号处于高电平状态；
一上拉单元，用于拉升本级扫描线的扫描驱动信号；
一下拉单元，用于拉低本级扫描线的扫描驱动信号；
一下拉维持单元，用于生成本级扫描线的低电平的扫描驱动信号；
一下传单元，用于输出本级的级传信号；
一自举电容，用于生成本级扫描线的低电平或高电平的扫描驱动信号；
第一恒压负电平电源，用于提供第一恒压负电平信号；
第二恒压负电平电源，用于提供第二恒压负电平信号；
其中，所述第一恒压负电平电源分别与所述下拉维持单元和所述下拉单元连接，所述第二恒压负电平电源与所述下拉维持单元连接。
优选地，其中所述第二恒压负电平电源输出电平的电位小于所述第一恒压负电平电源输出电平的电位。
优选地，其中所述第一恒压负电平信号与所述第二恒压负电平信号的电位均小于所述IGZO薄膜晶体管的阈值电位。
优选地，其中所述上拉控制单元包括第一薄膜晶体管、第二薄膜晶体管及第三薄膜晶体管；其中，
所述第一薄膜晶体管的源极与第n-4级的级传信号输入端ST（n-4）或开启信号输入端连接，其漏极分别与所述第二薄膜晶体管和所述第三薄膜晶体管的源极连接，其栅极与所述第三薄膜晶体管的栅极连接；
所述第二薄膜晶体管的的漏极与本级的扫描驱动信号输出端连接，其栅极连接第一节点；
所述第三薄膜晶体管的漏极与所述第一节点连接，其栅极输入与第n-4级的级传信号输入端ST（n-4）或开启信号输入端连接。
优选地，其中所述下传单元包括第四薄膜晶体管，所述第四薄膜晶体管的源极输入本级的时钟信号，其漏极与本级的级传信号输出端连接，其栅极与所述第一节点连接。
优选地，其中所述上拉单元包括第五薄膜晶体管，所述第五薄膜晶体管的源极输入本级的时钟信号，其漏极与本级的扫描驱动信号输出端连接，其栅极与所述第一节点连接。
优选地，其中所述下拉单元包括第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管与第十一薄膜晶体管，其中，
所述第六薄膜晶体管的栅极与所述第一节点连接，其漏极与本级的扫描驱动信号输出端连接，其源极分别与所述第七薄膜晶体管的源极和所述第八薄膜晶体管的漏极连接；
所述第七薄膜晶体管的漏极与本级的扫描驱动信号输出端连接，其源极与所述第八薄膜晶体管的漏极连接，其栅极与所述第八薄膜晶体管的栅极连接；
所述第八薄膜晶体管的源极与所述第一恒压负电平电源连接，其栅极与第N+4级的扫描驱动信号输出端连接；
所述第九薄膜晶体管的漏极与所述第一节点连接，其源极与所述第十薄膜晶体管的漏极连接，其栅极与所述第三薄膜晶体管的的栅极连接；
所述第十薄膜晶体管的栅极与第N+4级的扫描驱动信号输出端连接，其源极与所述第一恒压负电平电源连接；
所述第十一薄膜晶体管的栅极与所述第一节点连接，其漏极与本级的扫描驱动信号输出端连接，其源极与所述第十薄膜晶体管的漏极连接。
优选地，其中所述下拉维持单元包括第十二薄膜晶体管、第十三薄膜晶体管、第十四薄膜晶体管、第十五薄膜晶体管、第十六薄膜晶体管、第十七薄膜晶体管与第十八薄膜晶体管，其中，
所述第十二薄膜晶体管的源极与所述第一恒压负电平电源连接，其漏极与本级的级传信号输出端连接，其栅极与第二节点连接；
所述第十三薄膜晶体管的源极与所述第一恒压负电平电源连接，其漏极与本级的级传信号输出端连接，其栅极与第二节点连接；
所述第十四薄膜晶体管的源极与所述第二节点连接，其漏极与恒压高电平电源输入端或本级的时钟信号输入端连接，其栅极分别与所述第十七薄膜晶体管的源极和所述第十六薄膜晶体管的漏极连接；
所述第十五薄膜晶体管的漏极与所述第二节点连接，其源极与第二恒压负电平电源连接，其栅极与所述第一节点连接；
所述第十六薄膜晶体管的源极与所述第二恒压负电平电源连接，其漏极与所述第十七薄膜晶体管的源极连接，其栅极与所述第一节点连接；
所述第十七薄膜晶体管的漏极与所述第十四薄膜晶体管的漏极连接，其栅极与所述恒压高电平电源输入端或本级的所述时钟信号输入端连接；
所述第十八薄膜晶体管的栅极与所述第二节点连接，其源极与所述第一恒压负电平电源连接，其漏极与所述第一节点连接。
优选地，其中所述自举电容的一端连接所述第一节点，另一端连接本级的扫描驱动信号输出端。
 有益效果
本发明的一种IGZO薄膜晶体管的GOA电路及显示装置，通过在GOA电路设置第一恒压负电平电源和第二恒压负电平电源，并使所述第一恒压负电平电源分别与所述下拉维持单元和所述下拉单元连接，所述第二恒压负电平电源与所述下拉维持单元连接，解决了IGZO薄膜晶体管的阈值电压容易为负值，导致GOA电路失效的问题。
 附图说明
图1为本发明实施例的一种IGZO薄膜晶体管的GOA电路的整体结构示意图；
图2为本发明实施例的一种IGZO薄膜晶体管的GOA电路的信号波形和电位的关系示意图；
图3为本发明实施例的一种IGZO薄膜晶体管的GOA电路的以第32级GOA为例说明工作原理的波形示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。
实施例一
IGZO(Indium Gallium Zinc Oxide)为氧化铟镓锌的缩写，它是一种薄膜电晶体技术，在TFT-LCD主动层之上打上的一层金属氧化物。IGZO材料具有较高的迁移率，和良好的器件稳定性。
请参考图1，图1为本实施例的一种IGZO薄膜晶体管的GOA电路的整体结构示意图。从图1可以看到，本发明的一种IGZO薄膜晶体管的GOA电路，包括多个级联的GOA单元，设N为正整数，第N级所述GOA单元包括：
一上拉控制单元100，用于控制本级扫描线的扫描驱动信号处于高电平状态。
一上拉单元200，用于拉升本级扫描线的扫描驱动信号。
一下拉单元500，用于拉低本级扫描线的扫描驱动信号。
一下拉维持单元400，用于生成本级扫描线的低电平的扫描驱动信号。
一下传单元300，用于输出本级的级传信号。
一自举电容Cb，用于生成本级扫描线的低电平或高电平的扫描驱动信号。
第一恒压负电平电源VSS1，用于提供第一恒压负电平信号，其为负的DC直流电源。
第二恒压负电平电源VSS2，用于提供第二恒压负电平信号，其为负的DC直流电源。
其中，所述第一恒压负电平电源VSS1分别与所述下拉维持单元400和所述下拉单元500连接，所述第二恒压负电平电源VSS2与所述下拉维持单元400连接。
在本实施例中，所述第二恒压负电平电源VSS2输出电平的电位小于所述第一恒压负电平电源VSS1输出电平的电位。
在本实施例中，所述第一恒压负电平信号与所述第二恒压负电平信号的电位均小于所述IGZO薄膜晶体管的阈值电位。
在本实施例中，所述上拉控制单元100包括第一薄膜晶体管T1、第二薄膜晶体管T2及第三薄膜晶体管T3；其中，
所述第一薄膜晶体管T1的源极与第n-4级的级传信号输入端ST（n-4）或开启信号输入端STV连接，其漏极分别与所述第二薄膜晶体管T2和所述第三薄膜晶体管T3的源极连接，其栅极与所述第三薄膜晶体管T3的栅极连接；
所述第二薄膜晶体管T2的的漏极与本级的扫描驱动信号输出端G（n）连接，其栅极连接第一节点Q（n）；
所述第三薄膜晶体管T3的漏极与所述第一节点Q（n）连接，其栅极输入与第n-4级的级传信号输入端ST（n-4）或开启信号输入端STV连接。
在本实施例中，所述下传单元300包括第四薄膜晶体管T4，所述第四薄膜晶体管T4的源极输入本级的时钟信号，其漏极与本级的级传信号输出端ST（n）连接，其栅极与所述第一节点Q（n）连接。
在本实施例中，所述上拉单元200包括第五薄膜晶体管T5，所述第五薄膜晶体管T5的源极输入本级的时钟信号，其漏极与本级的扫描驱动信号输出端G（n）连接，其栅极与所述第一节点Q（n）连接。
在本实施例中，所述下拉单元500包括第六薄膜晶体管T6、第七薄膜晶体管T7、第八薄膜晶体管T8、第九薄膜晶体管T9、第十薄膜晶体管T10与第十一薄膜晶体管T11，其中，
所述第六薄膜晶体管T6的栅极与所述第一节点Q（n）连接，其漏极与本级的扫描驱动信号输出端G（n）连接，其源极分别与所述第七薄膜晶体管T7的源极和所述第八薄膜晶体管T8的漏极连接；
所述第七薄膜晶体管T7的漏极与本级的扫描驱动信号输出端G（n）连接，其源极与所述第八薄膜晶体管T8的漏极连接，其栅极与所述第八薄膜晶体管T8的栅极连接；
所述第八薄膜晶体管T8的源极与所述第一恒压负电平电源VSS1连接，其栅极与第N+4级的扫描驱动信号输出端连接；
所述第九薄膜晶体管T9的漏极与所述第一节点Q（n）连接，其源极与所述第十薄膜晶体管T10的漏极连接，其栅极与所述第三薄膜晶体管T3的的栅极连接；
所述第十薄膜晶体管T10的栅极与第N+4级的扫描驱动信号输出端连接，其源极与所述第一恒压负电平电源VSS1连接；
所述第十一薄膜晶体管T11的栅极与所述第一节点Q（n）连接，其漏极与本级的扫描驱动信号输出端G（n）连接，其源极与所述第十薄膜晶体管T10的漏极连接。
在本实施例中，所述下拉维持单元400包括第十二薄膜晶体管T12、第十三薄膜晶体管T13、第十四薄膜晶体管T14、第十五薄膜晶体管T15、第十六薄膜晶体管T16、第十七薄膜晶体管T17与第十八薄膜晶体管T18，其中，
所述第十二薄膜晶体管T12的源极与所述第一恒压负电平电源VSS1连接，其漏极与本级的级传信号输出端ST（n）连接，其栅极与第二节点P（n）连接；
所述第十三薄膜晶体管T13的源极与所述第一恒压负电平电源VSS1连接，其漏极与本级的级传信号输出端ST（n）连接，其栅极与第二节点P（n）连接；
所述第十四薄膜晶体管T14的源极与所述第二节点P（n）连接，其漏极与恒压高电平电源输入端或本级的时钟信号输入端连接，其栅极分别与所述第十七薄膜晶体管T17的源极和所述第十六薄膜晶体管T16的漏极连接；
所述第十五薄膜晶体管T15的漏极与所述第二节点P（n）连接，其源极与第二恒压负电平电源VSS2连接，其栅极与所述第一节点Q（n）连接；
所述第十六薄膜晶体管T16的源极与所述第二恒压负电平电源VSS2连接，其漏极与所述第十七薄膜晶体管T17的源极连接，其栅极与所述第一节点Q（n）连接；
所述第十七薄膜晶体管T17的漏极与所述第十四薄膜晶体管T14的漏极连接，其栅极与所述恒压高电平电源输入端或本级的所述时钟信号输入端连接；
所述第十八薄膜晶体管T18的栅极与所述第二节点P（n）连接，其源极与所述第一恒压负电平电源VSS1连接，其漏极与所述第一节点Q（n）连接。
在本实施例中，所述自举电容Cb的一端连接所述第一节点Q（n），另一端连接本级的扫描驱动信号输出端G（n）。
请参考图2，图2为本实施例的一种IGZO薄膜晶体管的GOA电路的信号波形和电位的关系示意图。本发明以8K4K显示为基础，进行专利介绍。本发明采用8个CK（时钟）信号，CK信号和CK信号之间的重叠的时间取名叫做CDT,重叠的时间长度为3.75us。本发明的STV是开始脉冲（start pulse）触发信号，每一帧有一个脉冲。脉宽为8*CDT,STV和CK之间的重叠时间为CDT。
STV为高频交流信号，每一帧出现一次，CK也为高频交流信号。ST(N-4)连接前面第四级的级传输出信号，例如，当前级为第10级，则ST(N)=ST(10),ST(N-4)=ST(6)，其中，前四级的第一薄膜晶体管T1和第二薄膜晶体管T2，跟STV相连。
下面对本发明的工作原理进行说明。
请参考图3，图3为本实施例的一种IGZO薄膜晶体管的GOA电路的以第32级GOA为例说明工作原理的波形示意图。从图3可以看到：
当G(N)=G(32)时，ST(N-4)=ST(28)，G(32)由CK8控制，当ST(28)为高电位的时候，第一薄膜晶体管T1，第三薄膜晶体管T3打开，ST(28)高电位传入到第一节点Q(32)，Q点为高电位。同时,第五薄膜晶体管T5打开，此时，CK8是低电位，所以G(32)为低电位。同时，第二节点P（32）为低电位，第十三薄膜晶体管T13，第十八薄膜晶体管T18,第十二薄膜晶体管T12均关闭，第一恒压负电平电源VSS1的低电位不会影响第一节点G(N)的电位；
接着，ST(28)转为低电位，第一薄膜晶体管T1，第三薄膜晶体管T3关闭，此时，CK8为高电位，G(32)输出高电位,第一节点Q(32)受到电容耦合效应，被抬升到更高的电位，第二节点P(32)继续保持低电位。
需要说明的是，此时，一般的GOA电路，如果第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第九薄膜晶体管T9、第十薄膜晶体管T10和第十一薄膜晶体管T11的阈值电压过负，第一节点Q(32)的高电位会漏掉，第五薄膜晶体管T5关闭，CK高电位输入不到G(32)，导致G(32)失效。或者第六薄膜晶体管T6、第七薄膜晶体管T7和第八薄膜晶体管T8的阈值电压过负，G(32)的高电位被漏电，G(32)波形高电位拉下来，波形不能正常输出。本发明的上拉控制单元100的第一薄膜晶体管T1、第二薄膜晶体管T2和第三薄膜晶体管T3，下拉单元500的第六薄膜晶体管T6、第七薄膜晶体管T7、第八薄膜晶体管T8、第九薄膜晶体管T9、第十薄膜晶体管T10和第十一薄膜晶体管T11，采用了三颗薄膜晶体管组成的结构，当这个工作时间段时，第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第九薄膜晶体管T9、第十薄膜晶体管T10和第十一薄膜晶体管T11的击穿电压远远小于0，能够很好的防止IGZO薄膜晶体管的阈值电压太负,保证G(N)波形的正常输出。
再接着，G(36)为高电位，第七薄膜晶体管T7、第八薄膜晶体管T8、第九薄膜晶体管T9和第十薄膜晶体管T10打开，第一节点Q(32)，G(32)被拉到低电位。第二节点P(32)为高电位，第九薄膜晶体管T9、第十薄膜晶体管T10和第十一薄膜晶体管T11、第十二薄膜晶体管T12，第十三薄膜晶体管T13,第十八薄膜晶体管T18打开，第一节点Q(32)，G(32)保持低电位。
另外，当下拉维持单元400采用CK(n)为取代传统的VDD的直流电源，可以有效避免第十四薄膜晶体管T14和第十七薄膜晶体管T17受到严重的PBTS（Positive bias temperature stress,正向偏压温度应力）测试影响，导致IGZO薄膜晶体管的阈值电压正向移动非常严重，从而导致电路失效。
本发明的一种IGZO薄膜晶体管的GOA电路及显示装置，通过在GOA电路设置第一恒压负电平电源VSS1和第二恒压负电平电源VSS2，并使所述第一恒压负电平电源VSS1分别与所述下拉维持单元400和所述下拉单元500连接，所述第二恒压负电平电源VSS2与所述下拉维持单元400连接，并且所述第一恒压负电平信号与所述第二恒压负电平信号的电位均小于所述IGZO薄膜晶体管的阈值电位，解决了IGZO薄膜晶体管的阈值电压容易为负值，导致GOA电路失效的问题。
实施例二
本实施例提供一种显示装置，该显示装置包括一实施例一所述的IGZO薄膜晶体管的GOA电路，该IGZO薄膜晶体管的GOA电路已经在实施例一中进行了详细的说明，在此不再重复论述。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (18)

  1. 一种IGZO薄膜晶体管的GOA电路，其包括多个级联的GOA单元，设N为正整数，第N级所述GOA单元包括：
    一上拉控制单元，用于控制本级扫描线的扫描驱动信号处于高电平状态；
    一上拉单元，用于拉升本级扫描线的扫描驱动信号；
    一下拉单元，用于拉低本级扫描线的扫描驱动信号；
    一下拉维持单元，用于生成本级扫描线的低电平的扫描驱动信号；
    一下传单元，用于输出本级的级传信号；
    一自举电容，用于生成本级扫描线的低电平或高电平的扫描驱动信号；
    第一恒压负电平电源，用于提供第一恒压负电平信号；
    第二恒压负电平电源，用于提供第二恒压负电平信号；
    其中，所述第一恒压负电平电源分别与所述下拉维持单元和所述下拉单元连接，所述第二恒压负电平电源与所述下拉维持单元连接。
  2. 根据权利要求1所述的IGZO薄膜晶体管的GOA电路，其中所述第二恒压负电平电源输出电平的电位小于所述第一恒压负电平电源输出电平的电位。
  3. 根据权利要求1所述的IGZO薄膜晶体管的GOA电路，其中所述第一恒压负电平信号与所述第二恒压负电平信号的电位均小于所述IGZO薄膜晶体管的阈值电位。
  4. 根据权利要求1所述的IGZO薄膜晶体管的GOA电路，其中所述上拉控制单元包括第一薄膜晶体管、第二薄膜晶体管及第三薄膜晶体管；其中，
    所述第一薄膜晶体管的源极与第n-4级的级传信号输入端ST（n-4）或开启信号输入端连接，其漏极分别与所述第二薄膜晶体管和所述第三薄膜晶体管的源极连接，其栅极与所述第三薄膜晶体管的栅极连接；
    所述第二薄膜晶体管的的漏极与本级的扫描驱动信号输出端连接，其栅极连接第一节点；
    所述第三薄膜晶体管的漏极与所述第一节点连接，其栅极输入与第n-4级的级传信号输入端ST（n-4）或开启信号输入端连接。
  5. 根据权利要求4所述的IGZO薄膜晶体管的GOA电路，其中所述下传单元包括第四薄膜晶体管，所述第四薄膜晶体管的源极输入本级的时钟信号，其漏极与本级的级传信号输出端连接，其栅极与所述第一节点连接。
  6. 根据权利要求4所述的IGZO薄膜晶体管的GOA电路，其中所述上拉单元包括第五薄膜晶体管，所述第五薄膜晶体管的源极输入本级的时钟信号，其漏极与本级的扫描驱动信号输出端连接，其栅极与所述第一节点连接。
  7. 根据权利要求4所述的IGZO薄膜晶体管的GOA电路，其中所述下拉单元包括第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管与第十一薄膜晶体管，其中，
    所述第六薄膜晶体管的栅极与所述第一节点连接，其漏极与本级的扫描驱动信号输出端连接，其源极分别与所述第七薄膜晶体管的源极和所述第八薄膜晶体管的漏极连接；
    所述第七薄膜晶体管的漏极与本级的扫描驱动信号输出端连接，其源极与所述第八薄膜晶体管的漏极连接，其栅极与所述第八薄膜晶体管的栅极连接；
    所述第八薄膜晶体管的源极与所述第一恒压负电平电源连接，其栅极与第N+4级的扫描驱动信号输出端连接；
    所述第九薄膜晶体管的漏极与所述第一节点连接，其源极与所述第十薄膜晶体管的漏极连接，其栅极与所述第三薄膜晶体管的的栅极连接；
    所述第十薄膜晶体管的栅极与第N+4级的扫描驱动信号输出端连接，其源极与所述第一恒压负电平电源连接；
    所述第十一薄膜晶体管的栅极与所述第一节点连接，其漏极与本级的扫描驱动信号输出端连接，其源极与所述第十薄膜晶体管的漏极连接。
  8. 根据权利要求4所述的IGZO薄膜晶体管的GOA电路，其中所述下拉维持单元包括第十二薄膜晶体管、第十三薄膜晶体管、第十四薄膜晶体管、第十五薄膜晶体管、第十六薄膜晶体管、第十七薄膜晶体管与第十八薄膜晶体管，其中，
    所述第十二薄膜晶体管的源极与所述第一恒压负电平电源连接，其漏极与本级的级传信号输出端连接，其栅极与第二节点连接；
    所述第十三薄膜晶体管的源极与所述第一恒压负电平电源连接，其漏极与本级的级传信号输出端连接，其栅极与第二节点连接；
    所述第十四薄膜晶体管的源极与所述第二节点连接，其漏极与恒压高电平电源输入端或本级的时钟信号输入端连接，其栅极分别与所述第十七薄膜晶体管的源极和所述第十六薄膜晶体管的漏极连接；
    所述第十五薄膜晶体管的漏极与所述第二节点连接，其源极与第二恒压负电平电源连接，其栅极与所述第一节点连接；
    所述第十六薄膜晶体管的源极与所述第二恒压负电平电源连接，其漏极与所述第十七薄膜晶体管的源极连接，其栅极与所述第一节点连接；
    所述第十七薄膜晶体管的漏极与所述第十四薄膜晶体管的漏极连接，其栅极与所述恒压高电平电源输入端或本级的所述时钟信号输入端连接；
    所述第十八薄膜晶体管的栅极与所述第二节点连接，其源极与所述第一恒压负电平电源连接，其漏极与所述第一节点连接。
  9. 根据权利要求4所述的IGZO薄膜晶体管的GOA电路，其中所述自举电容的一端连接所述第一节点，另一端连接本级的扫描驱动信号输出端。
  10. 一种显示装置，其包括一IGZO薄膜晶体管的GOA电路，该IGZO薄膜晶体管的GOA电路包括：
    多个级联的GOA单元，设N为正整数，第N级所述GOA单元包括：
    一上拉控制单元，用于控制本级扫描线的扫描驱动信号处于高电平状态；
    一上拉单元，用于拉升本级扫描线的扫描驱动信号；
    一下拉单元，用于拉低本级扫描线的扫描驱动信号；
    一下拉维持单元，用于生成本级扫描线的低电平的扫描驱动信号；
    一下传单元，用于输出本级的级传信号；
    一自举电容，用于生成本级扫描线的低电平或高电平的扫描驱动信号；
    第一恒压负电平电源，用于提供第一恒压负电平信号；
    第二恒压负电平电源，用于提供第二恒压负电平信号；
    其中，所述第一恒压负电平电源分别与所述下拉维持单元和所述下拉单元连接，所述第二恒压负电平电源与所述下拉维持单元连接。
  11. 根据权利要求10所述的显示装置，其中所述第二恒压负电平电源输出电平的电位小于所述第一恒压负电平电源输出电平的电位。
  12. 根据权利要求10所述的显示装置，其中所述第一恒压负电平信号与所述第二恒压负电平信号的电位均小于所述IGZO薄膜晶体管的阈值电位。
  13. 根据权利要求10所述的显示装置，其中所述上拉控制单元包括第一薄膜晶体管、第二薄膜晶体管及第三薄膜晶体管；其中，
    所述第一薄膜晶体管的源极与第n-4级的级传信号输入端ST（n-4）或开启信号输入端连接，其漏极分别与所述第二薄膜晶体管和所述第三薄膜晶体管的源极连接，其栅极与所述第三薄膜晶体管的栅极连接；
    所述第二薄膜晶体管的的漏极与本级的扫描驱动信号输出端连接，其栅极连接第一节点；
    所述第三薄膜晶体管的漏极与所述第一节点连接，其栅极输入与第n-4级的级传信号输入端ST（n-4）或开启信号输入端连接。
  14. 根据权利要求13所述的显示装置，其中所述下传单元包括第四薄膜晶体管，所述第四薄膜晶体管的源极输入本级的时钟信号，其漏极与本级的级传信号输出端连接，其栅极与所述第一节点连接。
  15. 根据权利要求13所述的显示装置，其中所述上拉单元包括第五薄膜晶体管，所述第五薄膜晶体管的源极输入本级的时钟信号，其漏极与本级的扫描驱动信号输出端连接，其栅极与所述第一节点连接。
  16. 根据权利要求13所述的显示装置，其中所述下拉单元包括第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管与第十一薄膜晶体管，其中，
    所述第六薄膜晶体管的栅极与所述第一节点连接，其漏极与本级的扫描驱动信号输出端连接，其源极分别与所述第七薄膜晶体管的源极和所述第八薄膜晶体管的漏极连接；
    所述第七薄膜晶体管的漏极与本级的扫描驱动信号输出端连接，其源极与所述第八薄膜晶体管的漏极连接，其栅极与所述第八薄膜晶体管的栅极连接；
    所述第八薄膜晶体管的源极与所述第一恒压负电平电源连接，其栅极与第N+4级的扫描驱动信号输出端连接；
    所述第九薄膜晶体管的漏极与所述第一节点连接，其源极与所述第十薄膜晶体管的漏极连接，其栅极与所述第三薄膜晶体管的的栅极连接；
    所述第十薄膜晶体管的栅极与第N+4级的扫描驱动信号输出端连接，其源极与所述第一恒压负电平电源连接；
    所述第十一薄膜晶体管的栅极与所述第一节点连接，其漏极与本级的扫描驱动信号输出端连接，其源极与所述第十薄膜晶体管的漏极连接。
  17. 根据权利要求13所述的显示装置，其中所述下拉维持单元包括第十二薄膜晶体管、第十三薄膜晶体管、第十四薄膜晶体管、第十五薄膜晶体管、第十六薄膜晶体管、第十七薄膜晶体管与第十八薄膜晶体管，其中，
    所述第十二薄膜晶体管的源极与所述第一恒压负电平电源连接，其漏极与本级的级传信号输出端连接，其栅极与第二节点连接；
    所述第十三薄膜晶体管的源极与所述第一恒压负电平电源连接，其漏极与本级的级传信号输出端连接，其栅极与第二节点连接；
    所述第十四薄膜晶体管的源极与所述第二节点连接，其漏极与恒压高电平电源输入端或本级的时钟信号输入端连接，其栅极分别与所述第十七薄膜晶体管的源极和所述第十六薄膜晶体管的漏极连接；
    所述第十五薄膜晶体管的漏极与所述第二节点连接，其源极与第二恒压负电平电源连接，其栅极与所述第一节点连接；
    所述第十六薄膜晶体管的源极与所述第二恒压负电平电源连接，其漏极与所述第十七薄膜晶体管的源极连接，其栅极与所述第一节点连接；
    所述第十七薄膜晶体管的漏极与所述第十四薄膜晶体管的漏极连接，其栅极与所述恒压高电平电源输入端或本级的所述时钟信号输入端连接；
    所述第十八薄膜晶体管的栅极与所述第二节点连接，其源极与所述第一恒压负电平电源连接，其漏极与所述第一节点连接。
  18. 根据权利要求13所述的显示装置，其中所述自举电容的一端连接所述第一节点，另一端连接本级的扫描驱动信号输出端。
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