WO2017000359A1 - 一种扫描驱动电路 - Google Patents

一种扫描驱动电路 Download PDF

Info

Publication number
WO2017000359A1
WO2017000359A1 PCT/CN2015/086485 CN2015086485W WO2017000359A1 WO 2017000359 A1 WO2017000359 A1 WO 2017000359A1 CN 2015086485 W CN2015086485 W CN 2015086485W WO 2017000359 A1 WO2017000359 A1 WO 2017000359A1
Authority
WO
WIPO (PCT)
Prior art keywords
switch tube
signal
control
output
output end
Prior art date
Application number
PCT/CN2015/086485
Other languages
English (en)
French (fr)
Inventor
赵莽
田勇
易士娟
Original Assignee
武汉华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US14/779,016 priority Critical patent/US9786240B2/en
Publication of WO2017000359A1 publication Critical patent/WO2017000359A1/zh

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present invention relates to the field of display driving, and more particularly to a scan driving circuit.
  • GOA Gate Driver On Array
  • the existing scan driving circuit needs to be driven by using the clock signal CK and the clock signal XCK, wherein the clock signal CK and the clock signal XCK are mutually inverted signals. Therefore, the existing scan driving circuit needs to invert the clock signal CK of each of the cascaded scan driving circuits to obtain the clock signal XCK, resulting in a large dynamic power consumption of the entire scan driving circuit.
  • An embodiment of the present invention provides a scan driving circuit for driving a cascaded scan line, which includes:
  • An input control module configured to input a first clock signal of the current stage and a cascade signal of the previous stage, and generate a control signal according to the first clock signal of the current stage and the cascaded signal of the previous stage;
  • a latching module configured to perform a latching operation on the control signal
  • a driving signal generating module configured to generate a driving signal according to the control signal and the second clock signal of the current stage
  • An output control module configured to output a scan signal of the current stage and a cascade signal of the current stage according to the driving signal
  • Constant voltage low level source for providing low level voltage
  • the cascading signal includes a first cascading signal and a second cascading signal, and the first cascading signal and the second cascading signal are opposite in phase;
  • the input control module includes a first switch tube, a second switch tube, a third switch tube, and a fourth switch tube;
  • the control end of the first switch tube inputs the first cascade signal of the upper stage, the input end of the first switch tube is connected to the constant voltage high level source, and the output of the first switch tube The end is connected to the input end of the second switch tube;
  • the control end of the second switch tube inputs the first clock signal of the current stage, and the output end of the second switch tube is respectively connected to the input end of the third switch tube and the control signal output end;
  • the control end of the third switch tube inputs the first clock signal of the current stage, and the output end of the third switch tube is connected to the output end of the fourth switch tube;
  • the control end of the fourth switch tube inputs the second cascade signal of the upper stage, and the input end of the fourth switch tube is connected to the constant voltage low level source;
  • the latch module includes a fifth switch tube, a sixth switch tube, a seventh switch tube, and an eighth switch tube;
  • An input end of the fifth switch tube is connected to the constant voltage high level source, and an output end of the fifth switch tube is connected to the control signal output end;
  • a control end of the sixth switch tube is connected to a control end of the fifth switch tube, an input end of the sixth switch tube is connected to the constant voltage low level source, and an output end of the sixth switch tube Connected to the output of the control signal;
  • a control end of the seventh switch tube is connected to the control signal output end, an input end of the seventh switch tube is connected to the constant voltage high level source, and an output end of the seventh switch tube is Connecting the control end of the fifth switch tube;
  • a control end of the eighth switch tube is connected to the control signal output end, an input end of the eighth switch tube is connected to the constant voltage low level source, and an output end of the eighth switch tube is Connecting the control end of the fifth switch tube;
  • the fifth switch tube and the seventh switch tube are PMOS tubes, and the sixth switch tube and the eighth switch tube are NMOS tubes.
  • the first cascade signal of the upper stage input by the scan driving circuit of the first stage is an enable signal
  • the previous one of the scan drive circuit inputs of the first stage is
  • the second cascaded signal of the stage is an inverted signal of the enable signal
  • the driving signal generating module includes a ninth switch tube, a tenth switch tube, an eleventh switch tube, and a twelfth switch tube;
  • a control end of the ninth switch tube is connected to an output end of the latch module, an input end of the ninth switch tube is connected to the constant voltage high level source, and an output end of the ninth switch tube is The output of the driving signal generating module is connected;
  • the control end of the tenth switch tube inputs a second clock signal of the current stage, the input end of the tenth switch tube is connected to the constant voltage high level source, and the output end of the tenth switch tube is The output of the driving signal generating module is connected;
  • a control end of the eleventh switch tube is connected to an output end of the latch module, and an input end of the eleventh switch tube is connected to an output end of the twelfth switch tube, the eleventh switch An output end of the tube is connected to an output end of the driving signal generating module;
  • the control end of the twelfth switch tube inputs a second clock signal of the current stage, and the input end of the twelfth switch tube is connected to the constant voltage low level source;
  • the ninth switch tube and the tenth switch tube are PMOS tubes, and the eleventh switch tube and the twelfth switch tube are NMOS tubes.
  • the output end of the driving signal generating module outputs a driving signal of the current stage, and the driving signal is also the second cascade signal of the current stage.
  • the output control module includes a thirteenth switch tube, a fourteenth switch tube, a fifteenth switch tube, a sixteenth switch tube, a seventeenth switch tube, and an eighteenth turning tube;
  • a control end of the thirteenth switch tube is connected to an output end of the driving signal generating module, and an input end of the thirteenth switch tube is connected to the constant voltage high level source, the thirteenth switch tube
  • the output ends are respectively connected to the control end of the fifteenth switch tube and the control end of the sixteenth switch tube;
  • a control end of the fourteenth switch tube is connected to an output end of the driving signal generating module, and an input end of the fourteenth switch tube is connected to the constant voltage low level source, the fourteenth switch tube
  • the output ends are respectively connected to the control end of the fifteen switch tube and the control end of the sixteenth switch tube;
  • An input end of the fifteenth switch tube is connected to the constant voltage high level source, and an output end of the fifteenth switch tube is respectively connected to a control end of the seventeenth switch tube and the eighteenth switch The control end of the tube is connected;
  • the input end of the sixteenth switch tube is connected to the constant voltage low level source, and the output end of the sixteenth switch tube and the control end of the seventeenth switch tube and the eighteenth switch respectively The control end of the tube is connected;
  • An input end of the seventeenth switch tube is connected to the constant voltage high level source, and an output end of the seventeenth switch tube is connected to an output end of the output control module;
  • An input end of the eighteenth switch tube is connected to the constant voltage low level source, and an output end of the eighteenth switch tube is connected to an output end of the output control module;
  • the thirteenth switch tube, the fifteenth switch tube, and the seventeenth switch tube are PMOS tubes, the fourteenth switch tube, the sixteenth switch tube, and the eighteenth switch
  • the tube is an NMOS tube.
  • the output end of the thirteenth switch tube outputs the first cascade signal of the current stage.
  • the first switching transistor, the second switching transistor, the third switching transistor, and the fourth switching transistor are all NMOS transistors or PMOS transistors.
  • the first switching transistor and the fourth switching transistor are NMOS transistors, the second switching transistor and the PMOS transistor of the third switching transistor.
  • the first switching transistor and the fourth switching transistor are PMOS transistors
  • the second switching transistor and the third switching transistor are NMOS transistors.
  • An embodiment of the present invention provides a scan driving circuit for driving a cascaded scan line, which includes:
  • An input control module configured to input a first clock signal of the current stage and a cascade signal of the previous stage, and generate a control signal according to the first clock signal of the current stage and the cascaded signal of the previous stage;
  • a latching module configured to perform a latching operation on the control signal
  • a driving signal generating module configured to generate a driving signal according to the control signal and the second clock signal of the current stage
  • An output control module configured to output a scan signal of the current stage and a cascade signal of the current stage according to the driving signal
  • a constant voltage low level source that provides a low level voltage.
  • the cascaded signal includes a first concatenated signal and a second concatenated signal, and the first concatenated signal and the second concatenated signal have opposite phases;
  • the input control module includes a first switch tube, a second switch tube, a third switch tube, and a fourth switch tube;
  • the control end of the first switch tube inputs the first cascade signal of the upper stage, the input end of the first switch tube is connected to the constant voltage high level source, and the output of the first switch tube The end is connected to the input end of the second switch tube;
  • the control end of the second switch tube inputs the first clock signal of the current stage, and the output end of the second switch tube is respectively connected to the input end of the third switch tube and the control signal output end;
  • the control end of the third switch tube inputs the first clock signal of the current stage, and the output end of the third switch tube is connected to the output end of the fourth switch tube;
  • the control end of the fourth switch tube inputs the second cascade signal of the upper stage, and the input end of the fourth switch tube is connected to the constant voltage low level source.
  • the first cascade signal of the upper stage input by the scan driving circuit of the first stage is an enable signal
  • the previous one of the scan drive circuit inputs of the first stage is
  • the second cascaded signal of the stage is an inverted signal of the enable signal
  • the latch module includes a fifth switch tube, a sixth switch tube, a seventh switch tube, and an eighth switch tube;
  • An input end of the fifth switch tube is connected to the constant voltage high level source, and an output end of the fifth switch tube is connected to the control signal output end;
  • a control end of the sixth switch tube is connected to a control end of the fifth switch tube, an input end of the sixth switch tube is connected to the constant voltage low level source, and an output end of the sixth switch tube Connected to the output of the control signal;
  • a control end of the seventh switch tube is connected to the control signal output end, an input end of the seventh switch tube is connected to the constant voltage high level source, and an output end of the seventh switch tube is Connecting the control end of the fifth switch tube;
  • a control end of the eighth switch tube is connected to the control signal output end, an input end of the eighth switch tube is connected to the constant voltage low level source, and an output end of the eighth switch tube is Connecting the control end of the fifth switch tube;
  • the fifth switch tube and the seventh switch tube are PMOS tubes, and the sixth switch tube and the eighth switch tube are NMOS tubes.
  • the driving signal generating module includes a ninth switch tube, a tenth switch tube, an eleventh switch tube, and a twelfth switch tube;
  • a control end of the ninth switch tube is connected to an output end of the latch module, an input end of the ninth switch tube is connected to the constant voltage high level source, and an output end of the ninth switch tube is The output of the driving signal generating module is connected;
  • the control end of the tenth switch tube inputs a second clock signal of the current stage, the input end of the tenth switch tube is connected to the constant voltage high level source, and the output end of the tenth switch tube is The output of the driving signal generating module is connected;
  • a control end of the eleventh switch tube is connected to an output end of the latch module, and an input end of the eleventh switch tube is connected to an output end of the twelfth switch tube, the eleventh switch An output end of the tube is connected to an output end of the driving signal generating module;
  • the control end of the twelfth switch tube inputs a second clock signal of the current stage, and the input end of the twelfth switch tube is connected to the constant voltage low level source;
  • the ninth switch tube and the tenth switch tube are PMOS tubes, and the eleventh switch tube and the twelfth switch tube are NMOS tubes.
  • the output end of the driving signal generating module outputs a driving signal of the current stage, and the driving signal is also the second cascade signal of the current stage.
  • the output control module includes a thirteenth switch tube, a fourteenth switch tube, a fifteenth switch tube, a sixteenth switch tube, a seventeenth switch tube, and an eighteenth turning tube;
  • a control end of the thirteenth switch tube is connected to an output end of the driving signal generating module, and an input end of the thirteenth switch tube is connected to the constant voltage high level source, the thirteenth switch tube
  • the output ends are respectively connected to the control end of the fifteenth switch tube and the control end of the sixteenth switch tube;
  • a control end of the fourteenth switch tube is connected to an output end of the driving signal generating module, and an input end of the fourteenth switch tube is connected to the constant voltage low level source, the fourteenth switch tube
  • the output ends are respectively connected to the control end of the fifteen switch tube and the control end of the sixteenth switch tube;
  • An input end of the fifteenth switch tube is connected to the constant voltage high level source, and an output end of the fifteenth switch tube is respectively connected to a control end of the seventeenth switch tube and the eighteenth switch The control end of the tube is connected;
  • the input end of the sixteenth switch tube is connected to the constant voltage low level source, and the output end of the sixteenth switch tube and the control end of the seventeenth switch tube and the eighteenth switch respectively The control end of the tube is connected;
  • An input end of the seventeenth switch tube is connected to the constant voltage high level source, and an output end of the seventeenth switch tube is connected to an output end of the output control module;
  • An input end of the eighteenth switch tube is connected to the constant voltage low level source, and an output end of the eighteenth switch tube is connected to an output end of the output control module;
  • the thirteenth switch tube, the fifteenth switch tube, and the seventeenth switch tube are PMOS tubes, the fourteenth switch tube, the sixteenth switch tube, and the eighteenth switch
  • the tube is an NMOS tube.
  • the output end of the thirteenth switch tube outputs the first cascade signal of the current stage.
  • the first switching transistor, the second switching transistor, the third switching transistor, and the fourth switching transistor are all NMOS transistors or PMOS transistors.
  • the first switching transistor and the fourth switching transistor are NMOS transistors, the second switching transistor and the PMOS transistor of the third switching transistor.
  • the first switching transistor and the fourth switching transistor are PMOS transistors
  • the second switching transistor and the third switching transistor are NMOS transistors.
  • the scan driving circuit of the present invention drives the latch module through the inverted first cascade signal and the second cascade signal, and does not need to perform an inversion operation on the clock signal, thereby
  • the dynamic power consumption of the scan driving circuit is small; the technical problem of the dynamic power consumption of the existing scan driving circuit is solved.
  • FIG. 1 is a schematic structural view of a first preferred embodiment of a scan driving circuit of the present invention
  • FIG. 2 is a schematic diagram of a cascade structure of a first preferred embodiment of a scan driving circuit of the present invention
  • FIG. 3 is a schematic diagram of signal waveforms of a first preferred embodiment of a scan driving circuit of the present invention
  • FIG. 4 is a schematic structural view of a second preferred embodiment of a scan driving circuit of the present invention.
  • FIG. 5 is a schematic structural view of a third preferred embodiment of a scan driving circuit of the present invention.
  • Figure 6 is a block diagram showing the structure of a fourth preferred embodiment of the scan driving circuit of the present invention.
  • FIG. 1 is a schematic structural view of a first preferred embodiment of a scan driving circuit of the present invention.
  • the scan driving circuit of the preferred embodiment is used for driving the cascaded scan lines.
  • the scan drive circuit 10 of each stage includes an input control module 11, a latch module 12, a drive signal generating module 13, and an output control module 14. Constant voltage high level source VGH and constant voltage low level source VGL.
  • the input control module 11 is configured to input the first clock signal CK_1 of the current stage and the cascade signal of the previous stage, and generate the control signal Q_N according to the first clock signal CK_1 of the current stage and the cascaded signal of the previous stage.
  • the latch module 12 is configured to perform a latch operation on the control signal Q_N.
  • the driving signal generating module 13 is configured to generate a driving signal according to the control signal Q_N and the second clock signal CK_2 of the current stage.
  • the output control module 14 is configured to output the scan signal G_N of the current stage and the cascade signal of the current stage according to the driving signal.
  • the constant voltage high level source VGH is used to supply a high level voltage.
  • the constant voltage low level source VGL is used to supply a low level voltage.
  • the cascading signal includes a first cascading signal ST_N and a second cascading signal XST_N, and the phases of the first cascading signal ST_N and the second cascading signal XST_N are opposite.
  • the input control module 11 of the preferred embodiment includes a first switch tube PT1, a second switch tube PT2, a third switch tube PT3, and a fourth switch tube PT4.
  • the control end of the first switch tube PT1 inputs the first cascade signal ST_N-1 of the previous stage, the input end of the first switch tube PT1 is connected to the constant voltage high level source VGH, and the output end of the first switch tube PT1 is The output ends of the two switch tubes PT2 are connected.
  • the control end of the second switch PT2 is input to the first clock signal CK_1 of the current stage, and the output end of the second switch PT2 is respectively connected to the output end of the third switch tube PT3 and the control signal output end.
  • the control end of the third switch PT3 is input to the first clock signal CK_1 of the current stage, and the output end of the third switch PT3 is connected to the output end of the fourth switch PT4.
  • the control end of the fourth switch tube PT4 inputs the second cascade signal XST_N-1 of the previous stage, and the input end of the fourth switch tube PT4 is connected to the constant voltage low level source VGL.
  • the latch module 12 of the preferred embodiment includes a fifth switch tube PT5, a sixth switch tube PT6, a seventh switch tube PT7, and an eighth switch tube PT8.
  • the input end of the fifth switch tube PT5 is connected to the constant voltage high level source VGH, and the output end of the fifth switch tube PT5 is connected to the control signal output end.
  • the control end of the sixth switch tube PT6 is connected to the control end of the fifth switch tube PT5, the input end of the sixth switch tube PT6 is connected to the constant voltage low level source VGL, and the output end of the sixth switch tube PT6 and the control signal output end are connected. connection.
  • the control end of the seventh switch tube PT7 is connected with the control signal output end, the input end of the seventh switch tube PT7 is connected with the constant voltage high level source VGH, the output end of the seventh switch tube PT7 and the control end of the fifth switch tube PT5 connection.
  • the control end of the eighth switch tube PT8 is connected with the control signal output end, the input end of the eighth switch tube PT8 is connected with the constant voltage low level source VGL, the output end of the eighth switch tube PT8 and the control end of the fifth switch tube PT5 connection.
  • the driving signal generating module 13 of the preferred embodiment includes a ninth switching transistor PT9, a tenth switching transistor PT10, an eleventh switching transistor PT11, and a twelfth switching transistor PT12.
  • the control end of the ninth switch tube PT9 is connected to the output end of the latch module 12, the input end of the ninth switch tube PT9 is connected to the constant voltage high level source VGH, and the output end of the ninth switch tube PT9 and the drive signal generating module 13 The output is connected.
  • the control terminal of the tenth switch tube PT10 inputs the second clock signal CK_2 of the current stage, the input end of the tenth switch tube PT10 is connected with the constant voltage high level source VGH, and the output end of the tenth switch tube PT10 and the drive signal generation module 13 The output is connected.
  • the control end of the eleventh switch tube PT11 is connected to the output end of the latch module 12, the input end of the eleventh switch tube PT11 is connected to the output end of the twelfth switch tube PT12, and the output end of the eleventh switch tube PT11 is The output of the drive signal generating module 13 is connected.
  • the control end of the twelfth switch tube PT12 is input to the second clock signal CK_2 of the current stage, and the input end of the twelfth switch tube PT12 is connected to the constant voltage low level source VGL.
  • the output control module 14 includes a thirteenth switch tube PT13, a fourteenth switch tube PT14, a fifteenth switch tube PT15, a sixteenth switch tube PT16, a seventeenth switch tube PT17, and an eighteenth switch tube PT18.
  • the control end of the thirteenth switch tube PT13 is connected to the output end of the drive signal generating module 13, the input end of the thirteenth switch tube PT13 is connected to the constant voltage high level source VGH, and the output end of the thirteenth switch tube PT13 is respectively
  • the control end of the fifteenth switch tube PT15 is connected to the control end of the sixteenth switch tube PT16.
  • the control end of the fourteenth switch tube PT14 is connected to the output end of the drive signal generating module 13, the input end of the fourteenth switch tube PT14 is connected to the constant voltage low level source VGL, and the output end of the fourteenth switch tube PT14 is respectively
  • the control end of the fifteenth switch tube PT15 is connected to the control end of the sixteenth switch tube PT16.
  • the input end of the fifteenth switch tube PT15 is connected with the constant voltage high level source VGH, and the output end of the fifteenth switch tube PT15 is respectively connected with the control end of the seventeenth switch tube PT17 and the control end of the eighteenth switch tube PT18. .
  • the input end of the sixteenth switch tube PT16 is connected with the constant voltage low level source VGL, and the output end of the sixteenth switch tube PT16 is respectively connected with the control end of the seventeenth switch tube PT17 and the control end of the eighteenth switch tube PT18. .
  • the input end of the seventeenth switch tube PT17 is connected to the constant voltage high level source VGH, and the output end of the seventeenth switch tube PT17 is connected to the output end of the output control module 14.
  • the input end of the eighteenth switch tube PT18 is connected to the constant voltage low level source VGL, and the output end of the eighteenth switch tube PT18 is connected to the output end of the output control module 14.
  • the first switch tube PT1, the second switch tube PT2, the third switch tube PT3, and the fourth switch tube PT4 are all NMOS tubes
  • the fifth switch tube PT5 and the seventh switch tube PT7 are PMOS tubes
  • the six switch tube PT6 and the eighth switch tube PT8 are NMOS tubes
  • the ninth switch tube PT9 and the tenth switch tube PT10 are PMOS tubes
  • the eleventh switch tube PT11 and the twelfth switch tube PT12 are NMOS tubes
  • the thirteenth switch The tube PT13, the fifteenth switch tube PT15, and the seventeenth switch tube PT17 are PMOS tubes
  • the fourteenth switch tube PT14, the sixteenth switch tube PT16, and the eighteenth switch tube PT18 are NMOS tubes.
  • FIG. 2 is a schematic diagram of a cascade structure of a first preferred embodiment of a scan driving circuit according to the present invention
  • FIG. 3 is a schematic diagram of a scan driving circuit of the present invention.
  • the scan drive circuit of the first stage replaces the first cascaded signal ST_N-1 of the previous stage with the start signal STV, and replaces the second of the previous stage with the reverse start signal XSTV formed by the first cascade signal and the inverter.
  • the cascade signal XST_N-1 as shown in FIG. 3, when the first cascaded signal ST_N-1 of the previous stage is at a high level, the second cascaded signal XST_N-1 of the previous stage is at a low level, the current level
  • the first clock signal CK_1 is also at a high level.
  • the first switch tube PT1, the second switch tube PT2, and the third switch tube PT3 are turned on, and the fourth switch tube PT4 is turned off, and the high level voltage of the constant voltage high level source VGH passes through the first switch tube PT1 and the first
  • the second switch tube PT2 outputs a high level control signal from the control signal output end, and the fourth switch tube PT4 disconnects the control signal output end from the constant voltage low level source VGL.
  • the first clock signal CK_1 of the current stage is turned to a low level
  • the second switch tube PT2 and the third switch tube PT3 are disconnected
  • the control signal of the high level outputted by the control signal output end of the input control module 11 passes through the latch module. 12 performs a latch operation.
  • the eighth switch tube PT8 is turned on under the action of the high level control signal
  • the sixth switch tube PT6 is turned off under the action of the high level control signal, so that the constant voltage low level source VGL is low.
  • the flat voltage is applied to the control end of the fifth switch tube PT5 and the control end of the seventh switch tube PT7 through the eighth switch tube PT8, and the fifth switch tube PT5 is turned on under the action of the low level voltage, and the seventh switch tube PT7 is Under the action of the low level voltage, the high level voltage of the constant voltage high level source VGH acts on the control signal Q_N through the fifth switching tube PT5, so that the control signal Q_N can always remain in the high level state.
  • the control signal Q_N is switched to the low state until the second switching transistor PT7 and the third switching transistor PT3 are turned on by the high level first clock signal CK_1.
  • the driving signal generating module 13 functions as a NAND gate, that is, the control signal Q_N outputted by the latching module 12 is NANDed with the second clock signal CK_2 of the current stage. Specifically, when the control signal Q_N and the second clock signal CK_2 of the current stage are simultaneously at a high level, the ninth switch tube PT9 and the tenth switch tube PT10 are disconnected, and the eleventh switch tube PT11 and the twelfth switch tube PT12 lead In this case, the output terminal of the driving signal generating module 13 outputs a low level voltage of the constant voltage low level source VGL.
  • the twelfth switch tube PT12 When the second clock signal CK_2 of the current stage is low, the twelfth switch tube PT12 is turned off, the tenth switch tube PT10 is turned on, and the output end of the drive signal generating module 13 outputs the high voltage high level source VGH. Level voltage; when the control signal Q_N enters a low level, the ninth switch tube PT9 is turned on, the eleventh switch tube PT11 is turned off, and the output end of the drive signal generating module 13 outputs a constant voltage high level source VGH high power Flat voltage.
  • the output terminal of the driving signal generating module 13 outputs a driving signal, which is output as a second cascade signal XST_N of the current stage to the scan driving circuit of the next stage.
  • the output end of the thirteenth switch tube PT13 outputs the first cascade signal ST_N of the current stage, and outputs to the scan drive circuit of the next stage.
  • the fourteenth switch tube PT14 When the driving signal is high level, the fourteenth switch tube PT14 is turned on, and the thirteenth switch tube PT13 is turned off; the low level voltage of the constant voltage low level source VGL is input to the control end of the fifteenth switch tube PT15 And the control end of the sixteenth switch tube PT16, the fifteenth switch tube PT15 is turned on, the sixteenth switch tube PT16 is turned off, the high level voltage of the constant voltage high level source VGH is input to the seventeenth switch tube PT17 The control end and the control end of the eighteenth switch tube PT18, the seventeenth switch tube PT17 is turned off, the eighteenth switch tube PT18 is turned on, and the output control module 13 outputs the scan signal G_N of the current level of the low level.
  • the fourteenth switch tube PT14 When the driving signal is low level, the fourteenth switch tube PT14 is turned off, and the thirteenth switch tube PT13 is turned on; the high level voltage of the constant voltage high level source VGH is input to the control end of the fifteenth switch tube PT15 And the control end of the sixteenth switch tube PT16, the sixteenth switch tube PT16 is turned off, the fifteenth switch tube PT15 is turned on, the low voltage of the constant voltage low level source VGL is input to the seventeenth switch tube PT17 The control terminal and the control end of the eighteenth switch tube PT18, the seventeenth switch tube PT17 is turned on, the eighteenth switch tube PT18 is turned off, and the output control module 13 outputs the scan signal G_N of the current level of the high level.
  • the scan lines of the odd rows are cascaded with each other, and the scan lines of the even rows are cascaded with each other, where the scan signals of the first clock signal CK_1 and the even rows of the scan drive circuit 10 of the odd rows are here.
  • the second clock signal CK_2 of the circuit is in phase, and the second clock signal CK_2 of the scan drive circuit of the odd rows is in phase with the first clock signal CK_1 of the scan drive circuit of the even rows.
  • the scan signal G_N of the current stage, the scan signal G_N+2 of the next two stages corresponds to the second clock signal CK_2 of the high level, and the scan signal G_N+1 of the next stage and the scan signal G_N+3 of the lower three stages are high.
  • the first clock signal CK_1 of the level corresponds.
  • the scan driving circuit of the preferred embodiment drives the latch module through the inverted first cascode signal and the second cascode signal, and does not need to perform an inversion operation on the clock signal, so that the dynamic power consumption of the entire scan driving circuit is relatively small.
  • FIG. 4 is a schematic structural view of a second preferred embodiment of the scan driving circuit of the present invention.
  • the first switching transistor PT1 and the fourth switching transistor PT4 of the input control module 21 of the scan driving circuit 20 of the preferred embodiment are an NMOS transistor, a second switching transistor PT2 and a third switching transistor.
  • the control end of the first switch tube PT1 inputs the first cascade signal ST_N-1 of the previous stage, and the control end of the fourth switch tube PT4 inputs the second cascade signal XST_N-1 of the previous stage
  • the control terminal of the second switch PT2 is input to the first clock signal CK_1 of the current stage
  • the control terminal of the third switch PT3 is also input with the first clock signal CK_1 of the current stage.
  • the first clock signal CK_1 of the present stage is opposite to the first clock signal in the first preferred embodiment, and the same technical effect as the first preferred embodiment can be achieved.
  • the capacitive coupling effect during the scan driving current operation can be effectively reduced.
  • the scan driving circuit of the preferred embodiment further enhances the reliability and stability of the scan driving circuit based on the first preferred embodiment.
  • FIG. 5 is a schematic structural diagram of a third preferred embodiment of the scan driving circuit of the present invention.
  • the first switch tube PT1, the second switch tube PT2, the third switch tube PT3, and the fourth switch tube PT4 of the input control module 31 of the scan driving circuit 30 of the preferred embodiment are both The PMOS tube, the control end of the first switch tube PT1 inputs the second cascade signal XST_N-1 of the previous stage, and the control end of the fourth switch tube PT4 inputs the first cascade signal ST_N-1 of the previous stage, the second switch The control terminal of the tube PT2 inputs the first clock signal CK_1 of the current stage, and the control terminal of the third switch tube PT3 also inputs the first clock signal CK_1 of the current stage.
  • the first clock signal CK_1 of the present stage is opposite to the first clock signal in the first preferred embodiment, and the same technical effect as the first preferred embodiment can be achieved.
  • the capacitive coupling effect during the scan driving current operation can be effectively reduced.
  • the scan driving circuit of the preferred embodiment further enhances the reliability and stability of the scan driving circuit based on the first preferred embodiment.
  • FIG. 6 is a schematic structural view of a fourth preferred embodiment of the scan driving circuit of the present invention.
  • the first switch tube PT1 and the fourth switch tube PT4 of the input control module 41 of the scan driving circuit 40 of the preferred embodiment are a PMOS tube, a second switch tube PT2 and a third switch tube.
  • the control end of the first switch tube PT1 inputs the second cascade signal XST_N-1 of the previous stage, and the control end of the fourth switch tube PT4 inputs the first cascade signal ST_N-1 of the previous stage
  • the control terminal of the second switch PT2 is input to the first clock signal CK_1 of the current stage
  • the control terminal of the third switch PT3 is also input with the first clock signal CK_1 of the current stage.
  • the first clock signal CK_1 of the present stage is in the same direction as the first clock signal in the first preferred embodiment, and the same technical effect as the first preferred embodiment can be achieved.
  • the capacitive coupling effect during the scan driving current operation can be effectively reduced.
  • the scan driving circuit of the preferred embodiment further enhances the reliability and stability of the scan driving circuit based on the first preferred embodiment.
  • the scan driving circuit of the present invention drives the latch module by the inverted first cascode signal and the second cascode signal, and does not need to perform an inversion operation on the clock signal, thereby reducing the overall volume of the scan driving circuit, and
  • the dynamic power consumption of the entire scan driving circuit is small; the technical problem of the large size and dynamic power consumption of the existing scan driving circuit is solved.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种扫描驱动电路（10），用于对级联的扫描线进行驱动操作，其包括输入控制模块（11）、锁存模块（12）、驱动信号产生模块（13）、输出控制模块（14）、恒压高电平源（VGH）以及恒压低电平源（VGL）。该扫描驱动电路（10）通过反相的第一级联信号（ST_N）以及第二级联信号（XST_N）进行锁存模块（12）的驱动，不需要对时钟信号进行反相操作，从而整个扫描驱动电路（10）的动态功耗较小。

Description

一种扫描驱动电路 技术领域
本发明涉及显示驱动领域，特别是涉及一种扫描驱动电路。
 背景技术
Gate Driver On Array，简称GOA，即在现有薄膜晶体管液晶显示器的阵列基板上制作扫描驱动电路，实现对扫描线逐行扫描的驱动方式。
但是现有的扫描驱动电路均需要使用时钟信号CK和时钟信号XCK进行驱动，其中时钟信号CK和时钟信号XCK互为反相信号。因此现有的扫描驱动电路需要对级联的每一级的扫描驱动电路的时钟信号CK进行反相处理，以获取时钟信号XCK，造成整个扫描驱动电路的动态功耗较大。
故，有必要提供一种扫描驱动电路，以解决现有技术所存在的问题。
 技术问题
本发明的目的在于提供一种结构简单且功耗较小的扫描驱动电路，以解决现有的扫描驱动电路的动态功耗较大的技术问题。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明实施例提供一种扫描驱动电路，用于对级联的扫描线进行驱动操作，其包括：
输入控制模块，用于输入本级的第一时钟信号以及上一级的级联信号，并根据本级的所述第一时钟信号以及上一级的所述级联信号产生控制信号；
锁存模块，用于对所述控制信号进行锁存操作；
驱动信号产生模块，用于根据所述控制信号以及本级的第二时钟信号产生驱动信号；
输出控制模块，用于根据所述驱动信号输出本级的扫描信号以及本级的级联信号；
恒压高电平源，用于提供高电平电压；以及
恒压低电平源，用于提供低电平电压；
其中所述级联信号包括第一级联信号以及第二级联信号，所述第一级联信号和所述第二级联信号的相位相反；
所述输入控制模块包括第一开关管、第二开关管、第三开关管以及第四开关管；
所述第一开关管的控制端输入上一级的所述第一级联信号，所述第一开关管的输入端与所述恒压高电平源连接，所述第一开关管的输出端与所述第二开关管的输入端连接；
所述第二开关管的控制端输入本级的所述第一时钟信号，所述第二开关管的输出端分别与所述第三开关管的输入端以及控制信号输出端连接；
所述第三开关管的控制端输入本级的所述第一时钟信号，所述第三开关管的输出端与所述第四开关管的输出端连接；
所述第四开关管的控制端输入上一级的所述第二级联信号，所述第四开关管的输入端与所述恒压低电平源连接；
所述锁存模块包括第五开关管、第六开关管、第七开关管以及第八开关管；
所述第五开关管的输入端与所述恒压高电平源连接，所述第五开关管的输出端与所述控制信号输出端连接；
所述第六开关管的控制端与所述第五开关管的控制端连接，所述第六开关管的输入端与所述恒压低电平源连接，所述第六开关管的输出端与所述控制信号输出端连接；
所述第七开关管的控制端与所述控制信号输出端连接，所述第七开关管的输入端与所述恒压高电平源连接，所述第七开关管的输出端与所述第五开关管的控制端连接；
所述第八开关管的控制端与所述控制信号输出端连接，所述第八开关管的输入端与所述恒压低电平源连接，所述第八开关管的输出端与所述第五开关管的控制端连接；
其中所述第五开关管和所述第七开关管为PMOS管，所述第六开关管和第八开关管为NMOS管。
在本发明所述的扫描驱动电路中，第一级的所述扫描驱动电路输入的上一级的所述第一级联信号为启动信号，第一级的所述扫描驱动电路输入的上一级的所述第二级联信号为所述启动信号的反相信号。
在本发明所述的扫描驱动电路中，所述驱动信号产生模块包括第九开关管、第十开关管、第十一开关管以及第十二开关管；
所述第九开关管的控制端与所述锁存模块的输出端连接，所述第九开关管的输入端与所述恒压高电平源连接，所述第九开关管的输出端与所述驱动信号产生模块的输出端连接；
所述第十开关管的控制端输入本级的第二时钟信号，所述第十开关管的输入端与所述恒压高电平源连接，所述第十开关管的输出端与所述驱动信号产生模块的输出端连接；
所述第十一开关管的控制端与所述锁存模块的输出端连接，所述第十一开关管的输入端与所述第十二开关管的输出端连接，所述第十一开关管的输出端与所述驱动信号产生模块的输出端连接；
所述第十二开关管的控制端输入本级的第二时钟信号，所述第十二开关管的输入端与所述恒压低电平源连接；
其中所述第九开关管和所述第十开关管为PMOS管，所述第十一开关管和第十二开关管为NMOS管。
在本发明所述的扫描驱动电路中，所述驱动信号产生模块的输出端输出本级的驱动信号，所述驱动信号也为本级的第二级联信号。
在本发明所述的扫描驱动电路中，所述输出控制模块包括第十三开关管、第十四开关管、第十五开关管、第十六开关管、第十七开关管以及第十八开关管；
所述第十三开关管的控制端与所述驱动信号产生模块的输出端连接，所述第十三开关管的输入端与所述恒压高电平源连接，所述第十三开关管的输出端分别与所述第十五开关管的控制端和所述第十六开关管的控制端连接；
所述第十四开关管的控制端与所述驱动信号产生模块的输出端连接，所述第十四开关管的输入端与所述恒压低电平源连接，所述第十四开关管的输出端分别与所述十五开关管的控制端和所述第十六开关管的控制端连接；
所述第十五开关管的输入端与所述恒压高电平源连接，所述第十五开关管的输出端分别与所述第十七开关管的控制端和所述第十八开关管的控制端连接；
所述第十六开关管的输入端与所述恒压低电平源连接，所述第十六开关管的输出端分别与所述第十七开关管的控制端和所述第十八开关管的控制端连接；
所述第十七开关管的输入端与所述恒压高电平源连接，所述第十七开关管的输出端与所述输出控制模块的输出端连接；
所述第十八开关管的输入端与所述恒压低电平源连接，所述第十八开关管的输出端与所述输出控制模块的输出端连接；
其中所述第十三开关管、所述第十五开关管以及所述第十七开关管为PMOS管，所述第十四开关管、所述第十六开关管以及所述第十八开关管为NMOS管。
在本发明所述的扫描驱动电路中，所述第十三开关管的输出端输出本级的第一级联信号。
在本发明所述的扫描驱动电路中，所述第一开关管、所述第二开关管、所述第三开关管以及所述第四开关管均为NMOS管或PMOS管。
在本发明所述的扫描驱动电路中，所述第一开关管和所述第四开关管为NMOS管，所述第二开关管和所述第三开关管的PMOS管。
在本发明所述的扫描驱动电路中，所述第一开关管和所述第四开关管为PMOS管，所述第二开关管和所述第三开关管为NMOS管。
本发明实施例提供一种扫描驱动电路，用于对级联的扫描线进行驱动操作，其包括：
输入控制模块，用于输入本级的第一时钟信号以及上一级的级联信号，并根据本级的所述第一时钟信号以及上一级的所述级联信号产生控制信号；
锁存模块，用于对所述控制信号进行锁存操作；
驱动信号产生模块，用于根据所述控制信号以及本级的第二时钟信号产生驱动信号；
输出控制模块，用于根据所述驱动信号输出本级的扫描信号以及本级的级联信号；
恒压高电平源，用于提供高电平电压；以及
恒压低电平源，用于提供低电平电压。
在本发明所述的扫描驱动电路中，所述级联信号包括第一级联信号以及第二级联信号，所述第一级联信号和所述第二级联信号的相位相反；
所述输入控制模块包括第一开关管、第二开关管、第三开关管以及第四开关管；
所述第一开关管的控制端输入上一级的所述第一级联信号，所述第一开关管的输入端与所述恒压高电平源连接，所述第一开关管的输出端与所述第二开关管的输入端连接；
所述第二开关管的控制端输入本级的所述第一时钟信号，所述第二开关管的输出端分别与所述第三开关管的输入端以及控制信号输出端连接；
所述第三开关管的控制端输入本级的所述第一时钟信号，所述第三开关管的输出端与所述第四开关管的输出端连接；
所述第四开关管的控制端输入上一级的所述第二级联信号，所述第四开关管的输入端与所述恒压低电平源连接。
在本发明所述的扫描驱动电路中，第一级的所述扫描驱动电路输入的上一级的所述第一级联信号为启动信号，第一级的所述扫描驱动电路输入的上一级的所述第二级联信号为所述启动信号的反相信号。
在本发明所述的扫描驱动电路中，所述锁存模块包括第五开关管、第六开关管、第七开关管以及第八开关管；
所述第五开关管的输入端与所述恒压高电平源连接，所述第五开关管的输出端与所述控制信号输出端连接；
所述第六开关管的控制端与所述第五开关管的控制端连接，所述第六开关管的输入端与所述恒压低电平源连接，所述第六开关管的输出端与所述控制信号输出端连接；
所述第七开关管的控制端与所述控制信号输出端连接，所述第七开关管的输入端与所述恒压高电平源连接，所述第七开关管的输出端与所述第五开关管的控制端连接；
所述第八开关管的控制端与所述控制信号输出端连接，所述第八开关管的输入端与所述恒压低电平源连接，所述第八开关管的输出端与所述第五开关管的控制端连接；
其中所述第五开关管和所述第七开关管为PMOS管，所述第六开关管和第八开关管为NMOS管。
在本发明所述的扫描驱动电路中，所述驱动信号产生模块包括第九开关管、第十开关管、第十一开关管以及第十二开关管；
所述第九开关管的控制端与所述锁存模块的输出端连接，所述第九开关管的输入端与所述恒压高电平源连接，所述第九开关管的输出端与所述驱动信号产生模块的输出端连接；
所述第十开关管的控制端输入本级的第二时钟信号，所述第十开关管的输入端与所述恒压高电平源连接，所述第十开关管的输出端与所述驱动信号产生模块的输出端连接；
所述第十一开关管的控制端与所述锁存模块的输出端连接，所述第十一开关管的输入端与所述第十二开关管的输出端连接，所述第十一开关管的输出端与所述驱动信号产生模块的输出端连接；
所述第十二开关管的控制端输入本级的第二时钟信号，所述第十二开关管的输入端与所述恒压低电平源连接；
其中所述第九开关管和所述第十开关管为PMOS管，所述第十一开关管和第十二开关管为NMOS管。
在本发明所述的扫描驱动电路中，所述驱动信号产生模块的输出端输出本级的驱动信号，所述驱动信号也为本级的第二级联信号。
在本发明所述的扫描驱动电路中，所述输出控制模块包括第十三开关管、第十四开关管、第十五开关管、第十六开关管、第十七开关管以及第十八开关管；
所述第十三开关管的控制端与所述驱动信号产生模块的输出端连接，所述第十三开关管的输入端与所述恒压高电平源连接，所述第十三开关管的输出端分别与所述第十五开关管的控制端和所述第十六开关管的控制端连接；
所述第十四开关管的控制端与所述驱动信号产生模块的输出端连接，所述第十四开关管的输入端与所述恒压低电平源连接，所述第十四开关管的输出端分别与所述十五开关管的控制端和所述第十六开关管的控制端连接；
所述第十五开关管的输入端与所述恒压高电平源连接，所述第十五开关管的输出端分别与所述第十七开关管的控制端和所述第十八开关管的控制端连接；
所述第十六开关管的输入端与所述恒压低电平源连接，所述第十六开关管的输出端分别与所述第十七开关管的控制端和所述第十八开关管的控制端连接；
所述第十七开关管的输入端与所述恒压高电平源连接，所述第十七开关管的输出端与所述输出控制模块的输出端连接；
所述第十八开关管的输入端与所述恒压低电平源连接，所述第十八开关管的输出端与所述输出控制模块的输出端连接；
其中所述第十三开关管、所述第十五开关管以及所述第十七开关管为PMOS管，所述第十四开关管、所述第十六开关管以及所述第十八开关管为NMOS管。
在本发明所述的扫描驱动电路中，所述第十三开关管的输出端输出本级的第一级联信号。
在本发明所述的扫描驱动电路中，所述第一开关管、所述第二开关管、所述第三开关管以及所述第四开关管均为NMOS管或PMOS管。
在本发明所述的扫描驱动电路中，所述第一开关管和所述第四开关管为NMOS管，所述第二开关管和所述第三开关管的PMOS管。
在本发明所述的扫描驱动电路中，所述第一开关管和所述第四开关管为PMOS管，所述第二开关管和所述第三开关管为NMOS管。
 有益效果
相较于现有的扫描驱动电路，本发明的扫描驱动电路通过反相的第一级联信号以及第二级联信号进行锁存模块的驱动，不需要对时钟信号进行反相操作，从而整个扫描驱动电路的动态功耗较小；解决了现有的扫描驱动电路的动态功耗较大的技术问题。
 附图说明
图1为本发明的扫描驱动电路的第一优选实施例的结构示意图；
图2为本发明的扫描驱动电路的第一优选实施例的级联结构示意图；
图3为本发明的扫描驱动电路的第一优选实施例的信号波形示意图；
图4为本发明的扫描驱动电路的第二优选实施例的结构示意图；
图5为本发明的扫描驱动电路的第三优选实施例的结构示意图；
图6为本发明的扫描驱动电路的第四优选实施例的结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的单元是以相同标号表示。
请参照图1，图1为本发明的扫描驱动电路的第一优选施实施例的结构示意图。本优选实施例的扫描驱动电路用于对级联的扫描线进行驱动操作，每一级的扫描驱动电路10包括输入控制模块11、锁存模块12、驱动信号产生模块13、输出控制模块14、恒压高电平源VGH以及恒压低电平源VGL。
输入控制模块11用于输入本级的第一时钟信号CK_1以及上一级的级联信号，并根据本级的第一时钟信号CK_1以及上一级的级联信号产生控制信号Q_N。锁存模块12用于对控制信号Q_N进行锁存操作。驱动信号产生模块13用于根据控制信号Q_N以及本级的第二时钟信号CK_2产生驱动信号。输出控制模块14用于根据驱动信号输出本级的扫描信号G_N以及本级的级联信号。恒压高电平源VGH用于提供高电平电压。恒压低电平源VGL用于提供低电平电压。
其中级联信号包括第一级联信号ST_N以及第二级联信号XST_N，第一级联信号ST_N和第二级联信号XST_N的相位相反。
本优选实施例的输入控制模块11包括第一开关管PT1、第二开关管PT2、第三开关管PT3以及第四开关管PT4。
第一开关管PT1的控制端输入上一级的第一级联信号ST_N-1，第一开关管PT1的输入端与恒压高电平源VGH连接，第一开关管PT1的输出端与第二开关管PT2的输出端连接。
第二开关管PT2的控制端输入本级的第一时钟信号CK_1，第二开关管PT2的输出端分别与第三开关管PT3的输出端以及控制信号输出端连接。
第三开关管PT3的控制端输入本级的第一时钟信号CK_1，第三开关管PT3的输出端与第四开关管PT4的输出端连接。
第四开关管PT4的控制端输入上一级的第二级联信号XST_N-1，第四开关管PT4的输入端与恒压低电平源VGL连接。
本优选实施例的锁存模块12包括第五开关管PT5、第六开关管PT6、第七开关管PT7以及第八开关管PT8。
第五开关管PT5的输入端与恒压高电平源VGH连接，第五开关管PT5的输出端与控制信号输出端连接。
第六开关管PT6的控制端与第五开关管PT5的控制端连接，第六开关管PT6的输入端与恒压低电平源VGL连接，第六开关管PT6的输出端与控制信号输出端连接。
第七开关管PT7的控制端与控制信号输出端连接，第七开关管PT7的输入端与恒压高电平源VGH连接，第七开关管PT7的输出端与第五开关管PT5的控制端连接。
第八开关管PT8的控制端与控制信号输出端连接，第八开关管PT8的输入端与恒压低电平源VGL连接，第八开关管PT8的输出端与第五开关管PT5的控制端连接。
本优选实施例的驱动信号产生模块13包括第九开关管PT9、第十开关管PT10、第十一开关管PT11以及第十二开关管PT12。
第九开关管PT9的控制端与锁存模块12的输出端连接，第九开关管PT9的输入端与恒压高电平源VGH连接，第九开关管PT9的输出端与驱动信号产生模块13的输出端连接。
第十开关管PT10的控制端输入本级的第二时钟信号CK_2，第十开关管PT10的输入端与恒压高电平源VGH连接，第十开关管PT10的输出端与驱动信号产生模块13的输出端连接。
第十一开关管PT11的控制端与锁存模块12的输出端连接，第十一开关管PT11的输入端与第十二开关管PT12的输出端连接，第十一开关管PT11的输出端与驱动信号产生模块13的输出端连接。
第十二开关管PT12的控制端输入本级的第二时钟信号CK_2，第十二开关管PT12的输入端与恒压低电平源VGL连接。
输出控制模块14包括第十三开关管PT13、第十四开关管PT14、第十五开关管PT15、第十六开关管PT16、第十七开关管PT17以及第十八开关管PT18。
第十三开关管PT13的控制端与驱动信号产生模块13的输出端连接，第十三开关管PT13的输入端与恒压高电平源VGH连接，第十三开关管PT13的输出端分别与第十五开关管PT15的控制端和第十六开关管PT16的控制端连接。
第十四开关管PT14的控制端与驱动信号产生模块13的输出端连接，第十四开关管PT14的输入端与恒压低电平源VGL连接，第十四开关管PT14的输出端分别与第十五开关管PT15的控制端和第十六开关管PT16的控制端连接。
第十五开关管PT15的输入端与恒压高电平源VGH连接，第十五开关管PT15的输出端分别与第十七开关管PT17的控制端和第十八开关管PT18的控制端连接。
第十六开关管PT16的输入端与恒压低电平源VGL连接，第十六开关管PT16的输出端分别与第十七开关管PT17的控制端和第十八开关管PT18的控制端连接。
第十七开关管PT17的输入端和恒压高电平源VGH连接，第十七开关管PT17的输出端与输出控制模块14的输出端连接。
第十八开关管PT18的输入端与恒压低电平源VGL连接，第十八开关管PT18的输出端与输出控制模块14的输出端连接。
在本优选实施例中第一开关管PT1、第二开关管PT2、第三开关管PT3以及第四开关管PT4均为NMOS管，第五开关管PT5和第七开关管PT7为PMOS管，第六开关管PT6和第八开关管PT8为NMOS管，第九开关管PT9和第十开关管PT10为PMOS管，第十一开关管PT11和第十二开关管PT12为NMOS管，第十三开关管PT13、第十五开关管PT15以及第十七开关管PT17为PMOS管，第十四开关管PT14、第十六开关管PT16以及第十八开关管PT18为NMOS管。
本优选实施例的扫描驱动电路使用时，请参照图1至图3，图2为本发明的扫描驱动电路的第一优选实施例的级联结构示意图；图3为本发明的扫描驱动电路的第一优选实施例的信号波形示意图。
第一级的扫描驱动电路使用启动信号STV替代上一级的第一级联信号ST_N-1，使用通过第一级联信号和反相器形成的反向启动信号XSTV替代上一级的第二级联信号XST_N-1，如图3所示，当上一级的第一级联信号ST_N-1为高电平时，上一级的第二级联信号XST_N-1为低电平，本级的第一时钟信号CK_1也为高电平。这时第一开关管PT1、第二开关管PT2以及第三开关管PT3导通，第四开关管PT4断开，恒压高电平源VGH的高电平电压通过第一开关管PT1以及第二开关管PT2从控制信号输出端输出高电平的控制信号，第四开关管PT4将控制信号输出端与恒压低电平源VGL断开。
随后本级的第一时钟信号CK_1转为低电平，第二开关管PT2和第三开关管PT3断开，输入控制模块11的控制信号输出端输出的高电平的控制信号通过锁存模块12进行锁存操作。具体为，第八开关管PT8在高电平的控制信号的作用下导通，第六开关管PT6在高电平的控制信号的作用下断开，这样恒压低电平源VGL的低电平电压通过第八开关管PT8作用于第五开关管PT5的控制端以及第七开关管PT7的控制端，第五开关管PT5在低电平电压的作用下导通，第七开关管PT7在低电平电压的作用下断开，恒压高电平源VGH的高电平电压通过第五开关管PT5作用于控制信号Q_N，使得控制信号Q_N可一直保持高电平状态。直至第二开关管PT7和第三开关管PT3在高电平的第一时钟信号CK_1的作用下导通后，该控制信号Q_N才转换为低电平状态。
驱动信号产生模块13起到一个与非门的作用，即将锁存模块12输出的控制信号Q_N与本级的第二时钟信号CK_2进行与非运算。具体为，当控制信号Q_N和本级的第二时钟信号CK_2同时为高电平时，第九开关管PT9和第十开关管PT10断开，第十一开关管PT11和第十二开关管PT12导通，这时驱动信号产生模块13的输出端输出恒压低电平源VGL的低电平电压。当本级的第二时钟信号CK_2进为低电平时，第十二开关管PT12断开，第十开关管PT10导通，驱动信号产生模块13的输出端输出恒压高电平源VGH的高电平电压；当控制信号Q_N进为低电平时，第九开关管PT9导通，第十一开关管PT11断开，驱动信号产生模块13的输出端输出恒压高电平源VGH的高电平电压。
驱动信号产生模块13的输出端输出驱动信号，该驱动信号作为本级的第二级联信号XST_N，输出至下一级的扫描驱动电路。第十三开关管PT13的输出端输出本级的第一级联信号ST_N，输出至下一级的扫描驱动电路。
当该驱动信号为高电平时，第十四开关管PT14导通，第十三开关管PT13断开；恒压低电平源VGL的低电平电压输入到第十五开关管PT15的控制端以及第十六开关管PT16的控制端，第十五开关管PT15导通，第十六开关管PT16断开，恒压高电平源VGH的高电平电压输入到第十七开关管PT17的控制端和第十八开关管PT18的控制端，第十七开关管PT17断开，第十八开关管PT18导通，输出控制模块13输出低电平的本级的扫描信号G_N。
当该驱动信号为低电平时，第十四开关管PT14断开，第十三开关管PT13导通；恒压高电平源VGH的高电平电压输入至第十五开关管PT15的控制端以及第十六开关管PT16的控制端，第十六开关管PT16断开，第十五开关管PT15导通，恒压低电平源VGL的低电平电压输入至第十七开关管PT17的控制端和第十八开关管PT18的控制端，第十七开关管PT17导通，第十八开关管PT18断开，输出控制模块13输出高电平的本级的扫描信号G_N。
请参照图2，在本优选实施例中，奇数行的扫描线相互级联，偶数行的扫描线相互级联，这里奇数行的扫描驱动电路10的第一时钟信号CK_1与偶数行的扫描驱动电路的第二时钟信号CK_2同相位，奇数行的扫描驱动电路的第二时钟信号CK_2与偶数行的扫描驱动电路的第一时钟信号CK_1同相位。因此本级的扫描信号G_N，下两级的扫描信号G_N+2与高电平的第二时钟信号CK_2对应，下一级的扫描信号G_N+1和下三级的扫描信号G_N+3与高电平的第一时钟信号CK_1对应。
这样即完成了本优选实施例的扫描驱动电路的扫描线的驱动过程。
本优选实施例的扫描驱动电路通过反相的第一级联信号以及第二级联信号进行锁存模块的驱动，不需要对时钟信号进行反相操作，从而整个扫描驱动电路的动态功耗较小。
请参照图4，图4为本发明的扫描驱动电路的第二优选实施例的结构示意图。在第一优选实施例的基础上，本优选实施例的扫描驱动电路20的输入控制模块21的第一开关管PT1和第四开关管PT4为NMOS管，第二开关管PT2和第三开关管PT3为PMOS管，第一开关管PT1的控制端输入上一级的第一级联信号ST_N-1，第四开关管PT4的控制端输入上一级的第二级联信号XST_N-1，第二开关管PT2的控制端输入本级的第一时钟信号CK_1，第三开关管PT3的控制端也输入本级的第一时钟信号CK_1。这里的本级的第一时钟信号CK_1与第一优选实施例中的第一时钟信号反向，即可达到与第一优选实施例同样的技术效果。同时由于NMOS管和PMOS管互补的特性，可以有效的降低扫描驱动电流工作时的电容耦合效应。
本优选实施例的扫描驱动电路的具体工作原理与上述的第一优选实施例的描述相同或相似，具体请参见上述第一优选实施例中的相关描述。
因此本优选实施例的扫描驱动电路在第一优选实施例的基础上进一步加强了扫描驱动电路的可靠性以及稳定性。
请参照图5，图5为本发明的扫描驱动电路的第三优选实施例的结构示意图。在第一优选实施例的基础上，本优选实施例的扫描驱动电路30的输入控制模块31的第一开关管PT1、第二开关管PT2、第三开关管PT3以及第四开关管PT4均为PMOS管，第一开关管PT1的控制端输入上一级的第二级联信号XST_N-1，第四开关管PT4的控制端输入上一级的第一级联信号ST_N-1，第二开关管PT2的控制端输入本级的第一时钟信号CK_1，第三开关管PT3的控制端也输入本级的第一时钟信号CK_1。这里的本级的第一时钟信号CK_1与第一优选实施例中的第一时钟信号反向，即可达到与第一优选实施例同样的技术效果。同时由于NMOS管和PMOS管互补的特性，可以有效的降低扫描驱动电流工作时的电容耦合效应。
本优选实施例的扫描驱动电路的具体工作原理与上述的第一优选实施例的描述相同或相似，具体请参见上述第一优选实施例中的相关描述。
因此本优选实施例的扫描驱动电路在第一优选实施例的基础上进一步加强了扫描驱动电路的可靠性以及稳定性。
请参照图6，图6为本发明的扫描驱动电路的第四优选实施例的结构示意图。在第一优选实施例的基础上，本优选实施例的扫描驱动电路40的输入控制模块41的第一开关管PT1和第四开关管PT4为PMOS管，第二开关管PT2和第三开关管PT3为NMOS管，第一开关管PT1的控制端输入上一级的第二级联信号XST_N-1，第四开关管PT4的控制端输入上一级的第一级联信号ST_N-1，第二开关管PT2的控制端输入本级的第一时钟信号CK_1，第三开关管PT3的控制端也输入本级的第一时钟信号CK_1。这里的本级的第一时钟信号CK_1与第一优选实施例中的第一时钟信号同向，即可达到与第一优选实施例同样的技术效果。同时由于NMOS管和PMOS管互补的特性，可以有效的降低扫描驱动电流工作时的电容耦合效应。
本优选实施例的扫描驱动电路的具体工作原理与上述的第一优选实施例的描述相同或相似，具体请参见上述第一优选实施例中的相关描述。
因此本优选实施例的扫描驱动电路在第一优选实施例的基础上进一步加强了扫描驱动电路的可靠性以及稳定性。
本发明的扫描驱动电路通过反相的第一级联信号以及第二级联信号进行锁存模块的驱动，不需要对时钟信号进行反相操作，从而减小了扫描驱动电路的总体体积，且整个扫描驱动电路的动态功耗较小；解决了现有的扫描驱动电路的体积较大且动态功耗较大的技术问题。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种扫描驱动电路，用于对级联的扫描线进行驱动操作，其包括：
    输入控制模块，用于输入本级的第一时钟信号以及上一级的级联信号，并根据本级的所述第一时钟信号以及上一级的所述级联信号产生控制信号；
    锁存模块，用于对所述控制信号进行锁存操作；
    驱动信号产生模块，用于根据所述控制信号以及本级的第二时钟信号产生驱动信号；
    输出控制模块，用于根据所述驱动信号输出本级的扫描信号以及本级的级联信号；
    恒压高电平源，用于提供高电平电压；以及
    恒压低电平源，用于提供低电平电压；
    其中所述级联信号包括第一级联信号以及第二级联信号，所述第一级联信号和所述第二级联信号的相位相反；
    所述输入控制模块包括第一开关管、第二开关管、第三开关管以及第四开关管；
    所述第一开关管的控制端输入上一级的所述第一级联信号，所述第一开关管的输入端与所述恒压高电平源连接，所述第一开关管的输出端与所述第二开关管的输入端连接；
    所述第二开关管的控制端输入本级的所述第一时钟信号，所述第二开关管的输出端分别与所述第三开关管的输入端以及控制信号输出端连接；
    所述第三开关管的控制端输入本级的所述第一时钟信号，所述第三开关管的输出端与所述第四开关管的输出端连接；
    所述第四开关管的控制端输入上一级的所述第二级联信号，所述第四开关管的输入端与所述恒压低电平源连接；
    所述锁存模块包括第五开关管、第六开关管、第七开关管以及第八开关管；
    所述第五开关管的输入端与所述恒压高电平源连接，所述第五开关管的输出端与所述控制信号输出端连接；
    所述第六开关管的控制端与所述第五开关管的控制端连接，所述第六开关管的输入端与所述恒压低电平源连接，所述第六开关管的输出端与所述控制信号输出端连接；
    所述第七开关管的控制端与所述控制信号输出端连接，所述第七开关管的输入端与所述恒压高电平源连接，所述第七开关管的输出端与所述第五开关管的控制端连接；
    所述第八开关管的控制端与所述控制信号输出端连接，所述第八开关管的输入端与所述恒压低电平源连接，所述第八开关管的输出端与所述第五开关管的控制端连接；
    其中所述第五开关管和所述第七开关管为PMOS管，所述第六开关管和第八开关管为NMOS管。
  2. 根据权利要求1所述的扫描驱动电路，其中第一级的所述扫描驱动电路输入的上一级的所述第一级联信号为启动信号，第一级的所述扫描驱动电路输入的上一级的所述第二级联信号为所述启动信号的反相信号。
  3. 根据权利要求1所述的扫描驱动电路，其中所述驱动信号产生模块包括第九开关管、第十开关管、第十一开关管以及第十二开关管；
    所述第九开关管的控制端与所述锁存模块的输出端连接，所述第九开关管的输入端与所述恒压高电平源连接，所述第九开关管的输出端与所述驱动信号产生模块的输出端连接；
    所述第十开关管的控制端输入本级的第二时钟信号，所述第十开关管的输入端与所述恒压高电平源连接，所述第十开关管的输出端与所述驱动信号产生模块的输出端连接；
    所述第十一开关管的控制端与所述锁存模块的输出端连接，所述第十一开关管的输入端与所述第十二开关管的输出端连接，所述第十一开关管的输出端与所述驱动信号产生模块的输出端连接；
    所述第十二开关管的控制端输入本级的第二时钟信号，所述第十二开关管的输入端与所述恒压低电平源连接；
    其中所述第九开关管和所述第十开关管为PMOS管，所述第十一开关管和第十二开关管为NMOS管。
  4. 根据权利要求3所述的扫描驱动电路，其中所述驱动信号产生模块的输出端输出本级的驱动信号，所述驱动信号也为本级的第二级联信号。
  5. 根据权利要求1所述的扫描驱动电路，其中所述输出控制模块包括第十三开关管、第十四开关管、第十五开关管、第十六开关管、第十七开关管以及第十八开关管；
    所述第十三开关管的控制端与所述驱动信号产生模块的输出端连接，所述第十三开关管的输入端与所述恒压高电平源连接，所述第十三开关管的输出端分别与所述第十五开关管的控制端和所述第十六开关管的控制端连接；
    所述第十四开关管的控制端与所述驱动信号产生模块的输出端连接，所述第十四开关管的输入端与所述恒压低电平源连接，所述第十四开关管的输出端分别与所述十五开关管的控制端和所述第十六开关管的控制端连接；
    所述第十五开关管的输入端与所述恒压高电平源连接，所述第十五开关管的输出端分别与所述第十七开关管的控制端和所述第十八开关管的控制端连接；
    所述第十六开关管的输入端与所述恒压低电平源连接，所述第十六开关管的输出端分别与所述第十七开关管的控制端和所述第十八开关管的控制端连接；
    所述第十七开关管的输入端与所述恒压高电平源连接，所述第十七开关管的输出端与所述输出控制模块的输出端连接；
    所述第十八开关管的输入端与所述恒压低电平源连接，所述第十八开关管的输出端与所述输出控制模块的输出端连接；
    其中所述第十三开关管、所述第十五开关管以及所述第十七开关管为PMOS管，所述第十四开关管、所述第十六开关管以及所述第十八开关管为NMOS管。
  6. 根据权利要求5所述的扫描驱动电路，其中所述第十三开关管的输出端输出本级的第一级联信号。
  7. 根据权利要求1所述的扫描驱动电路，其中所述第一开关管、所述第二开关管、所述第三开关管以及所述第四开关管均为NMOS管或PMOS管。
  8. 根据权利要求1所述的扫描驱动电路，其中所述第一开关管和所述第四开关管为NMOS管，所述第二开关管和所述第三开关管的PMOS管。
  9. 根据权利要求1所述的扫描驱动电路，其中所述第一开关管和所述第四开关管为PMOS管，所述第二开关管和所述第三开关管为NMOS管。
  10. 一种扫描驱动电路，用于对级联的扫描线进行驱动操作，其包括：
    输入控制模块，用于输入本级的第一时钟信号以及上一级的级联信号，并根据本级的所述第一时钟信号以及上一级的所述级联信号产生控制信号；
    锁存模块，用于对所述控制信号进行锁存操作；
    驱动信号产生模块，用于根据所述控制信号以及本级的第二时钟信号产生驱动信号；
    输出控制模块，用于根据所述驱动信号输出本级的扫描信号以及本级的级联信号；
    恒压高电平源，用于提供高电平电压；以及
    恒压低电平源，用于提供低电平电压。
  11. 根据权利要求10所述的扫描驱动电路，其中所述级联信号包括第一级联信号以及第二级联信号，所述第一级联信号和所述第二级联信号的相位相反；
    所述输入控制模块包括第一开关管、第二开关管、第三开关管以及第四开关管；
    所述第一开关管的控制端输入上一级的所述第一级联信号，所述第一开关管的输入端与所述恒压高电平源连接，所述第一开关管的输出端与所述第二开关管的输入端连接；
    所述第二开关管的控制端输入本级的所述第一时钟信号，所述第二开关管的输出端分别与所述第三开关管的输入端以及控制信号输出端连接；
    所述第三开关管的控制端输入本级的所述第一时钟信号，所述第三开关管的输出端与所述第四开关管的输出端连接；
    所述第四开关管的控制端输入上一级的所述第二级联信号，所述第四开关管的输入端与所述恒压低电平源连接。
  12. 根据权利要求11所述的扫描驱动电路，其中第一级的所述扫描驱动电路输入的上一级的所述第一级联信号为启动信号，第一级的所述扫描驱动电路输入的上一级的所述第二级联信号为所述启动信号的反相信号。
  13. 根据权利要求10所述的扫描驱动电路，其中所述锁存模块包括第五开关管、第六开关管、第七开关管以及第八开关管；
    所述第五开关管的输入端与所述恒压高电平源连接，所述第五开关管的输出端与所述控制信号输出端连接；
    所述第六开关管的控制端与所述第五开关管的控制端连接，所述第六开关管的输入端与所述恒压低电平源连接，所述第六开关管的输出端与所述控制信号输出端连接；
    所述第七开关管的控制端与所述控制信号输出端连接，所述第七开关管的输入端与所述恒压高电平源连接，所述第七开关管的输出端与所述第五开关管的控制端连接；
    所述第八开关管的控制端与所述控制信号输出端连接，所述第八开关管的输入端与所述恒压低电平源连接，所述第八开关管的输出端与所述第五开关管的控制端连接；
    其中所述第五开关管和所述第七开关管为PMOS管，所述第六开关管和第八开关管为NMOS管。
  14. 根据权利要求10所述的扫描驱动电路，其中所述驱动信号产生模块包括第九开关管、第十开关管、第十一开关管以及第十二开关管；
    所述第九开关管的控制端与所述锁存模块的输出端连接，所述第九开关管的输入端与所述恒压高电平源连接，所述第九开关管的输出端与所述驱动信号产生模块的输出端连接；
    所述第十开关管的控制端输入本级的第二时钟信号，所述第十开关管的输入端与所述恒压高电平源连接，所述第十开关管的输出端与所述驱动信号产生模块的输出端连接；
    所述第十一开关管的控制端与所述锁存模块的输出端连接，所述第十一开关管的输入端与所述第十二开关管的输出端连接，所述第十一开关管的输出端与所述驱动信号产生模块的输出端连接；
    所述第十二开关管的控制端输入本级的第二时钟信号，所述第十二开关管的输入端与所述恒压低电平源连接；
    其中所述第九开关管和所述第十开关管为PMOS管，所述第十一开关管和第十二开关管为NMOS管。
  15. 根据权利要求14所述的扫描驱动电路，其中所述驱动信号产生模块的输出端输出本级的驱动信号，所述驱动信号也为本级的第二级联信号。
  16. 根据权利要求10所述的扫描驱动电路，其中所述输出控制模块包括第十三开关管、第十四开关管、第十五开关管、第十六开关管、第十七开关管以及第十八开关管；
    所述第十三开关管的控制端与所述驱动信号产生模块的输出端连接，所述第十三开关管的输入端与所述恒压高电平源连接，所述第十三开关管的输出端分别与所述第十五开关管的控制端和所述第十六开关管的控制端连接；
    所述第十四开关管的控制端与所述驱动信号产生模块的输出端连接，所述第十四开关管的输入端与所述恒压低电平源连接，所述第十四开关管的输出端分别与所述十五开关管的控制端和所述第十六开关管的控制端连接；
    所述第十五开关管的输入端与所述恒压高电平源连接，所述第十五开关管的输出端分别与所述第十七开关管的控制端和所述第十八开关管的控制端连接；
    所述第十六开关管的输入端与所述恒压低电平源连接，所述第十六开关管的输出端分别与所述第十七开关管的控制端和所述第十八开关管的控制端连接；
    所述第十七开关管的输入端与所述恒压高电平源连接，所述第十七开关管的输出端与所述输出控制模块的输出端连接；
    所述第十八开关管的输入端与所述恒压低电平源连接，所述第十八开关管的输出端与所述输出控制模块的输出端连接；
    其中所述第十三开关管、所述第十五开关管以及所述第十七开关管为PMOS管，所述第十四开关管、所述第十六开关管以及所述第十八开关管为NMOS管。
  17. 根据权利要求16所述的扫描驱动电路，其中所述第十三开关管的输出端输出本级的第一级联信号。
  18. 根据权利要求11所述的扫描驱动电路，其中所述第一开关管、所述第二开关管、所述第三开关管以及所述第四开关管均为NMOS管或PMOS管。
  19. 根据权利要求11所述的扫描驱动电路，其中所述第一开关管和所述第四开关管为NMOS管，所述第二开关管和所述第三开关管的PMOS管。
  20. 根据权利要求11所述的扫描驱动电路，其中所述第一开关管和所述第四开关管为PMOS管，所述第二开关管和所述第三开关管为NMOS管。
PCT/CN2015/086485 2015-07-02 2015-08-10 一种扫描驱动电路 WO2017000359A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/779,016 US9786240B2 (en) 2015-07-02 2015-08-10 Scan driving circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510381670.7A CN105096853B (zh) 2015-07-02 2015-07-02 一种扫描驱动电路
CN201510381670.7 2015-07-02

Publications (1)

Publication Number Publication Date
WO2017000359A1 true WO2017000359A1 (zh) 2017-01-05

Family

ID=54577145

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/086485 WO2017000359A1 (zh) 2015-07-02 2015-08-10 一种扫描驱动电路

Country Status (3)

Country Link
US (1) US9786240B2 (zh)
CN (1) CN105096853B (zh)
WO (1) WO2017000359A1 (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105374331B (zh) * 2015-12-01 2017-11-17 武汉华星光电技术有限公司 栅极驱动电路和使用栅极驱动电路的显示器
KR102487109B1 (ko) * 2015-12-15 2023-01-09 엘지디스플레이 주식회사 게이트 구동회로 및 이를 포함하는 표시 장치
CN106098001B (zh) * 2016-08-04 2018-11-02 武汉华星光电技术有限公司 Goa电路及液晶显示面板
US10373578B2 (en) 2016-11-28 2019-08-06 Wuhan China Star Optoelectronics Technology Co., Ltd. GOA driving circuit
CN106710548B (zh) * 2016-12-28 2018-06-01 武汉华星光电技术有限公司 Cmos goa电路
CN107564459B (zh) * 2017-10-31 2021-01-05 合肥京东方光电科技有限公司 移位寄存器单元、栅极驱动电路、显示装置及驱动方法
KR102575564B1 (ko) * 2018-03-26 2023-09-08 삼성디스플레이 주식회사 주사 구동부
CN108538237B (zh) * 2018-04-26 2020-06-23 京东方科技集团股份有限公司 一种栅极驱动电路、方法及显示装置
KR102693252B1 (ko) * 2018-11-23 2024-08-12 삼성디스플레이 주식회사 주사 구동부
CN111261108A (zh) * 2020-02-11 2020-06-09 深圳市华星光电半导体显示技术有限公司 栅极驱动电路
KR20220092272A (ko) * 2020-12-24 2022-07-01 엘지디스플레이 주식회사 게이트 구동부 및 이를 포함하는 표시 장치

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110150169A1 (en) * 2009-12-22 2011-06-23 Au Optronics Corp. Shift register
CN104021750A (zh) * 2014-05-30 2014-09-03 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及驱动方法和显示装置
CN104409054A (zh) * 2014-11-03 2015-03-11 深圳市华星光电技术有限公司 低温多晶硅薄膜晶体管goa电路
CN104464659A (zh) * 2014-11-03 2015-03-25 深圳市华星光电技术有限公司 低温多晶硅薄膜晶体管goa电路
CN104464663A (zh) * 2014-11-03 2015-03-25 深圳市华星光电技术有限公司 低温多晶硅薄膜晶体管goa电路
CN104700799A (zh) * 2015-03-17 2015-06-10 深圳市华星光电技术有限公司 栅极驱动电路及显示装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4111128B2 (ja) * 2003-11-28 2008-07-02 カシオ計算機株式会社 表示駆動装置及び表示装置並びにその駆動制御方法
US9418613B2 (en) 2014-11-03 2016-08-16 Shenzhen China Star Optoelectronics Technology Co., Ltd. GOA circuit of LTPS semiconductor TFT
CN104700788B (zh) 2015-04-01 2017-12-08 京东方科技集团股份有限公司 一种显示面板的驱动装置及显示面板

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110150169A1 (en) * 2009-12-22 2011-06-23 Au Optronics Corp. Shift register
CN104021750A (zh) * 2014-05-30 2014-09-03 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及驱动方法和显示装置
CN104409054A (zh) * 2014-11-03 2015-03-11 深圳市华星光电技术有限公司 低温多晶硅薄膜晶体管goa电路
CN104464659A (zh) * 2014-11-03 2015-03-25 深圳市华星光电技术有限公司 低温多晶硅薄膜晶体管goa电路
CN104464663A (zh) * 2014-11-03 2015-03-25 深圳市华星光电技术有限公司 低温多晶硅薄膜晶体管goa电路
CN104700799A (zh) * 2015-03-17 2015-06-10 深圳市华星光电技术有限公司 栅极驱动电路及显示装置

Also Published As

Publication number Publication date
US20170004796A1 (en) 2017-01-05
CN105096853A (zh) 2015-11-25
CN105096853B (zh) 2017-04-19
US9786240B2 (en) 2017-10-10

Similar Documents

Publication Publication Date Title
WO2017000359A1 (zh) 一种扫描驱动电路
WO2018053957A1 (zh) 扫描驱动电路及显示装置
WO2017075843A1 (zh) 一种扫描驱动装置
WO2017197687A1 (zh) 一种cmos goa电路结构及液晶显示面板
WO2017049659A1 (zh) 一种goa电路、显示装置和goa电路的驱动方法
WO2016192176A1 (zh) 一种扫描驱动电路
WO2019109454A1 (zh) 一种 goa 电路
WO2016074269A1 (zh) 一种扫描驱动电路
WO2016074264A1 (zh) 一种扫描驱动电路
WO2015137709A1 (ko) 표시장치
WO2017020327A1 (zh) 一种扫描驱动电路
WO2016065657A1 (zh) 阵列基板行驱动电路及液晶显示装置
WO2017054262A1 (zh) 一种goa电路及液晶显示器
WO2015182998A1 (ko) 시프트 회로, 시프트 레지스터 및 표시장치
WO2018120676A1 (zh) 一种像素充电方法、电路、液晶显示屏及液晶显示装置
WO2017197686A1 (zh) Goa 驱动电路
WO2011095099A1 (zh) 栅极驱动电路单元、栅极驱动电路及显示装置
WO2017000360A1 (zh) 一种扫描驱动电路
WO2017124598A1 (zh) 一种栅极驱动电路及显示面板
WO2019010765A1 (zh) 一种 amoled 像素驱动电路及像素驱动方法
WO2016074283A1 (zh) 用于液晶显示的goa电路及液晶显示装置
WO2016074303A1 (zh) 一种扫描驱动电路
WO2016165178A1 (zh) 源极驱动器及液晶显示器
WO2017124597A1 (zh) 一种栅极驱动电路及其液晶显示器
WO2018014412A1 (zh) Goa电路及液晶显示面板

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14779016

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15896889

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15896889

Country of ref document: EP

Kind code of ref document: A1