WO2017124597A1 - 一种栅极驱动电路及其液晶显示器 - Google Patents

一种栅极驱动电路及其液晶显示器 Download PDF

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Publication number
WO2017124597A1
WO2017124597A1 PCT/CN2016/074227 CN2016074227W WO2017124597A1 WO 2017124597 A1 WO2017124597 A1 WO 2017124597A1 CN 2016074227 W CN2016074227 W CN 2016074227W WO 2017124597 A1 WO2017124597 A1 WO 2017124597A1
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WIPO (PCT)
Prior art keywords
switch tube
type switch
transmission
control signal
control
Prior art date
Application number
PCT/CN2016/074227
Other languages
English (en)
French (fr)
Inventor
赵莽
Original Assignee
武汉华星光电技术有限公司
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Priority to US14/917,947 priority Critical patent/US10115363B2/en
Publication of WO2017124597A1 publication Critical patent/WO2017124597A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0218—Addressing of scan or signal lines with collection of electrodes in groups for n-dimensional addressing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the invention relates to a device in the field of liquid crystal display technology, in particular to a blue phase liquid crystal display panel.
  • Gate Driver On Array is a technology that uses the existing thin film transistor liquid crystal display Array process to make the Gate scan drive signal circuit on the Array substrate to realize the drive mode of Gate progressive scan.
  • the scanning drive signal of the current stage is generated by controlling the voltage of the input node of the output circuit, but the voltage of the input node is generally generated by the high reference circuit path, and the high reference potential is divided by several transistors. The loss will in turn affect the speed of the scanning drive signal of this stage, which will affect the normal driving of the panel. In severe cases, the entire driving circuit will be ineffective.
  • the technical problem to be solved by the present invention is to provide a gate driving circuit and a liquid crystal display thereof, which can improve the driving capability of the intermediate transmission signal and reduce the generation delay of the scanning driving signal of the current stage.
  • a technical solution adopted by the present invention is to provide a gate driving circuit including: an input circuit, a reset and control circuit, an inverting circuit, a latch circuit, and an output circuit, and the input circuit is based on the upper phase of the upper stage.
  • the scan driving signal, the upper inverted scan drive signal, and the first control signal output by the latch circuit generate a second control signal
  • the reset and control circuit generates a third control signal according to the reset signal, the first control signal, and the second control signal
  • the phase circuit performs at least one inversion processing on the third control signal, and generates a fourth control signal
  • the output circuit generates the normal phase scan drive signal and the inversion scan drive signal of the current stage according to the fourth control signal and the first clock signal
  • the latch circuit generates a first control signal according to the third control signal and the second clock signal, and further latches or changes a voltage state of the third control signal according to the second clock signal;
  • the input circuit comprises a first transmission gate and a first P-type switch tube
  • the N-type control end of the first transmission gate receives the upper-stage inversion scan driving signal
  • the P-type control end of the first transmission gate receives the upper-level positive-phase scanning driving signal
  • the first transmission end of the first transmission gate receives the first control signal
  • a second transmission end of a transmission gate outputs a second control signal
  • the control end of the first P-type switch tube receives the upper-stage inversion scan driving signal, the first transmission end of the first P-type switch tube is connected to the high reference potential, and the second transmission end of the first P-type switch tube is connected to the first transmission gate Second transmission end;
  • the output circuit comprises a NAND gate and a plurality of second inverters arranged in series;
  • a first input end of the NAND gate receives a first clock signal
  • a second input end of the NAND gate receives a fourth control signal
  • an output end of the NAND gate is connected to an upstream input end of the plurality of second inverters arranged in series
  • the output ends of the even-numbered second inverters of the plurality of second inverters arranged in series output the inverted scanning drive signal of the current stage, and the odd-numbered second reverses of the plurality of second inverters arranged in series
  • the output of the phase converter outputs the positive phase scan drive signal of this stage.
  • the present invention further provides a gate driving circuit, comprising: an input circuit, a reset and control circuit, an inverting circuit, a latch circuit, and an output circuit, and the input circuit is driven by the upper-level positive phase scanning driving signal, the upper level
  • the inverting scan driving signal and the first control signal outputted by the latch circuit generate a second control signal
  • the reset and control circuit generates a third control signal according to the reset signal, the first control signal and the second control signal
  • the inverting circuit pairs the third
  • the control signal performs at least one inversion processing, and generates a fourth control signal
  • the output circuit generates the current-phase positive-phase scan driving signal and the current-stage inverted-scan driving signal according to the fourth control signal and the first clock signal
  • the latch circuit is The three control signals and the second clock signal generate a first control signal, thereby latching or changing the voltage state of the third control signal according to the second clock signal.
  • the input circuit comprises a first transmission gate and a first P-type switch tube
  • the N-type control end of the first transmission gate receives the upper-stage inversion scan driving signal
  • the P-type control end of the first transmission gate receives the upper-level positive-phase scanning driving signal
  • the first transmission end of the first transmission gate receives the first control signal
  • a second transmission end of a transmission gate outputs a second control signal
  • the control end of the first P-type switch tube receives the upper-stage inversion scan driving signal, the first transmission end of the first P-type switch tube is connected to the high reference potential, and the second transmission end of the first P-type switch tube is connected to the first transmission gate The second transmission end.
  • the reset and control circuit includes a second P-type switch tube, a third P-type switch tube, a fourth P-type switch tube, a first N-type switch tube, a second N-type switch tube, and a third N-type switch tube;
  • the first transmission end of the second P-type switch tube is connected to the high reference potential;
  • the first transmission end of the third P-type switch tube is connected to the second transmission end of the second P-type switch tube, and the control end of the second P-type switch tube and the One of the control terminals of the three P-type switch tube receives the first control signal, and the other of the control end of the second P-type switch tube and the control end of the third P-type switch tube receives the second control signal;
  • the fourth P-type The control end of the switch tube receives the reset signal, the first transmission end of the fourth P-type switch tube is connected to the high reference potential, and the second transmission end of the fourth P-type switch tube is connected to the second transmission end of the third P-type switch tube;
  • the third control signal is output from a connection node of the second transmission end of the third P-type switch tube and the second transmission end of the fourth P-type switch tube.
  • the inverting circuit includes a first inverter; the input of the first inverter receives the third control signal, and the output of the first inverter outputs the fourth control signal.
  • the output circuit comprises a NAND gate and a plurality of second inverters arranged in series;
  • a first input end of the NAND gate receives a first clock signal
  • a second input end of the NAND gate receives a fourth control signal
  • an output end of the NAND gate is connected to an upstream input end of the plurality of second inverters arranged in series
  • the output ends of the even-numbered second inverters of the plurality of second inverters arranged in series output the inverted scanning drive signal of the current stage, and the odd-numbered second reverses of the plurality of second inverters arranged in series
  • the output of the phase converter outputs the positive phase scan drive signal of this stage.
  • the latch circuit includes a second transmission gate and a fourth N-type switch tube; the P-type control terminal of the second transmission gate receives the third control signal, and the N-type control terminal of the second transmission gate receives the fourth control signal, and the second The first transmission end of the transmission gate receives the second clock signal, the second transmission end of the second transmission gate outputs the first control signal; the control end of the fourth N-type switch tube receives the third control signal, and the fourth N-type switch tube The first transmission end is connected to the low reference potential, and the first transmission end of the fourth N-type switch tube is connected to the second transmission end of the second transmission gate.
  • the latch circuit further includes a third inverter, the input of the third inverter receives the second clock signal, and the output of the third inverter is coupled to the first transmission end of the second transmission gate.
  • the input circuit includes a first transmission gate and a first N-type switch tube
  • the N-type control end of the first transmission gate receives the upper-stage inversion scan driving signal
  • the P-type control end of the first transmission gate receives the upper-level positive-phase scanning driving signal
  • the first transmission end of the first transmission gate receives the first control signal
  • a second transmission end of a transmission gate outputs a second control signal
  • the control end of the first N-type switch tube receives the upper-phase normal phase scan drive signal, the first transmission end of the first N-type switch tube is connected to the low reference potential, and the second pass of the first N-type switch tube
  • the reset and control circuit comprises a second N-type switch tube, a third N-type switch tube, a fourth N-type switch tube, a first P-type switch tube, a second P-type switch tube, and a third P-type switch tube;
  • the first transmission end of the second N-type switch tube is connected to a low reference potential
  • a first transmission end of the third N-type switch tube is connected to a second transmission end of the second N-type switch tube, and one of the control end of the second N-type switch tube and the third N-type switch tube receives the first control signal, The other of the control end of the second N-type switch tube and the third N-type switch tube receives the third control signal;
  • the control end of the fourth N-type switch tube receives the reset signal, the first transmission end of the fourth N-type switch tube is connected to the low reference potential, and the second transmission end of the fourth N-type switch tube is connected to the second end of the third N-type switch tube Transmission end
  • the control end of the first P-type switch tube receives a reset signal, and the first transmission end of the first P-type switch tube is connected to a high reference potential;
  • the control end of the second P-type switch tube receives the first control signal, the first transmission end of the second P-type switch tube is connected to the second transmission end of the first P-type switch tube, and the second transmission end of the second P-type switch tube Connecting a connection node of the second transmission end of the third N-type switch tube and the second transmission end of the fourth N-type switch tube;
  • the control end of the third P-type switch tube receives the second control signal, the first transmission end of the third P-type switch tube is connected to the second transmission end of the first P-type switch tube, and the second transmission end of the third P-type switch tube Connecting a connection node of the second transmission end of the third N-type switch tube and the second transmission end of the fourth N-type switch tube;
  • the third control signal is output from a connection node of the second transmission end of the third N-type switch tube and the second transmission end of the fourth N-type switch tube.
  • the inverter circuit comprises a first inverter and a second inverter
  • the input of the first inverter receives the third control signal
  • the input end of the second inverter is connected to the input end of the first inverter, and the input end of the second inverter outputs the fourth control signal;
  • the output circuit includes a NAND gate and a plurality of third inverters arranged in series;
  • a first input end of the NAND gate receives a first clock signal
  • a second input end of the NAND gate receives a fourth control signal
  • an output end of the NAND gate is connected to an upstream input end of the plurality of second inverters arranged in series
  • the output ends of the even-numbered second inverters of the plurality of second inverters arranged in series output the inverted scanning drive signal of the current stage, and the odd-numbered second reverses of the plurality of second inverters arranged in series
  • the output of the phase converter outputs the positive phase scan driving signal of the current stage;
  • the latch circuit includes a second transfer gate and a fourth P-type switch tube;
  • the N-type control terminal of the second transmission gate receives the third control signal
  • the P-type control terminal of the second transmission gate receives the fourth control signal
  • the first transmission terminal of the second transmission gate receives the second clock signal
  • the second transmission gate The second transmission end outputs a first control signal
  • the control end of the fourth P-type switch tube receives the third control signal, the first transmission end of the fourth P-type switch tube is connected to the low reference potential, and the first transmission end of the fourth P-type switch tube is connected to the second transmission gate. Transmitter.
  • the present invention further provides a liquid crystal display comprising a plurality of cascaded gate drive circuits, the gate drive circuit comprising: an input circuit, a reset and control circuit, an inverting circuit, and a latch circuit And an output circuit, the input circuit generates a second control signal according to the upper positive scan drive signal, the upper reverse scan drive signal, and the first control signal output by the latch circuit, and the reset and control circuit is configured according to the reset signal, the first control signal, and the first
  • the second control signal generates a third control signal
  • the inverting circuit performs at least one inversion processing on the third control signal, and generates a fourth control signal
  • the output circuit generates the current phase positive phase scan driving according to the fourth control signal and the first clock signal.
  • the signal and the current stage invert the scan driving signal, the latch circuit generates a first control signal according to the third control signal and the second clock signal, and further latches or changes the voltage state of the third control signal according to the second clock signal.
  • the input circuit comprises a first transmission gate and a first P-type switch tube
  • the N-type control end of the first transmission gate receives the upper-stage inversion scan driving signal
  • the P-type control end of the first transmission gate receives the upper-level positive-phase scanning driving signal
  • the first transmission end of the first transmission gate receives the first control signal
  • a second transmission end of a transmission gate outputs a second control signal
  • the control end of the first P-type switch tube receives the upper-stage inversion scan driving signal, the first transmission end of the first P-type switch tube is connected to the high reference potential, and the second transmission end of the first P-type switch tube is connected to the first transmission gate The second transmission end.
  • the reset and control circuit includes a second P-type switch tube, a third P-type switch tube, a fourth P-type switch tube, a first N-type switch tube, a second N-type switch tube, and a third N-type switch tube;
  • the first transmission end of the second P-type switch tube is connected to a high reference potential
  • the first transmission end of the third P-type switch tube is connected to the second transmission end of the second P-type switch tube, and the control end of the second P-type switch tube and the control end of the third P-type switch tube receive the first control a signal, the other of the control end of the second P-type switch tube and the control end of the third P-type switch tube receives the second control signal;
  • the control end of the fourth P-type switch tube receives the reset signal, the first transmission end of the fourth P-type switch tube is connected to the high reference potential, and the second transmission end of the fourth P-type switch tube is connected to the second of the third P-type switch tube Transmission end
  • the control end of the first N-type switch tube receives a reset signal, and the first transmission end of the first N-type switch tube is connected to the connection node of the second transmission end of the third P-type switch tube and the second transmission end of the fourth P-type switch tube ;
  • the control end of the second N-type switch tube receives the first control signal, the first transmission end of the second N-type switch tube is connected to the second transmission end of the first N-type switch tube, and the second transmission end of the second N-type switch tube Connect a low reference potential;
  • the control end of the third N-type switch tube receives the second control signal, the first transmission end of the third N-type switch tube is connected to the second transmission end of the first N-type switch tube, and the second transmission end of the third N-type switch tube Connect a low reference potential;
  • the third control signal is output from a connection node of the second transmission end of the third P-type switch tube and the second transmission end of the fourth P-type switch tube.
  • the inverter circuit comprises a first inverter
  • the input of the first inverter receives the third control signal, and the output of the first inverter outputs the fourth control signal.
  • the output circuit comprises a NAND gate and a plurality of second inverters arranged in series;
  • a first input end of the NAND gate receives a first clock signal
  • a second input end of the NAND gate receives a fourth control signal
  • an output end of the NAND gate is connected to an upstream input end of the plurality of second inverters arranged in series
  • the output ends of the even-numbered second inverters of the plurality of second inverters arranged in series output the inverted scanning drive signal of the current stage, and the odd-numbered second reverses of the plurality of second inverters arranged in series
  • the output of the phase converter outputs the positive phase scan drive signal of this stage.
  • the latch circuit comprises a second transmission gate and a fourth N-type switch tube
  • the P-type control terminal of the second transmission gate receives the third control signal
  • the N-type control terminal of the second transmission gate receives the fourth control signal
  • the first transmission terminal of the second transmission gate receives the second clock signal
  • the second transmission gate The second transmission end outputs a first control signal
  • the control end of the fourth N-type switch tube receives the third control signal, the first transmission end of the fourth N-type switch tube is connected to the low reference potential, and the first transmission end of the fourth N-type switch tube is connected to the second transmission gate. Transmitter.
  • the latch circuit further includes a third inverter, the input of the third inverter receives the second clock signal, and the output of the third inverter is coupled to the first transmission end of the second transmission gate.
  • the input circuit includes a first transmission gate and a first N-type switch tube
  • the N-type control end of the first transmission gate receives the upper-stage inversion scan driving signal
  • the P-type control end of the first transmission gate receives the upper-level positive-phase scanning driving signal
  • the first transmission end of the first transmission gate receives the first control signal
  • a second transmission end of a transmission gate outputs a second control signal
  • the control end of the first N-type switch tube receives the upper-phase normal phase scan drive signal, the first transmission end of the first N-type switch tube is connected to the low reference potential, and the second pass of the first N-type switch tube
  • the reset and control circuit comprises a second N-type switch tube, a third N-type switch tube, a fourth N-type switch tube, a first P-type switch tube, a second P-type switch tube, and a third P-type switch tube;
  • the first transmission end of the second N-type switch tube is connected to a low reference potential
  • a first transmission end of the third N-type switch tube is connected to a second transmission end of the second N-type switch tube, and one of the control end of the second N-type switch tube and the third N-type switch tube receives the first control signal, The other of the control end of the second N-type switch tube and the third N-type switch tube receives the third control signal;
  • the control end of the fourth N-type switch tube receives the reset signal, the first transmission end of the fourth N-type switch tube is connected to the low reference potential, and the second transmission end of the fourth N-type switch tube is connected to the second end of the third N-type switch tube Transmission end
  • the control end of the first P-type switch tube receives a reset signal, and the first transmission end of the first P-type switch tube is connected to a high reference potential;
  • the control end of the second P-type switch tube receives the first control signal, the first transmission end of the second P-type switch tube is connected to the second transmission end of the first P-type switch tube, and the second transmission end of the second P-type switch tube Connecting a connection node of the second transmission end of the third N-type switch tube and the second transmission end of the fourth N-type switch tube;
  • the control end of the third P-type switch tube receives the second control signal, the first transmission end of the third P-type switch tube is connected to the second transmission end of the first P-type switch tube, and the second transmission end of the third P-type switch tube Connecting a connection node of the second transmission end of the third N-type switch tube and the second transmission end of the fourth N-type switch tube;
  • the third control signal is output from a connection node of the second transmission end of the third N-type switch tube and the second transmission end of the fourth N-type switch tube.
  • the inverter circuit comprises a first inverter and a second inverter
  • the input of the first inverter receives the third control signal
  • the input end of the second inverter is connected to the input end of the first inverter, and the input end of the second inverter outputs the fourth control signal;
  • the output circuit includes a NAND gate and a plurality of third inverters arranged in series;
  • a first input terminal of the NAND gate receives a first clock signal
  • a second input terminal of the NAND gate receives a fourth control signal
  • an output terminal of the NAND gate is connected to an upstream input end of the plurality of third inverters disposed in series
  • the output ends of the even-numbered third inverters of the plurality of third inverters arranged in series output the inverted scanning drive signal of the current stage, and the odd-numbered third of the plurality of third inverters arranged in series
  • the output of the phase converter outputs the positive phase scan driving signal of the current stage;
  • the latch circuit includes a second transfer gate and a fourth P-type switch tube;
  • the N-type control terminal of the second transmission gate receives the third control signal
  • the P-type control terminal of the second transmission gate receives the fourth control signal
  • the first transmission terminal of the second transmission gate receives the second clock signal
  • the second transmission gate The second transmission end outputs a first control signal
  • the control end of the fourth P-type switch tube receives the third control signal, the first transmission end of the fourth P-type switch tube is connected to the low reference potential, and the first transmission end of the fourth P-type switch tube is connected to the second transmission gate. Transmitter.
  • the gate driving circuit of the present invention is improved by changing the original circuit design, changing the original "OR” logic, and replacing it with "or NAND” logic.
  • the driving capability of the intermediate transmission signal reduces the generation delay of the scanning drive signal of this stage.
  • FIG. 1 is a schematic diagram showing the circuit structure of a first embodiment of a gate driving circuit of the present invention
  • FIG. 2 is a waveform timing diagram of the operation of the first embodiment of the gate driving circuit of the present invention.
  • FIG. 3 is a schematic structural diagram of a circuit of a second embodiment of a gate driving circuit of the present invention.
  • FIG. 4 is a waveform timing diagram of the operation of the second embodiment of the gate driving circuit of the present invention.
  • Fig. 5 is a schematic structural view of an embodiment of a liquid crystal display of the present invention.
  • the gate driving circuit includes an input circuit 11, a reset and control circuit 12, an inverting circuit 13, a latch circuit 14, and an output circuit 15.
  • the input circuit 11 generates a second control signal according to the upper normal phase scan drive signal G(N-1), the upper reverse scan drive signal XG(N-1), and the first control signal D1(N) output from the latch circuit 14.
  • the reset and control circuit 12 generates a third control signal D3(N) according to the reset signal Reset, the first control signal D1(N) and the second control signal D2(N), and the inverting circuit 13 controls the third
  • the signal D3(N) performs at least one inversion processing, and generates a fourth control signal D4(N)
  • the output circuit 15 generates the current-phase positive-phase scan driving signal G according to the fourth control signal D4(N) and the first clock signal CK1.
  • the latch circuit 14 generates a first control signal D1(N) according to the third control signal D3(N) and the second clock signal CK2, and further according to the second clock Signal CK2 latches or changes the voltage state of third control signal D3(N).
  • the input circuit 11 includes a first transmission gate C1 and a first P-type switching transistor TP1.
  • the first input gate C1 may be a CMOS transmission gate, and is composed of an NMOS transistor TN and a PMOS transistor TP in parallel, due to the structure of the MOS transistor. It is symmetrical, that is, the source and the drain can be used interchangeably. Therefore, the input terminal and the output terminal of the transmission gate can be used interchangeably, that is, the CMOS transmission gate has bidirectionality, so it is also called a controllable bidirectional switch. Further, the switching transistor mentioned in the present invention may be a thin film transistor.
  • the N-type control terminal of the first transmission gate C1 receives the upper-stage inverted scan driving signal XG(N-1), and the P-type control terminal of the first transmission gate receives the upper-level normal-phase scanning driving signal G(N-1), the first transmission
  • the first transmission end of the gate receives the first control signal D1(N)
  • the second transmission end of the first transmission gate C1 outputs the second control signal D2(N);
  • the control end of the first P-type switch tube TP1 receives the upper-stage inverted scan drive signal XG(N-1), the first transmission end of the first P-type switch tube is connected to the high reference potential VGH, and the first P-type switch tube TP1 is The second transmission end is connected to the second transmission end of the first transmission gate C1.
  • the reset and control circuit 12 includes a second P-type switch tube TP2, a third P-type switch tube TP3, a fourth P-type switch tube TP4, a first N-type switch tube TN1, a second N-type switch tube TN2, and a third N-type switch tube TN3.
  • the first transmission end of the second P-type switch tube TP2 is connected to the high reference potential VGH, and the first transmission end of the third P-type switch tube TP3 is connected to the second transmission end of the second P-type switch tube TP2, and the second P-type switch tube
  • One of the control end of the TP2 and the control end of the third P-type switch tube TP3 receives the first control signal D1(N), the control end of the second P-type switch tube TP2, and the control end of the third P-type switch tube TP3 The other receives the second control signal D2(N).
  • the second P-type switch tube TP2 receives the first control signal D1(N)
  • the control end of the third P-type switch tube TP3 receives the second control signal D2(N), and vice versa.
  • the control end of the fourth P-type switch tube TP4 receives the reset signal Reset, the first transmission end of the fourth P-type switch tube TP4 is connected to the high reference potential VGH, and the second transmission end of the fourth P-type switch tube TP4 is connected to the third P type.
  • the control end of the first N-type switch tube TN1 receives the reset signal Reset, and the first transmission end of the first N-type switch tube TN1 is connected to the second transmission end of the third P-type switch tube TP3 and the fourth P-type switch tube TP4 The connection node of the second transmission end.
  • the control end of the second N-type switch tube TN2 receives the first control signal D1(N), and the first transmission end of the second N-type switch tube TN2 is connected to the second transmission end of the first N-type switch tube TN1, the second N-type The second transmission end of the switching transistor TN2 is connected to the low reference potential VGL.
  • the control end of the third N-type switch tube TN3 receives the second control signal D2(N), and the first transmission end of the third N-type switch tube TN3 is connected to the second transmission end of the first N-type switch tube TN1, the third N-type The second transmission end of the switching transistor TN3 is connected to the low reference potential VGL.
  • the third control signal D3(N) is output from the connection node of the second transmission end of the third P-type switch tube TP3 and the second transmission end of the fourth P-type switch tube TP4.
  • the inverter circuit 13 includes a first inverter F1; the input terminal of the first inverter F1 receives the third control signal D3(N), and the output terminal of the first inverter F1 outputs a fourth control signal D4 (N). ).
  • the inverter can reverse the phase of the input signal by 180 degrees.
  • This circuit can be used in analog circuits such as audio amplification, clock oscillators, etc.
  • the inverter can be a TTL NOT gate or a CMOS inverter. .
  • the output circuit 15 includes a NAND gate YF1 and a plurality of second inverters F2 arranged in series.
  • the first input terminal of the NAND gate YF1 receives the first clock signal CK1
  • the second input terminal of the NAND gate YF1 receives the fourth control signal D4(N)
  • the output terminal of the NAND gate CK1 is connected to the plurality of seconds arranged in series.
  • the upstream input end of the inverter F2, the output end of the even-numbered second inverter F2 of the plurality of second inverters F2 arranged in series outputs the in-phase inverted scan drive signal XG(N), which are arranged in series
  • the output of the odd-numbered second inverters F2 of the plurality of second inverters F2 outputs the current-stage positive phase scan drive signal G(N).
  • the latch circuit 14 includes a second transmission gate C2 and a fourth N-type switch tube TN4; the P-type control terminal of the second transmission gate C2 receives the third control signal D3(N), and the N-type control of the second transmission gate C2 The terminal receives the fourth control signal D4(N), the first transmission end of the second transmission gate C2 receives the second clock signal CK2, and the second transmission terminal of the second transmission gate C2 outputs the first control signal D1(N).
  • the control end of the fourth N-type switch tube TN4 receives the third control signal D3(N), the first transmission end of the fourth N-type switch tube TN4 is connected to the low reference potential VGL, and the first transmission end of the fourth N-type switch tube TN4 The second transmission end of the second transmission gate C2 is connected.
  • the latch circuit 14 further includes a third inverter F3.
  • the input end of the third inverter F3 receives the second clock signal CK2, and the output end of the third inverter F3 is connected to the first transmission of the second transmission gate C2. end.
  • FIG. 2 is a waveform timing diagram of the operation of the first embodiment of the gate driving circuit of the present invention.
  • the reset and control circuit 12 performs a reset process, wherein the fourth P-type switching transistor TP4 Turning on, the third control signal D3(N) outputted from the second transmission end of the third P-type switch tube TP3 and the connection node of the second transmission end of the fourth P-type switch tube TP4 is a high potential signal, and the inverting circuit 13
  • the first inverter F1 inverts the third control signal D3(N) to obtain a fourth control signal D4(N) of low potential, and the fourth N-type switching transistor (TN4) in the latch circuit 14 is turned on.
  • the first control signal D1(N) outputted by the latch circuit 14 is low, and the first transmission end of the first transmission gate C1 of the input circuit 11 receives the first control signal D1(N), since the first transmission gate at this time
  • the upper-stage inverted scan drive signal XG(N-1) received by the N-type control terminal of C1 is a high-potential signal, and the upper-order positive-phase scan drive signal G(N-1) received by the P-type control terminal of the first transmission gate is low.
  • the second control signal D2(N) outputted by the two transmitting ends is equal to the first control signal D2(N), that is, both are low potential signals, so that the second P-type switching transistor TP2 and the third P-type switch in the reset and control circuit When the tube is turned on, the output third control signal D3(N) is high potential.
  • the upper-phase normal-phase scan driving signal G(N-1) is a high-potential signal, that is, the upper-stage inverted scanning drive signal XG(N-1) is a low-potential signal
  • the first transmission gate C1 of the input circuit 11 is turned off
  • a P-type switch tube TP1 is turned on
  • the output second control signal D2(N) is a high potential signal
  • the second N-type switch tube (TN2) of the reset and control circuit 12 is turned on
  • the reset signal RESET is a high potential signal.
  • the third control signal D3(N) of low potential is output, and the fourth control signal D4(N) is outputted through the first inverter F1 of the inverter circuit 13, and further
  • the present stage normal phase scan drive signal G(N) and the local stage inverted scan drive signal XG(N) are output via the output circuit 15.
  • CK2 is a high potential signal
  • the second transmission gate C2 in the latch circuit 14 is turned on under the control of the third control signal D3(N) and the fourth control signal D4(N), and the first control for outputting the high voltage is performed.
  • G (N-1) is a low potential signal
  • the first transmission gate C1 is open
  • the second control signal D2 (N) is also a high voltage signal, then the first of 12 in the reset and control circuit
  • the two N-type switch tubes TN2 and the third N-type switch tubes TN3 are turned on.
  • the reset signal Reset is a high potential signal, so that the first N-type switch tube TN1 is also turned on, and the outputted third control signal is latched at a low potential.
  • the first embodiment of the present invention first obtains a low potential third control signal D3(N) by changing the circuit structure, and then inverts the inverter to obtain a fourth control signal D4(N), thereby avoiding signal voltage loss and reducing The generation of the positive phase scan drive signal G(N) is delayed.
  • the gate driving circuit includes an input circuit 31, a reset and control circuit 32, an inverting circuit 33, a latch circuit 34, and an output circuit. 35.
  • the input circuit 31 generates a second control according to the upper positive scan drive signal G(N-1), the upper reverse scan drive signal XG(N-1), and the first control signal D1(N) output by the latch circuit 34.
  • the signal D2(N), the reset and control circuit 32 generates a third control signal D3(N) according to the reset signal Reset, the first control signal D1(N) and the second control signal D2(N), and the inverting circuit 33 pairs the third
  • the control signal D3(N) performs at least one inversion processing and generates a fourth control signal D4(N)
  • the output circuit 35 generates the current-phase positive-phase scan driving signal according to the fourth control signal D4(N) and the first clock signal CK1.
  • the latch circuit 34 generates the first control signal D1(N) according to the third control signal D3(N) and the second clock signal CK2, and further according to the second The clock signal CK2 latches or changes the voltage state of the third control signal D3(N).
  • the input circuit 31 includes a first transmission gate C1 and a first N-type switching transistor TN1.
  • the first input gate C1 may be a CMOS transmission gate, and is composed of an NMOS transistor TN and a PMOS transistor TP in parallel, since the structure of the MOS transistor is symmetrical.
  • the source and the drain can be used interchangeably. Therefore, the input and output of the transmission gate can be used interchangeably, that is, the CMOS transmission gate has bidirectionality, so it is also called a controllable bidirectional switch.
  • the N-type control terminal of the first transmission gate C1 receives the upper-stage inverted scan driving signal XG(N-1), and the P-type control terminal of the first transmission gate receives the upper-level normal-phase scanning driving signal G(N-1), the first transmission
  • the first transmission end of the gate C1 receives the first control signal D1(N)
  • the second transmission end of the first transmission gate C1 outputs the second control signal D2(N);
  • the control end of the first N-type switch tube TN1 receives the upper-stage normal-phase scan drive signal G(N-1), the first transmission end of the first N-type switch tube TN1 is connected to the low reference potential VGL, and the first N-type switch tube TN1 The second transmission end is connected to the second transmission of the first transmission gate C1
  • the reset and control circuit 32 includes a second N-type switch tube TN2, a third N-type switch tube TN3, a fourth N-type switch tube TN4, a first P-type switch tube TP1, a second P-type switch tube TP2, and a third P-type.
  • the first transmission end of the second N-type switch tube TN2 is connected to the low reference potential VGL;
  • the first transmission end of the third N-type switch tube TN3 is connected to the second transmission end of the second N-type switch tube TN2, and the control end of the second N-type switch tube TN2 and one of the third N-type switch tube TN3 are received. a control signal, the other of the control end of the second N-type switch tube TN2 and the third N-type switch tube TN3 receiving the third control signal;
  • the control end of the fourth N-type switch tube TN4 receives the reset signal Reset, the first transmission end of the fourth N-type switch tube TN4 is connected to the low reference potential VGL, and the second transmission end of the fourth N-type switch tube TN4 is connected to the third N type a second transmission end of the switch tube TN3;
  • the control end of the first P-type switch tube TP3 receives the reset signal Reset, the first transmission end of the first P-type switch tube TP1 is connected to the high reference potential VGH;
  • the control end of the second P-type switch tube TP2 receives the first control signal D1(N), and the first transmission end of the second P-type switch tube TP2 is connected to the second transmission end of the first P-type switch tube TP1, and the second P-type The second transmission end of the switch tube TP2 is connected to the connection node of the second transmission end of the third N-type switch tube TN3 and the second transmission end of the fourth N-type switch tube TN4;
  • the control end of the third P-type switch tube TP3 receives the second control signal D2(N), and the first transmission end of the third P-type switch tube TP3 is connected to the second transmission end of the first P-type switch tube TP1, and the third P-type The second transmission end of the switch tube TP3 is connected to the connection node of the second transmission end of the third N-type switch tube TN3 and the second transmission end of the fourth N-type switch tube;
  • the third control signal is output from the connection node of the second transmission end of the third N-type switch tube TN3 and the second transmission end of the fourth N-type switch tube TN4.
  • the inverter circuit 33 includes a first inverter F1 and a second inverter F2;
  • the input of the first inverter F1 receives the third control signal D3(N);
  • the input end of the second inverter F2 is connected to the input end of the first inverter F1, the input end of the second inverter F2 outputs the fourth control signal D4 (N);
  • the output circuit 35 includes a NAND gate YF1 and a plurality of third inverters F3 arranged in series;
  • the first input terminal of the NAND gate YF1 receives the first clock signal D1(N), the second input terminal of the NAND gate YF1 receives the fourth control signal D4(N), and the output terminal of the NAND gate YF1 is connected in series.
  • the upstream input end of the third inverter F3, the output end of the even-numbered third inverter F3 of the plurality of third inverters F3 arranged in series outputs the inverting scan driving signal XG(N) of the current stage,
  • the output of the odd-numbered third inverter F3 of the plurality of third inverters F3 arranged in series outputs the current-phase positive-phase scan driving signal G(N);
  • the latch circuit 34 includes a second transfer gate C2 and a fourth P-type switch tube TP4;
  • the N-type control terminal of the second transmission gate C2 receives the third control signal D3(N), the P-type control terminal of the second transmission gate C2 receives the fourth control signal D4(N), and the first transmission end of the second transmission gate C2 Receiving a second clock signal CK2, the second transmission end of the second transmission gate C2 outputs a first control signal D1 (N);
  • the control end of the fourth P-type switch tube TP4 receives the third control signal D3(N), the first transmission end of the fourth P-type switch tube TP4 is connected to the low reference potential VGL, and the first transmission end of the fourth P-type switch tube TP4 The second transmission end of the second transmission gate C2 is connected.
  • FIG. 4 is a waveform timing diagram of the operation of the second embodiment of the gate driving circuit of the present invention.
  • the fourth N-type switching transistor TN4 of the reset and control circuit 33 is turned on.
  • the third control signal D3(N) of the low potential is output, and the fourth P-type switching transistor TP4 of the latch circuit 34 is turned on, and the latch circuit 34 outputs the first control signal D1(N) of the high potential, at which time the upper-level positive phase
  • the scan driving signal G(N-1) is a low potential signal
  • the upper inverting scan driving signal G(N-1) is a high potential signal
  • the first transmission gate C1 is opened
  • the first N-type switching tube TN1 is turned off
  • the second The control signal D2(N) is a high potential signal, so that the second N-type switching transistor and the third N-type switching transistor in the reset and control circuit 32 are turned on, so that the outputted third control signal D3(N) is latched at a low potential.
  • the upper-phase normal-phase scan driving signal G(N-1) is a high-potential signal, that is, the upper-stage inverted scanning drive signal G(N-1) is a low-potential signal
  • the first transmission gate C1 in the input circuit 31 is turned off.
  • the first N-type switch tube TN1 is turned on, and the second control signal D2(N) is output as a low potential signal.
  • the reset signal is a low potential signal
  • the first P-type switch tube in the reset and control circuit 32 is turned on
  • the third The P-type switch is turned on, so the outputted third control signal D3(N) is a high potential signal
  • the second transmission gate 2 in the latch circuit 34 is under the control of the third control signal D3(N) and its inverted signal.
  • the second clock signal CK2 is also a high potential signal at this time, so the first control signal D1(N) outputted by the latch circuit 34 is also a high potential signal; and the first inverse in the inverter circuit 33
  • the phase converter F1 and the second inverter F2 invert the third control signal D3(N) twice to obtain the fourth control signal D4(N), and finally output the normal phase scan driving signal G of the current stage by the output circuit 35 ( N) and the current stage inversion scan drive signal XG(N).
  • the third control signal D3(N) of high potential is first obtained, and the fourth control signal D4(N) is obtained by inverting the inverter multiple times, thereby avoiding the signal.
  • the voltage loss reduces the generation delay of the positive phase scan drive signal G(N) of this stage.
  • the liquid crystal display includes a display panel 501 and a backlight 502.
  • the display panel 501 includes a plurality of gate drive circuits arranged in cascade, wherein the gate drive circuit It is a gate drive circuit in a first embodiment and a possible combination of the gate drive circuit of the present invention.
  • the gate drive circuit in the liquid crystal display is the gate drive circuit in the second embodiment and possibly a combination of the gate drive circuit of the present invention.
  • the gate driving circuit described in the embodiment of the present invention is not limited to the liquid crystal display, and can be applied to the fields of the OLED display panel and the gate of the mobile phone, the display, and the television. Driving field.

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Abstract

一种栅极驱动电路及其液晶显示器。其中，输入电路（11）根据上级正相及反相扫描驱动信号（G(N-1)及XG(N-1)）以及锁存电路（14）输出的第一控制信号（D1(N)）产生第二控制信号（D2(N)），复位及控制电路（12）根据复位信号（Reset）、第一及第二控制信号（D1(N)及D2(N)）产生第三控制信号（D3(N)），反相电路（13）对第三控制信号（D3(N)）进行至少一次反相处理，并产生第四控制信号（D4(N)），输出电路（15）根据第四控制信号（D4(N)）和第一时钟信号（CK1）产生本级正相及反相扫描驱动信号（G(N)及XG(N)），锁存电路（14）根据第三控制信号（D3(N)）和第二时钟信号（CK2）产生第一控制信号（D1(N)），进而根据第二时钟信号（CK2）锁存或改变第三控制信号（D3(N)）的电压状态。通过改变电路的结构设计，提高了栅极驱动电路的中间传输信号的驱动能力，降低本级扫描驱动信号的产生延迟。

Description

一种栅极驱动电路及其液晶显示器
【技术领域】
本发明涉及一种液晶显示技术领域的装置，特别是涉及一种蓝相液晶显示面板。
【背景技术】
Gate Driver On Array，简称GOA，也就是利用现有薄膜晶体管液晶显示器Array制程将Gate行扫描驱动信号电路制作在Array基板上，实现对Gate逐行扫描的驱动方式的一项技术。
随着低温多晶硅（LTPS）半导体薄膜晶体管的发展，而且由于LTPS半导体本身超高载流子迁移率的特性，相应的面板周边集成电路也成为大家关注的焦点，并且很多人投入到System on Panel（SOP）的相关技术研究，并逐步成为现实。
在现有的栅极驱动电路中，通过控制输出电路的输入节点的电压来产生本级扫描驱动信号，但该输入节点的电压一般由高参考电路通路产生，高参考电位经若干晶体管的分压而造成损失，进而会影响本级扫描驱动信号的产生速度，进而影响面板的正常驱动，严重时会造成整个驱动电路的失效。
【发明内容】
本发明主要解决的技术问题是提供一种栅极驱动电路及其液晶显示器，能够提高中间传输信号的驱动能力，降低本级扫描驱动信号的产生延迟。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种栅极驱动电路，包括：输入电路、复位及控制电路、反相电路、锁存电路以及输出电路，输入电路根据上级正相扫描驱动信号、上级反相扫描驱动信号以及锁存电路输出的第一控制信号产生第二控制信号，复位及控制电路根据复位信号、第一控制信号和第二控制信号产生第三控制信号，反相电路对第三控制信号进行至少一次反相处理，并产生第四控制信号，输出电路根据第四控制信号和第一时钟信号产生本级正相扫描驱动信号和本级反相扫描驱动信号，锁存电路根据第三控制信号和第二时钟信号产生第一控制信号，进而根据第二时钟信号锁存或改变第三控制信号的电压状态；
其中，输入电路包括第一传输门以及第一P型开关管；
第一传输门的N型控制端接收上级反相扫描驱动信号，第一传输门的P型控制端接收上级正相扫描驱动信号，第一传输门的第一传输端接收第一控制信号，第一传输门的第二传输端输出第二控制信号；
第一P型开关管的控制端接收上级反相扫描驱动信号，第一P型开关管的第一传输端连接高参考电位，第一P型开关管的第二传输端连接第一传输门的第二传输端；
其中，输出电路包括与非门以及串联设置的多个第二反相器；
与非门的第一输入端接收第一时钟信号，与非门的第二输入端接收第四控制信号，与非门的输出端连接串联设置的多个第二反相器的上游输入端，串联设置的多个第二反相器中的第偶数个第二反相器的输出端输出本级反相扫描驱动信号，串联设置的多个第二反相器中的第奇数个第二反相器的输出端输出本级正相扫描驱动信号。
为解决上述技术问题，本发明还提供了一种栅极驱动电路，包括：输入电路、复位及控制电路、反相电路、锁存电路以及输出电路，输入电路根据上级正相扫描驱动信号、上级反相扫描驱动信号以及锁存电路输出的第一控制信号产生第二控制信号，复位及控制电路根据复位信号、第一控制信号和第二控制信号产生第三控制信号，反相电路对第三控制信号进行至少一次反相处理，并产生第四控制信号，输出电路根据第四控制信号和第一时钟信号产生本级正相扫描驱动信号和本级反相扫描驱动信号，锁存电路根据第三控制信号和第二时钟信号产生第一控制信号，进而根据第二时钟信号锁存或改变第三控制信号的电压状态。
其中，输入电路包括第一传输门以及第一P型开关管；
第一传输门的N型控制端接收上级反相扫描驱动信号，第一传输门的P型控制端接收上级正相扫描驱动信号，第一传输门的第一传输端接收第一控制信号，第一传输门的第二传输端输出第二控制信号；
第一P型开关管的控制端接收上级反相扫描驱动信号，第一P型开关管的第一传输端连接高参考电位，第一P型开关管的第二传输端连接第一传输门的第二传输端。
其中，复位及控制电路包括第二P型开关管、第三P型开关管、第四P型开关管、第一N型开关管、第二N型开关管以及第三N型开关管；第二P型开关管的第一传输端连接高参考电位；第三P型开关管的第一传输端连接第二P型开关管的第二传输端，第二P型开关管的控制端和第三P型开关管的控制端中的一个接收第一控制信号，第二P型开关管的控制端和第三P型开关管的控制端中的另一个接收第二控制信号；第四P型开关管的控制端接收复位信号，第四P型开关管的第一传输端连接高参考电位，第四P型开关管的第二传输端连接第三P型开关管的第二传输端；第一N型开关管的控制端接收复位信号，第一N型开关管的第一传输端连接第三P型开关管的第二传输端和第四P型开关管的第二传输端的连接节点；第二N型开关管的控制端接收第一控制信号，第二N型开关管的第一传输端连接第一N型开关管的第二传输端，第二N型开关管的第二传输端连接低参考电位；第三N型开关管的控制端接收第二控制信号，第三N型开关管的第一传输端连接第一N型开关管的第二传输端，第三N型开关管的第二传输端连接低参考电位；
其中，第三控制信号从第三P型开关管的第二传输端和第四P型开关管的第二传输端的连接节点输出。
其中，反相电路包括第一反相器；第一反相器的输入端接收第三控制信号，第一反相器的输出端输出第四控制信号。
其中，输出电路包括与非门以及串联设置的多个第二反相器；
与非门的第一输入端接收第一时钟信号，与非门的第二输入端接收第四控制信号，与非门的输出端连接串联设置的多个第二反相器的上游输入端，串联设置的多个第二反相器中的第偶数个第二反相器的输出端输出本级反相扫描驱动信号，串联设置的多个第二反相器中的第奇数个第二反相器的输出端输出本级正相扫描驱动信号。
其中，锁存电路包括第二传输门以及第四N型开关管；第二传输门的P型控制端接收第三控制信号，第二传输门的N型控制端接收第四控制信号，第二传输门的第一传输端接收第二时钟信号，第二传输门的第二传输端输出第一控制信号；第四N型开关管的控制端接收第三控制信号，第四N型开关管的第一传输端连接低参考电位，第四N型开关管的第一传输端连接第二传输门的第二传输端。
其中，锁存电路进一步包括第三反相器，第三反相器的输入端接收第二时钟信号，第三反相器的输出端连接第二传输门的第一传输端。
其中，输入电路包括第一传输门以及第一N型开关管；
第一传输门的N型控制端接收上级反相扫描驱动信号，第一传输门的P型控制端接收上级正相扫描驱动信号，第一传输门的第一传输端接收第一控制信号，第一传输门的第二传输端输出第二控制信号；
第一N型开关管的控制端接收上级正相扫描驱动信号，第一N型开关管的第一传输端连接低参考电位，第一N型开关管的第二传
复位及控制电路包括第二N型开关管、第三N型开关管、第四N型开关管、第一P型开关管、第二P型开关管、第三P型开关管；
第二N型开关管的第一传输端连接低参考电位；
第三N型开关管的第一传输端与第二N型开关管的第二传输端连接，第二N型开关管的控制端和第三N型开关管中的一个接收第一控制信号，第二N型开关管的控制端和第三N型开关管中的另一个接收第三控制信号；
第四N型开关管的控制端接收复位信号，第四N型开关管的第一传输端连接低参考电位，第四N型开关管的第二传输端连接第三N型开关管的第二传输端；
第一P型开关管的控制端接收复位信号，第一P型开关管的第一传输端连接高参考电位；
第二P型开关管的控制端接收第一控制信号，第二P型开关管的第一传输端连接第一P型开关管的第二传输端，第二P型开关管的第二传输端连接第三N型开关管的第二传输端与第四N型开关管的第二传输端的连接节点；
第三P型开关管的控制端接收第二控制信号，第三P型开关管的第一传输端连接第一P型开关管的第二传输端，第三P型开关管的第二传输端连接第三N型开关管的第二传输端与第四N型开关管的第二传输端的连接节点；
其中，第三控制信号从第三N型开关管的第二传输端与第四N型开关管的第二传输端的连接节点输出。
其中，反相电路包括第一反相器和第二反相器；
第一反相器的输入端接收第三控制信号；
第二反相器的输入端连接第一反相器的输入端，第二反相器的输入端输出第四控制信号；
输出电路包括与非门以及串联设置的多个第三反相器；
与非门的第一输入端接收第一时钟信号，与非门的第二输入端接收第四控制信号，与非门的输出端连接串联设置的多个第二反相器的上游输入端，串联设置的多个第二反相器中的第偶数个第二反相器的输出端输出本级反相扫描驱动信号，串联设置的多个第二反相器中的第奇数个第二反相器的输出端输出本级正相扫描驱动信号；
锁存电路包括第二传输门以及第四P型开关管；
第二传输门的N型控制端接收第三控制信号，第二传输门的P型控制端接收第四控制信号，第二传输门的第一传输端接收第二时钟信号，第二传输门的第二传输端输出第一控制信号；
第四P型开关管的控制端接收第三控制信号，第四P型开关管的第一传输端连接低参考电位，第四P型开关管的第一传输端连接第二传输门的第二传输端。
为了解决上述问题，本发明还提供了一种液晶显示器，液晶显示器包括多个级联设置的栅极驱动电路，栅极驱动电路包括：输入电路、复位及控制电路、反相电路、锁存电路以及输出电路，输入电路根据上级正相扫描驱动信号、上级反相扫描驱动信号以及锁存电路输出的第一控制信号产生第二控制信号，复位及控制电路根据复位信号、第一控制信号和第二控制信号产生第三控制信号，反相电路对第三控制信号进行至少一次反相处理，并产生第四控制信号，输出电路根据第四控制信号和第一时钟信号产生本级正相扫描驱动信号和本级反相扫描驱动信号，锁存电路根据第三控制信号和第二时钟信号产生第一控制信号，进而根据第二时钟信号锁存或改变第三控制信号的电压状态。
其中，输入电路包括第一传输门以及第一P型开关管；
第一传输门的N型控制端接收上级反相扫描驱动信号，第一传输门的P型控制端接收上级正相扫描驱动信号，第一传输门的第一传输端接收第一控制信号，第一传输门的第二传输端输出第二控制信号；
第一P型开关管的控制端接收上级反相扫描驱动信号，第一P型开关管的第一传输端连接高参考电位，第一P型开关管的第二传输端连接第一传输门的第二传输端。
其中，复位及控制电路包括第二P型开关管、第三P型开关管、第四P型开关管、第一N型开关管、第二N型开关管以及第三N型开关管；
第二P型开关管的第一传输端连接高参考电位；
第三P型开关管的第一传输端连接第二P型开关管的第二传输端，第二P型开关管的控制端和第三P型开关管的控制端中的一个接收第一控制信号，第二P型开关管的控制端和第三P型开关管的控制端中的另一个接收第二控制信号；
第四P型开关管的控制端接收复位信号，第四P型开关管的第一传输端连接高参考电位，第四P型开关管的第二传输端连接第三P型开关管的第二传输端；
第一N型开关管的控制端接收复位信号，第一N型开关管的第一传输端连接第三P型开关管的第二传输端和第四P型开关管的第二传输端的连接节点；
第二N型开关管的控制端接收第一控制信号，第二N型开关管的第一传输端连接第一N型开关管的第二传输端，第二N型开关管的第二传输端连接低参考电位；
第三N型开关管的控制端接收第二控制信号，第三N型开关管的第一传输端连接第一N型开关管的第二传输端，第三N型开关管的第二传输端连接低参考电位；
其中，第三控制信号从第三P型开关管的第二传输端和第四P型开关管的第二传输端的连接节点输出。
其中，反相电路包括第一反相器；
第一反相器的输入端接收第三控制信号，第一反相器的输出端输出第四控制信号。
其中，输出电路包括与非门以及串联设置的多个第二反相器；
与非门的第一输入端接收第一时钟信号，与非门的第二输入端接收第四控制信号，与非门的输出端连接串联设置的多个第二反相器的上游输入端，串联设置的多个第二反相器中的第偶数个第二反相器的输出端输出本级反相扫描驱动信号，串联设置的多个第二反相器中的第奇数个第二反相器的输出端输出本级正相扫描驱动信号。
其中，锁存电路包括第二传输门以及第四N型开关管；
第二传输门的P型控制端接收第三控制信号，第二传输门的N型控制端接收第四控制信号，第二传输门的第一传输端接收第二时钟信号，第二传输门的第二传输端输出第一控制信号；
第四N型开关管的控制端接收第三控制信号，第四N型开关管的第一传输端连接低参考电位，第四N型开关管的第一传输端连接第二传输门的第二传输端。
其中，锁存电路进一步包括第三反相器，第三反相器的输入端接收第二时钟信号，第三反相器的输出端连接第二传输门的第一传输端。
其中，输入电路包括第一传输门以及第一N型开关管；
第一传输门的N型控制端接收上级反相扫描驱动信号，第一传输门的P型控制端接收上级正相扫描驱动信号，第一传输门的第一传输端接收第一控制信号，第一传输门的第二传输端输出第二控制信号；
第一N型开关管的控制端接收上级正相扫描驱动信号，第一N型开关管的第一传输端连接低参考电位，第一N型开关管的第二传
复位及控制电路包括第二N型开关管、第三N型开关管、第四N型开关管、第一P型开关管、第二P型开关管、第三P型开关管；
第二N型开关管的第一传输端连接低参考电位；
第三N型开关管的第一传输端与第二N型开关管的第二传输端连接，第二N型开关管的控制端和第三N型开关管中的一个接收第一控制信号，第二N型开关管的控制端和第三N型开关管中的另一个接收第三控制信号；
第四N型开关管的控制端接收复位信号，第四N型开关管的第一传输端连接低参考电位，第四N型开关管的第二传输端连接第三N型开关管的第二传输端；
第一P型开关管的控制端接收复位信号，第一P型开关管的第一传输端连接高参考电位；
第二P型开关管的控制端接收第一控制信号，第二P型开关管的第一传输端连接第一P型开关管的第二传输端，第二P型开关管的第二传输端连接第三N型开关管的第二传输端与第四N型开关管的第二传输端的连接节点；
第三P型开关管的控制端接收第二控制信号，第三P型开关管的第一传输端连接第一P型开关管的第二传输端，第三P型开关管的第二传输端连接第三N型开关管的第二传输端与第四N型开关管的第二传输端的连接节点；
其中，第三控制信号从第三N型开关管的第二传输端与第四N型开关管的第二传输端的连接节点输出。
其中，反相电路包括第一反相器和第二反相器；
第一反相器的输入端接收第三控制信号；
第二反相器的输入端连接第一反相器的输入端，第二反相器的输入端输出第四控制信号；
输出电路包括与非门以及串联设置的多个第三反相器；
与非门的第一输入端接收第一时钟信号，与非门的第二输入端接收第四控制信号，与非门的输出端连接串联设置的多个第三反相器的上游输入端，串联设置的多个第三反相器中的第偶数个第三反相器的输出端输出本级反相扫描驱动信号，串联设置的多个第三反相器中的第奇数个第三反相器的输出端输出本级正相扫描驱动信号；
锁存电路包括第二传输门以及第四P型开关管；
第二传输门的N型控制端接收第三控制信号，第二传输门的P型控制端接收第四控制信号，第二传输门的第一传输端接收第二时钟信号，第二传输门的第二传输端输出第一控制信号；
第四P型开关管的控制端接收第三控制信号，第四P型开关管的第一传输端连接低参考电位，第四P型开关管的第一传输端连接第二传输门的第二传输端。
本发明的有益效果是：区别于现有技术的情况，本发明栅极驱动电路通过改变原来的电路设计，改变原有的“与或非”逻辑，替换成“或与非”逻辑，提高了中间传输信号的驱动能力，降低本级扫描驱动信号的产生延迟。
【附图说明】
图1是本发明栅极驱动电路第一实施方式的电路结构示意图；
图2是本发明栅极驱动电路第一实施方式工作的波形时序图；
图3是本发明栅极驱动电路第二实施方式的电路结构示意图；
图4是本发明栅极驱动电路第二实施方式工作的波形时序图；
图5是本发明液晶显示器一实施方式的结构示意图。
【具体实施方式】
在说明书及权利要求书当中使用了某些词汇来指称特定的组件，所属领域中的技术人员应该可以理解，制造商可能会用不同的名词来称呼同样的组件。本说明书及权利要求书并不以名称的差异来作为区分组件的方式，而是以组件在功能上的差异来作为区分的基准。下面结合附图和实施例对本发明进行详细说明。
参阅图1，是本发明栅极驱动电路第一实施方式的电路结构示意图，该栅极驱动电路包括：输入电路11、复位及控制电路12、反相电路13、锁存电路14以及输出电路15，输入电路11根据上级正相扫描驱动信号G(N-1)、上级反相扫描驱动信号XG(N-1)以及锁存电路14输出的第一控制信号D1(N)产生第二控制信号D2(N)，复位及控制电路12根据复位信号Reset、第一控制信号D1(N)和第二控制信号D2(N)产生第三控制信号D3(N)，反相电路13对第三控制信号D3(N)进行至少一次反相处理，并产生第四控制信号D4(N)，输出电路15根据第四控制信号D4(N)和第一时钟信号CK1产生本级正相扫描驱动信号G(N)和本级反相扫描驱动信号XG(N)，锁存电路14根据第三控制信号D3(N)和第二时钟信号CK2产生第一控制信号D1(N)，进而根据第二时钟信号CK2锁存或改变第三控制信号D3(N)的电压状态。
其中，输入电路11包括第一传输门C1以及第一P型开关管TP1；其中第一输入门C1可以是CMOS传输门，由一个NMOS管TN和一个PMOS管TP并联构成，由于MOS管的结构是对称的，即源极和漏极可以互换使用，因此，传输门的输入端和输出端可以互换使用，即CMOS传输门具有双向性，故又称为可控双向开关。此外，本发明中所提到的开关管可以是一种薄膜晶体管。
第一传输门C1的N型控制端接收上级反相扫描驱动信号XG(N-1)，第一传输门的P型控制端接收上级正相扫描驱动信号G(N-1)，第一传输门的第一传输端接收第一控制信号D1(N)，第一传输门C1的第二传输端输出第二控制信号D2(N)；
第一P型开关管TP1的控制端接收上级反相扫描驱动信号XG(N-1)，第一P型开关管的第一传输端连接高参考电位VGH，第一P型开关管TP1的第二传输端连接第一传输门C1的第二传输端。
其中，复位及控制电路12包括第二P型开关管TP2、第三P型开关管TP3、第四P型开关管TP4、第一N型开关管TN1、第二N型开关管TN2以及第三N型开关管TN3。第二P型开关管TP2的第一传输端连接高参考电位VGH，第三P型开关管TP3的第一传输端连接第二P型开关管TP2的第二传输端，第二P型开关管TP2的控制端和第三P型开关管TP3的控制端中的一个接收第一控制信号D1(N)，第二P型开关管TP2的控制端和第三P型开关管TP3的控制端中的另一个接收第二控制信号D2(N)。在本实施例中，第二P型开关管TP2接收第一控制信号D1(N)，第三P型开关管TP3的控制端接收第二控制信号D2(N)，反之亦然。
第四P型开关管TP4的控制端接收复位信号Reset，第四P型开关管TP4的第一传输端连接高参考电位VGH，第四P型开关管TP4的第二传输端连接第三P型开关管TP3的第二传输端。第一N型开关管TN1的控制端接收复位信号Reset，第一N型开关管TN1的第一传输端连接第三P型开关管TP3的第二传输端和第四P型开关管TP4的第二传输端的连接节点。第二N型开关管TN2的控制端接收第一控制信号D1(N)，第二N型开关管TN2的第一传输端连接第一N型开关管TN1的第二传输端，第二N型开关管TN2的第二传输端连接低参考电位VGL。第三N型开关管TN3的控制端接收第二控制信号D2(N)，第三N型开关管TN3的第一传输端连接第一N型开关管TN1的第二传输端，第三N型开关管TN3的第二传输端连接低参考电位VGL。
第三控制信号D3(N)从第三P型开关管TP3的第二传输端和第四P型开关管TP4的第二传输端的连接节点输出。
其中，反相电路13包括第一反相器F1；第一反相器F1的输入端接收第三控制信号D3(N)，第一反相器F1的输出端输出第四控制信号D4(N)。反相器可以将输入信号的相位反转180度，这种电路应用在模拟电路，比如说音频放大，时钟振荡器等，反相器可以是TTL非门，也可以是一种CMOS反相器。
其中，输出电路15包括与非门YF1以及串联设置的多个第二反相器F2。与非门YF1的第一输入端接收第一时钟信号CK1，与非门YF1的第二输入端接收第四控制信号D4(N)，与非门CK1的输出端连接串联设置的多个第二反相器F2的上游输入端，串联设置的多个第二反相器F2中的第偶数个第二反相器F2的输出端输出本级反相扫描驱动信号XG(N)，串联设置的多个第二反相器F2中的第奇数个第二反相器F2的输出端输出本级正相扫描驱动信号G(N)。
其中，锁存电路14包括第二传输门C2以及第四N型开关管TN4；第二传输门C2的P型控制端接收第三控制信号D3(N)，第二传输门C2的N型控制端接收第四控制信号D4(N)，第二传输门C2的第一传输端接收第二时钟信号CK2，第二传输门C2的第二传输端输出第一控制信号D1(N)。第四N型开关管TN4的控制端接收第三控制信号D3(N)，第四N型开关管TN4的第一传输端连接低参考电位VGL，第四N型开关管TN4的第一传输端连接第二传输门C2的第二传输端。
其中，锁存电路14进一步包括第三反相器F3，第三反相器F3的输入端接收第二时钟信号CK2，第三反相器F3的输出端连接第二传输门C2的第一传输端。
参阅图2，为本发明栅极驱动电路第一实施方式工作的波形时序图，当复位信号Reset变为低电位脉冲信号时，复位及控制电路12进行复位处理，其中第四P型开关管TP4打开，从第三P型开关管TP3的第二传输端和第四P型开关管TP4的第二传输端的连接节点输出的第三控制信号D3(N)为高电位信号，反相电路13的第一反相器F1对第三控制信号D3(N)进行反相处理，得到低电位的第四控制信号D4(N)，锁存电路14中的第四N型开关管(TN4)打开，该锁存电路14输出的第一控制信号D1(N)为低电位，输入电路11第一传输门C1的第一传输端接收到第一控制信号D1(N)，由于此时第一传输门C1的N型控制端接收的上级反相扫描驱动信号XG(N-1)为高电位信号，第一传输门的P型控制端接收的上级正相扫描驱动信号G(N-1)为低电位信号，所以第一传输门C1导通，而第一P型开关管TP1关闭，第一传输门C1的第二传输端输出的第二控制信号D2(N)等于第一控制信号D2(N)，即都为低电位信号，使得复位与控制电路中的第二P型开关管TP2和第三P型开关管打开，输出的第三控制信号D3(N)被所存在高电位。
而当上级正相扫描驱动信号G(N-1)为高电位信号时，即上级反相扫描驱动信号XG(N-1)为低电位信号，输入电路11的第一传输门C1关闭，第一P型开关管TP1打开，输出的第二控制信号D2(N)为高电位信号，复位及控制电路12的第二N型开关管(TN2)打开，此时复位信号RESET为高电位信号，使得第一N型开关管(TN1)打开，则输出低电位的第三控制信号D3(N)，经过反相电路13中的第一反相器F1输出第四控制信号D4(N)，进而经由输出电路15输出本级正相扫描驱动信号G(N)和本级反相扫描驱动信号XG(N)。而当CK2为高电位信号时，锁存电路14中的第二传输门C2在第三控制信号D3(N)和第四控制信号D4(N)的控制下打开，输出高电压的第一控制信号D1(N)，此时G(N-1)为低电位信号，第一传输门C1打开，第二控制信号D2(N)也为高电压信号，则复位及控制电路中12中的第二N型开关管TN2和第三N型开关管TN3打开，此时复位信号Reset为高电位信号，所以第一N型开关管TN1也打开，则输出的第三控制信号被锁存在低电位。
本发明第一实施方式通过改变电路结构首先得到低电位的第三控制信号D3(N)，再经过反相器反相得到第四控制信号D4(N)，从而避免信号的电压损失，降低了本级正相扫描驱动信号G(N)的产生延迟。
参照图3，为本发明栅极驱动电路第二实施方式的的电路结构示意图，该栅极驱动电路包括：输入电路31、复位及控制电路32、反相电路33、锁存电路34以及输出电路35，输入电路31根据上级正相扫描驱动信号G(N-1)、上级反相扫描驱动信号XG(N-1)以及锁存电路34输出的第一控制信号D1(N)产生第二控制信号D2(N)，复位及控制电路32根据复位信号Reset、第一控制信号D1(N)和第二控制信号D2(N)产生第三控制信号D3(N)，反相电路33对第三控制信号D3(N)进行至少一次反相处理，并产生第四控制信号D4(N)，输出电路35根据第四控制信号D4(N)和第一时钟信号CK1产生本级正相扫描驱动信号G(N)和本级反相扫描驱动信号XG(N)，锁存电路34根据第三控制信号D3(N)和第二时钟信号CK2产生第一控制信号D1(N)，进而根据第二时钟信号CK2锁存或改变第三控制信号D3(N)的电压状态。
输入电路31包括第一传输门C1以及第一N型开关管TN1；其中第一输入门C1可以是CMOS传输门，由一个NMOS管TN和一个PMOS管TP并联构成，由于MOS管的结构是对称的，即源极和漏极可以互换使用，因此，传输门的输入端和输出端可以互换使用，即CMOS传输门具有双向性，故又称为可控双向开关。
第一传输门C1的N型控制端接收上级反相扫描驱动信号XG(N-1)，第一传输门的P型控制端接收上级正相扫描驱动信号G(N-1)，第一传输门C1的第一传输端接收第一控制信号D1(N)，第一传输门C1的第二传输端输出第二控制信号D2(N)；
第一N型开关管TN1的控制端接收上级正相扫描驱动信号G(N-1)，第一N型开关管TN1的第一传输端连接低参考电位VGL，第一N型开关管TN1的第二传输端连接第一传输门C1的第二传输
复位及控制电路32包括第二N型开关管TN2、第三N型开关管TN3、第四N型开关管TN4、第一P型开关管TP1、第二P型开关管TP2、第三P型开关管TP3；
第二N型开关管TN2的第一传输端连接低参考电位VGL；
第三N型开关管TN3的第一传输端与第二N型开关管TN2的第二传输端连接，第二N型开关管TN2的控制端和第三N型开关管TN3中的一个接收第一控制信号，第二N型开关管TN2的控制端和第三N型开关管TN3中的另一个接收第三控制信号；
第四N型开关管TN4的控制端接收复位信号Reset，第四N型开关管TN4的第一传输端连接低参考电位VGL，第四N型开关管TN4的第二传输端连接第三N型开关管TN3的第二传输端；
第一P型开关管TP3的控制端接收所述复位信号Reset，第一P型开关管TP1的第一传输端连接高参考电位VGH；
第二P型开关管TP2的控制端接收第一控制信号D1(N)，第二P型开关管TP2的第一传输端连接第一P型开关管TP1的第二传输端，第二P型开关管TP2的第二传输端连接第三N型开关管TN3的第二传输端与第四N型开关管TN4的第二传输端的连接节点；
第三P型开关管TP3的控制端接收第二控制信号D2(N)，第三P型开关管TP3的第一传输端连接第一P型开关管TP1的第二传输端，第三P型开关管TP3的第二传输端连接第三N型开关管TN3的第二传输端与第四N型开关管的第二传输端的连接节点；
其中，第三控制信号从第三N型开关管TN3的第二传输端与第四N型开关管TN4的第二传输端的连接节点输出。
其中，反相电路33包括第一反相器F1和第二反相器F2；
第一反相器F1的输入端接收第三控制信号D3(N)；
第二反相器F2的输入端连接第一反相器F1的输入端，第二反相器F2的输入端输出第四控制信号D4(N)；
输出电路35包括与非门YF1以及串联设置的多个第三反相器F3；
与非门YF1的第一输入端接收第一时钟信号D1(N)，与非门YF1的第二输入端接收第四控制信号D4(N)，与非门YF1的输出端连接串联设置的多个第三反相器F3的上游输入端，串联设置的多个第三反相器F3中的第偶数个第三反相器F3的输出端输出本级反相扫描驱动信号XG(N)，串联设置的多个第三反相器F3中的第奇数个第三反相器F3的输出端输出本级正相扫描驱动信号G(N)；
锁存电路34包括第二传输门C2以及第四P型开关管TP4；
第二传输门C2的N型控制端接收第三控制信号D3(N)，第二传输门C2的P型控制端接收第四控制信号D4(N)，第二传输门C2的第一传输端接收第二时钟信号CK2，第二传输门C2的第二传输端输出第一控制信号D1(N)；
第四P型开关管TP4的控制端接收第三控制信号D3(N)，第四P型开关管TP4的第一传输端连接低参考电位VGL，第四P型开关管TP4的第一传输端连接第二传输门C2的第二传输端。
参阅图4，为本发明栅极驱动电路第二实施方式工作的波形时序图，当复位信号Reset变为高电位脉冲信号时，复位及控制电路33的第四N型开关管TN4打开，该电路输出低电位的第三控制信号D3(N)，锁存电路34中第四P型开关管TP4打开，该锁存电路34输出高电位的第一控制信号D1(N)，此时上级正相扫描驱动信号G(N-1)为低电位信号，上级反相扫描驱动信号G(N-1)为高电位信号，第一传输门C1打开，第一N型开关管TN1关闭，则第二控制信号D2(N)为高电位信号，因此复位及控制电路32中的第二N型开关管和第三N型开关管打开，使输出的第三控制信号D3(N)锁存在低电位。
而当上级正相扫描驱动信号G(N-1)为高电位信号时，即上级反相扫描驱动信号G(N-1)为低电位信号，输入电路31中的第一传输门C1关闭，第一N型开关管TN1打开，输出第二控制信号D2(N)为低电位信号，此时复位信号为低电位信号，所以复位及控制电路32中的第一P型开关管打开，第三P型开关管打开，所以输出的第三控制信号D3(N)为高电位信号，锁存电路34中的第二传输门2在第三控制信号D3(N)及其反相信号的控制下打开，如图4，此时第二时钟信号CK2也为高电位信号，因此锁存电路34输出的第一控制信号D1(N)也为高电位信号；而反相电路33中的第一反相器F1和第二反相器F2对第三控制信号D3(N)进行两次反相后得到第四控制信号D4(N)，最终由输出电路35输出本级正相扫描驱动信号G(N)和本级反相扫描驱动信号XG(N)。
在本发明第二实施方式中，通过改变电路结构，首先得到高电位的第三控制信号D3(N)，再经过反相器多次反相得到第四控制信号D4(N)，从而避免信号的电压损失，降低了本级正相扫描驱动信号G(N)的产生延迟。
参阅图5，为本发明一种液晶显示器一实施例的结构示意图，该液晶显示器包括显示面板501及背光502，显示面板501中包括多个级联设置的栅极驱动电路，其中栅极驱动电路为本发明栅极驱动电路第一实施方式以及可能的组合中的栅极驱动电路。
在本发明液晶显示器的后续实施例中，液晶显示器中的栅极驱动电路为本发明栅极驱动电路第二实施方式以及可能的组合中的栅极驱动电路。
此外，本发明实施例中所述的栅极驱动电路不仅仅局限应用于液晶显示器，本领域技术人员可以知道，还可以应用于OLED显示面板等领域，以及应用于手机、显示器、电视的栅极驱动领域。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (19)

  1. 一种栅极驱动电路，其中，包括：输入电路、复位及控制电路、反相电路、锁存电路以及输出电路，所述输入电路根据上级正相扫描驱动信号、上级反相扫描驱动信号以及所述锁存电路输出的第一控制信号产生第二控制信号，所述复位及控制电路根据复位信号、所述第一控制信号和所述第二控制信号产生第三控制信号，所述反相电路对所述第三控制信号进行至少一次反相处理，并产生第四控制信号，所述输出电路根据所述第四控制信号和第一时钟信号产生本级正相扫描驱动信号和本级反相扫描驱动信号，所述锁存电路根据所述第三控制信号和第二时钟信号产生所述第一控制信号，进而根据所述第二时钟信号锁存或改变所述第三控制信号的电压状态；
    其中，所述输入电路包括第一传输门以及第一P型开关管；
    所述第一传输门的N型控制端接收所述上级反相扫描驱动信号，所述第一传输门的P型控制端接收上级正相扫描驱动信号，所述第一传输门的第一传输端接收所述第一控制信号，所述第一传输门的第二传输端输出所述第二控制信号；
    所述第一P型开关管的控制端接收所述上级反相扫描驱动信号，所述第一P型开关管的第一传输端连接高参考电位，所述第一P型开关管的第二传输端连接所述第一传输门的第二传输端；
    其中，所述输出电路包括与非门以及串联设置的多个第二反相器；
    所述与非门的第一输入端接收第一时钟信号，所述与非门的第二输入端接收第四控制信号，所述与非门的输出端连接所述串联设置的多个第二反相器的上游输入端，所述串联设置的多个第二反相器中的第偶数个第二反相器的输出端输出所述本级反相扫描驱动信号，所述串联设置的多个第二反相器中的第奇数个第二反相器的输出端输出所述本级正相扫描驱动信号。
  2. 一种栅极驱动电路，其中，包括：输入电路、复位及控制电路、反相电路、锁存电路以及输出电路，所述输入电路根据上级正相扫描驱动信号、上级反相扫描驱动信号以及所述锁存电路输出的第一控制信号产生第二控制信号，所述复位及控制电路根据复位信号、所述第一控制信号和所述第二控制信号产生第三控制信号，所述反相电路对所述第三控制信号进行至少一次反相处理，并产生第四控制信号，所述输出电路根据所述第四控制信号和第一时钟信号产生本级正相扫描驱动信号和本级反相扫描驱动信号，所述锁存电路根据所述第三控制信号和第二时钟信号产生所述第一控制信号，进而根据所述第二时钟信号锁存或改变所述第三控制信号的电压状态。
  3. 根据权利要求2所述的栅极驱动电路，其中，所述输入电路包括第一传输门以及第一P型开关管；
    所述第一传输门的N型控制端接收所述上级反相扫描驱动信号，所述第一传输门的P型控制端接收上级正相扫描驱动信号，所述第一传输门的第一传输端接收所述第一控制信号，所述第一传输门的第二传输端输出所述第二控制信号；
    所述第一P型开关管的控制端接收所述上级反相扫描驱动信号，所述第一P型开关管的第一传输端连接高参考电位，所述第一P型开关管的第二传输端连接所述第一传输门的第二传输端。
  4. 根据权利要求3所述的栅极驱动电路，其中，所述复位及控制电路包括第二P型开关管、第三P型开关管、第四P型开关管、第一N型开关管、第二N型开关管以及第三N型开关管；
    所述第二P型开关管的第一传输端连接高参考电位；
    所述第三P型开关管的第一传输端连接所述第二P型开关管的第二传输端，所述第二P型开关管的控制端和所述第三P型开关管的控制端中的一个接收所述第一控制信号，所述第二P型开关管的控制端和所述第三P型开关管的控制端中的另一个接收所述第二控制信号；
    所述第四P型开关管的控制端接收所述复位信号，所述第四P型开关管的第一传输端连接高参考电位，所述第四P型开关管的第二传输端连接所述第三P型开关管的第二传输端；
    所述第一N型开关管的控制端接收所述复位信号，所述第一N型开关管的第一传输端连接所述第三P型开关管的第二传输端和所述第四P型开关管的第二传输端的连接节点；
    所述第二N型开关管的控制端接收所述第一控制信号，所述第二N型开关管的第一传输端连接所述第一N型开关管的第二传输端，所述第二N型开关管的第二传输端连接低参考电位；
    所述第三N型开关管的控制端接收所述第二控制信号，所述第三N型开关管的第一传输端连接所述第一N型开关管的第二传输端，所述第三N型开关管的第二传输端连接低参考电位；
    其中，所述第三控制信号从所述第三P型开关管的第二传输端和所述第四P型开关管的第二传输端的连接节点输出。
  5. 根据权利要求4所述的栅极驱动电路，其中，所述反相电路包括第一反相器；
    所述第一反相器的输入端接收所述第三控制信号，所述第一反相器的输出端输出所述第四控制信号。
  6. 根据权利要求2所述的栅极驱动电路，其中，所述输出电路包括与非门以及串联设置的多个第二反相器；
    所述与非门的第一输入端接收第一时钟信号，所述与非门的第二输入端接收第四控制信号，所述与非门的输出端连接所述串联设置的多个第二反相器的上游输入端，所述串联设置的多个第二反相器中的第偶数个第二反相器的输出端输出所述本级反相扫描驱动信号，所述串联设置的多个第二反相器中的第奇数个第二反相器的输出端输出所述本级正相扫描驱动信号。
  7. 根据权利要求5所述的栅极驱动电路，其中，所述锁存电路包括第二传输门以及第四N型开关管；
    所述第二传输门的P型控制端接收所述第三控制信号，所述第二传输门的N型控制端接收所述第四控制信号，所述第二传输门的第一传输端接收所述第二时钟信号，所述第二传输门的第二传输端输出所述第一控制信号；
    所述第四N型开关管的控制端接收所述第三控制信号，所述第四N型开关管的第一传输端连接低参考电位，所述第四N型开关管的第一传输端连接所述第二传输门的第二传输端。
  8. 根据权利要求7所述的栅极驱动电路，其中，所述锁存电路进一步包括第三反相器，所述第三反相器的输入端接收第二时钟信号，所述第三反相器的输出端连接所述第二传输门的第一传输端。
  9. 根据权利要求2所述的栅极驱动电路，其中，所述输入电路包括第一传输门以及第一N型开关管；
    所述第一传输门的N型控制端接收所述上级反相扫描驱动信号，所述第一传输门的P型控制端接收所述上级正相扫描驱动信号，所述第一传输门的第一传输端接收所述第一控制信号，所述第一传输门的第二传输端输出所述第二控制信号；
    所述第一N型开关管的控制端接收所述上级正相扫描驱动信号，所述第一N型开关管的第一传输端连接低参考电位，所述第一
    所述复位及控制电路包括第二N型开关管、第三N型开关管、第四N型开关管、第一P型开关管、第二P型开关管、第三P型开关管；
    所述第二N型开关管的第一传输端连接低参考电位；
    所述第三N型开关管的第一传输端与所述第二N型开关管的第二传输端连接，所述第二N型开关管的控制端和所述第三N型开关管中的一个接收所述第一控制信号，所述第二N型开关管的控制端和所述第三N型开关管中的另一个接收所述第三控制信号；
    所述第四N型开关管的控制端接收所述复位信号，所述第四N型开关管的第一传输端连接低参考电位，所述第四N型开关管的第二传输端连接所述第三N型开关管的第二传输端；
    所述第一P型开关管的控制端接收所述复位信号，所述第一P型开关管的第一传输端连接高参考电位；
    所述第二P型开关管的控制端接收所述第一控制信号，所述第二P型开关管的第一传输端连接所述第一P型开关管的第二传输端，所述第二P型开关管的第二传输端连接所述第三N型开关管的第二传输端与所述第四N型开关管的第二传输端的连接节点；
    所述第三P型开关管的控制端接收所述第二控制信号，所述第三P型开关管的第一传输端连接所述第一P型开关管的第二传输端，所述第三P型开关管的第二传输端连接所述第三N型开关管的第二传输端与所述第四N型开关管的第二传输端的连接节点；
    其中，所述第三控制信号从所述第三N型开关管的第二传输端与所述第四N型开关管的第二传输端的连接节点输出。
  10. 根据权利要求9所述的栅极驱动电路，其中，所述反相电路包括第一反相器和第二反相器；
    所述第一反相器的输入端接收所述第三控制信号；
    所述第二反相器的输入端连接所述第一反相器的输入端，所述第二反相器的输入端输出所述第四控制信号；
    所述输出电路包括与非门以及串联设置的多个第三反相器；
    所述与非门的第一输入端接收第一时钟信号，所述与非门的第二输入端接收第四控制信号，所述与非门的输出端连接所述串联设置的多个第三反相器的上游输入端，所述串联设置的多个第三反相器中的第偶数个第三反相器的输出端输出所述本级反相扫描驱动信号，所述串联设置的多个第三反相器中的第奇数个第三反相器的输出端输出所述本级正相扫描驱动信号；
    所述锁存电路包括第二传输门以及第四P型开关管；
    所述第二传输门的N型控制端接收所述第三控制信号，所述第二传输门的P型控制端接收所述第四控制信号，所述第二传输门的第一传输端接收所述第二时钟信号，所述第二传输门的第二传输端输出所述第一控制信号；
    所述第四P型开关管的控制端接收所述第三控制信号，所述第四P型开关管的第一传输端连接低参考电位，所述第四P型开关管的第一传输端连接所述第二传输门的第二传输端。
  11. 一种液晶显示器，其中，所述液晶显示器包括多个级联设置的栅极驱动电路，所述栅极驱动电路包括：输入电路、复位及控制电路、反相电路、锁存电路以及输出电路，所述输入电路根据上级正相扫描驱动信号、上级反相扫描驱动信号以及所述锁存电路输出的第一控制信号产生第二控制信号，所述复位及控制电路根据复位信号、所述第一控制信号和所述第二控制信号产生第三控制信号，所述反相电路对所述第三控制信号进行至少一次反相处理，并产生第四控制信号，所述输出电路根据所述第四控制信号和第一时钟信号产生本级正相扫描驱动信号和本级反相扫描驱动信号，所述锁存电路根据所述第三控制信号和第二时钟信号产生所述第一控制信号，进而根据所述第二时钟信号锁存或改变所述第三控制信号的电压状态。
  12. 根据权利要求11所述的液晶显示器，其中，所述输入电路包括第一传输门以及第一P型开关管；
    所述第一传输门的N型控制端接收所述上级反相扫描驱动信号，所述第一传输门的P型控制端接收上级正相扫描驱动信号，所述第一传输门的第一传输端接收所述第一控制信号，所述第一传输门的第二传输端输出所述第二控制信号；
    所述第一P型开关管的控制端接收所述上级反相扫描驱动信号，所述第一P型开关管的第一传输端连接高参考电位，所述第一P型开关管的第二传输端连接所述第一传输门的第二传输端。
  13. 根据权利要求12所述的液晶显示器，其中，所述复位及控制电路包括第二P型开关管、第三P型开关管、第四P型开关管、第一N型开关管、第二N型开关管以及第三N型开关管；
    所述第二P型开关管的第一传输端连接高参考电位；
    所述第三P型开关管的第一传输端连接所述第二P型开关管的第二传输端，所述第二P型开关管的控制端和所述第三P型开关管的控制端中的一个接收所述第一控制信号，所述第二P型开关管的控制端和所述第三P型开关管的控制端中的另一个接收所述第二控制信号；
    所述第四P型开关管的控制端接收所述复位信号，所述第四P型开关管的第一传输端连接高参考电位，所述第四P型开关管的第二传输端连接所述第三P型开关管的第二传输端；
    所述第一N型开关管的控制端接收所述复位信号，所述第一N型开关管的第一传输端连接所述第三P型开关管的第二传输端和所述第四P型开关管的第二传输端的连接节点；
    所述第二N型开关管的控制端接收所述第一控制信号，所述第二N型开关管的第一传输端连接所述第一N型开关管的第二传输端，所述第二N型开关管的第二传输端连接低参考电位；
    所述第三N型开关管的控制端接收所述第二控制信号，所述第三N型开关管的第一传输端连接所述第一N型开关管的第二传输端，所述第三N型开关管的第二传输端连接低参考电位；
    其中，所述第三控制信号从所述第三P型开关管的第二传输端和所述第四P型开关管的第二传输端的连接节点输出。
  14. 根据权利要求13所述的液晶显示器，其中，所述反相电路包括第一反相器；
    所述第一反相器的输入端接收所述第三控制信号，所述第一反相器的输出端输出所述第四控制信号。
  15. 根据权利要求11所述的液晶显示器，其中，所述输出电路包括与非门以及串联设置的多个第二反相器；
    所述与非门的第一输入端接收第一时钟信号，所述与非门的第二输入端接收第四控制信号，所述与非门的输出端连接所述串联设置的多个第二反相器的上游输入端，所述串联设置的多个第二反相器中的第偶数个第二反相器的输出端输出所述本级反相扫描驱动信号，所述串联设置的多个第二反相器中的第奇数个第二反相器的输出端输出所述本级正相扫描驱动信号。
  16. 根据权利要求14所述的液晶显示器，其中，所述锁存电路包括第二传输门以及第四N型开关管；
    所述第二传输门的P型控制端接收所述第三控制信号，所述第二传输门的N型控制端接收所述第四控制信号，所述第二传输门的第一传输端接收所述第二时钟信号，所述第二传输门的第二传输端输出所述第一控制信号；
    所述第四N型开关管的控制端接收所述第三控制信号，所述第四N型开关管的第一传输端连接低参考电位，所述第四N型开关管的第一传输端连接所述第二传输门的第二传输端。
  17. 根据权利要求16所述的液晶显示器，其中，所述锁存电路进一步包括第三反相器，所述第三反相器的输入端接收第二时钟信号，所述第三反相器的输出端连接所述第二传输门的第一传输端。
  18. 根据权利要求11所述的液晶显示器，其中，所述输入电路包括第一传输门以及第一N型开关管；
    所述第一传输门的N型控制端接收所述上级反相扫描驱动信号，所述第一传输门的P型控制端接收所述上级正相扫描驱动信号，所述第一传输门的第一传输端接收所述第一控制信号，所述第一传输门的第二传输端输出所述第二控制信号；
    所述第一N型开关管的控制端接收所述上级正相扫描驱动信号，所述第一N型开关管的第一传输端连接低参考电位，所述第一
    所述复位及控制电路包括第二N型开关管、第三N型开关管、第四N型开关管、第一P型开关管、第二P型开关管、第三P型开关管；
    所述第二N型开关管的第一传输端连接低参考电位；
    所述第三N型开关管的第一传输端与所述第二N型开关管的第二传输端连接，所述第二N型开关管的控制端和所述第三N型开关管中的一个接收所述第一控制信号，所述第二N型开关管的控制端和所述第三N型开关管中的另一个接收所述第三控制信号；
    所述第四N型开关管的控制端接收所述复位信号，所述第四N型开关管的第一传输端连接低参考电位，所述第四N型开关管的第二传输端连接所述第三N型开关管的第二传输端；
    所述第一P型开关管的控制端接收所述复位信号，所述第一P型开关管的第一传输端连接高参考电位；
    所述第二P型开关管的控制端接收所述第一控制信号，所述第二P型开关管的第一传输端连接所述第一P型开关管的第二传输端，所述第二P型开关管的第二传输端连接所述第三N型开关管的第二传输端与所述第四N型开关管的第二传输端的连接节点；
    所述第三P型开关管的控制端接收所述第二控制信号，所述第三P型开关管的第一传输端连接所述第一P型开关管的第二传输端，所述第三P型开关管的第二传输端连接所述第三N型开关管的第二传输端与所述第四N型开关管的第二传输端的连接节点；
    其中，所述第三控制信号从所述第三N型开关管的第二传输端与所述第四N型开关管的第二传输端的连接节点输出。
  19. 根据权利要求18所述的液晶显示器，其中，所述反相电路包括第一反相器和第二反相器；
    所述第一反相器的输入端接收所述第三控制信号；
    所述第二反相器的输入端连接所述第一反相器的输入端，所述第二反相器的输入端输出所述第四控制信号；
    所述输出电路包括与非门以及串联设置的多个第三反相器；
    所述与非门的第一输入端接收第一时钟信号，所述与非门的第二输入端接收第四控制信号，所述与非门的输出端连接所述串联设置的多个第三反相器的上游输入端，所述串联设置的多个第三反相器中的第偶数个第三反相器的输出端输出所述本级反相扫描驱动信号，所述串联设置的多个第三反相器中的第奇数个第三反相器的输出端输出所述本级正相扫描驱动信号；
    所述锁存电路包括第二传输门以及第四P型开关管；
    所述第二传输门的N型控制端接收所述第三控制信号，所述第二传输门的P型控制端接收所述第四控制信号，所述第二传输门的第一传输端接收所述第二时钟信号，所述第二传输门的第二传输端输出所述第一控制信号；
    所述第四P型开关管的控制端接收所述第三控制信号，所述第四P型开关管的第一传输端连接低参考电位，所述第四P型开关管的第一传输端连接所述第二传输门的第二传输端。
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106023937B (zh) * 2016-07-28 2018-09-18 武汉华星光电技术有限公司 栅极驱动电路
CN107610737B (zh) * 2017-10-26 2023-07-21 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN107633817B (zh) 2017-10-26 2023-12-05 京东方科技集团股份有限公司 源极驱动单元及其驱动方法、源极驱动电路、显示装置
CN108520725A (zh) * 2018-04-20 2018-09-11 京东方科技集团股份有限公司 一种源极驱动电路、显示设备及驱动方法
WO2023133826A1 (zh) * 2022-01-14 2023-07-20 京东方科技集团股份有限公司 驱动控制电路、栅极驱动电路、显示基板及显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100205233B1 (ko) * 1996-06-14 1999-07-01 김탁중 게이트 구동회로
CN104361853A (zh) * 2014-12-02 2015-02-18 京东方科技集团股份有限公司 移位寄存器单元、移位寄存器、栅极驱动电路和显示装置
CN104485080A (zh) * 2014-12-31 2015-04-01 深圳市华星光电技术有限公司 用于液晶显示装置的goa电路
CN104992660A (zh) * 2015-07-29 2015-10-21 武汉华星光电技术有限公司 驱动电路
CN105096891A (zh) * 2015-09-02 2015-11-25 深圳市华星光电技术有限公司 Cmos goa电路
CN105185338A (zh) * 2015-09-28 2015-12-23 武汉华星光电技术有限公司 Cmos goa电路

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104575408B (zh) * 2013-10-16 2017-12-12 天钰科技股份有限公司 栅极脉冲调变电路及其削角调变方法
CN104392686B (zh) * 2014-10-21 2017-01-25 厦门天马微电子有限公司 移位寄存单元及驱动电路及显示装置
US9678593B2 (en) * 2014-12-31 2017-06-13 Shenzhen China Star Optoelectronics Technology Co. Gate on array circuit applied to liquid crystal display device
CN105118463B (zh) * 2015-09-22 2018-01-09 深圳市华星光电技术有限公司 一种goa电路及液晶显示器
CN105096900B (zh) * 2015-09-23 2019-01-25 深圳市华星光电技术有限公司 扫描驱动电路及具有该电路的液晶显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100205233B1 (ko) * 1996-06-14 1999-07-01 김탁중 게이트 구동회로
CN104361853A (zh) * 2014-12-02 2015-02-18 京东方科技集团股份有限公司 移位寄存器单元、移位寄存器、栅极驱动电路和显示装置
CN104485080A (zh) * 2014-12-31 2015-04-01 深圳市华星光电技术有限公司 用于液晶显示装置的goa电路
CN104992660A (zh) * 2015-07-29 2015-10-21 武汉华星光电技术有限公司 驱动电路
CN105096891A (zh) * 2015-09-02 2015-11-25 深圳市华星光电技术有限公司 Cmos goa电路
CN105185338A (zh) * 2015-09-28 2015-12-23 武汉华星光电技术有限公司 Cmos goa电路

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