WO2017049742A1 - 一种goa电路及其驱动方法、液晶显示器 - Google Patents
一种goa电路及其驱动方法、液晶显示器 Download PDFInfo
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- WO2017049742A1 WO2017049742A1 PCT/CN2015/093975 CN2015093975W WO2017049742A1 WO 2017049742 A1 WO2017049742 A1 WO 2017049742A1 CN 2015093975 W CN2015093975 W CN 2015093975W WO 2017049742 A1 WO2017049742 A1 WO 2017049742A1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
- G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
- G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0404—Matrix technologies
- G09G2300/0408—Integration of the drivers onto the display substrate
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0202—Addressing of scan or signal lines
- G09G2310/0218—Addressing of scan or signal lines with collection of electrodes in groups for n-dimensional addressing
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/026—Arrangements or methods related to booting a display
Definitions
- the present invention relates to the field of display technologies, and in particular, to a GOA circuit, a driving method thereof, and a liquid crystal display.
- Array substrate row driver (GOA, Gate Driver On Array or Gate On The Array) circuit is formed by using a conventional thin film transistor display device (TFT-LCD) array (Array) process to form a gate line scan driving signal circuit on the array substrate to realize a progressive scanning operation on the gate line.
- TFT-LCD thin film transistor display device
- Array gate line scan driving signal circuit on the array substrate to realize a progressive scanning operation on the gate line.
- COF flexible circuit board
- COG glass circuit board
- the GOA circuit needs to implement the function of stopping the signal to match the touch screen, such as scanning with the touch screen.
- the display device Normally, after the GOA circuit stops in the implementation signal, the display device needs to be black-awakeed.
- the GOA circuit needs to set all the gate lines to be in a conductive state for a period of time, by applying a black voltage to the data lines. Clear the level remaining in the pixel capacitor to make the display device display well. This period of time is called the gate line full open (All Gate On) stage.
- the GOA circuit may have a functional failure risk when implementing All Gate On, and thus the All Gate On function cannot be stably implemented.
- the technical problem to be solved by the present invention is to provide a GOA circuit and a driving method thereof, and a liquid crystal display, which can open the gate end of each pixel when the black screen of the display wakes up, and input a low level signal to each pixel to prevent the display from waking up in a black screen. Leakage conditions, while improving the stability of the circuit.
- a technical solution adopted by the present invention is to provide a GOA circuit for a liquid crystal display, the GOA circuit comprising a plurality of cascaded GOA units, and setting N to a positive integer, wherein the Nth stage
- the GOA unit includes an Nth stage pass circuit, an Nth stage Q point control circuit, an Nth stage P point control circuit, an Nth stage output circuit, and a first switch circuit; wherein the Nth stage pass circuit is connected to the Nth stage Q Point control circuit, the Nth stage Q point control circuit is connected to the Nth stage output circuit through the Q point, the Nth stage level transmission circuit is connected to the Nth stage P point control circuit, and the Nth stage P point control circuit is connected to the Nth stage through the P point An output circuit, the Nth output circuit connection is further connected to the Nth scan line; the first switch circuit is connected to the Nth scan line for inputting an open signal to the Nth scan line before the liquid crystal display is displayed, so that The thin film transistor in the pixel connected to
- the first switching circuit includes a first thin film transistor, and a source thereof is connected to the Nth-level scan line.
- the gate of the first thin film transistor is connected to a high-level first turn-on signal, so that the first A source and a drain of a thin film transistor are turned on, and a high level signal is applied to the Nth-order scan line to turn on the thin film transistor in the pixel connected to the Nth-order scan line.
- the GOA unit further includes a second switching circuit;
- the second switching circuit includes a second thin film transistor having a drain connected to the Nth-th scan line, and after passing a high level signal to the Nth-order scan line, to the second thin film
- the gate of the transistor is connected to a second high-level turn-on signal to turn on the source and drain of the second thin film transistor, and to pass a low-level signal to the N-th scan line to make the Nth stage
- the thin film transistor in the pixel connected to the scan line is turned off.
- the Nth stage pass circuit includes a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, and a sixth thin film transistor; the gates of the third thin film transistor and the fourth thin film transistor are connected to the forward scan control signal, And accessing the N-2th scanning signal through the third thin film transistor during the forward scanning, and accessing the N+1th clock signal through the fourth thin film transistor; and connecting the gates of the fifth thin film transistor and the sixth thin film transistor A reverse scan control signal is input for accessing the N+2th scan signal through the fifth thin film transistor during the reverse scan and the N-1th stage clock signal through the sixth thin film transistor.
- the Nth-level Q-point control circuit includes: a seventh thin film transistor T7 whose gate is connected to the N-2th-level clock signal, and whose drain is connected to the N-2th-level scan signal during the forward scan or is in the opposite direction.
- the N+2 scanning signal is connected to the scanning period, and the source is connected to the Q point;
- the eighth thin film transistor has a gate connected to the N-2th scanning signal, and the drain is connected to the P point, and the source is connected.
- the Nth P point control circuit includes: a tenth thin film transistor whose gate accesses the N+1th clock signal during the forward scan or the N-2th clock signal during the reverse scan, The drain is connected to a high level signal, and its source is connected to the P point; the eleventh thin film transistor has a gate connected to the Q point, a drain connected to the P point, and a source connected to a low level signal.
- the Nth P point control circuit further includes: a twelfth thin film transistor having a gate connected to the first turn-on signal, a drain connected to the P point, and a source connected to a low level signal.
- the Nth stage output circuit includes: a thirteenth thin film transistor having a gate connected to the Q point, a drain connected to the Nth stage clock signal, a source connected to the Nth stage scan line, and a fourteenth thin film transistor
- the gate is connected to the P point, the drain is connected to the Nth scan line, and the source is connected to a low level signal.
- another technical solution adopted by the present invention is to provide a driving method of a GOA circuit, which is applied to a GOA circuit, and the GOA circuit includes a plurality of cascaded GOA units, and N is set to a positive integer, wherein The Nth stage GOA unit includes a first switching circuit, and the first switching circuit is connected to the Nth scanning line.
- the method includes: opening a first switching circuit of each stage of the GOA unit, and inputting an opening signal to each of the scanning lines of the stage The thin film transistors in the pixels connected to the scan lines of each stage are turned on; the switching circuit of each stage GOA unit is turned off, and scanning is started from the first stage GOA unit or the last stage GOA unit.
- a liquid crystal display including a GOA circuit, the GOA circuit including a plurality of cascaded GOA units, and setting N to a positive integer
- the Nth stage GOA unit includes an Nth stage level transmission circuit, an Nth stage Q point control circuit, an Nth stage P point control circuit, an Nth stage output circuit, and a first switching circuit; wherein, the Nth stage level transmission circuit is connected N-level Q-point control circuit, the N-th Q-point control circuit is connected to the N-th stage output circuit through the Q point, the N-th stage-level transmission circuit is connected to the N-th P-point control circuit, and the N-th P-point control circuit is connected through the P point.
- the Nth output circuit is connected to the Nth scan line; the first switch circuit is connected to the Nth scan line for inputting an open signal to the Nth scan line before the liquid crystal display is displayed.
- the thin film transistors in the pixels connected to the Nth-order scan lines are turned on.
- the first switching circuit includes a first thin film transistor, and a source thereof is connected to the Nth-level scan line.
- the gate of the first thin film transistor is connected to a high-level first turn-on signal, so that the first A source and a drain of a thin film transistor are turned on, and a high level signal is applied to the Nth-order scan line to turn on the thin film transistor in the pixel connected to the Nth-order scan line.
- the GOA unit further includes a second switching circuit;
- the second switching circuit includes a second thin film transistor having a drain connected to the Nth-th scan line, and after passing a high level signal to the Nth-order scan line, to the second thin film
- the gate of the transistor is connected to a second high-level turn-on signal to turn on the source and drain of the second thin film transistor, and to pass a low-level signal to the N-th scan line to make the Nth stage
- the thin film transistor in the pixel connected to the scan line is turned off.
- the Nth stage pass circuit includes a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, and a sixth thin film transistor; the gates of the third thin film transistor and the fourth thin film transistor are connected to the forward scan control signal, And accessing the N-2th scanning signal through the third thin film transistor during the forward scanning, and accessing the N+1th clock signal through the fourth thin film transistor; and connecting the gates of the fifth thin film transistor and the sixth thin film transistor A reverse scan control signal is input for accessing the N+2th scan signal through the fifth thin film transistor during the reverse scan and the N-1th stage clock signal through the sixth thin film transistor.
- the Nth-level Q-point control circuit includes: a seventh thin film transistor having a gate connected to the N-2th clock signal, the drain of which is connected to the N-2th scanning signal during the forward scanning or in the reverse direction During the scanning period, the N+2th scanning signal is connected, and the source thereof is connected to the Q point; the eighth thin film transistor has a gate connected to the N-2th scanning signal, the drain thereof is connected to the P point, and the source thereof is connected to the first point. a low-level signal; a ninth thin film transistor having a gate connected to a drain of the eighth thin film transistor, a drain connected to a source of the seventh thin film transistor, and a source connected to a low level signal.
- the Nth P point control circuit includes: a tenth thin film transistor whose gate accesses the N+1th clock signal during the forward scan or the N-2th clock signal during the reverse scan, The drain is connected to a high level signal, and its source is connected to the P point; the eleventh thin film transistor has a gate connected to the Q point, a drain connected to the P point, and a source connected to a low level signal.
- the Nth P point control circuit further includes: a twelfth thin film transistor having a gate connected to the first turn-on signal, a drain connected to the P point, and a source connected to a low level signal.
- the Nth stage output circuit includes: a thirteenth thin film transistor having a gate connected to the Q point, a drain connected to the Nth stage clock signal, a source connected to the Nth stage scan line, and a fourteenth thin film transistor
- the gate is connected to the P point, the drain is connected to the Nth scan line, and the source is connected to a low level signal.
- the present invention adds a first switching circuit and a second switching circuit on the Nth scanning line of each stage of the GOA unit of the GOA circuit, the first switching circuit is used for Before the display panel is displayed, a high level signal is sent to the Nth scan line of each level of the GOA unit, and the second switch circuit is used to open an open signal at the Nth scan line to turn on the TFT of each pixel. And pass a low level signal to each pixel to remove the residual charge in the pixel capacitance, thereby achieving All The Gate On function helps prevent the display from leaking when the black screen wakes up, and improves the stability of the circuit.
- FIG. 1 is a schematic structural diagram of a circuit of a first embodiment of a GOA circuit of the present invention
- FIG. 2 is a circuit diagram of a GOA unit in a first embodiment of the GOA circuit of the present invention
- FIG. 3 is a schematic structural diagram of a circuit of a second embodiment of the GOA circuit of the present invention.
- Figure 4 is a circuit diagram of a second embodiment of the GOA circuit of the present invention.
- Figure 5 is a circuit timing diagram of a second embodiment of the GOA circuit of the present invention.
- FIG. 6 is a flow chart of an embodiment of a GOA circuit driving method of the present invention.
- Fig. 7 is a schematic structural view of an embodiment of a liquid crystal display of the present invention.
- the GOA circuit includes a plurality of cascaded GOA units, and N is set to a positive integer.
- the Nth stage GOA unit 100 includes an Nth stage scan driving circuit 101.
- the Nth-order scan line G(N) for driving the display area, the Nth stage GOA unit further includes a first switch circuit 102, and the first switch circuit 102 is connected to the Nth-order scan line G(N) for use in the liquid crystal
- the display is turned on in response to the first turn-on signal Gas1, and an open signal is applied to the N-th scan line G(N) to enable the thin film transistor in the pixel connecting the Nth-order scan line G(N). through.
- the Nth stage GOA unit 100 further includes a second switch circuit 103, and the second switch circuit 103 is connected to the Nth stage scan line G(N) for the Nth scan line at the first switch circuit 102.
- G(N) is supplied with a turn-off signal to turn off the thin film transistor in the pixel to which the Nth scanning line G(N) is connected.
- the Nth stage GOA unit 100 includes the first switch circuit 102 and the second switch circuit 103, that is, the GOA unit of each stage includes the first switch circuit 102 and the second switch circuit 103.
- the N-th scan line G(N) is connected to the first switch circuit 102 and the second switch circuit 103, and is used to sequentially turn on an open signal to the gate end to make each pixel when the display panel is awake.
- the gate is open.
- the first switching circuit includes a first thin film transistor T1 whose source is connected to the Nth-order scan line G(N), and the gate of the first thin film transistor T1 is displayed before the liquid crystal display is displayed.
- a first open signal Gas1 of a high level is connected to enable the source and the drain of the first thin film transistor T1 to be turned on, and a high level signal is applied to the Nth scanning line G(N);
- the switching circuit includes a second thin film transistor T2 whose drain is connected to the Nth-th scanning line G(N), and after a high-level signal is applied to the N-th scanning line G(N), the gate of the second thin film transistor T2 is connected.
- a second high-level second turn-on signal Gas2 is connected to turn on the source and the drain of the second thin film transistor T2, and a low-level signal is applied to the N-th scan line G(N).
- the TFTs in each pixel are also N-type.
- the first thin film transistor T1 is N-type, in All Gate.
- the On phase when the first turn-on signal Gas1 is at a high level, the first transistor T1 is turned on, and the first turn-on signal Gas1 of the drain thereof is transmitted to the source, and the Nth-th scan line G(N) is also high. Flat, that is, the horizontal scanning line of this level is turned on and a low level signal is applied.
- the first turn-on signal Gas1 is at a low level, the first transistor T1 is turned off, but the second turn-on signal Gas2 is at a high level, and the second transistor T2 is turned on, and then passes to the Nth-th scan line G(N).
- this phase can be called the reset phase.
- each stage of the GOA unit performs the same operation, and the first enable signal Gas1 and the second enable signal Gas2 may be shared by each level of the GOA unit.
- first transistor T1 and the second transistor T2 are P-type
- the first transistor T1 and the second transistor T2 are P-type gate-connected first turn-on signal Gas1 and second turn-on signal Gas2 Exchange each other.
- the P-type or the N-type of the thin film transistor in each of the following embodiments or each circuit can be replaced, and those skilled in the art can obtain other deformation circuits that only change the type of the thin film transistor according to the circuit of the present invention, which will not be described below.
- a first switch circuit and a second switch circuit are added on the Nth scan line G(N) of each level of the GOA unit of the GOA circuit, and the first switch circuit is used in the display panel.
- the Nth scan line G(N) to each level of the GOA unit a turn-on signal to turn on the TFT of each pixel, and a low-level signal is applied to each pixel, and the second switch circuit is configured to pass a low-level signal to the N-th scan line G(N) Clear the residual charge in the pixel capacitor to achieve All The Gate On function helps prevent the display from leaking when the black screen wakes up, and improves the stability of the circuit.
- the Nth stage scan driving circuit includes an Nth stage stage transmission circuit 301, an Nth stage Q point control circuit 302, an Nth stage P point control circuit 303, and The Nth stage output circuit 304.
- the Nth stage pass circuit 301 is connected to the Nth stage Q point control circuit 302, and the Nth stage Q point control circuit 302 is connected to the Nth stage output circuit 304 through the Q point for pulling up the level of the Q point during the scan to The Nth stage output circuit 304 is caused to output a scan signal.
- the Nth stage pass circuit 301 is connected to the Nth stage P point control circuit 303, and the Nth stage P point control circuit 303 is connected to the Nth stage output circuit 304 through the P point for pulling up the level of the P point during the non-scanning period.
- the Nth stage output circuit 304 outputs a signal of a low level.
- FIG. 4 a circuit diagram of a second embodiment of the GOA circuit of the present invention, in a specific circuit:
- the Nth stage pass circuit 301 includes a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5, and a sixth thin film transistor T6; the gates of the third thin film transistor T3 and the fourth thin film transistor T4 are forward-connected Scanning control signal U2D for accessing the N-2th scanning signal G(N-2) through the third thin film transistor T3 during the forward scanning, and accessing the N+1th clock signal through the fourth thin film transistor T4 CK(N+1); the gates of the fifth thin film transistor T5 and the sixth thin film transistor T6 are connected to the reverse scan control signal D2U for accessing the N+2 stage through the fifth thin film transistor T5 during the reverse scan The signal G(N+2) is scanned, and the N-1th clock signal CK(N-1) is accessed through the sixth thin film transistor T6.
- the Nth-order Q-point 302 control circuit includes: a seventh thin film transistor T7 whose gate is connected to the N-2th-level clock signal CK(N-2), and whose drain is connected to the N-2th stage during the forward scanning period. Scanning signal G(N-2) or accessing N+2th scanning signal G(N+2) during reverse scanning, the source is connected to Q point; the eighth thin film transistor T8 is connected to the Nth gate -2 scanning signal G(N-2) having a drain connected to P point and a source connected to a low level signal; a ninth thin film transistor T9 having a gate connected to the drain of the eighth thin film transistor T8, The drain is connected to the source of the seventh thin film transistor T7, and the source thereof is connected to a low level signal.
- the Nth stage P point control circuit 303 includes: a tenth thin film transistor T10 whose gate accesses the N+1th clock signal CK(N+1) during the forward scan or the Nth during the reverse scan.
- the second-level clock signal CK(N-1) has a drain connected to a high-level signal, and its source is connected to the P point;
- the eleventh thin film transistor T11 has a gate connected to the Q point and a drain connected to the P point. Its source is connected to a low level signal.
- the Nth stage P point control circuit 303 may further include: a twelfth thin film transistor T12 having a gate connected to the first turn-on signal Gas1, a drain connected to the P point, and a source connected to a low level signal.
- the Nth stage output circuit 304 includes: a thirteenth thin film transistor T13 having a gate connected to the Q point, a drain connected to the Nth stage clock signal CK(N), and a source connected to the Nth stage scan line G(N)
- the fourteenth thin film transistor T14 has a gate connected to the P point, a drain connected to the Nth scanning line G(N), and a source connected to a low level signal.
- H represents a high level signal
- L represents a low level signal
- the N-2th scanning line G(N-2) and the N+1th stage clock signal CK(N+1) are supplied.
- U2D is low level
- D2U is high level
- third thin film transistor T3 and fourth thin film transistor T4 are turned off
- fifth thin film transistor T5 and sixth thin film transistor are turned off.
- T6 is turned on to pass the N+2th scanning line G(N+2) and the N-1th clock signal CK(N-1) to the Nth Q point 302 and the Nth P point control circuit 303.
- the Gas1 signal is at a high level, and the first thin film transistor T1 is turned on, and a high level signal is input to the Nth scanning line G(N), thereby turning on the TFT in each pixel.
- the signal line of the pixel is connected to the touch signal, so that the display screen is black-awakeed at any time.
- a low level ie, black voltage
- the Nth-th scanning line G(N) outputs a high-level signal regardless of how the N-th scanning driving circuit operates.
- the Gas1 signal is at a low level
- the first thin film transistor T1 is turned off
- the Gas2 signal is at a high level
- the second thin film transistor T2 is turned on
- the Nth scanning line G(N) is turned on.
- a low level signal is input so that the TFT in each pixel is turned off, and the output signal of the Nth scanning line G(N) is reset.
- the reset interval since the low-level signal L directly enters the N-th scanning line G(N), the N-th scanning line G(N) outputs a low power regardless of how the N-th scanning driving circuit operates. Flat signal.
- the Gas1 signal and the Gas2 signal are both low, the first thin film transistor T1 and the second thin film transistor T2 are both turned off, and the signals output by the Nth scanning line G(N) are
- the Nth stage transmission circuit 301, the Nth stage Q point control circuit 302, the Nth stage P point control circuit 303, and the Nth stage output circuit 304 are determined.
- the N-2th clock signal CK(N-2) is at a high level
- the (N+1)th clock signal CK(N+1) is at a low level
- G(N-2) is at a high level.
- the eighth thin film transistor T8 is turned on, and the P point is low level, so that the fourteenth thin film transistor T14 is turned off, and at this time, the seventh thin film transistor T7 is turned on, and the Q point is high level, the thirteenth thin film transistor is turned on.
- T13 is turned on, and the Nth stage clock signal CK(N) is supplied to the Nth stage scanning line G(N), that is, the low level signal.
- the N-2th clock signal CK(N-2) When the N-2th clock signal CK(N-2) is low, the N+1th clock signal CK(N+1) is low, and G(N-2) is low, the seventh The thin film transistor T7 and the eighth thin film transistor T8 are both turned off, and the levels of the Q point and the P point remain unchanged, that is, the Q point is still at a high level, the P point is still at a low level, and the Nth stage clock signal CK(N) The Nth scanning line G(N) is passed, that is, a low level signal.
- the N-2th clock signal CK(N-2) When the N-2th clock signal CK(N-2) is low, the N+1th clock signal CK(N+1) is low, and G(N-2) is low, the seventh The thin film transistor T7 and the eighth thin film transistor T8 are both turned off, and the levels of the Q point and the P point remain unchanged, that is, the Q point is still at a high level, the P point is still at a low level, and the Nth stage clock signal CK(N)
- the Nth-level scan line G(N) that is, the high level signal, is passed, that is, the output of the stage is completed.
- a first switch circuit and a second switch circuit are added on the Nth scan line G(N) of each level of the GOA unit of the GOA circuit, and the first switch circuit is used in the display panel.
- a high level signal is applied to the Nth scanning line G(N) of each stage of the GOA unit, and the second switching circuit is used after the low level signal is applied to the Nth scanning line G(N).
- the Gate On function helps prevent the display from leaking when the black screen wakes up, and improves the stability of the circuit.
- FIG. 6 a flowchart of an embodiment of a GOA circuit driving method of the present invention is applied to the GOA circuit as described above.
- the method includes:
- Step 601 Turn on the first switch circuit of each stage of the GOA unit, and input an open signal to the scan lines of each stage to turn on the thin film transistors in the pixels connected to the scan lines of each stage.
- Step 602 Turn off the switching circuit of each level of the GOA unit, and start scanning from the first stage GOA unit or the last stage GOA unit.
- This embodiment is based on a driving method of each of the above-described GOA circuits, and an embodiment thereof refers to the above various embodiments, and details are not described herein again.
- a schematic structural diagram of an embodiment of a liquid crystal display according to the present invention includes a display panel 701 and a backlight 702.
- the display panel 701 includes a GOA circuit, wherein the GOA circuit is a GOA circuit according to various embodiments described above. The specific implementation is similar, and details are not described herein again.
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Abstract
Description
Claims (17)
- 一种GOA电路,用于液晶显示器,其中,所述GOA电路包括多个级联的GOA单元,设定N为正整数,其中,第N级GOA单元包括第N级级传电路、第N级Q点控制电路、第N级P点控制电路、第N级输出电路以及第一开关电路;其中,所述第N级级传电路连接所述第N级Q点控制电路,所述第N级Q点控制电路通过Q点连接所述第N级输出电路,所述第N级级传电路连接所述第N级P点控制电路,所述第N级P点控制电路通过P点连接所述第N级输出电路,所述第N级输出电路连接还连接第N级扫描线;所述第一开关电路连接所述第N级扫描线,用于在所述液晶显示器显示前向所述第N级扫描线通入一开启信号,以使所述第N级扫描线连接的像素中的薄膜晶体管导通。
- 根据权利要求1所述的电路,其中,所述第一开关电路包括第一薄膜晶体管,其源极连接所述第N级扫描线,在所述液晶显示器显示前,所述第一薄膜晶体管的栅极接入一高电平的第一开启信号,以使所述第一薄膜晶体管的源极和漏极导通,并向所述第N级扫描线通入高电平信号,以使所述第N级扫描线连接的像素中的薄膜晶体管导通。
- 根据权利要求1所述的电路,其中,所述GOA单元还包括第二开关电路;所述第二开关电路包括第二薄膜晶体管,其漏极连接所述第N级扫描线,在向所述第N级扫描线通入高电平信号后,向所述第二薄膜晶体管的栅极接入一高电平的第二开启信号,以使所述第二薄膜晶体管的源极和漏极导通,并向所述第N级扫描线通入低电平信号,以使所述第N级扫描线连接的像素中的薄膜晶体管关闭。
- 根据权利要求1所述的电路,其中,所述第N级级传电路包括第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管以及第六薄膜晶体管;所述第三薄膜晶体管和第四薄膜晶体管的栅极接入正向扫描控制信号,用于在正向扫描期间通过所述第三薄膜晶体管接入第N-2级扫描信号,并通过所述第四薄膜晶体管接入第N+1级时钟信号;所述第五薄膜晶体管和第六薄膜晶体管的栅极接入反向扫描控制信号,用于在反向扫描期间通过所述第五薄膜晶体管接入第N+2级扫描信号,并通过所述第六薄膜晶体管接入第N-1级时钟信号。
- 根据权利要求1所述的电路,其中,所述第N级Q点控制电路包括:第七薄膜晶体管,其栅极接入第N-2级时钟信号,其漏极在正向扫描期间接入第N-2级扫描信号或在反向扫描期间接入第N+2级扫描信号,其源极连接所述Q点;第八薄膜晶体管,其栅极接入所述第N-2级扫描信号,其漏极连接所述P点,其源极接入一低电平信号;第九薄膜晶体管,其栅极连接所述第八薄膜晶体管的漏极,其漏极连接所述第七薄膜晶体管的源极,其源极连接一低电平信号。
- 根据权利要求1所述的电路,其中,所述第N级P点控制电路包括:第十薄膜晶体管,其栅极在正向扫描期间接入第N+1级时钟信号或在反向扫描期间接入第N-2级时钟信号,其漏极接入一高电平信号,其源极连接所述P点;第十一薄膜晶体管,其栅极连接所述Q点,其漏极连接所述P点,其源极接入一低电平信号。
- 根据权利要求6所述的电路,其中,所述第N级P点控制电路还包括:第十二薄膜晶体管,其栅极接入所述第一开启信号,其漏极连接所述P点,其源极接入一低电平信号。
- 根据权利要求1所述的电路,其中,所述第N级输出电路包括:第十三薄膜晶体管,其栅极连接所述Q点,其漏极接入第N级时钟信号,其源极连接所述第N级扫描线;第十四薄膜晶体管,其栅极连接所述P点,其漏极连接所述第N级扫描线,其源极连接一低电平信号。
- 一种GOA电路的驱动方法,应用于GOA电路,所述GOA电路包括多个级联的GOA单元,设定N为正整数,其中,第N级GOA单元包括第一开关电路,所述第一开关电路连接所述第N级扫描线,其中,包括:打开每一级GOA单元的第一开关电路,向每一级的扫描线通入一开启信号,以使所述每一级的扫描线连接的像素中的薄膜晶体管导通;关闭每一级GOA单元的所述开关电路,从第一级GOA单元或最后一级GOA单元开始扫描。
- 一种液晶显示器,其中,所述液晶显示器包括GOA电路,所述GOA电路包括多个级联的GOA单元,设定N为正整数,其中,第N级GOA单元包括第N级级传电路、第N级Q点控制电路、第N级P点控制电路、第N级输出电路以及第一开关电路;其中,所述第N级级传电路连接所述第N级Q点控制电路,所述第N级Q点控制电路通过Q点连接所述第N级输出电路,所述第N级级传电路连接所述第N级P点控制电路,所述第N级P点控制电路通过P点连接所述第N级输出电路,所述第N级输出电路连接还连接第N级扫描线;所述第一开关电路连接所述第N级扫描线,用于在所述液晶显示器显示前向所述第N级扫描线通入一开启信号,以使所述第N级扫描线连接的像素中的薄膜晶体管导通。
- 根据权利要求10所述的液晶显示器,其中,所述第一开关电路包括第一薄膜晶体管,其源极连接所述第N级扫描线,在所述液晶显示器显示前,所述第一薄膜晶体管的栅极接入一高电平的第一开启信号,以使所述第一薄膜晶体管的源极和漏极导通,并向所述第N级扫描线通入高电平信号,以使所述第N级扫描线连接的像素中的薄膜晶体管导通。
- 根据权利要求10所述的液晶显示器,其中,所述GOA单元还包括第二开关电路;所述第二开关电路包括第二薄膜晶体管,其漏极连接所述第N级扫描线,在向所述第N级扫描线通入高电平信号后,向所述第二薄膜晶体管的栅极接入一高电平的第二开启信号,以使所述第二薄膜晶体管的源极和漏极导通,并向所述第N级扫描线通入低电平信号,以使所述第N级扫描线连接的像素中的薄膜晶体管关闭。
- 根据权利要求10所述的液晶显示器,其中,所述第N级级传电路包括第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管以及第六薄膜晶体管;所述第三薄膜晶体管和第四薄膜晶体管的栅极接入正向扫描控制信号,用于在正向扫描期间通过所述第三薄膜晶体管接入第N-2级扫描信号,并通过所述第四薄膜晶体管接入第N+1级时钟信号;所述第五薄膜晶体管和第六薄膜晶体管的栅极接入反向扫描控制信号,用于在反向扫描期间通过所述第五薄膜晶体管接入第N+2级扫描信号,并通过所述第六薄膜晶体管接入第N-1级时钟信号。
- 根据权利要求10所述的液晶显示器,其中,所述第N级Q点控制电路包括:第七薄膜晶体管,其栅极接入第N-2级时钟信号,其漏极在正向扫描期间接入第N-2级扫描信号或在反向扫描期间接入第N+2级扫描信号,其源极连接所述Q点;第八薄膜晶体管,其栅极接入所述第N-2级扫描信号,其漏极连接所述P点,其源极接入一低电平信号;第九薄膜晶体管,其栅极连接所述第八薄膜晶体管的漏极,其漏极连接所述第七薄膜晶体管的源极,其源极连接一低电平信号。
- 根据权利要求10所述的液晶显示器,其中,所述第N级P点控制电路包括:第十薄膜晶体管,其栅极在正向扫描期间接入第N+1级时钟信号或在反向扫描期间接入第N-2级时钟信号,其漏极接入一高电平信号,其源极连接所述P点;第十一薄膜晶体管,其栅极连接所述Q点,其漏极连接所述P点,其源极接入一低电平信号。
- 根据权利要求15所述的液晶显示器,其中,所述第N级P点控制电路还包括:第十二薄膜晶体管,其栅极接入所述第一开启信号,其漏极连接所述P点,其源极接入一低电平信号。
- 根据权利要求10所述的液晶显示器,其中,所述第N级输出电路包括:第十三薄膜晶体管,其栅极连接所述Q点,其漏极接入第N级时钟信号,其源极连接所述第N级扫描线;第十四薄膜晶体管,其栅极连接所述P点,其漏极连接所述第N级扫描线,其源极连接一低电平信号。
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KR1020187011174A KR102043575B1 (ko) | 2015-09-23 | 2015-11-06 | Goa 회로 및 그 구동 방법, 액정 디스플레이 |
JP2018514283A JP6555842B2 (ja) | 2015-09-23 | 2015-11-06 | Goa回路及びその駆動方法、液晶ディスプレイ |
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- 2015-11-06 GB GB1805515.2A patent/GB2557820B/en active Active
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DE112015006930T5 (de) | 2018-05-30 |
GB2557820B (en) | 2021-09-15 |
GB201805515D0 (en) | 2018-05-16 |
US20170256219A1 (en) | 2017-09-07 |
JP6555842B2 (ja) | 2019-08-07 |
KR102043575B1 (ko) | 2019-11-11 |
GB2557820A (en) | 2018-06-27 |
CN105118464B (zh) | 2018-01-26 |
JP2018530779A (ja) | 2018-10-18 |
CN105118464A (zh) | 2015-12-02 |
KR20180084753A (ko) | 2018-07-25 |
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