CN106683631B - 一种igzo薄膜晶体管的goa电路及显示装置 - Google Patents
一种igzo薄膜晶体管的goa电路及显示装置 Download PDFInfo
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Abstract
本发明提供一种IGZO薄膜晶体管的GOA电路及显示装置,该GOA电路包括多个级联的GOA单元,设N为正整数,第N级所述GOA单元包括一上拉控制单元、一上拉单元、一下拉单元、一下拉维持单元、一下传单元、一自举电容、第一恒压负电平电源与第二恒压负电平电源,其中,所述第一恒压负电平电源分别与所述下拉维持单元和所述下拉单元连接,所述第二恒压负电平电源与所述下拉维持单元连接,所述第一恒压负电平信号与所述第二恒压负电平信号的电位均小于所述IGZO薄膜晶体管阈值电位。本发明解决了IGZO薄膜晶体管的阈值电压容易为负值,导致GOA电路失效的问题。
Description
【技术领域】
本发明涉及液晶面板技术领域,特别涉及一种IGZO薄膜晶体管的GOA电路及显示装置。
【背景技术】
目前,一般采用在阵列基板上制备栅极驱动(Gate Driver On Array,GOA)技术制备显示基板,GOA电路是指直接制备在阵列基板上的扫描线驱动电路。GOA电路包括多级依次连接的移位寄存器,每个移位寄存器驱动一条扫描线,并为下一级移位寄存器提供开启信号,从而GOA电路整体上可实现使扫描线逐行开启的目的。GOA技术相比传统工艺,不仅节省了成本,同时由于可以省去栅极方向上的绑定工艺,对提升产能极为有利,并提高了液晶显示面板的集成度。
通常,GOA电路主要由上拉部分(Pull-up part)、上拉控制部分(Pull-up controlpart)、下传部分(Transfer part)、下拉部分(Pull-down part)、下拉维持电路部分(Pull-down Holding part)、以及负责电位抬升的上升部分(Boost part)组成,上升部分一般由一自举电容构成。上拉部分主要负责将输入的时钟信号(Clock)输出至薄膜晶体管的栅极,作为液晶显示器的驱动信号。上拉控制部分主要负责控制上拉部分的打开,一般是由上级GOA电路传递来的信号作用。下拉部分主要负责在输出扫描信号后,快速地将扫描信号(亦即薄膜晶体管的栅极的电位)拉低为低电平。下拉维持电路部分则主要负责将扫描信号和上拉部分的信号保持在关闭状态(即设定的负电位)。上升部分则主要负责对上拉部分的电位进行二次抬升,确保上拉部分的正常输出。IGZO材料具有较高的迁移率,和良好的器件稳定性。这些优点,可减少GOA电路的复杂程度。由于高迁移率,GOA中TFT的尺寸相对a-Si可以做小,有利于窄边框显示器的制作。器件的稳定,可以减少用来稳定TFT的性能的电源和TFT的个数,从而可以做相对简单的电路,并且降低功耗。然而,由于IGZO-TFTVth(即晶体管的阈值电压)容易为负值,会导致GOA电路失效。另外,IGZO-TFT对DC的正向偏压温度应力测试(PBTS)非常敏感,长期的应力测试(Stress)会导致IGZO薄膜晶体管的阈值电压(Vth)正向的移动非常严重。从而导致电路失效。
【发明内容】
本发明的目的在于提供一种IGZO薄膜晶体管的GOA电路及显示装置,以解决现有技术中,IGZO薄膜晶体管的阈值电压容易为负值,导致GOA电路失效的问题。
本发明的技术方案如下:
一种IGZO薄膜晶体管的GOA电路,包括多个级联的GOA单元,设N为正整数,第N级所述GOA单元包括:
一上拉控制单元,用于控制本级扫描线的扫描驱动信号处于高电平状态;
一上拉单元,用于拉升本级扫描线的扫描驱动信号;
一下拉单元,用于拉低本级扫描线的扫描驱动信号;
一下拉维持单元,用于生成本级扫描线的低电平的扫描驱动信号;
一下传单元,用于输出本级的级传信号;
一自举电容,用于生成本级扫描线的低电平或高电平的扫描驱动信号;
第一恒压负电平电源,用于提供第一恒压负电平信号;
第二恒压负电平电源,用于提供第二恒压负电平信号;
其中,所述第一恒压负电平电源分别与所述下拉维持单元和所述下拉单元连接,所述第二恒压负电平电源与所述下拉维持单元连接。
优选地,所述第二恒压负电平电源输出电平的电位小于所述第一恒压负电平电源输出电平的电位。
优选地,所述第一恒压负电平信号与所述第二恒压负电平信号的电位均小于所述IGZO薄膜晶体管的阈值电位。
优选地,所述上拉控制单元包括第一薄膜晶体管、第二薄膜晶体管及第三薄膜晶体管;其中,
所述第一薄膜晶体管的源极与第n-4级的级传信号输入端ST(n-4)或开启信号输入端连接,其漏极分别与所述第二薄膜晶体管和所述第三薄膜晶体管的源极连接,其栅极与所述第三薄膜晶体管的栅极连接;
所述第二薄膜晶体管的的漏极与本级的扫描驱动信号输出端连接,其栅极连接第一节点;
所述第三薄膜晶体管的漏极与所述第一节点连接,其栅极输入与第n-4级的级传信号输入端ST(n-4)或开启信号输入端连接。
优选地,所述下传单元包括第四薄膜晶体管,所述第四薄膜晶体管的源极输入本级的时钟信号,其漏极与本级的级传信号输出端连接,其栅极与所述第一节点连接。
优选地,所述上拉单元包括第五薄膜晶体管,所述第五薄膜晶体管的源极输入本级的时钟信号,其漏极与本级的扫描驱动信号输出端连接,其栅极与所述第一节点连接。
优选地,所述下拉单元包括第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管与第十一薄膜晶体管,其中,
所述第六薄膜晶体管的栅极与所述第一节点连接,其漏极与本级的扫描驱动信号输出端连接,其源极分别与所述第七薄膜晶体管的源极和所述第八薄膜晶体管的漏极连接;
所述第七薄膜晶体管的漏极与本级的扫描驱动信号输出端连接,其源极与所述第八薄膜晶体管的漏极连接,其栅极与所述第八薄膜晶体管的栅极连接;
所述第八薄膜晶体管的源极与所述第一恒压负电平电源连接,其栅极与第N+4级的扫描驱动信号输出端连接;
所述第九薄膜晶体管的漏极与所述第一节点连接,其源极与所述第十薄膜晶体管的漏极连接,其栅极与所述第三薄膜晶体管的的栅极连接;
所述第十薄膜晶体管的栅极与第N+4级的扫描驱动信号输出端连接,其源极与所述第一恒压负电平电源连接;
所述第十一薄膜晶体管的栅极与所述第一节点连接,其漏极与本级的扫描驱动信号输出端连接,其源极与所述第十薄膜晶体管的漏极连接。
优选地,所述下拉维持单元包括第十二薄膜晶体管、第十三薄膜晶体管、第十四薄膜晶体管、第十五薄膜晶体管、第十六薄膜晶体管、第十七薄膜晶体管与第十八薄膜晶体管,其中,
所述第十二薄膜晶体管的源极与所述第一恒压负电平电源连接,其漏极与本级的级传信号输出端连接,其栅极与第二节点连接;
所述第十三薄膜晶体管的源极与所述第一恒压负电平电源连接,其漏极与本级的级传信号输出端连接,其栅极与第二节点连接;
所述第十四薄膜晶体管的源极与所述第二节点连接,其漏极与恒压高电平电源输入端或本级的时钟信号输入端连接,其栅极分别与所述第十七薄膜晶体管的源极和所述第十六薄膜晶体管的漏极连接;
所述第十五薄膜晶体管的漏极与所述第二节点连接,其源极与第二恒压负电平电源连接,其栅极与所述第一节点连接;
所述第十六薄膜晶体管的源极与所述第二恒压负电平电源连接,其漏极与所述第十七薄膜晶体管的源极连接,其栅极与所述第一节点连接;
所述第十七薄膜晶体管的漏极与所述第十四薄膜晶体管的漏极连接,其栅极与所述恒压高电平电源输入端或本级的所述时钟信号输入端连接;
所述第十八薄膜晶体管的栅极与所述第二节点连接,其源极与所述第一恒压负电平电源连接,其漏极与所述第一节点连接。
优选地,所述自举电容的一端连接所述第一节点,另一端连接本级的扫描驱动信号输出端。
一种显示装置,其包括上述任一项所述的IGZO薄膜晶体管的GOA电路。
本发明的有益效果:
本发明的一种IGZO薄膜晶体管的GOA电路及显示装置,通过在GOA电路设置第一恒压负电平电源和第二恒压负电平电源,并使所述第一恒压负电平电源分别与所述下拉维持单元和所述下拉单元连接,所述第二恒压负电平电源与所述下拉维持单元连接,解决了IGZO薄膜晶体管的阈值电压容易为负值,导致GOA电路失效的问题。
【附图说明】
图1为本发明实施例的一种IGZO薄膜晶体管的GOA电路的整体结构示意图;
图2为本发明实施例的一种IGZO薄膜晶体管的GOA电路的信号波形和电位的关系示意图;
图3为本发明实施例的一种IGZO薄膜晶体管的GOA电路的以第32级GOA为例说明工作原理的波形示意图。
【具体实施方式】
以下各实施例的说明是参考附加的图式,用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语,例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等,仅是参考附加图式的方向。因此,使用的方向用语是用以说明及理解本发明,而非用以限制本发明。在图中,结构相似的单元是以相同标号表示。
实施例一
IGZO(IndiumGalliumZincOxide)为氧化铟镓锌的缩写,它是一种薄膜电晶体技术,在TFT-LCD主动层之上打上的一层金属氧化物。IGZO材料具有较高的迁移率,和良好的器件稳定性。
请参考图1,图1为本实施例的一种IGZO薄膜晶体管的GOA电路的整体结构示意图。从图1可以看到,本发明的一种IGZO薄膜晶体管的GOA电路,包括多个级联的GOA单元,设N为正整数,第N级所述GOA单元包括:
一上拉控制单元100,用于控制本级扫描线的扫描驱动信号处于高电平状态。
一上拉单元200,用于拉升本级扫描线的扫描驱动信号。
一下拉单元500,用于拉低本级扫描线的扫描驱动信号。
一下拉维持单元400,用于生成本级扫描线的低电平的扫描驱动信号。
一下传单元300,用于输出本级的级传信号。
一自举电容Cb,用于生成本级扫描线的低电平或高电平的扫描驱动信号。
第一恒压负电平电源VSS1,用于提供第一恒压负电平信号,其为负的DC直流电源。
第二恒压负电平电源VSS2,用于提供第二恒压负电平信号,其为负的DC直流电源。
其中,所述第一恒压负电平电源VSS1分别与所述下拉维持单元400和所述下拉单元500连接,所述第二恒压负电平电源VSS2与所述下拉维持单元400连接。
在本实施例中,所述第二恒压负电平电源VSS2输出电平的电位小于所述第一恒压负电平电源VSS1输出电平的电位。
在本实施例中,所述第一恒压负电平信号与所述第二恒压负电平信号的电位均小于所述IGZO薄膜晶体管的阈值电位。
在本实施例中,所述上拉控制单元100包括第一薄膜晶体管T1、第二薄膜晶体管T2及第三薄膜晶体管T3;其中,
所述第一薄膜晶体管T1的源极与第n-4级的级传信号输入端ST(n-4)或开启信号输入端STV连接,其漏极分别与所述第二薄膜晶体管T2和所述第三薄膜晶体管T3的源极连接,其栅极与所述第三薄膜晶体管T3的栅极连接;
所述第二薄膜晶体管T2的的漏极与本级的扫描驱动信号输出端G(n)连接,其栅极连接第一节点Q(n);
所述第三薄膜晶体管T3的漏极与所述第一节点Q(n)连接,其栅极输入与第n-4级的级传信号输入端ST(n-4)或开启信号输入端STV连接。
在本实施例中,所述下传单元300包括第四薄膜晶体管T4,所述第四薄膜晶体管T4的源极输入本级的时钟信号,其漏极与本级的级传信号输出端ST(n)连接,其栅极与所述第一节点Q(n)连接。
在本实施例中,所述上拉单元200包括第五薄膜晶体管T5,所述第五薄膜晶体管T5的源极输入本级的时钟信号,其漏极与本级的扫描驱动信号输出端G(n)连接,其栅极与所述第一节点Q(n)连接。
在本实施例中,所述下拉单元500包括第六薄膜晶体管T6、第七薄膜晶体管T7、第八薄膜晶体管T8、第九薄膜晶体管T9、第十薄膜晶体管T10与第十一薄膜晶体管T11,其中,
所述第六薄膜晶体管T6的栅极与所述第一节点Q(n)连接,其漏极与本级的扫描驱动信号输出端G(n)连接,其源极分别与所述第七薄膜晶体管T7的源极和所述第八薄膜晶体管T8的漏极连接;
所述第七薄膜晶体管T7的漏极与本级的扫描驱动信号输出端G(n)连接,其源极与所述第八薄膜晶体管T8的漏极连接,其栅极与所述第八薄膜晶体管T8的栅极连接;
所述第八薄膜晶体管T8的源极与所述第一恒压负电平电源VSS1连接,其栅极与第N+4级的扫描驱动信号输出端连接;
所述第九薄膜晶体管T9的漏极与所述第一节点Q(n)连接,其源极与所述第十薄膜晶体管T10的漏极连接,其栅极与所述第三薄膜晶体管T3的的栅极连接;
所述第十薄膜晶体管T10的栅极与第N+4级的扫描驱动信号输出端连接,其源极与所述第一恒压负电平电源VSS1连接;
所述第十一薄膜晶体管T11的栅极与所述第一节点Q(n)连接,其漏极与本级的扫描驱动信号输出端G(n)连接,其源极与所述第十薄膜晶体管T10的漏极连接。
在本实施例中,所述下拉维持单元400包括第十二薄膜晶体管T12、第十三薄膜晶体管T13、第十四薄膜晶体管T14、第十五薄膜晶体管T15、第十六薄膜晶体管T16、第十七薄膜晶体管T17与第十八薄膜晶体管T18,其中,
所述第十二薄膜晶体管T12的源极与所述第一恒压负电平电源VSS1连接,其漏极与本级的级传信号输出端ST(n)连接,其栅极与第二节点P(n)连接;
所述第十三薄膜晶体管T13的源极与所述第一恒压负电平电源VSS1连接,其漏极与本级的级传信号输出端ST(n)连接,其栅极与第二节点P(n)连接;
所述第十四薄膜晶体管T14的源极与所述第二节点P(n)连接,其漏极与恒压高电平电源输入端或本级的时钟信号输入端连接,其栅极分别与所述第十七薄膜晶体管T17的源极和所述第十六薄膜晶体管T16的漏极连接;
所述第十五薄膜晶体管T15的漏极与所述第二节点P(n)连接,其源极与第二恒压负电平电源VSS2连接,其栅极与所述第一节点Q(n)连接;
所述第十六薄膜晶体管T16的源极与所述第二恒压负电平电源VSS2连接,其漏极与所述第十七薄膜晶体管T17的源极连接,其栅极与所述第一节点Q(n)连接;
所述第十七薄膜晶体管T17的漏极与所述第十四薄膜晶体管T14的漏极连接,其栅极与所述恒压高电平电源输入端或本级的所述时钟信号输入端连接;
所述第十八薄膜晶体管T18的栅极与所述第二节点P(n)连接,其源极与所述第一恒压负电平电源VSS1连接,其漏极与所述第一节点Q(n)连接。
在本实施例中,所述自举电容Cb的一端连接所述第一节点Q(n),另一端连接本级的扫描驱动信号输出端G(n)。
请参考图2,图2为本实施例的一种IGZO薄膜晶体管的GOA电路的信号波形和电位的关系示意图。本发明以8K4K显示为基础,进行专利介绍。本发明采用8个CK(时钟)信号,CK信号和CK信号之间的重叠的时间取名叫做CDT,重叠的时间长度为3.75us。本发明的STV是开始脉冲(start pulse)触发信号,每一帧有一个脉冲。脉宽为8*CDT,STV和CK之间的重叠时间为CDT。
STV为高频交流信号,每一帧出现一次,CK也为高频交流信号。ST(N-4)连接前面第四级的级传输出信号,例如,当前级为第10级,则ST(N)=ST(10),ST(N-4)=ST(6),其中,前四级的第一薄膜晶体管T1和第二薄膜晶体管T2,跟STV相连。
下面对本发明的工作原理进行说明。
请参考图3,图3为本实施例的一种IGZO薄膜晶体管的GOA电路的以第32级GOA为例说明工作原理的波形示意图。从图3可以看到:
当G(N)=G(32)时,ST(N-4)=ST(28),G(32)由CK8控制,当ST(28)为高电位的时候,第一薄膜晶体管T1,第三薄膜晶体管T3打开,ST(28)高电位传入到第一节点Q(32),Q点为高电位。同时,第五薄膜晶体管T5打开,此时,CK8是低电位,所以G(32)为低电位。同时,第二节点P(32)为低电位,第十三薄膜晶体管T13,第十八薄膜晶体管T18,第十二薄膜晶体管T12均关闭,第一恒压负电平电源VSS1的低电位不会影响第一节点G(N)的电位;
接着,ST(28)转为低电位,第一薄膜晶体管T1,第三薄膜晶体管T3关闭,此时,CK8为高电位,G(32)输出高电位,第一节点Q(32)受到电容耦合效应,被抬升到更高的电位,第二节点P(32)继续保持低电位。
需要说明的是,此时,一般的GOA电路,如果第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第九薄膜晶体管T9、第十薄膜晶体管T10和第十一薄膜晶体管T11的阈值电压过负,第一节点Q(32)的高电位会漏掉,第五薄膜晶体管T5关闭,CK高电位输入不到G(32),导致G(32)失效。或者第六薄膜晶体管T6、第七薄膜晶体管T7和第八薄膜晶体管T8的阈值电压过负,G(32)的高电位被漏电,G(32)波形高电位拉下来,波形不能正常输出。本发明的上拉控制单元100的第一薄膜晶体管T1、第二薄膜晶体管T2和第三薄膜晶体管T3,下拉单元500的第六薄膜晶体管T6、第七薄膜晶体管T7、第八薄膜晶体管T8、第九薄膜晶体管T9、第十薄膜晶体管T10和第十一薄膜晶体管T11,采用了三颗薄膜晶体管组成的结构,当这个工作时间段时,第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第九薄膜晶体管T9、第十薄膜晶体管T10和第十一薄膜晶体管T11的击穿电压远远小于0,能够很好的防止IGZO薄膜晶体管的阈值电压太负,保证G(N)波形的正常输出。
再接着,G(36)为高电位,第七薄膜晶体管T7、第八薄膜晶体管T8、第九薄膜晶体管T9和第十薄膜晶体管T10打开,第一节点Q(32),G(32)被拉到低电位。第二节点P(32)为高电位,第九薄膜晶体管T9、第十薄膜晶体管T10和第十一薄膜晶体管T11、第十二薄膜晶体管T12,第十三薄膜晶体管T13,第十八薄膜晶体管T18打开,第一节点Q(32),G(32)保持低电位。
另外,当下拉维持单元400采用CK(n)为取代传统的VDD的直流电源,可以有效避免第十四薄膜晶体管T14和第十七薄膜晶体管T17受到严重的PBTS(Positive biastemperature stress,正向偏压温度应力)测试影响,导致IGZO薄膜晶体管的阈值电压正向移动非常严重,从而导致电路失效。
本发明的一种IGZO薄膜晶体管的GOA电路及显示装置,通过在GOA电路设置第一恒压负电平电源VSS1和第二恒压负电平电源VSS2,并使所述第一恒压负电平电源VSS1分别与所述下拉维持单元400和所述下拉单元500连接,所述第二恒压负电平电源VSS2与所述下拉维持单元400连接,并且所述第一恒压负电平信号与所述第二恒压负电平信号的电位均小于所述IGZO薄膜晶体管的阈值电位,解决了IGZO薄膜晶体管的阈值电压容易为负值,导致GOA电路失效的问题。
实施例二
本实施例提供一种显示装置,该显示装置包括一实施例一所述的IGZO薄膜晶体管的GOA电路,该IGZO薄膜晶体管的GOA电路已经在实施例一中进行了详细的说明,在此不再重复论述。
综上所述,虽然本发明已以优选实施例揭露如上,但上述优选实施例并非用以限制本发明,本领域的普通技术人员,在不脱离本发明的精神和范围内,均可作各种更动与润饰,因此本发明的保护范围以权利要求界定的范围为准。
Claims (9)
1.一种IGZO薄膜晶体管的GOA电路,其特征在于,包括多个级联的GOA单元,设N为正整数,第N级所述GOA单元包括:
一上拉控制单元,用于控制本级扫描线的扫描驱动信号处于高电平状态;
一上拉单元,用于拉升本级扫描线的扫描驱动信号;
一下拉单元,用于拉低本级扫描线的扫描驱动信号;
一下拉维持单元,用于生成本级扫描线的低电平的扫描驱动信号;
一下传单元,用于输出本级的级传信号;
一自举电容,用于生成本级扫描线的低电平或高电平的扫描驱动信号;
第一恒压负电平电源,用于提供第一恒压负电平信号;
第二恒压负电平电源,用于提供第二恒压负电平信号;
其中,所述第一恒压负电平电源分别与所述下拉维持单元和所述下拉单元连接,所述第二恒压负电平电源与所述下拉维持单元连接;
所述上拉控制单元包括第一薄膜晶体管、第二薄膜晶体管及第三薄膜晶体管;其中,
所述第一薄膜晶体管的源极与第n-4级的级传信号输入端ST(n-4)或开启信号输入端连接,其漏极分别与所述第二薄膜晶体管和所述第三薄膜晶体管的源极连接,其栅极与所述第三薄膜晶体管的栅极连接;
所述第二薄膜晶体管的漏极与本级的扫描驱动信号输出端连接,其栅极连接第一节点;
所述第三薄膜晶体管的漏极与所述第一节点连接,其栅极输入与第n-4级的级传信号输入端ST(n-4)或开启信号输入端连接。
2.根据权利要求1所述的IGZO薄膜晶体管的GOA电路,其特征在于,所述第二恒压负电平电源输出电平的电位小于所述第一恒压负电平电源输出电平的电位。
3.根据权利要求1所述的IGZO薄膜晶体管的GOA电路,其特征在于,所述第一恒压负电平信号与所述第二恒压负电平信号的电位均小于所述IGZO薄膜晶体管的阈值电位。
4.根据权利要求1所述的IGZO薄膜晶体管的GOA电路,其特征在于,所述下传单元包括第四薄膜晶体管,所述第四薄膜晶体管的源极输入本级的时钟信号,其漏极与本级的级传信号输出端连接,其栅极与所述第一节点连接。
5.根据权利要求1所述的IGZO薄膜晶体管的GOA电路,其特征在于,所述上拉单元包括第五薄膜晶体管,所述第五薄膜晶体管的源极输入本级的时钟信号,其漏极与本级的扫描驱动信号输出端连接,其栅极与所述第一节点连接。
6.根据权利要求1所述的IGZO薄膜晶体管的GOA电路,其特征在于,所述下拉单元包括第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管与第十一薄膜晶体管,其中,
所述第六薄膜晶体管的栅极与所述第一节点连接,其漏极与本级的扫描驱动信号输出端连接,其源极分别与所述第七薄膜晶体管的源极和所述第八薄膜晶体管的漏极连接;
所述第七薄膜晶体管的漏极与本级的扫描驱动信号输出端连接,其源极与所述第八薄膜晶体管的漏极连接,其栅极与所述第八薄膜晶体管的栅极连接;
所述第八薄膜晶体管的源极与所述第一恒压负电平电源连接,其栅极与第N+4级的扫描驱动信号输出端连接;
所述第九薄膜晶体管的漏极与所述第一节点连接,其源极与所述第十薄膜晶体管的漏极连接,其栅极与所述第三薄膜晶体管的栅极连接;
所述第十薄膜晶体管的栅极与第N+4级的扫描驱动信号输出端连接,其源极与所述第一恒压负电平电源连接;
所述第十一薄膜晶体管的栅极与所述第一节点连接,其漏极与本级的扫描驱动信号输出端连接,其源极与所述第十薄膜晶体管的漏极连接。
7.根据权利要求1所述的IGZO薄膜晶体管的GOA电路,其特征在于,所述下拉维持单元包括第十二薄膜晶体管、第十三薄膜晶体管、第十四薄膜晶体管、第十五薄膜晶体管、第十六薄膜晶体管、第十七薄膜晶体管与第十八薄膜晶体管,其中,
所述第十二薄膜晶体管的源极与所述第一恒压负电平电源连接,其漏极与本级的级传信号输出端连接,其栅极与第二节点连接;
所述第十三薄膜晶体管的源极与所述第一恒压负电平电源连接,其漏极与本级的级传信号输出端连接,其栅极与第二节点连接;
所述第十四薄膜晶体管的源极与所述第二节点连接,其漏极与恒压高电平电源输入端或本级的时钟信号输入端连接,其栅极分别与所述第十七薄膜晶体管的源极和所述第十六薄膜晶体管的漏极连接;
所述第十五薄膜晶体管的漏极与所述第二节点连接,其源极与第二恒压负电平电源连接,其栅极与所述第一节点连接;
所述第十六薄膜晶体管的源极与所述第二恒压负电平电源连接,其漏极与所述第十七薄膜晶体管的源极连接,其栅极与所述第一节点连接;
所述第十七薄膜晶体管的漏极与所述第十四薄膜晶体管的漏极连接,其栅极与所述恒压高电平电源输入端或本级的所述时钟信号输入端连接;
所述第十八薄膜晶体管的栅极与所述第二节点连接,其源极与所述第一恒压负电平电源连接,其漏极与所述第一节点连接。
8.根据权利要求1所述的IGZO薄膜晶体管的GOA电路,其特征在于,所述自举电容的一端连接所述第一节点,另一端连接本级的扫描驱动信号输出端。
9.一种显示装置,其特征在于,其包括权利要求1~8任一项所述的IGZO薄膜晶体管的GOA电路。
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