WO2018047861A1 - Carte de circuit imprimé et procédé de fabrication d'une carte de circuit imprimé - Google Patents

Carte de circuit imprimé et procédé de fabrication d'une carte de circuit imprimé Download PDF

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Publication number
WO2018047861A1
WO2018047861A1 PCT/JP2017/032105 JP2017032105W WO2018047861A1 WO 2018047861 A1 WO2018047861 A1 WO 2018047861A1 JP 2017032105 W JP2017032105 W JP 2017032105W WO 2018047861 A1 WO2018047861 A1 WO 2018047861A1
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WO
WIPO (PCT)
Prior art keywords
wiring board
pad
wiring
interposer
layer
Prior art date
Application number
PCT/JP2017/032105
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English (en)
Japanese (ja)
Inventor
泰人 芥川
明彦 古屋
Original Assignee
凸版印刷株式会社
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Application filed by 凸版印刷株式会社 filed Critical 凸版印刷株式会社
Priority to JP2018538440A priority Critical patent/JP7092031B2/ja
Publication of WO2018047861A1 publication Critical patent/WO2018047861A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/32—Holders for supporting the complete device in operation, i.e. detachable fixtures
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits

Definitions

  • the present invention relates to a wiring board and a method for manufacturing the wiring board.
  • connection terminals with semiconductor chips be narrowed and the substrate wirings be made finer for FCBGA (Flip Chip-Ball Grid Array) wiring boards.
  • FCBGA Flexible Chip-Ball Grid Array
  • the connection between the FCBGA wiring board and the motherboard is required to be made with connection terminals having a pitch that is almost the same as in the prior art.
  • the silicon interposer method is manufactured using equipment for semiconductor pre-process using a silicon wafer. Since silicon wafers are limited in shape and size, the number of interposers that can be manufactured from a single wafer is small, and the manufacturing equipment is expensive, so the interposers are also expensive. In addition, since the silicon wafer is a semiconductor, there is a problem that transmission characteristics are also deteriorated.
  • the present invention has been made paying attention to the above-described problems, and suppresses a decrease in the yield of the FCBGA wiring board provided with an interposer and enables a semiconductor chip to be mounted satisfactorily. It aims at providing the manufacturing method of a board
  • a first wiring board and a second wiring board composed of a build-up board bonded to the first wiring board are provided, and the second wiring board has a thickness of 10 ⁇ m or more and 300 ⁇ m or less.
  • the first wiring board and the second wiring board are electrically joined via the protruding electrodes, and a gap between the first wiring board and the second wiring board is filled with an insulating adhesive member.
  • the substrate is provided with a wiring substrate having a pad on a surface opposite to the first wiring substrate.
  • the first wiring board and the second wiring board manufactured separately can be formed by bonding. Therefore, by selecting only non-defective products for the first wiring board and the second wiring board and combining them, one wiring board can be obtained, and a decrease in yield as a wiring board can be suppressed. Further, the semiconductor chip is bonded to the first wiring board via the second wiring board. Since the second wiring board is a relatively thin board, the CTE (Coefficient) is applied to the bonding between the first wiring board and the semiconductor chip. of Thermal Expansion The effect of the difference is small. And since an underfill acts as a buffer material, the influence by the CTE difference of a 1st wiring board and a semiconductor chip can be reduced, and a semiconductor chip can be mounted favorably.
  • FIG. 5 is a cross-sectional view showing a continuation of the manufacturing process of FIG. 4.
  • FIG. 6 is a cross-sectional view showing a continuation of the manufacturing process of FIG. 5.
  • FIG. 7 is a cross-sectional view showing a continuation of the manufacturing process of FIG. 6.
  • FIG. 8 is a cross-sectional view showing a continuation of the manufacturing process of FIG. 7.
  • FIG. 9 is a cross-sectional view showing a continuation of the manufacturing process in FIG. 8.
  • FIG. 10 is a cross-sectional view showing a continuation of the manufacturing process of FIG. 9. It is sectional drawing which shows the continuation of the manufacturing process of FIG.
  • FIG. 12 is a sectional view showing a continuation of the manufacturing process in FIG. 11. It is sectional drawing for demonstrating the shape of a connection pad. It is sectional drawing which shows an example of a connection pad.
  • a wiring board according to an embodiment of the present invention will be described below with reference to the drawings.
  • the same reference numerals are given to portions corresponding to each other in the drawings to be described below, and description of the overlapping portions will be omitted as appropriate.
  • Each drawing is exaggerated as appropriate for easy explanation.
  • the embodiment of the present invention exemplifies a configuration for embodying the technical idea of the present invention, and specifies the material, shape, structure, arrangement, dimensions, etc. of each part as follows. Not. The technical idea of the present invention can be variously modified within the technical scope defined by the claims described in the claims.
  • FIG. 1 is a cross-sectional view showing an example of a semiconductor package in which a semiconductor chip is mounted on a wiring board according to an embodiment of the present invention.
  • a semiconductor package according to an embodiment of the present invention includes a thin interposer 3 having a fine wiring layer formed only of a build-up wiring layer in which a resin and wiring are laminated on one surface of an FCBGA wiring board 1. Are joined by solder bumps, Cu posts (Cu pillars) or gold bumps 24. The gap between the FCBGA wiring board 1 and the interposer 3 is filled with an underfill (resin) 2 as an insulating adhesive member.
  • an underfill (resin) 2 as an insulating adhesive member.
  • connection pads 14 formed on the surface opposite to the FCBGA wiring substrate 1 of the interposer 3 and the semiconductor chip 4 are joined by solder bumps, Cu pillars, or gold bumps 31, and the semiconductor chip 4 and the interposer 3 are connected.
  • the gap is filled with the underfill 32.
  • the surface of the connection pad 14 and the surface of the interposer 3 are flush with each other.
  • the end of the connection pad 14 on the FCBGA wiring board 1 side is wider than the end of the connection pad 14 on the surface side in a cross-sectional view in the thickness direction of the connection pad 14.
  • the underfill 2 is an adhesive used for fixing and sealing the FCBGA wiring board 1 and the interposer 3.
  • the underfill 2 for example, one of epoxy resin, polyurethane resin, silicon resin, polyester resin, oxetane resin, and maleimide resin or a mixture of two or more of these resins, silica as a filler, A material to which titanium oxide, aluminum oxide, magnesium oxide, zinc oxide, or the like is added is used.
  • the underfill 2 may be formed by filling a liquid resin.
  • an anisotropic conductive film (ACF) or a film-like connection material (NCF) having the functions of adhesion and insulation at the same time is used as an insulating adhesive member.
  • the interposer 3 may be fixed and sealed between them.
  • the underfill 32 is an adhesive used for fixing and sealing the semiconductor chip 4 and the interposer 3, and is made of the same material as the underfill 2.
  • an anisotropic conductive film (ACF) or a film-like connection material (NCF) may be used instead of the underfill 32.
  • the wiring pitch of the portion of the interposer 3 to be bonded to the semiconductor chip 4 is that of the portion of the FCBGA wiring board 1 to be bonded to the semiconductor chip 4 when the semiconductor chip 4 and the FCBGA wiring board 1 are directly bonded. It is narrower than the wiring pitch. That is, the surface of the interposer 3 on the side on which the semiconductor chip 4 is mounted has finer wiring than the FCBGA wiring board 1 when bonded to the semiconductor chip 4.
  • the interposer 3 needs to have a wiring width of 2 ⁇ m or more and 6 ⁇ m or less.
  • the insulating film thickness between the wirings is 2.5 ⁇ m.
  • the thickness of one layer including the wiring is 4.5 ⁇ m, and when the five-layer interposer 3 is manufactured with this thickness, the interposer 3 is an extremely thin interposer with a total thickness of about 25 ⁇ m. That is, in order to make the total thickness of the interposer 3 about 10 ⁇ m, it is sufficient to stack two layers having the thickness of 4.5 ⁇ m.
  • the wiring thickness when it is necessary to suppress the loss of electrical characteristics, it is necessary to increase the wiring thickness in order to reduce the electrical resistance. In that case, it is necessary to increase the thickness of the insulating layer in order to adjust the impedance. Even if the number of layers is five, the total thickness of the interposer 3 may be about 100 ⁇ m. Furthermore, it is necessary to increase the number of stacked interposers 3 by increasing the number of pins of a device chip such as the semiconductor chip 4 and combining power supply lines and ground layers, and the total thickness of the interposer 3 may be about 300 ⁇ m.
  • FIG. 2B is an enlarged view of a part including the solder bumps 24 of FIG. Further, as illustrated in FIG. 2B, for example, an adhesive layer 7 or a copper foil 11 may be formed between the release layer 6 and the connection pad 14.
  • the wiring layer 3a as formed on the carrier substrate 5 is flip-chip mounted on the separately manufactured FCBGA wiring substrate 1 as shown in FIG. Then, the space between the FCBGA wiring board 1 and the wiring layer 3a is solidified with a resin such as an underfill 2, and then the carrier substrate 5 and the like are peeled off from the wiring layer 3a, and the semiconductor chip 4 formed on the wiring layer 3a The connection pad 14 for bonding is exposed. Thereby, the wiring board 100 according to the embodiment of the present invention is formed. In FIG. 3, the description of the adhesive layer 7 and the copper foil 11 shown in FIG. 2B is omitted.
  • the thin wiring layer 3 a having a thickness of 300 ⁇ m or less can be flatly bonded to the FCBGA wiring substrate 1.
  • the wiring board 1 for FCBGA is rigid, and if the CTE (thermal expansion coefficient) difference from the semiconductor chip 4 is present, the bonding is easily broken, but if the bonding height is high, the bonding is difficult to break. is there.
  • the FCBGA wiring board 1 and the semiconductor chip 4 are joined by two-stage joining via a thin interposer 3. For this reason, it is difficult to influence the mutual CTE difference, and high reliability can be ensured.
  • a glass substrate is used as the carrier substrate 5.
  • the glass substrate has excellent flatness and is suitable for forming a fine pattern of the wiring layer 3a. Further, since the CTE has a small CTE and is not easily distorted, the glass substrate is excellent in ensuring the pattern placement accuracy and flatness when bonded to the FCBGA wiring substrate 1.
  • the glass substrate is preferably thicker from the viewpoint of suppressing warpage in the manufacturing process, and is preferably about 0.7 mm to 1.1 mm, for example.
  • the CTE of the glass substrate is preferably about 9 ppm / ° C.
  • a wiring board to be the interposer 3 is created.
  • a release layer 6 for peeling the carrier substrate 5 is formed on one surface of the carrier substrate 5 in a subsequent step.
  • the release layer 6 is adjusted to have a thickness that transmits ultraviolet rays to some extent.
  • an adhesive that cures by ultraviolet rays is applied on the release layer 6 to form an adhesive layer 7.
  • the carrier layer 5 on which the adhesive layer 7 is formed is applied on the thin copper foil 11 laid on the flat surface plate 10 in a vacuum.
  • the adhesive layer 7 is cured by irradiating with ultraviolet rays 12 in this state. Since the copper foil 11 is hardened while maintaining the flatness of the surface plate 10, a fine pattern can be formed thereon.
  • connection pad 14 has a structure in which, after bonding the wiring layer 3 a serving as the interposer 3 to the FCBGA wiring substrate 1, the carrier substrate 5 and the like are peeled off to expose the connection pad 14.
  • Au / Ni / Cu and plating are formed from the copper foil 11 side so that the surface of the connection pad 14 is Au.
  • Au / Ni / Cu plating is performed after forming thin Ni between the copper foil 11 and Au.
  • the resist pattern 13 is removed as shown in FIG.
  • connection pad 14 since the connection pad 14 is formed, the exposed surface of the connection pad 14 and the exposed surface of the interposer 3 (wiring layer 3a) can be flush with each other.
  • the cross-sectional shape of the opening 13a of the resist pattern 13 is tapered so that the copper foil 11 side is narrower and becomes wider toward the opening end side of the opening 13a.
  • the width of the end on one side can be made wider than the width of the end on the exposed surface side of the connection pad 14.
  • Various shapes of the opening 13a of the resist pattern 13 will be described later.
  • an insulating resin 15 is formed as shown in FIG.
  • the insulating resin 15 is formed so that the connection pad 14 is embedded in the layer of the insulating resin 15.
  • the insulating resin 15 is formed by spin coating using a photosensitive epoxy resin.
  • the photosensitive epoxy resin can be cured at a relatively low temperature, and it is possible to suppress a level difference due to less shrinkage due to curing (curing) after the subsequent formation of the conductive via, and it is excellent in subsequent fine pattern formation.
  • the insulating resin 15 may be formed by spin-coating using a photosensitive epoxy resin, or may be formed by compressing and curing an insulating resin film with a vacuum laminator. In this case, the flatness is good.
  • An insulating film can be formed. Polyimide may be used as the insulating resin 15 as long as a slight level difference is allowed in the exposure process.
  • conductive vias 17 are formed in the connection pads 14.
  • a photosensitive epoxy resin is used for the insulating resin 15, and the conductive via 17 can be formed by performing UV exposure 16 and development.
  • the conductive via 17 may be formed by laser light irradiation.
  • Ti and Cu are continuously sputtered to form a seed layer 18 of electrolytic copper plating as shown in FIG. A fine pattern is formed on the seed layer 18, and Ti can improve adhesion to the underlying insulating resin 15, and can prevent pattern peeling and falling after plating.
  • the seed layer 18 may be formed by continuous sputtering of TiW and Cu. Sputtered Cu is formed so as to have a thickness of about 300 nm or less so that wiring thinning can be suppressed in the step of etching the seed layer 18 after electrolytic copper plating.
  • a resist pattern 19 is formed on the insulating resin 15, and wiring 20 is formed in the opening 19a by electrolytic copper plating.
  • FIG. 8C after the resist pattern 19 is removed, the sputtered copper and sputtered Ti constituting the seed layer 18 are etched using the wiring 20 as a mask. Note that an etching solution that suppresses the thinning of the wiring is selected according to the width of the wiring 20, and etching is performed using this etching solution.
  • 6 to 8 described above is a wiring layer forming step, and the wiring layer forming steps shown in FIGS. 6 to 8 are repeated according to the number of wiring layers to be stacked.
  • an insulating resin layer 21 that is the outermost surface of the interposer 3 on the FCBGA wiring board 1 side is formed.
  • the insulating resin layer 21 is formed using a photosensitive epoxy resin as the insulating resin.
  • an insulating resin layer 21 is formed so as to cover a region including the wiring 20 and the insulating resin 15.
  • FIG. 9B by performing UV exposure 22 and development, the wiring 20 is exposed to form an opening 21a, and the insulating resin layer 21 is cured and stabilized by baking.
  • surface treatment is performed to prevent Cu oxidation on the surface of the wiring 20 and improve the wettability of the solder bumps.
  • a pad surface treatment layer 23 made of Ni / Pd / Au is formed on the surface of the wiring 20.
  • An OSP (Organic Solderability Preservative surface treatment with water-soluble preflux) film may be formed on the surface of the wiring 20.
  • the carrier substrate 5 is attached to the terminal of the interposer 3 with the carrier substrate 5, that is, the FCBGA wiring substrate 1 designed and manufactured according to the position of the solder bump 24 by flip chip.
  • the interposer 3 is joined and hardened with the underfill 2 as shown in FIG.
  • “interposer 3 with carrier substrate 5” is indicated by reference numeral 3b.
  • the laser beam 25 is interfaced with the carrier substrate 5 from the back surface of the carrier substrate 5, that is, the surface opposite to the FCBGA wiring substrate 1 of the carrier substrate 5.
  • the carrier layer 5 is removed by irradiating the release layer 6 formed on the substrate.
  • the adhesive layer such as the adhesive tape 26 is bonded to the adhesive layer 7 that has bonded the carrier substrate 5 and the peeling layer 6 to the copper foil 11. Peel off. That is, the adhesive tape 26 is attached to the part to which the carrier substrate 5 is adhered after the carrier substrate 5 is peeled off, and the adhesive tape 26 is peeled off to adhere to the interposer 3 side.
  • the adhesive layer 7 is removed.
  • the adhesive layer 7 has heat resistance and can be easily removed without being deteriorated by heat of the manufacturing process of the interposer 3.
  • the manufacturing process temperature of the interposer 3 is heat resistant, and foaming is performed at a temperature higher than the manufacturing process temperature of the interposer 3 and lower than the heat resistance temperature of the interposer 3, and has an adhesive force.
  • the carrier substrate 5 may be peeled off by using a material that does not exist as the adhesive layer 7. As shown in FIG. 3, when the carrier substrate 5 is peeled off, the peeling layer 6, the adhesive layer 7, and the copper foil 11 may be removed together with the carrier substrate 5.
  • the copper foil 11 and thin Ni are etched to expose the connection pads 14 connected to the semiconductor chip 4.
  • the wiring substrate 100 with the ultra-thin interposer 3 is completed.
  • Au is exposed on the surface of the connection pad 14.
  • the semiconductor chip 4 is mounted on the interposer 3 side of the wiring board 100 via the solder bumps 31, the solder bumps 33 are mounted on the pads of the wiring board 100 on the opposite side, and reflow is performed.
  • the underfill 32 By filling the underfill 32 in between, a semiconductor package as shown in FIG. 1 can be manufactured.
  • the FCBGA wiring substrate 1 and the wiring layer 3a formed on the carrier substrate 5 to be the interposer 3 are separately manufactured and joined to each other.
  • a wiring board 100 with three is realized.
  • the FCBGA wiring board 1 and the wiring layer 3a including the carrier board 5 only the respective non-defective products are selected, and the non-defective products are joined together to form the wiring board 100, thereby reducing the yield. Can be prevented.
  • a substrate other than the silicon substrate for example, a glass substrate
  • FCBGA wiring substrate 1 and the wiring layer 3a including the carrier substrate 5 are joined and bonded after the respective manufacturing processes are completed, the wiring density, the number of layers, and the structure of the front and back surfaces of the substrate are determined. It is possible to avoid warping of the wiring board 100 due to the difference. Further, by using a rigid, low CTE, low distortion carrier as the carrier substrate 5, the surface of the wiring layer after removing the carrier is flat, the pad placement accuracy is high, and chip mounting is facilitated. .
  • the interposer 3 when the interposer 3 is a thin film-like substrate, it is difficult to join the FCBGA wiring board 1 via solder bumps.
  • the wiring layer 3a is formed on the carrier substrate 5, and the wiring layer 3a including the carrier substrate 5 is bonded to the FCBGA wiring substrate 1 via the solder bumps 24.
  • the carrier substrate 5 is removed, thereby realizing the wiring substrate 100 in which the interposer 3 is bonded to the FCBGA wiring substrate 1. Therefore, even if the interposer 3 is a thin substrate, it can be easily bonded to the FCBGA wiring substrate 1 via the solder bumps 24. Further, since Cu posts or Au bumps can be used in place of the solder bumps 24, the versatility of the wiring board can be enhanced.
  • the interposer 3 having a small thickness has little influence even if it has its own CTE difference because the stress caused by the interposer 3 is small. Can be improved. That is, even if the interposer 3 is thick, the wiring substrate 100 can be realized. If the thickness is 300 ⁇ m or less, the effect of the wiring substrate 100 according to the present embodiment is sufficiently exerted, and the interposer 3 has a thickness of 100 ⁇ m or less. If it is thick, the effect of the wiring board 100 is more fully exhibited. Further, by making the surface of the connection pad 14 and the surface of the interposer 3 flush with each other, the thickness of the wiring board 100 can be further reduced.
  • connection pad 14 when the wiring board 100 is produced by the above procedure, as shown in FIG. 11, when the connection pad 14 is exposed after the interposer 3 is joined to the FCBGA wiring board 1, the connection pad 14 is viewed from above. There is a possibility that a structure called SMD (Solder Mask Defined) that is pressed by resin may not be formed. That is, as shown in FIG. 13, the surface of the connection pad 14 has the same height as the insulating resin 15, and there is a possibility that the connection pad 14 is easily removed compared to the SMD structure.
  • SMD Silicon Mask Defined
  • connection pad 14 In particular, in the process of bonding the semiconductor chip 4 to the wiring board, it is before being fixed by the underfill 2, so that stress is easily concentrated on the bonding portion due to the CTE difference between the semiconductor chip 4 and the wiring board, and the connection pad 14 is damaged. there is a possibility. After the semiconductor chip 4 is bonded and fixed with the underfill 2, the connection pad 14 does not come out of the underfill 2, but in order to improve the reliability until it is fixed with the underfill 2, In order to prevent the pad 14 from being damaged, in the step of forming the connection pad 14 on the copper foil 11, the connection pad 14 is formed so that the cross-sectional shape thereof becomes the shape shown in FIGS. 14 (a) to (c). Also good.
  • a resist pattern 13 is formed using a thin resist layer, a copper plating layer is formed thicker than the resist pattern 13 in the opening 13a, and a portion protruding from the opening 13a to the upper part of the resist pattern 13 is formed. It is used as an anchor.
  • FIG. 14B shows a taper shape in which the cross-sectional shape of the connection pad 14 is narrow on the copper foil 11 side and becomes wider as it approaches the opening end side of the opening 13a. By blurring the edge of the exposure pattern of the positive resist and making the resist pattern 13 have a forward taper shape, a reverse taper plating pattern as shown in FIG. 14B can be formed.
  • FIG. 14 (c) shows, for example, a step-like pattern formed by adjusting the exposure energy of the pattern edge of a positive resist to form a connection pad having an anchor effect due to protrusion of the plating even if the plating thickness is thin. It is.
  • connection pad 14 may be formed in a tapered shape so that the connection pad 14 becomes wider toward the side opposite to the peeling layer 6.
  • the end of the connection pad 14 opposite to the peeling layer 6 may be formed in an anchor shape that is wider than the other part of the connection pad 14 in a cross-sectional view in the vertical direction.
  • the connection pad 14 produced by the method described above has an end portion on the FCBGA wiring board 1 side of the connection pad 14 that is wider than the end portion on the surface side of the connection pad 14 in a sectional view in the thickness direction of the connection pad 14. Therefore, it is possible to make it difficult to remove the connection pad 14 from the insulating resin 15.
  • the shape of these resist patterns 13 can be controlled by a flow of resist heating, exposure focus adjustment, a gradation exposure function of a direct drawing exposure machine, or the like.
  • a process involving a temperature change is performed in the process of mounting the semiconductor chip 4 on the wiring substrate 100, and the wiring is caused by the CTE difference or the like. Even if a force is applied to the substrate 100, the connection pad 14 can be prevented from coming off from the insulating resin 15.
  • the carrier substrate 5 As the carrier substrate 5, a metal substrate having flatness with little distortion, a ceramic substrate, or the like can be used. For example, in a ceramic substrate, it is easy to intentionally control the CTE, and the CTE can be changed according to the constituent material of the interposer 3.
  • a metal substrate or a ceramic substrate is applied as the carrier substrate 5, for example, a foamed resin layer that is foamed by heating is used as the release layer 6, and after the wiring layer 3a with the carrier substrate 5 is joined to the FCBGA wiring substrate 1, The carrier substrate 5 may be peeled off from the wiring layer 3a by heating and foaming the foamed resin layer.
  • the FCBGA wiring board 1 corresponds to the first wiring board
  • the interposer 3 corresponds to the second wiring board
  • the solder bumps 24 correspond to the protruding electrodes.
  • the carrier substrate 5 corresponds to the support
  • the connection pad 14 corresponds to the first pad
  • the wiring layer 3a corresponds to the wiring layer
  • the pad surface treatment layer 23 corresponds to the second pad.
  • the present invention is not limited to the above embodiment, and is required in consideration of the use as a wiring board without departing from the technical idea of the present embodiment. It goes without saying that other layers and structures can be arbitrarily formed for the purpose of improving the other physical properties such as rigidity, strength, impact property and the like.
  • the present invention has been described above with reference to specific embodiments, the present invention is not limited to these descriptions. From the description of the invention, other embodiments of the invention will be apparent to persons skilled in the art, along with various variations of the disclosed embodiments. Therefore, it is to be understood that the claims encompass these modifications and embodiments that fall within the scope and spirit of the present invention.
  • the present invention can be used for a semiconductor device including a wiring board such as an interposer interposed between a main board and an IC chip.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
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  • Combinations Of Printed Boards (AREA)

Abstract

L'invention concerne : une carte de circuit imprimé et un procédé de fabrication de carte de circuit imprimé, permettant de supprimer une diminution du rendement d'une carte de circuit imprimé équipée d'un interposeur pour FCBGA et de monter favorablement une puce à semi-conducteur. Une carte de circuit imprimé (100) selon le présent mode de réalisation comporte : une carte de circuit imprimé (1) pour FCBGA ; et un interposeur (3) comprenant un substrat intégré joint à la carte de circuit imprimé (1) pour FCBGA, l'interposeur (3) ayant une épaisseur de 10 à 300 µm ; la carte de circuit imprimé (1) pour FCBGA et l'interposeur (3) étant électriquement connectés par des bossages (24) disposés entre la carte de circuit imprimé (1) pour FCBGA et l'interposeur (3) ; un espace entre la carte de circuit imprimé (1) pour FCBGA et l'interposeur (3) est rempli d'un matériau de remplissage diélectrique (2) ; et l'interposeur (3) comporte une plage d'accueil (14) pour connecter une puce à semi-conducteur (4), la plage d'accueil (14) étant disposée sur la surface du côté opposé à la carte de circuit imprimé (1) pour FCBGA.
PCT/JP2017/032105 2016-09-08 2017-09-06 Carte de circuit imprimé et procédé de fabrication d'une carte de circuit imprimé WO2018047861A1 (fr)

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Application Number Priority Date Filing Date Title
JP2018538440A JP7092031B2 (ja) 2016-09-08 2017-09-06 配線基板の製造方法

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JP2016175459 2016-09-08
JP2016-175459 2016-09-08

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Cited By (16)

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JP2019169559A (ja) * 2018-03-22 2019-10-03 凸版印刷株式会社 微細配線層付きコアレス基板、半導体パッケージおよび半導体装置、並びに微細配線層付きコアレス基板および半導体パッケージの製造方法
WO2020085382A1 (fr) * 2018-10-26 2020-04-30 凸版印刷株式会社 Substrat de câblage pour boîtier de semi-conducteur et procédé de fabrication de substrat de câblage pour boîtier de semi-conducteur
WO2020090601A1 (fr) * 2018-10-30 2020-05-07 凸版印刷株式会社 Substrat de câblage d'encapsulation de semi-conducteur et procédé de fabrication de substrat de câblage d'encapsulation de semi-conducteur
WO2020122014A1 (fr) * 2018-12-10 2020-06-18 凸版印刷株式会社 Carte de câblage pour dispositif à semi-conducteurs, son procédé de fabrication et dispositif à semi-conducteurs
JP2020191323A (ja) * 2019-05-20 2020-11-26 凸版印刷株式会社 半導体パッケージ用配線基板及び半導体パッケージ、並びにそれらの製造方法
JP2020191397A (ja) * 2019-05-23 2020-11-26 凸版印刷株式会社 複合配線基板及びその製造方法
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JP2021512487A (ja) * 2018-09-20 2021-05-13 エルジー・ケム・リミテッド 多層印刷回路基板、その製造方法およびこれを用いた半導体装置
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JP2020191323A (ja) * 2019-05-20 2020-11-26 凸版印刷株式会社 半導体パッケージ用配線基板及び半導体パッケージ、並びにそれらの製造方法
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