WO2017198045A1 - 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置 - Google Patents
移位寄存器单元及其驱动方法、栅极驱动电路、显示装置 Download PDFInfo
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- WO2017198045A1 WO2017198045A1 PCT/CN2017/081824 CN2017081824W WO2017198045A1 WO 2017198045 A1 WO2017198045 A1 WO 2017198045A1 CN 2017081824 W CN2017081824 W CN 2017081824W WO 2017198045 A1 WO2017198045 A1 WO 2017198045A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
- G11C19/287—Organisation of a multiplicity of shift registers
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0404—Matrix technologies
- G09G2300/0408—Integration of the drivers onto the display substrate
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
Definitions
- the present disclosure relates to the field of display technologies, and in particular, to a shift register unit and a driving method thereof, a gate driving circuit, and a display device.
- a gate drive circuit is a circuit for supplying a drive signal to a pixel switch in a pixel circuit.
- the gate drive circuit typically includes a plurality of cascaded gate drive cells that can provide drive signals to pixel cells of different rows, each gate drive cell being actually also a shift register cell.
- each of the gate driving units is connected to at least one high voltage DC terminal and one low voltage DC terminal, and the high voltage DC terminal can receive a high level signal as the operating voltage (supply voltage) of the gate driving unit, and the low voltage DC terminal is actually A low level reference voltage terminal in the circuit of the gate drive unit, which can be understood as a reference ground in the circuit.
- embodiments of the present disclosure provide a shift register unit and a driving method thereof, a gate driving circuit, and a display device, which can reduce DC power consumption.
- the present disclosure provides a shift register unit including an input module, an output module, a reset module, a reset module, and a second node control module.
- the input module is connected to the scan pulse input end and the first node, and is adapted to set the first node to a first level when the scan pulse signal is at a first level;
- the output module is connected to the first node, a clock signal input end and an output end of the shift register unit, configured to set the output end to a level of a first clock signal input by the first clock signal input end when the first node is at a first level, And maintaining the level of the first node when the first node is suspended;
- the second node control module is connected to the scan pulse input end, the output end of the shift register unit, the second clock signal input end, and the second node And a first level DC voltage terminal and a second level DC voltage terminal, and are adapted to: when the scan pulse signal is at a first level or an output signal of the output terminal is at a first level,
- the second node control module includes a first control unit and a second control unit, the first control unit is coupled to the second node and the first level DC voltage terminal, and is adapted to be in the The second node is electrically connected to the first level DC voltage terminal when the second clock signal is at a set level; the second control unit is connected to the scan pulse input end, the output end, and the second node And a second level DC voltage terminal, wherein the second node and the second level DC are adapted when the scan pulse signal of the scan pulse input terminal is at a first level or the output signal of the output terminal is at a first level The voltage terminal is turned on.
- the first control unit includes a first transistor, a control electrode of the first transistor is connected to the second clock signal input end, a first pole is connected to the second node, and a second pole is connected a level DC voltage terminal; the conduction level of the first transistor is the set level.
- the second control unit includes a second transistor and a third transistor, and the conduction current of the second transistor and the third transistor is averaged to a first level; and the second transistor is controlled
- the pole is connected to the scan pulse input end, the first pole is connected to the second node, the second pole is connected to the second level voltage line; the control pole of the third transistor is connected to the output end, and the first pole is connected
- the second node is connected to the second level DC voltage terminal.
- the shift register unit further includes a global reset control module.
- the global reset control module is connected to the first node and the reset signal input end, and is adapted to be in the The second node is set to a first level when the reset signal at the reset signal terminal is at a first level.
- the global reset control module includes a fourth transistor, a first pole of the fourth transistor is coupled to the control electrode to the reset signal input terminal, and a second pole is coupled to the second node;
- the conduction level of the fourth transistor is at a first level.
- the shift register unit further includes a voltage stabilizing module coupled to the second node for maintaining a level of the second node when the second node is suspended.
- the voltage stabilizing module includes a first capacitor, one pole of the first capacitor is connected to the second node, and the other pole is connected to the first level DC voltage terminal and the second level DC voltage terminal. one of the.
- the input module includes a fifth transistor, a control electrode of the fifth transistor is connected to the scan pulse input end, a first pole is connected to the first level DC voltage terminal, and a second pole is connected to the first One node.
- the output module includes a sixth transistor and a second capacitor; a control electrode of the sixth transistor is connected to the first node, a first pole is connected to the first clock signal input end, and a second pole is connected to the second pole An output terminal; one pole of the second capacitor is connected to the first node, and the other pole is connected to one of a first level DC voltage terminal and a second level DC voltage terminal.
- the reset module includes a seventh transistor, a control electrode of the seventh transistor is connected to the second node, a first pole is connected to the first node, and a second pole is connected to a second level DC voltage. end.
- the reset module includes an eighth transistor, a control electrode of the eighth transistor is coupled to the second node, a first pole is coupled to the output terminal, and a second pole is coupled to the second level DC voltage terminal.
- the first level and the set level may be a high level; and the second level may be a low level.
- the present disclosure further provides a driving method for driving a shift register unit according to any of the above embodiments, including:
- the duty ratios of the first levels of the first clock signal and the second clock signal are the same; and the width of each of the first clock signals and each of the first clock signals
- the flat width is the same as the width of the effective level in the scan pulse signal; in one time period, the start time of the active level of the scan pulse signal is the end time of a first level in the second clock signal, The end time is the start time of the first level in the first clock signal adjacent to the active level in the scan pulse signal.
- the present disclosure further provides a gate driving circuit comprising a plurality of cascaded shift register units, the shift register unit being the shift register unit of any of the preceding embodiments.
- the present disclosure further provides a display device, including the gate driving circuit described in any of the foregoing embodiments.
- Embodiments of the present disclosure may make the first voltage input line to which the shift register unit provided by the present disclosure is connected by using the second clock signal, the scan pulse signal input by the scan pulse input terminal, and the output signal at the output of the shift register.
- a DC loop is not formed with the second voltage input line, thereby reducing DC losses.
- 1 is a circuit diagram of a conventional shift register unit composed of 7T1C;
- Figure 2 is a timing chart showing the operation of the shift register unit shown in Figure 1;
- FIG. 3 is a structural block diagram of a shift register unit according to an embodiment of the present disclosure.
- FIG. 4 is a structural block diagram of a shift register unit according to another embodiment of the present disclosure.
- FIG. 5 is a structural block diagram of a shift register unit according to still another embodiment of the present disclosure.
- FIG. 6 is a circuit diagram of a shift register unit provided by an embodiment of the present disclosure.
- Figure 7 is a timing chart showing the operation of the shift register unit shown in Figure 6;
- FIG. 8 is a structural block diagram of a gate driving circuit according to an embodiment of the present disclosure.
- Fig. 1 shows a conventional GOA circuit which employs a 7T1C structure, that is, consists of seven transistors (M1 to M7) and one capacitor (C1).
- the working process includes: in the first stage, the input signal Input is at a high level, and the clock signal CLK and the reset signal Reset are both low level signals.
- the transistor M1 is turned on, and the capacitor C1 is charged.
- the PU point is high and the transistor M6 is turned on.
- the transistors M5 and M6 are all turned on at this time, by setting the size of the transistors M5 and M6, the PD point can be made low, so that the transistors M4 and M7 are turned off to ensure normal output.
- the input signal Input is low and M1 is turned off. Capacitor C1 is charged during the first phase, at which point it can keep the PU point high and transistor M3 on.
- the clock signal CLK is high
- the output Output is high.
- the input signal Input and the clock signal CLK are both low level, M1 is turned off; the reset signal reset is high level, the transistor M2 is turned on, the potential of the PU point is low level, and the transistor M3 is turned off; The point is pulled low, the transistor M6 is turned off, the PD point is high, the transistors M4 and M7 are turned on, and the output is low, that is, the transistor M5 and M4, M7 are simultaneously turned on.
- the embodiment of the present disclosure provides a shift register unit, as shown in FIG. 3, including an input module 1, an output module 2, a second node control module 3, a reset module 4, and a reset module 5, and has a scan pulse input end.
- the input module 1 is connected to the scan pulse input terminal Gate_N-1 and the first node PU, and is adapted to set the first node PU to a first level when the scan pulse signal is at a first level;
- the output module 2 is connected to the first node PU, a clock signal input terminal CK and an output terminal Gate_N of the shift register unit are adapted to set the output terminal Gate_N to the first clock signal input by the first clock signal input terminal CK when the first node PU is at the first level.
- the second node control module 3 is connected to the scan pulse input terminal Gate_N-1, the shift register unit output terminal Gate_N, the second clock signal input terminal CKB, the second node PD, and
- the first level DC voltage terminal VGH and the second level DC voltage terminal VGL are adapted to switch the second node PD and the second level DC when the scan pulse signal is at the first level or the output terminal Gate_N is at the first level
- the voltage terminal VGL is turned on, and when the scan pulse signal and the output signal of the output terminal Gate_N are both at the second level and the second clock signal at the second clock signal input terminal CKB is at the set level, the second node PD is The first level DC voltage terminal VGH is turned on; the reset module 4 is connected to the first node PU and the second node PD, and is adapted to set the first node to the second level when the second
- first level and the “second level” herein refer to two mutually non-intersecting potential level ranges at a certain node position in the circuit, for example, one of a high level and a low level, respectively.
- the disclosure does not limit this.
- the first stage the scan pulse signal at the scan pulse input terminal Gate_N-1 is at the first level, at which time the input module 1 sets the first node PU to the first level; the first at the first clock signal input terminal CK The clock signal is at a second level, the output module 2 outputs a clock signal (ie, a second level) at the first clock signal input terminal CK; and the second clock signal at the second clock signal input terminal CKB is at a second level.
- the second node control module 3 sets the second node PD to the second level, further ensuring that the shift register unit output terminal Gate_N outputs the second level.
- the first clock signal at the first clock signal input terminal CK is at the first level
- the second clock signal input terminal is at the CKB.
- the second clock signal is at a second level.
- the input module 1 does not provide an output
- the first node PU is at a first level
- the output module 2 outputs a level (ie, a first level) of the first clock signal at the first clock signal input terminal CK. Since the output level Gate_N outputs the first level, the second node control module 3 continues to conduct the second node PD and the second level DC voltage terminal VGL to maintain the second node PD at the second level, further ensuring The first level is correctly output at the output Gate_N.
- the third stage the scan pulse input terminal Gate_N-1 is still at the second level, the first clock The signal and the second clock signal are both at the second level. Since the first node PU is still at the first level, the output Gate_N outputs a second level.
- the fourth stage the second clock signal at the second clock signal input terminal CKB changes to a set level, at which time the second node control module 3 turns on the second node PD and the first level DC voltage terminal VGH, so that The second node PD becomes the first level.
- the reset module 4 is turned on to dispose the first node PU to the second level, the reset module 5 is turned on, and the output terminal Gate_N is set to the second level.
- Embodiments of the present disclosure may enable a first voltage input line to which the provided shift register unit is connected by utilizing a second clock signal, an input signal of a scan pulse input terminal, and an output signal at an output terminal of the shift register unit (No.
- the one-level DC voltage terminal VGH is connected to the first voltage input line
- the second voltage input line is not directly electrically connected, so that a direct connection between the two cannot be formed
- the DC loop which in turn reduces DC losses.
- the shift register unit provided by the present disclosure further includes a global reset module 6.
- the global reset control module 6 is connected to the second node PD and the reset signal input terminal G_R, and is adapted to set the second node PD to a first level when the reset signal is at the first level.
- the shift register unit provided by the present disclosure further includes a voltage stabilizing module 7.
- the voltage stabilizing module 7 is connected to the second node PD and the second level DC voltage terminal VGL for maintaining the level of the second node PD when the second node PD is suspended.
- the functions of the input module 1, the output module 2, the second node control module 3, the reset module 4, and the reset module 5 and the cooperative working principle of each module are described above, and those skilled in the art can know that the corresponding Any circuit of the function can be applied to the corresponding module in the shift register of the present disclosure, and the present disclosure does not limit the specific circuit of each module.
- the above-mentioned global reset module 6 and the voltage stabilizing module 7 can be set as needed, and are not limited by the specific circuits of the input module 1, the output module 2, the second node control module 3, the reset module 4, and the reset module 5. .
- the circuits of the global reset module 6 and the voltage stabilizing module 7 can also be appropriately combined into other modules of the shift register unit without affecting the shift register unit of the present disclosure to prevent or overcome the direct connection of the first voltage line and the second voltage line.
- the problem of DC loss caused by the connection That is, the shift register unit configured by arbitrarily combining the circuits of the above modules without affecting the problem of preventing or overcoming the DC loss caused by the direct electrical connection between the first voltage line and the second voltage line
- the circuit also falls within the scope of the present invention.
- FIG. 6 is a specific circuit diagram of a second node control module 3 in a shift register unit according to an embodiment of the present disclosure.
- the second node control module 3 in the embodiment of the present disclosure includes a first control unit 31 and a second control unit 32.
- the first control unit 31 is connected to the second node PD and the first level DC voltage terminal VGH, and is adapted to switch the second node PD and the first power when the second clock signal at the second clock signal input terminal CKB is at a set level.
- the flat DC voltage terminal VGH is turned on.
- the second control unit 32 is connected to the scan pulse input terminal Gate_N-1, the output terminal Gate_N, the second node PD and the second level DC voltage terminal VGL, and is adapted to be at the first level or output of the scan pulse input terminal Gate_N-1.
- the second node PD is turned on with the second level DC voltage terminal VGL.
- the embodiment may of course be adopted, and the disclosure is not limited.
- circuits that can implement the functions of the first control unit 31 and the second control unit 32 can be applied to the corresponding units, and the disclosure is not limited.
- the first control unit 31 includes a first transistor M1.
- the control electrode of the first transistor M1 is connected to the second clock signal input terminal CKB, the first pole is connected to the second node PD, and the second pole is connected to the first level DC voltage terminal VGH; the conduction level of the first transistor M1 is set. Level.
- the second control unit 32 includes a second transistor M2 and a third transistor M3.
- the conduction current of the second transistor M2 and the third transistor M3 is averaged to a first level;
- the control electrode of the second transistor M2 is connected to the scan pulse input terminal Gate_N-1, the first pole is connected to the second node PD, and the second pole is connected to the second pole
- the control terminal of the third transistor M3 is connected to the output terminal Gate_N, the first pole is connected to the second node PD, and the second pole is connected to the second level DC voltage terminal VGL.
- the second transistor M2 turns on the second node PD and the second level DC voltage terminal VGL, thereby placing the second node PD Is the second level.
- the third transistor M3 turns on the second node PD and the second level DC voltage terminal VGL, thereby disposing the second node PD to the second level.
- the first transistor M1 turns on the second node PD and the first level DC voltage terminal VGH, thereby disposing the second node PD to the first level.
- the global reset control module 6 described above includes a fourth transistor M4.
- the first pole and the control electrode of the fourth transistor M4 are connected to the global reset signal input terminal G_R, and the second pole is connected to the second node PD; the conduction level of the fourth transistor is the first level.
- the fourth transistor M4 sets the second node PD to the first level.
- the voltage stabilizing module 7 includes a first capacitor C1.
- One pole of the first capacitor C1 is connected to the second node PD, and the other pole is connected to the second level DC voltage terminal VGL. It can be seen that when the second node PD is at the first level, the first capacitor C1 is charged, and the first capacitor C1 can keep the second node PD at the first level, thereby keeping the reset module 4 and the reset module 5 open. status.
- the input module 1 in the embodiment of the present disclosure includes a fifth transistor M5.
- the control electrode of the fifth transistor M5 is connected to the scan pulse input terminal Gate_N-1, the first pole is connected to the first level DC voltage terminal VGH, and the second pole is connected to the first node PU.
- the fifth transistor M5 turns on the first node and the first level DC voltage terminal VGH, thereby setting the first node PU to the first level. .
- the other pole of the first capacitor C1 in the embodiment of the present disclosure may also be connected to the second level DC voltage terminal VGH, the output terminal Gate_N or the first clock signal input terminal CK, so that the first capacitor C1 can also be Achieving the effect of maintaining the second level at the second node PD is achieved.
- the output module 2 in the embodiment of the present disclosure includes a sixth transistor M6 and a second capacitor C2.
- the control electrode of the sixth transistor M6 is connected to the first node PU, the first pole is connected to the first clock signal input terminal CK, and the second pole is connected to the output terminal Gate_N.
- One pole of the second capacitor C2 is connected to the first node PU, and the other pole is connected to the second level DC voltage terminal VGL.
- the sixth transistor M6 turns on the first clock signal input terminal CK and the output terminal Gate_N, so that the output terminal Gate_N outputs the first clock signal at the first clock signal input terminal CK. .
- the other pole of the second capacitor C2 in the embodiment of the present disclosure may also be connected to the second level DC voltage terminal VGH, the output terminal Gate_N or the first clock signal input terminal CK, so that the second capacitor C2 can also be Achieving the effect of maintaining the second level at the second node PD is achieved.
- the reset module 4 includes a seventh transistor M7.
- the control electrode of the seventh transistor M7 is connected to the second node PD, the first pole is connected to the first node PU, and the second pole is connected to the second level DC voltage terminal VGL. It can be seen that when the second node PD is at the first level, the seventh transistor M7 turns on the first node PU and the second level DC voltage terminal VGL, thereby disposing the first node PU to the second level.
- the reset module 5 in the embodiment of the present disclosure includes an eighth transistor M8.
- the control electrode of the eighth transistor M8 is connected to the second node PD, the first pole is connected to the output terminal Gate_N, and the second pole is connected to the second level DC voltage terminal VGL. It can be seen that when the second node PD is at the first level, the eighth transistor M8 turns on the output terminal Gate_N and the second level DC voltage terminal VGL, thereby disposing the output Gate_N to the second level.
- the first level, the set level may be a high level; the second level may be a low level.
- the first transistor M1 to the eighth transistor M8 in the shift register unit shown in FIG. 6 adopt an N-type transistor (when the gate is at a high level, the source and the drain of the transistor are turned on), The active level at its gate is high, the first level.
- the first transistor M1 to the eighth transistor M8 may use a P-type transistor (when the gate is at a low level, the source and the drain of the transistor are turned on, that is, at the gate
- the present disclosure does not limit the effective level to a low level, that is, a second level.
- connection between the source and the drain of the transistor can be determined according to the type of transistor selected, and when the transistor has a structure in which the source and the drain are symmetric, the source and the drain can be regarded as two that are not particularly distinguished. Electrodes, which are well known to those skilled in the art, are not described herein.
- FIG. 7 is a timing chart showing the operation of the shift register unit circuit according to the embodiment of the present disclosure. The operation of the gate driving circuit shown in FIG. 6 of the embodiment of the present disclosure will be described below with reference to FIG. 7 . See Figure 7:
- Phase I The scan pulse signal at the scan pulse input terminal Gate_N-1 is at a high level, and the fifth transistor M5 is turned on to turn on the first node PU and the first level DC voltage terminal VGH, thereby setting the first node PU to High level.
- the second capacitor C2 is charged, and the first capacitor C1 is discharged.
- the first node PU is at a high level, and the sixth transistor M6 is turned on to turn on the first clock signal input terminal CK and the output terminal Gate_N. Since the first clock signal input terminal CK is at a low level, the shift register output Gate_N outputs a low level.
- the second transistor M2 Since the scan pulse input terminal Gate_N-1 is at a high level, the second transistor M2 is turned on. Thereby, the second node PD and the first level DC voltage terminal VGL are turned on, thereby setting the second node PD to a low level. At this time, the seventh transistor M7 and the eighth transistor M8 are turned off to ensure voltage stabilization at the first node PU and stabilization of the shift register output signal.
- the second clock signal at the second clock signal input terminal CKB is at a low level, at which time the first transistor M1 is turned off.
- Phase II The scan pulse input terminal Gate_N-1 is at a low level, and the second transistor M2 and the fifth transistor are turned off. Since the second capacitor C2 is charged in the first stage, the first node PU is kept at a high level.
- the sixth transistor M6 continues to be turned on, and the first clock signal at the input terminal CK of the first clock signal is at a high level, and at this time, the output terminal Gate_N outputs a high level.
- the third transistor M3 Since the output terminal Gate_N outputs a high level, the third transistor M3 is turned on, turning on the second node PD and the second voltage DC voltage terminal VGL, setting the second node PD to a low level, and the seventh transistor M7 and the eighth transistor M8 Turn off to ensure voltage stabilization at the first node PU and stabilization of the shift register output signal.
- the second clock signal at the second clock signal input terminal CKB is at a low level, and the first transistor M1 is turned off.
- Stage III The scan pulse signal at the scan pulse input Gate_N-1 is at a low level, and the second transistor M2 and the fifth transistor M5 are turned off.
- the first node PU is at a high level
- the first clock signal at the first clock signal input terminal CK is at a low level, and at this time, the output terminal Gate_N outputs a low level.
- the third transistor M3 is turned off.
- the second clock signal at the second clock signal input terminal CKB is at a low level, and at this time, the second node PD is at a low level in the second phase.
- the first capacitor C1 keeps the second node PD low.
- Stage IV The second clock input terminal CKB changes to a high level.
- the first transistor M1 is turned on, turning on the first level DC voltage terminal VGH and the second node PD, thereby setting the second node PD to be high. Level, while charging the first capacitor C1.
- the seventh transistor M7 and the eighth transistor M8 are turned on, and the seventh transistor M7 turns on the first node PU and the first level DC voltage terminal VGL to dispose the first node PU to a low level and discharge the second capacitor C2;
- the eighth transistor M8 turns on the output terminal Gate_N and the first level DC voltage terminal VGL, and sets the output terminal Gate_N to a low level.
- the fourth transistor M4 when the global reset signal input terminal G_R inputs a reset pulse, the fourth transistor M4 is turned on, the second node PD is pulled up to a high level, and the seventh transistor M7 and the eighth transistor M8 are simultaneously turned on. And the first node PU and the output Gate_N are set to a low level, thereby realizing resetting of the shift register unit. If the first capacitor C1 is present, the first capacitor C1 maintains a high state at the second node PD, so that the output Gate_N continues to output a low level.
- the scan pulse signal input at the scan pulse input terminal Gate_N-1 is a scan pulse whose effective level is the first level.
- a first clock signal is input to the first clock signal input terminal CK, and a second clock signal is input to the second clock signal input terminal CKB.
- the duty ratios of the first level of the first clock signal and the second clock signal are the same; and the width of a first level of the first clock signal and the width of a first level of the second clock signal are both scanned
- the effective levels in the pulse signal have the same width. As shown in FIG.
- the start time of an active level of the scan pulse signal is the end time of the first level signal in the second clock signal, and the end time of the active level of the scan pulse signal is the first clock signal.
- the start time of the first level adjacent to the active level in the scan pulse signal that is, in a time period as shown in FIG. 7, the effective level of the scan pulse signal is just at a first level signal of the second clock signal CKB and the first level signal immediately following the second clock signal. Between the first level signals of the first clock signal.
- Embodiments of the present disclosure utilize a scan pulse signal at a scan pulse input terminal Gate_N-1, a second clock signal at a second clock signal input terminal CKB, a first clock signal at a first clock signal input terminal CK, and a shift
- the output signal at the output of the register, Gate_N can form a DC path between the first level DC voltage terminal VGL and the second level DC voltage terminal VGH, thereby alleviating or solving the DC loss of the shift register unit in the prior art. Too big a problem.
- the present disclosure also provides a driving method for a shift register unit as described above. See Figure 7, including:
- a further embodiment of the present disclosure provides a gate driving circuit, as shown in FIG. 8, including a plurality of cascaded shift register units, which are described in the above embodiments. Shift register unit.
- the first clock signal input terminal CK and the second clock signal input terminal CKB of the previous shift register unit and the subsequent shift register unit The received clock signals are opposite to each other.
- the first clock signal input terminal CK and the second clock signal input terminal CKB of the previous shift register unit respectively receive the first clock signal and the second clock signal, and the first clock of the subsequent shift register unit
- the signal input terminal CK and the second clock signal input terminal CKB receive the second clock signal and the first clock signal, respectively.
- the two shift register units operate in the same principle and will not be described in detail herein.
- a further embodiment of the present disclosure also provides a display device comprising the shift register unit or gate drive circuit of any of the above embodiments.
- the display device in this embodiment may be any product or component having a display function such as a display panel, an electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator, and the like.
- the orientation or positional relationship of the terms “upper”, “lower” and the like is based on the orientation or positional relationship shown in the drawings, and is merely for convenience of description of the present disclosure and simplified description, rather than indicating or implying
- the device or component referred to must have a particular orientation, configuration and operation in a particular orientation, and thus is not to be construed as limiting the invention.
- the terms “mounted,” “connected,” and “connected” are used in a broad sense and may be, for example, a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection, It can also be an electrical connection; it can be directly connected, or it can be connected indirectly through an intermediate medium, which can be the internal connection of two components.
- the specific meanings of the above terms in the present disclosure can be understood by those skilled in the art on a case-by-case basis.
Abstract
Description
Claims (16)
- 一种移位寄存器单元,包括输入模块、输出模块、复位模块、重置模块和第二节点控制模块,其中:所述输入模块连接扫描脉冲输入端与第一节点,适于在扫描脉冲信号为第一电平时将所述第一节点置为第一电平;所述输出模块连接所述第一节点、第一时钟信号输入端、以及移位寄存器单元的输出端,适于在所述第一节点为第一电平时将所述输出端置为第一时钟信号输入端输入的第一时钟信号的电平,并在所述第一节点悬浮时维持所述第一节点的电平;所述第二节点控制模块连接扫描脉冲输入端、移位寄存器单元的输出端、第二时钟信号输入端、第二节点以及第一电平直流电压端和第二电平直流电压端,适于在所述扫描脉冲信号为第一电平或者所述输出端的输出信号为第一电平时将所述第二节点与第二电平直流电压端导通,并在所述扫描脉冲信号和所述输出端的输出信号均为第二电平且第二时钟信号为设定电平时,将所述第二节点与第一电平直流电压端导通;所述复位模块连接所述第一节点与所述第二节点,适于在所述第二节点为第一电平时将所述第一节点置为第二电平;所述重置模块连接所述第二节点与所述输出端,适于在所述第二节点为第一电平时将所述输出端置为第二电平。
- 根据权利要求1所述的移位寄存器单元,其中所述第二节点控制模块包括第一控制单元和第二控制单元,其中:所述第一控制单元连接所述第二节点和第一电平直流电压端,适于在所述第二时钟信号为设定电平时将所述第二节点与第一电平直流电压端导通;所述第二控制单元连接所述扫描脉冲输入端、所述输出端、所述第二节点和第二电平直流电压端,适于在所述扫描脉冲输入端的扫描脉冲信号为第一电平或所述输出端的输出信号为第一电平时将所述第二节点与第二电平直流电压端导通。
- 根据权利要求2所述的移位寄存器单元,其中所述第一控制单元包括第一晶体管,所述第一晶体管的控制极连接所述第二时钟信号 输入端,第一极连接所述第二节点,第二极连接第一电平直流电压端;所述第一晶体管的导通电平为所述设定电平。
- 根据权利要求2所述的移位寄存器单元,其中所述第二控制单元包括第二晶体管和第三晶体管,所述第二晶体管和所述第三晶体管的导通电平均为第一电平;所述第二晶体管的控制极连接所述扫描脉冲输入端,第一极连接所述第二节点,第二极连接所述第二电平电压线;所述第三晶体管的控制极连接所述输出端,第一极连接所述第二节点,第二极连接用于第二电平直流电压端。
- 根据权利要求1所述的移位寄存器单元,还包括全局复位控制模块;所述全局复位控制模块连接所述第一节点和复位信号输入端,适于在复位信号端处的复位信号为第一电平时将所述第二节点置为第一电平。
- 根据权利要求5所述的移位寄存器单元,其中所述全局复位控制模块包括第四晶体管,所述第四晶体管的第一极与控制极连接所述复位信号输入端,第二极与所述第二节点相连接;所述第四晶体管的导通电平为第一电平。
- 根据权利要求1所述的移位寄存器单元,还包括与所述第二节点连接的稳压模块,用于在所述第二节点悬浮时维持所述第二节点的电平。
- 根据权利要求7所述的移位寄存器单元,其中所述稳压模块包括第一电容,所述第一电容的一极连接所述第二节点,另一极连接第一电平直流电压端和第二电平直流电压端中的一个。
- 根据权利要求1所述的移位寄存器单元,其中所述输入模块包括第五晶体管,所述第五晶体管的控制极连接所述扫描脉冲输入端,第一极连接第一电平直流电压端,第二极连接所述第一节点。
- 根据权利要求1所述的移位寄存器单元,其中所述输出模块包括第六晶体管和第二电容;所述第六晶体管的控制极连接所述第一节点,第一极连接第一时钟信号输入端,第二极连接所述输出端;所述第二电容的一极连接所述第一节点,另一极连接第一电平直 流电压端和第二电平直流电压端中的一个。
- 根据权利要求1所述的移位寄存器单元,其中所述复位模块包括第七晶体管,所述第七晶体管的控制极连接所述第二节点,第一极连接所述第一节点,第二极连接第二电平直流电压端。
- 根据权利要求1所述的移位寄存器单元,其中所述重置模块包括第八晶体管,所述第八晶体管的控制极连接第二节点,第一极连接所述输出端,第二极连接第二电平直流电压端。
- 根据权利要求1~12任意一项所述的移位寄存器单元,其中所述第一电平、所述设定电平为高电平;所述第二电平为低电平。
- 一种用于驱动如权利要求1~13任意一项所述的移位寄存器单元的驱动方法,包括:在扫描脉冲输入端输入有效电平为第一电平的扫描脉冲信号;并在第一时钟信号输入端输入第一时钟信号、在第二时钟信号输入端输入第二时钟信号;其中,第一时钟信号和第二时钟信号的第一电平的占空比相同;且第一时钟信号中的每个第一电平的宽度与第二时钟信号中每个第一电平的宽度均与扫描脉冲信号中的有效电平的宽度相同;其中在一个时间周期内,扫描脉冲信号的有效电平的起始时刻为第二时钟信号中的一个第一电平的结束时刻,结束时刻为第一时钟信号中与扫描脉冲信号中的该有效电平相邻的第一电平的起始时刻。
- 一种栅极驱动电路,包括多个级联的移位寄存器单元,所述移位寄存器单元为如权利要求1~13任意一项所述的移位寄存器单元。
- 一种显示装置,包括权利要求15所述的栅极驱动电路。
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