WO2017198045A1

WO2017198045A1 - Shifting register and driving method therefor, gate driving circuit and display device

Info

Publication number: WO2017198045A1
Application number: PCT/CN2017/081824
Authority: WO
Inventors: 冯思林; 李红敏
Original assignee: 京东方科技集团股份有限公司; 合肥京东方光电科技有限公司
Priority date: 2016-05-16
Filing date: 2017-04-25
Publication date: 2017-11-23
Also published as: US10096375B2; CN105761660A; US20180226133A1; CN105761660B

Abstract

A shifting register and a driving method therefor, a gate driving circuit and a display device. The shift register unit comprises: an input module (1), adapted to set a first node (PU) to a first level when a scan pulse input terminal (Gate_N-1) is at the first level; an output module (2), adapted to set an output terminal (Gate_N) of the shift register to a level of a first clock signal when the first node (PU) is at the first level, and to maintain the level of the first node (PU) when the first node (PU) is suspended; a second node control module (3), adapted to establish a conduction between a second node (PD) and a second Level DC voltage terminal (VGL) when a scan pulse signal is at the first level or an output signal of the output terminal (Gate_N) is at the first level, and to establish a conduction between the second node (PD) and a first Level DC voltage terminal (VGH) when the scan pulse signal and the output signal are at a second level and a second clock signal is at a set level; a reset module (4), adapted to set the first node (PU) to the second level when the second node (PD) is at the first level; a restart module (5), adapted to set the output terminal (Gate_N) to the second level when the second node (PD) is at the first level.

Description

Shift register unit and driving method thereof, gate driving circuit, and display device

Cross-reference to related applications

The present application claims priority to the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the

Technical field

The present disclosure relates to the field of display technologies, and in particular, to a shift register unit and a driving method thereof, a gate driving circuit, and a display device.

Background technique

In the field of display technology, a gate drive circuit (GOA) is a circuit for supplying a drive signal to a pixel switch in a pixel circuit. The gate drive circuit typically includes a plurality of cascaded gate drive cells that can provide drive signals to pixel cells of different rows, each gate drive cell being actually also a shift register cell. Moreover, each of the gate driving units is connected to at least one high voltage DC terminal and one low voltage DC terminal, and the high voltage DC terminal can receive a high level signal as the operating voltage (supply voltage) of the gate driving unit, and the low voltage DC terminal is actually A low level reference voltage terminal in the circuit of the gate drive unit, which can be understood as a reference ground in the circuit.

However, for the existing gate driving circuit, when it is in operation, there is generally a case where the high voltage DC terminal and the low voltage DC terminal are electrically connected to directly form a DC path, thereby generating DC loss. Moreover, as the frequency of use of the gate driving circuit increases and the operating time increases, such DC loss continues to accumulate, resulting in an increase in power consumption of the display device.

Summary of the invention

In view of the defects in the prior art, embodiments of the present disclosure provide a shift register unit and a driving method thereof, a gate driving circuit, and a display device, which can reduce DC power consumption.

In a first aspect, the present disclosure provides a shift register unit including an input module, an output module, a reset module, a reset module, and a second node control module. The input module is connected to the scan pulse input end and the first node, and is adapted to set the first node to a first level when the scan pulse signal is at a first level; the output module is connected to the first node, a clock signal input end and an output end of the shift register unit, configured to set the output end to a level of a first clock signal input by the first clock signal input end when the first node is at a first level, And maintaining the level of the first node when the first node is suspended; the second node control module is connected to the scan pulse input end, the output end of the shift register unit, the second clock signal input end, and the second node And a first level DC voltage terminal and a second level DC voltage terminal, and are adapted to: when the scan pulse signal is at a first level or an output signal of the output terminal is at a first level, The two-level DC voltage terminal is turned on, and when the scan pulse signal and the output signal of the output terminal are at a second level and the second clock signal is at a set level, the second node and the first level are The DC voltage terminal is turned on; the reset module is connected to the first node and the second node, and is adapted to set the first node to a second level when the second node is at a first level; The reset module is connected to the first And said output node, said second node adapted to a first level of said output terminal is set to a second level.

In some cases, the second node control module includes a first control unit and a second control unit, the first control unit is coupled to the second node and the first level DC voltage terminal, and is adapted to be in the The second node is electrically connected to the first level DC voltage terminal when the second clock signal is at a set level; the second control unit is connected to the scan pulse input end, the output end, and the second node And a second level DC voltage terminal, wherein the second node and the second level DC are adapted when the scan pulse signal of the scan pulse input terminal is at a first level or the output signal of the output terminal is at a first level The voltage terminal is turned on.

In some embodiments, the first control unit includes a first transistor, a control electrode of the first transistor is connected to the second clock signal input end, a first pole is connected to the second node, and a second pole is connected a level DC voltage terminal; the conduction level of the first transistor is the set level.

In some embodiments, the second control unit includes a second transistor and a third transistor, and the conduction current of the second transistor and the third transistor is averaged to a first level; and the second transistor is controlled The pole is connected to the scan pulse input end, the first pole is connected to the second node, the second pole is connected to the second level voltage line; the control pole of the third transistor is connected to the output end, and the first pole is connected The second node is connected to the second level DC voltage terminal.

In some embodiments, the shift register unit further includes a global reset control module. The global reset control module is connected to the first node and the reset signal input end, and is adapted to be in the The second node is set to a first level when the reset signal at the reset signal terminal is at a first level.

In some embodiments, the global reset control module includes a fourth transistor, a first pole of the fourth transistor is coupled to the control electrode to the reset signal input terminal, and a second pole is coupled to the second node; The conduction level of the fourth transistor is at a first level.

In some embodiments, the shift register unit further includes a voltage stabilizing module coupled to the second node for maintaining a level of the second node when the second node is suspended.

In some embodiments, the voltage stabilizing module includes a first capacitor, one pole of the first capacitor is connected to the second node, and the other pole is connected to the first level DC voltage terminal and the second level DC voltage terminal. one of the.

In some embodiments, the input module includes a fifth transistor, a control electrode of the fifth transistor is connected to the scan pulse input end, a first pole is connected to the first level DC voltage terminal, and a second pole is connected to the first One node.

In some embodiments, the output module includes a sixth transistor and a second capacitor; a control electrode of the sixth transistor is connected to the first node, a first pole is connected to the first clock signal input end, and a second pole is connected to the second pole An output terminal; one pole of the second capacitor is connected to the first node, and the other pole is connected to one of a first level DC voltage terminal and a second level DC voltage terminal.

In some embodiments, the reset module includes a seventh transistor, a control electrode of the seventh transistor is connected to the second node, a first pole is connected to the first node, and a second pole is connected to a second level DC voltage. end.

In some embodiments, the reset module includes an eighth transistor, a control electrode of the eighth transistor is coupled to the second node, a first pole is coupled to the output terminal, and a second pole is coupled to the second level DC voltage terminal.

For the shift register unit described in any of the above embodiments, the first level and the set level may be a high level; and the second level may be a low level.

In a second aspect, the present disclosure further provides a driving method for driving a shift register unit according to any of the above embodiments, including:

And inputting a scan pulse signal whose level is a first level at the scan pulse input end; and inputting a first clock signal at the first clock signal input end and inputting the second clock signal at the second clock signal input end. The duty ratios of the first levels of the first clock signal and the second clock signal are the same; and the width of each of the first clock signals and each of the first clock signals The flat width is the same as the width of the effective level in the scan pulse signal; in one time period, the start time of the active level of the scan pulse signal is the end time of a first level in the second clock signal, The end time is the start time of the first level in the first clock signal adjacent to the active level in the scan pulse signal.

In a third aspect, the present disclosure further provides a gate driving circuit comprising a plurality of cascaded shift register units, the shift register unit being the shift register unit of any of the preceding embodiments.

In a fourth aspect, the present disclosure further provides a display device, including the gate driving circuit described in any of the foregoing embodiments.

Embodiments of the present disclosure may make the first voltage input line to which the shift register unit provided by the present disclosure is connected by using the second clock signal, the scan pulse signal input by the scan pulse input terminal, and the output signal at the output of the shift register. A DC loop is not formed with the second voltage input line, thereby reducing DC losses.

DRAWINGS

In order to more clearly illustrate the technical solutions provided by the embodiments of the present disclosure, a brief description of the drawings to be used in the description of the embodiments will be briefly described. It is obvious that the drawings in the following description are some embodiments of the present disclosure. Other drawings may also be obtained from those of ordinary skill in the art in light of the inventive work.

1 is a circuit diagram of a conventional shift register unit composed of 7T1C;

Figure 2 is a timing chart showing the operation of the shift register unit shown in Figure 1;

3 is a structural block diagram of a shift register unit according to an embodiment of the present disclosure;

4 is a structural block diagram of a shift register unit according to another embodiment of the present disclosure;

FIG. 5 is a structural block diagram of a shift register unit according to still another embodiment of the present disclosure;

6 is a circuit diagram of a shift register unit provided by an embodiment of the present disclosure;

Figure 7 is a timing chart showing the operation of the shift register unit shown in Figure 6;

FIG. 8 is a structural block diagram of a gate driving circuit according to an embodiment of the present disclosure.

detailed description

The technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the drawings in the embodiments of the present disclosure. Is a part of the embodiment of the invention, not All embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present disclosure without departing from the inventive scope are the scope of the invention.

Fig. 1 shows a conventional GOA circuit which employs a 7T1C structure, that is, consists of seven transistors (M1 to M7) and one capacitor (C1). As shown in FIG. 2, the working process includes: in the first stage, the input signal Input is at a high level, and the clock signal CLK and the reset signal Reset are both low level signals. At this time, the transistor M1 is turned on, and the capacitor C1 is charged. The PU point is high and the transistor M6 is turned on. Although the transistors M5 and M6 are all turned on at this time, by setting the size of the transistors M5 and M6, the PD point can be made low, so that the transistors M4 and M7 are turned off to ensure normal output. In the second phase, the input signal Input is low and M1 is turned off. Capacitor C1 is charged during the first phase, at which point it can keep the PU point high and transistor M3 on. When the clock signal CLK is high, the output Output is high. In the third stage, the input signal Input and the clock signal CLK are both low level, M1 is turned off; the reset signal reset is high level, the transistor M2 is turned on, the potential of the PU point is low level, and the transistor M3 is turned off; The point is pulled low, the transistor M6 is turned off, the PD point is high, the transistors M4 and M7 are turned on, and the output is low, that is, the transistor M5 and M4, M7 are simultaneously turned on. It can be seen that when the conventional GOA circuit shown in FIG. 1 is operated, there are cases where the transistors M5 and M6 are simultaneously turned on, and the transistors M5, M7 and M4 are simultaneously turned on. In these cases, the DC high voltage GCH and the DC low voltage are present. The flat VGL forms a DC path that produces DC losses. When the frequency of use of the GOA circuit shown in FIG. 1 is high, such DC loss continues to accumulate, resulting in an increase in power consumption of the display device.

The embodiment of the present disclosure provides a shift register unit, as shown in FIG. 3, including an input module 1, an output module 2, a second node control module 3, a reset module 4, and a reset module 5, and has a scan pulse input end. Gate_N-1, the first node PU, the second node PD, and the output Gate_N.

The input module 1 is connected to the scan pulse input terminal Gate_N-1 and the first node PU, and is adapted to set the first node PU to a first level when the scan pulse signal is at a first level; the output module 2 is connected to the first node PU, a clock signal input terminal CK and an output terminal Gate_N of the shift register unit are adapted to set the output terminal Gate_N to the first clock signal input by the first clock signal input terminal CK when the first node PU is at the first level. Level, and floating at the first node PU (floating, means that the PU and the circuit connected to it have no input current or electricity The state of the first node PU is maintained; the second node control module 3 is connected to the scan pulse input terminal Gate_N-1, the shift register unit output terminal Gate_N, the second clock signal input terminal CKB, the second node PD, and The first level DC voltage terminal VGH and the second level DC voltage terminal VGL are adapted to switch the second node PD and the second level DC when the scan pulse signal is at the first level or the output terminal Gate_N is at the first level The voltage terminal VGL is turned on, and when the scan pulse signal and the output signal of the output terminal Gate_N are both at the second level and the second clock signal at the second clock signal input terminal CKB is at the set level, the second node PD is The first level DC voltage terminal VGH is turned on; the reset module 4 is connected to the first node PU and the second node PD, and is adapted to set the first node to the second level when the second node PD is at the first level; The setting module 5 is connected to the second node PD and the output terminal Gate_N, and is adapted to set the output terminal Gate_N to the second level when the second node PD is at the first level.

The "first level" and the "second level" herein refer to two mutually non-intersecting potential level ranges at a certain node position in the circuit, for example, one of a high level and a low level, respectively. The disclosure does not limit this.

In order to more clearly illustrate the structure and function of each of the above units, a brief description of the operation of the shift register unit will be given below. The working process of the shift register unit provided by the above embodiment of the present disclosure may include the following stages.

The first stage: the scan pulse signal at the scan pulse input terminal Gate_N-1 is at the first level, at which time the input module 1 sets the first node PU to the first level; the first at the first clock signal input terminal CK The clock signal is at a second level, the output module 2 outputs a clock signal (ie, a second level) at the first clock signal input terminal CK; and the second clock signal at the second clock signal input terminal CKB is at a second level. The second node control module 3 sets the second node PD to the second level, further ensuring that the shift register unit output terminal Gate_N outputs the second level.

The second stage: the scan pulse input terminal Gate_N-1 becomes the second level. At this time, the first clock signal at the first clock signal input terminal CK is at the first level, and the second clock signal input terminal is at the CKB. The second clock signal is at a second level. The input module 1 does not provide an output, the first node PU is at a first level, and the output module 2 outputs a level (ie, a first level) of the first clock signal at the first clock signal input terminal CK. Since the output level Gate_N outputs the first level, the second node control module 3 continues to conduct the second node PD and the second level DC voltage terminal VGL to maintain the second node PD at the second level, further ensuring The first level is correctly output at the output Gate_N.

The third stage: the scan pulse input terminal Gate_N-1 is still at the second level, the first clock The signal and the second clock signal are both at the second level. Since the first node PU is still at the first level, the output Gate_N outputs a second level.

The fourth stage: the second clock signal at the second clock signal input terminal CKB changes to a set level, at which time the second node control module 3 turns on the second node PD and the first level DC voltage terminal VGH, so that The second node PD becomes the first level. At this time, the reset module 4 is turned on to dispose the first node PU to the second level, the reset module 5 is turned on, and the output terminal Gate_N is set to the second level.

Embodiments of the present disclosure may enable a first voltage input line to which the provided shift register unit is connected by utilizing a second clock signal, an input signal of a scan pulse input terminal, and an output signal at an output terminal of the shift register unit (No. The one-level DC voltage terminal VGH is connected to the first voltage input line) and the second voltage input line (the second-level DC voltage terminal VGL is connected to the second voltage input line) is not directly electrically connected, so that a direct connection between the two cannot be formed The DC loop, which in turn reduces DC losses.

In another implementation, as shown in FIG. 4, the shift register unit provided by the present disclosure further includes a global reset module 6. The global reset control module 6 is connected to the second node PD and the reset signal input terminal G_R, and is adapted to set the second node PD to a first level when the reset signal is at the first level.

In another embodiment, as shown in FIG. 5, the shift register unit provided by the present disclosure further includes a voltage stabilizing module 7. The voltage stabilizing module 7 is connected to the second node PD and the second level DC voltage terminal VGL for maintaining the level of the second node PD when the second node PD is suspended.

It should be noted that the functions of the input module 1, the output module 2, the second node control module 3, the reset module 4, and the reset module 5 and the cooperative working principle of each module are described above, and those skilled in the art can know that the corresponding Any circuit of the function can be applied to the corresponding module in the shift register of the present disclosure, and the present disclosure does not limit the specific circuit of each module. In addition, the above-mentioned global reset module 6 and the voltage stabilizing module 7 can be set as needed, and are not limited by the specific circuits of the input module 1, the output module 2, the second node control module 3, the reset module 4, and the reset module 5. . The circuits of the global reset module 6 and the voltage stabilizing module 7 can also be appropriately combined into other modules of the shift register unit without affecting the shift register unit of the present disclosure to prevent or overcome the direct connection of the first voltage line and the second voltage line. The problem of DC loss caused by the connection. That is, the shift register unit configured by arbitrarily combining the circuits of the above modules without affecting the problem of preventing or overcoming the DC loss caused by the direct electrical connection between the first voltage line and the second voltage line The circuit also falls within the scope of the present invention.

FIG. 6 is a specific circuit diagram of a second node control module 3 in a shift register unit according to an embodiment of the present disclosure. Referring to FIG. 6, the second node control module 3 in the embodiment of the present disclosure includes a first control unit 31 and a second control unit 32. The first control unit 31 is connected to the second node PD and the first level DC voltage terminal VGH, and is adapted to switch the second node PD and the first power when the second clock signal at the second clock signal input terminal CKB is at a set level. The flat DC voltage terminal VGH is turned on. The second control unit 32 is connected to the scan pulse input terminal Gate_N-1, the output terminal Gate_N, the second node PD and the second level DC voltage terminal VGL, and is adapted to be at the first level or output of the scan pulse input terminal Gate_N-1. When the Gate_N is at the first level, the second node PD is turned on with the second level DC voltage terminal VGL.

An example of the second node control module 3 is described above. The embodiment may of course be adopted, and the disclosure is not limited. In addition, circuits that can implement the functions of the first control unit 31 and the second control unit 32 can be applied to the corresponding units, and the disclosure is not limited.

In order to enable those skilled in the art to better understand the cooperative working process of the first control unit and the second control unit and other individual modules in the present disclosure, the embodiments of the present disclosure are described in detail using a specific circuit.

Referring to FIG. 6, the first control unit 31 includes a first transistor M1. The control electrode of the first transistor M1 is connected to the second clock signal input terminal CKB, the first pole is connected to the second node PD, and the second pole is connected to the first level DC voltage terminal VGH; the conduction level of the first transistor M1 is set. Level. The second control unit 32 includes a second transistor M2 and a third transistor M3. The conduction current of the second transistor M2 and the third transistor M3 is averaged to a first level; the control electrode of the second transistor M2 is connected to the scan pulse input terminal Gate_N-1, the first pole is connected to the second node PD, and the second pole is connected to the second pole The two-level DC voltage terminal VGL; the control terminal of the third transistor M3 is connected to the output terminal Gate_N, the first pole is connected to the second node PD, and the second pole is connected to the second level DC voltage terminal VGL.

It can be seen that when the scan pulse signal at the scan pulse input terminal Gate_N-1 is at the first level, the second transistor M2 turns on the second node PD and the second level DC voltage terminal VGL, thereby placing the second node PD Is the second level. Alternatively, when the output signal of the output Gate_N is at the first level, the third transistor M3 turns on the second node PD and the second level DC voltage terminal VGL, thereby disposing the second node PD to the second level. When the second clock signal at the second clock signal CKB is at a set level, the first transistor M1 turns on the second node PD and the first level DC voltage terminal VGH, thereby disposing the second node PD to the first level. .

The global reset control module 6 described above includes a fourth transistor M4. The first pole and the control electrode of the fourth transistor M4 are connected to the global reset signal input terminal G_R, and the second pole is connected to the second node PD; the conduction level of the fourth transistor is the first level. When the reset signal of the first level is input at the global reset signal input terminal G_R, the fourth transistor M4 sets the second node PD to the first level.

The voltage stabilizing module 7 includes a first capacitor C1. One pole of the first capacitor C1 is connected to the second node PD, and the other pole is connected to the second level DC voltage terminal VGL. It can be seen that when the second node PD is at the first level, the first capacitor C1 is charged, and the first capacitor C1 can keep the second node PD at the first level, thereby keeping the reset module 4 and the reset module 5 open. status.

As an example, as shown in FIG. 6, the input module 1 in the embodiment of the present disclosure includes a fifth transistor M5. The control electrode of the fifth transistor M5 is connected to the scan pulse input terminal Gate_N-1, the first pole is connected to the first level DC voltage terminal VGH, and the second pole is connected to the first node PU. When the scan pulse signal at the scan pulse input terminal Gate_N-1 is at the first level, the fifth transistor M5 turns on the first node and the first level DC voltage terminal VGH, thereby setting the first node PU to the first level. .

It should be noted that the other pole of the first capacitor C1 in the embodiment of the present disclosure may also be connected to the second level DC voltage terminal VGH, the output terminal Gate_N or the first clock signal input terminal CK, so that the first capacitor C1 can also be Achieving the effect of maintaining the second level at the second node PD is achieved.

As a specific example, the output module 2 in the embodiment of the present disclosure includes a sixth transistor M6 and a second capacitor C2. The control electrode of the sixth transistor M6 is connected to the first node PU, the first pole is connected to the first clock signal input terminal CK, and the second pole is connected to the output terminal Gate_N. One pole of the second capacitor C2 is connected to the first node PU, and the other pole is connected to the second level DC voltage terminal VGL. When the first node PU is at the first level, the second capacitor C2 is charged, so that when the first node PU is suspended, the second capacitor C2 can maintain its potential at the first level. In addition, when the first node PU is at the first level, the sixth transistor M6 turns on the first clock signal input terminal CK and the output terminal Gate_N, so that the output terminal Gate_N outputs the first clock signal at the first clock signal input terminal CK. .

It should be noted that the other pole of the second capacitor C2 in the embodiment of the present disclosure may also be connected to the second level DC voltage terminal VGH, the output terminal Gate_N or the first clock signal input terminal CK, so that the second capacitor C2 can also be Achieving the effect of maintaining the second level at the second node PD is achieved.

As a specific example, the reset module 4 includes a seventh transistor M7. The control electrode of the seventh transistor M7 is connected to the second node PD, the first pole is connected to the first node PU, and the second pole is connected to the second level DC voltage terminal VGL. It can be seen that when the second node PD is at the first level, the seventh transistor M7 turns on the first node PU and the second level DC voltage terminal VGL, thereby disposing the first node PU to the second level.

The reset module 5 in the embodiment of the present disclosure includes an eighth transistor M8. The control electrode of the eighth transistor M8 is connected to the second node PD, the first pole is connected to the output terminal Gate_N, and the second pole is connected to the second level DC voltage terminal VGL. It can be seen that when the second node PD is at the first level, the eighth transistor M8 turns on the output terminal Gate_N and the second level DC voltage terminal VGL, thereby disposing the output Gate_N to the second level.

In one embodiment, the first level, the set level may be a high level; the second level may be a low level.

It should be noted that the first transistor M1 to the eighth transistor M8 in the shift register unit shown in FIG. 6 adopt an N-type transistor (when the gate is at a high level, the source and the drain of the transistor are turned on), The active level at its gate is high, the first level. However, in other embodiments of the present invention, the first transistor M1 to the eighth transistor M8 may use a P-type transistor (when the gate is at a low level, the source and the drain of the transistor are turned on, that is, at the gate Instead, the present disclosure does not limit the effective level to a low level, that is, a second level. In addition, the connection between the source and the drain of the transistor can be determined according to the type of transistor selected, and when the transistor has a structure in which the source and the drain are symmetric, the source and the drain can be regarded as two that are not particularly distinguished. Electrodes, which are well known to those skilled in the art, are not described herein.

FIG. 7 is a timing chart showing the operation of the shift register unit circuit according to the embodiment of the present disclosure. The operation of the gate driving circuit shown in FIG. 6 of the embodiment of the present disclosure will be described below with reference to FIG. 7 . See Figure 7:

Phase I: The scan pulse signal at the scan pulse input terminal Gate_N-1 is at a high level, and the fifth transistor M5 is turned on to turn on the first node PU and the first level DC voltage terminal VGH, thereby setting the first node PU to High level. At this stage, the second capacitor C2 is charged, and the first capacitor C1 is discharged. The first node PU is at a high level, and the sixth transistor M6 is turned on to turn on the first clock signal input terminal CK and the output terminal Gate_N. Since the first clock signal input terminal CK is at a low level, the shift register output Gate_N outputs a low level.

Since the scan pulse input terminal Gate_N-1 is at a high level, the second transistor M2 is turned on. Thereby, the second node PD and the first level DC voltage terminal VGL are turned on, thereby setting the second node PD to a low level. At this time, the seventh transistor M7 and the eighth transistor M8 are turned off to ensure voltage stabilization at the first node PU and stabilization of the shift register output signal. The second clock signal at the second clock signal input terminal CKB is at a low level, at which time the first transistor M1 is turned off.

It can be seen that in the first stage, no DC path is formed between the first level DC voltage terminal VGL and the second level DC voltage terminal VGH, so that there is no DC loss.

Phase II: The scan pulse input terminal Gate_N-1 is at a low level, and the second transistor M2 and the fifth transistor are turned off. Since the second capacitor C2 is charged in the first stage, the first node PU is kept at a high level. The sixth transistor M6 continues to be turned on, and the first clock signal at the input terminal CK of the first clock signal is at a high level, and at this time, the output terminal Gate_N outputs a high level.

Since the output terminal Gate_N outputs a high level, the third transistor M3 is turned on, turning on the second node PD and the second voltage DC voltage terminal VGL, setting the second node PD to a low level, and the seventh transistor M7 and the eighth transistor M8 Turn off to ensure voltage stabilization at the first node PU and stabilization of the shift register output signal. The second clock signal at the second clock signal input terminal CKB is at a low level, and the first transistor M1 is turned off.

It can be seen that in the second stage, no DC path is formed between the first level DC voltage terminal VGL and the second level DC voltage terminal VGH, so that there is no DC loss.

Stage III: The scan pulse signal at the scan pulse input Gate_N-1 is at a low level, and the second transistor M2 and the fifth transistor M5 are turned off. The first node PU is at a high level, and the first clock signal at the first clock signal input terminal CK is at a low level, and at this time, the output terminal Gate_N outputs a low level. The third transistor M3 is turned off. The second clock signal at the second clock signal input terminal CKB is at a low level, and at this time, the second node PD is at a low level in the second phase. The first capacitor C1 keeps the second node PD low.

It can be seen that in the third stage, no DC path is formed between the first level DC voltage terminal VGL and the second level DC voltage terminal VGH, so that there is no DC loss.

Stage IV: The second clock input terminal CKB changes to a high level. At this time, the first transistor M1 is turned on, turning on the first level DC voltage terminal VGH and the second node PD, thereby setting the second node PD to be high. Level, while charging the first capacitor C1. The seventh transistor M7 and the eighth transistor M8 are turned on, and the seventh transistor M7 turns on the first node PU and the first level DC voltage terminal VGL to dispose the first node PU to a low level and discharge the second capacitor C2; The eighth transistor M8 turns on the output terminal Gate_N and the first level DC voltage terminal VGL, and sets the output terminal Gate_N to a low level.

It can be seen that in the IV phase, no DC path is formed between the first level DC voltage terminal VGL and the second level DC voltage terminal VGH, so that there is no DC loss.

In any of the above stages, when the global reset signal input terminal G_R inputs a reset pulse, the fourth transistor M4 is turned on, the second node PD is pulled up to a high level, and the seventh transistor M7 and the eighth transistor M8 are simultaneously turned on. And the first node PU and the output Gate_N are set to a low level, thereby realizing resetting of the shift register unit. If the first capacitor C1 is present, the first capacitor C1 maintains a high state at the second node PD, so that the output Gate_N continues to output a low level.

As shown in FIG. 7, in one embodiment of the present disclosure, the scan pulse signal input at the scan pulse input terminal Gate_N-1 is a scan pulse whose effective level is the first level. A first clock signal is input to the first clock signal input terminal CK, and a second clock signal is input to the second clock signal input terminal CKB. The duty ratios of the first level of the first clock signal and the second clock signal are the same; and the width of a first level of the first clock signal and the width of a first level of the second clock signal are both scanned The effective levels in the pulse signal have the same width. As shown in FIG. 7, the start time of an active level of the scan pulse signal is the end time of the first level signal in the second clock signal, and the end time of the active level of the scan pulse signal is the first clock signal. The start time of the first level adjacent to the active level in the scan pulse signal. That is, in a time period as shown in FIG. 7, the effective level of the scan pulse signal is just at a first level signal of the second clock signal CKB and the first level signal immediately following the second clock signal. Between the first level signals of the first clock signal.

Embodiments of the present disclosure utilize a scan pulse signal at a scan pulse input terminal Gate_N-1, a second clock signal at a second clock signal input terminal CKB, a first clock signal at a first clock signal input terminal CK, and a shift The output signal at the output of the register, Gate_N, can form a DC path between the first level DC voltage terminal VGL and the second level DC voltage terminal VGH, thereby alleviating or solving the DC loss of the shift register unit in the prior art. Too big a problem.

In another aspect, the present disclosure also provides a driving method for a shift register unit as described above. See Figure 7, including:

Inputting a scan pulse signal whose active level is the first level at the scan pulse input terminal Gate_N-1; and inputting the first clock signal at the first clock signal input terminal CK and inputting the second clock signal at the second clock signal input terminal CKB . The duty ratio of the first level of the first clock signal and the second clock signal is the same; and the width of the first level of the first clock signal is the same as the first The width of a first level of the two clock signals is the same as the width of the active level in the scan pulse signal; in one time period, the start time of the active level of the scan pulse signal is one of the second clock signals The end time of the first level, the end time is the start time of the first level adjacent to the active level in the scan pulse signal in the first clock signal. Further, a further embodiment of the present disclosure provides a gate driving circuit, as shown in FIG. 8, including a plurality of cascaded shift register units, which are described in the above embodiments. Shift register unit. It should be noted that, for two adjacent shift register units in the gate driving circuit, the first clock signal input terminal CK and the second clock signal input terminal CKB of the previous shift register unit and the subsequent shift register unit The received clock signals are opposite to each other. As shown in FIG. 8, the first clock signal input terminal CK and the second clock signal input terminal CKB of the previous shift register unit respectively receive the first clock signal and the second clock signal, and the first clock of the subsequent shift register unit The signal input terminal CK and the second clock signal input terminal CKB receive the second clock signal and the first clock signal, respectively. However, the two shift register units operate in the same principle and will not be described in detail herein.

A further embodiment of the present disclosure also provides a display device comprising the shift register unit or gate drive circuit of any of the above embodiments. The display device in this embodiment may be any product or component having a display function such as a display panel, an electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator, and the like.

Since the shift register unit provided in the embodiment of the present disclosure is included in both the gate driving circuit and the display device provided by the present disclosure, the same technical effects can be achieved, and details are not described herein again.

Numerous specific details are set forth in the description of the disclosure. However, it is understood that the embodiments of the present disclosure may be practiced without these specific details. In some instances, well-known methods, structures, and techniques are not shown in detail so as not to obscure the understanding of the description.

In the description of the exemplary embodiments of the present disclosure, various features are sometimes grouped together into a single embodiment, figure, Or in the description of it. However, the disclosure should not be interpreted as reflecting the intention that the claimed invention requires more features than those explicitly recited in each claim. Rather, as the claims reflect, the claimed embodiments may be less than all features of a single embodiment described in the specification. Therefore, the claims following the specific embodiments The specific embodiments are hereby expressly incorporated by reference to the claims of the claims

In the description of the present disclosure, the orientation or positional relationship of the terms "upper", "lower" and the like is based on the orientation or positional relationship shown in the drawings, and is merely for convenience of description of the present disclosure and simplified description, rather than indicating or implying The device or component referred to must have a particular orientation, configuration and operation in a particular orientation, and thus is not to be construed as limiting the invention. Unless specifically stated and limited, the terms "mounted," "connected," and "connected" are used in a broad sense and may be, for example, a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection, It can also be an electrical connection; it can be directly connected, or it can be connected indirectly through an intermediate medium, which can be the internal connection of two components. The specific meanings of the above terms in the present disclosure can be understood by those skilled in the art on a case-by-case basis.

It should also be noted that, in this context, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying such entities or operations. There is any such actual relationship or order between them. Furthermore, the term "comprises" or "comprises" or "comprises" or any other variations thereof is intended to encompass a non-exclusive inclusion, such that a process, method, article, or device that comprises a plurality of elements includes not only those elements but also Other elements, or elements that are inherent to such a process, method, item, or device. In the absence of further limitation, an element defined by the phrase "comprising a singular" does not exclude the presence of the same element in the process, method, article, or device.

The above embodiments are only used to illustrate the technical solutions of the embodiments of the present disclosure, and are not intended to be limiting; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that The technical solutions described in the embodiments are modified, or the equivalents of the technical features are replaced by the equivalents of the technical solutions of the embodiments of the present disclosure.

Claims

A shift register unit includes an input module, an output module, a reset module, a reset module, and a second node control module, wherein:

The input module is connected to the scan pulse input end and the first node, and is adapted to set the first node to a first level when the scan pulse signal is at a first level;

The output module is connected to the first node, the first clock signal input end, and the output end of the shift register unit, and is adapted to set the output end to be the first clock when the first node is at the first level Level of the first clock signal input by the signal input terminal, and maintaining the level of the first node when the first node is suspended;

The second node control module is connected to the scan pulse input end, the output end of the shift register unit, the second clock signal input end, the second node, and the first level DC voltage terminal and the second level DC voltage terminal, and is suitable for The second node and the second level DC voltage terminal are turned on when the scan pulse signal is at a first level or the output signal of the output terminal is at a first level, and the scan pulse signal and the When the output signal of the output terminal is the second level and the second clock signal is at the set level, the second node is turned on with the first level DC voltage terminal;

The reset module is connected to the first node and the second node, and is adapted to set the first node to a second level when the second node is at a first level;

The reset module is connected to the second node and the output end, and is adapted to set the output terminal to a second level when the second node is at a first level.
The shift register unit of claim 1, wherein the second node control module comprises a first control unit and a second control unit, wherein:

The first control unit is connected to the second node and the first level DC voltage terminal, and is adapted to: when the second clock signal is at a set level, the second node and the first level DC voltage terminal through;

The second control unit is connected to the scan pulse input end, the output end, the second node and the second level DC voltage terminal, and the scan pulse signal suitable for the scan pulse input end is at a first level Or the second node is electrically connected to the second level DC voltage terminal when the output signal of the output terminal is at the first level.
The shift register unit according to claim 2, wherein said first control unit comprises a first transistor, and said gate of said first transistor is coupled to said second clock signal The first terminal is connected to the second node, and the second pole is connected to the first level DC voltage terminal; the conduction level of the first transistor is the set level.
The shift register unit according to claim 2, wherein said second control unit comprises a second transistor and a third transistor, and said second transistor and said third transistor are electrically connected to a first level;

a control electrode of the second transistor is connected to the scan pulse input end, a first pole is connected to the second node, and a second pole is connected to the second level voltage line;

The control electrode of the third transistor is connected to the output terminal, the first pole is connected to the second node, and the second pole is connected to the second level DC voltage terminal.
The shift register unit of claim 1 further comprising a global reset control module;

The global reset control module is coupled to the first node and the reset signal input end, and is adapted to set the second node to a first level when the reset signal at the reset signal end is at a first level.
The shift register unit according to claim 5, wherein said global reset control module comprises a fourth transistor, said first transistor of said fourth transistor being connected to said control electrode to said reset signal input terminal, said second electrode and said The second node is connected; the conduction level of the fourth transistor is a first level.
The shift register unit of claim 1, further comprising a voltage stabilizing module coupled to said second node for maintaining a level of said second node when said second node is suspended.
The shift register unit according to claim 7, wherein said voltage stabilizing module comprises a first capacitor, one pole of said first capacitor is connected to said second node, and the other pole is connected to said first level DC voltage terminal and One of the second level DC voltage terminals.
The shift register unit according to claim 1, wherein the input module comprises a fifth transistor, a control electrode of the fifth transistor is connected to the scan pulse input terminal, and a first electrode is connected to the first level DC voltage terminal. The second pole is connected to the first node.
The shift register unit of claim 1, wherein the output module comprises a sixth transistor and a second capacitor;

The control electrode of the sixth transistor is connected to the first node, the first pole is connected to the first clock signal input end, and the second pole is connected to the output end;

One pole of the second capacitor is connected to the first node, and the other pole is connected to the first level One of a current voltage terminal and a second level DC voltage terminal.
The shift register unit according to claim 1, wherein said reset module comprises a seventh transistor, said gate of said seventh transistor being connected to said second node, said first pole being connected to said first node, said second pole Connect the second level DC voltage terminal.
The shift register unit according to claim 1, wherein said reset module comprises an eighth transistor, said control electrode of said eighth transistor is connected to said second node, said first electrode is connected to said output terminal, and said second electrode is connected to said second terminal Two-level DC voltage terminal.
The shift register unit according to any one of claims 1 to 12, wherein said first level and said set level are at a high level; and said second level is at a low level.
A driving method for driving a shift register unit according to any one of claims 1 to 13, comprising:

Inputting a scan pulse signal whose active level is a first level at a scan pulse input end; and inputting a first clock signal at a first clock signal input end and a second clock signal at a second clock signal input end;

Wherein the first clock of the first clock signal and the second clock have the same duty ratio; and the width of each of the first clock signals and the first level of the second clock signal The width is the same as the width of the effective level in the scan pulse signal;

The start time of the active level of the scan pulse signal is the end time of a first level of the second clock signal in one time period, and the end time is the valid in the first clock signal and the scan pulse signal. The starting moment of the first level adjacent to the level.
A gate driving circuit comprising a plurality of cascaded shift register units, the shift register unit being a shift register unit according to any one of claims 1 to 13.
A display device comprising the gate drive circuit of claim 15.