WO2016061715A1 - 金属氧化物薄膜晶体管制备方法 - Google Patents

金属氧化物薄膜晶体管制备方法 Download PDF

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WO2016061715A1
WO2016061715A1 PCT/CN2014/000963 CN2014000963W WO2016061715A1 WO 2016061715 A1 WO2016061715 A1 WO 2016061715A1 CN 2014000963 W CN2014000963 W CN 2014000963W WO 2016061715 A1 WO2016061715 A1 WO 2016061715A1
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layer
region
metal
thin film
metal layer
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PCT/CN2014/000963
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French (fr)
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张盛东
邵阳
肖祥
贺鑫
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北京大学深圳研究生院
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Priority to US15/521,246 priority Critical patent/US9991135B2/en
Publication of WO2016061715A1 publication Critical patent/WO2016061715A1/zh

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Definitions

  • the present invention relates to a method of fabricating a transistor, and more particularly to a method of fabricating a metal oxide thin film transistor.
  • Thin film transistors have always been an integrated component of flat panel display switch control elements or peripheral drive circuits.
  • thin film transistors have also been widely studied in the fields of sensors, memories, processors, and the like.
  • Thin film transistors currently widely used in the industry are mainly conventional silicon-based thin film transistors such as amorphous silicon thin film transistors and polysilicon thin film transistors.
  • silicon-based thin film transistors are beginning to fail to meet the increasing demands of flat panel display technology.
  • amorphous silicon thin film transistors there are mainly shortcomings such as low mobility and easy degradation of performance, and are greatly limited in applications such as OLED pixel driving and integration of LCD and OLED peripheral driving circuits.
  • the polysilicon thin film transistor has a high process temperature, high fabrication cost, and poor uniformity of device performance, so it is not suitable for large-size flat panel display applications. Therefore, in order to develop flat panel display technology, metal oxide thin film transistor is a new thin film transistor technology that has been widely studied in recent years.
  • Metal oxide thin film transistors have low process temperature, low process cost, high carrier mobility, and uniform and stable device performance, which not only combine the advantages of both amorphous silicon and polysilicon thin film transistors, but also have visible light transmission.
  • the high rate of over-rate is very promising for the next generation of large-size, high-resolution, high frame rate transparent display.
  • the channel layer material used in the metal oxide thin film transistor mainly includes zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium zinc oxide (GIZO), zinc tin oxide (ZTO), indium zinc oxide (IZO), Indium tin zinc tin (TIZO), tin oxide (SnO 2 ), stannous oxide (SnO), cuprous oxide (Cu 2 O), and the like.
  • the passivation layer is usually a layer that is indispensable after the formation of the channel layer and the source and drain, and the protective layer is isolated from the atmosphere, but the growth conditions of the passivation layer are usually Will affect the electrical characteristics of the device, such as the commonly used plasma enhanced chemical vapor deposition (PECVD) process in the long SiO 2 passivation layer, the back channel is usually subjected to plasma bombardment, the introduction of hydrogen ions, etc., making the channel The layer becomes conductive, the threshold is negatively drifted, the device characteristics are degraded, and leakage is increased. These detrimental effects make the growth conditions of the passivation layer harsh and difficult to grasp.
  • PECVD plasma enhanced chemical vapor deposition
  • the channel layer is a high-resistance layer with a low carrier concentration, and in order to reduce the parasitic resistance, the source and drain portions require an additional low-resistance metal layer process, which increases the complexity of the fabrication process.
  • an object of the present invention is to provide a method for fabricating a metal oxide thin film transistor which can protect the back side of the channel from plasma bombardment and prevent damage to the device characteristics caused by damage to the back channel.
  • Another object is that the method is simple in process and saves production costs.
  • Another object is that in the anodized double-layer metal, the bottom metal is not directly in contact with the solution due to the protection of the upper metal. Therefore, some metals and oxides which are not resistant to acids and alkalis may also be protected by the upper metal. Anode oxidation is achieved.
  • a method for preparing a metal oxide thin film transistor comprising the steps of: 1) selecting a substrate, growing a metal film or a transparent conductive film on the substrate, and then A gate electrode is formed on the metal film or the transparent conductive film by photolithography and etching at the center of the substrate; 2) an insulating medium or a high dielectric constant medium is grown on the substrate and covered on the gate electrode as a gate dielectric 3) forming a layer of 10 to 100 nm thick first metal layer on the gate dielectric layer by DC magnetron sputtering using a metal or alloy target with a purity of ⁇ 99.99% and a sputtering gas pressure of 0.3 Between ⁇ 2.5Pa, the gas is pure argon; 4) a second metal layer of 50-300 nm thick is formed on the first metal layer, and the growth method is also performed by DC magnetron sputtering using metal or alloy The target has a purity of ⁇
  • the region is located at an upper portion of the channel region; then the metal of the channel region and the passivation region is anodized at normal pressure and room temperature, and the anodization causes the first metal layer to be a semiconductor metal oxide layer and the second metal layer to become a metal oxide layer of an insulating medium; the semiconductor metal oxide layer is a channel layer of the thin film transistor, and the metal oxide layer of the insulating medium serves as a passivation layer of the channel layer; 6) the source and drain regions are formed to form a source comprising The active region of the region, the drain region and the channel region; the source region and the drain region are located on both sides of the channel region and are connected to the channel region, and the source region and the drain region are formed by the first metal layer not subjected to anodization and a two-layer metal composition of the two metal layers; 7) depositing a silicon nitride layer on the active region by plasma enhanced chemical vapor deposition or magnetron sputtering, the silicon nitrid
  • the channel region and the passivation region are prepared as follows: a 50 nm thick silicon nitride film is grown on the second metal layer by plasma enhanced chemical vapor deposition. a dielectric protective layer, and coating a photoresist on the dielectric protective layer, performing photolithography and etching on the dielectric protective layer, exposing the passivation region at a position intermediate the second metal layer, the blunt The region on the first metal layer corresponding to the chemical region is the channel region.
  • the channel region and the passivation region are prepared as follows: a 50 nm thick silicon nitride film is grown on the second metal layer by plasma enhanced chemical vapor deposition. a dielectric protective layer, and coating a photoresist on the dielectric protective layer, and then performing pattern exposure and development on the photoresist, opening a window on the dielectric protective layer, but not etching the dielectric protective layer
  • the window region corresponds to a channel region and a passivation region of the transistor.
  • the source region and the drain region are formed by removing the photoresist, and performing photolithography on the dielectric protection layer and the first metal layer and the second metal layer under the dielectric protection layer. And etching to form the source and drain regions.
  • the channel region and the passivation region are prepared as follows: a photoresist is coated on the second metal layer, and then the photoresist is exposed and developed to make the first The passivation region on the two metal layers is exposed, and the region on the first metal layer corresponding to the passivation region is the channel region, and the remaining portion is covered by the photoresist layer to protect.
  • the source region and the drain region are formed by removing the photoresist layer, and performing photolithography and etching on the first metal layer and the second metal layer to form the source. Zone and drain zone.
  • the substrate is made of a high temperature resistant glass substrate or a non-high temperature resistant flexible plastic substrate.
  • the metal thin film is formed by magnetron sputtering or thermal evaporation, and the transparent conductive film is formed by a magnetron sputtering method.
  • a method for growing an insulating medium on the substrate is as follows: a layer of insulating medium is grown on the substrate by a plasma enhanced chemical vapor deposition method; and a substrate is grown on the substrate
  • a method of laminating a high dielectric constant medium is as follows: a layer of high dielectric constant medium is grown on the substrate by magnetron sputtering or anodization.
  • the method for anodizing the metal in the channel region and the passivation region is: an oxidation method using a constant voltage mode after constant current mode oxidation, that is, a current density of 0.01 to 10 mA at a constant current.
  • a constant voltage mode after constant current mode oxidation that is, a current density of 0.01 to 10 mA at a constant current.
  • the present invention has the following advantages due to the above technical solution: 1.
  • the present invention adopts anodization treatment of the first metal layer and the second metal layer, so that the first metal layer becomes a metal oxide layer of the semiconductor, and the second metal The layer becomes a metal oxide layer of an insulating medium.
  • the semiconductor metal oxide layer is a channel layer, and the metal oxide layer of the insulating medium serves as a passivation layer of the channel layer. With this treatment method, the surface of the channel region is protected from plasma bombardment. 2.
  • the present invention is formed because the source and drain regions of the thin film transistor are formed of a double metal of a first metal layer and a second metal layer which are not anodized, and no additional source/drain metal layer process steps are required, thereby simplifying The preparation process of the transistor. 3.
  • the invention is only required to be carried out under normal pressure and room temperature environment, and the operation is simple, and the experimental equipment is simple. Through anodization, not only the channel layer and the passivation layer are formed, but also the source region and the drain region are ensured. Low-resistance metal simplifies the process of the device and saves production costs.
  • the bottom metal is not in direct contact with the solution due to the protection of the upper metal. Therefore, some metals that are not resistant to acids and alkalis and their oxides may also be anodized under the protection of the upper metal.
  • the invention can be widely applied in the field of thin film transistors.
  • Figure 1.1 is a schematic view showing the fabrication of a gate electrode in the first embodiment of the present invention.
  • Figure 1.2 is a schematic view showing the formation of a gate dielectric layer in the first embodiment of the present invention.
  • Figure 1.3 is a schematic view showing the fabrication of a first metal layer in the first embodiment of the present invention.
  • Figure 1.4 is a schematic view showing the fabrication of a second metal layer in the first embodiment of the present invention.
  • Figure 1.5 is a schematic view showing the fabrication of a dielectric protective layer in the first embodiment of the present invention.
  • Figure 1.6 is a schematic view showing the fabrication of a channel region in the first embodiment of the present invention.
  • 1.7 is a lithography and etching of a dielectric protection layer, a first metal layer, and a second metal layer in the first embodiment of the present invention to form an active region including a source region, a drain region, and a channel region, and a channel region.
  • Figure 1.8 is a schematic view showing the fabrication of a passivation layer and a contact hole in the first embodiment of the present invention
  • 1.9 is a schematic cross-sectional view of a metal oxide thin film transistor fabricated in the first embodiment of the present invention.
  • Figure 2.1 is a schematic view showing the fabrication of a gate electrode in the second embodiment of the present invention.
  • Figure 2.2 is a schematic view showing the formation of a gate dielectric layer in the second embodiment of the present invention.
  • Figure 2.3 is a schematic view showing the fabrication of the first metal layer in the second embodiment of the present invention.
  • Figure 2.4 is a schematic view showing the second metal layer in the second embodiment of the present invention.
  • Figure 2.5 is a schematic view showing the fabrication of a dielectric protective layer in the second embodiment of the present invention.
  • 2.6 is a schematic diagram of a channel region formed in Embodiment 2 of the present invention.
  • 2.7 is a lithography and etching of a dielectric protection layer, a first metal layer, and a second metal layer in the second embodiment of the present invention to form an active region including a source region, a drain region, and a channel region, and a channel region.
  • 2.8 is a schematic view showing a passivation layer and a contact hole in the second embodiment of the present invention.
  • 2.9 is a schematic cross-sectional view of a metal oxide thin film transistor fabricated in Embodiment 2 of the present invention.
  • FIG. 3.1 is a schematic view showing a gate electrode fabricated in Embodiment 3 of the present invention.
  • Figure 3.2 is a schematic view showing a gate dielectric layer formed in Embodiment 3 of the present invention.
  • Figure 3.3 is a schematic view showing the fabrication of the first metal layer in the third embodiment of the present invention.
  • 3.4 is a schematic view showing the second metal layer in the third embodiment of the present invention.
  • FIG. 3.5 is a schematic diagram of a channel region formed in Embodiment 3 of the present invention.
  • 3.6 is a schematic diagram showing an active region including a source region, a drain region, and a channel region and a passivation region over the channel region in Embodiment 3 of the present invention
  • 3.7 is a schematic view showing a passivation layer and a contact hole formed in Embodiment 3 of the present invention.
  • Figure 3.8 is a schematic cross-sectional view showing a metal oxide thin film transistor fabricated in Embodiment 3 of the present invention.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • the present invention provides a method for preparing a metal oxide thin film transistor, which simultaneously forms a channel layer and a passivation layer by anodizing a double-layer metal. It specifically includes the following steps:
  • a substrate 1 is selected, and a metal film such as chromium, molybdenum, titanium, tantalum, niobium or aluminum or a transparent conductive film is grown on the substrate 1, and then on the metal film or the transparent conductive film.
  • a gate electrode 2 is formed at a central position of the substrate 1 by photolithography and etching; wherein
  • the metal thin film or the transparent conductive film has a thickness of 100 to 300 nm; the metal thin film is formed by magnetron sputtering or thermal evaporation, and a transparent conductive film such as indium tin oxide (ITO) or the like is formed by a magnetron sputtering method.
  • ITO indium tin oxide
  • an insulating medium or a high-k dielectric is grown on the substrate 1, and is overlaid on the gate electrode 2 as the gate dielectric layer 3;
  • a method of growing an insulating medium on the substrate 1 is as follows: a 100-300 nm thick insulating medium is grown on the substrate 1 by a plasma enhanced chemical vapor deposition (PECVD) method, and the insulating medium is silicon nitride. Or silicon oxide, etc.;
  • PECVD plasma enhanced chemical vapor deposition
  • a method of growing a high dielectric constant medium on the substrate 1 is as follows: a high dielectric constant medium having a thickness of 100 to 300 nm is grown on the substrate 1 by magnetron sputtering or anodization.
  • the electric constant medium is cerium oxide, cerium oxide, aluminum oxide or a laminate composed of cerium oxide, cerium oxide, aluminum oxide and other oxides, etc., that is, the high dielectric constant medium may be a single layer, a double layer or a plurality of layers. Material composition.
  • the growth method may be a DC magnetron sputtering method using a metal or alloy target with a purity of ⁇ 99.99. %, the sputtering pressure is between 0.3 and 2.5 Pa, and the gas is pure argon;
  • the first metal layer 4 is a metal material, and may be a single material or an alloy material. Elemental materials such as indium (In), zinc (Zn), tin (Sn), copper (Cu), nickel (Ni), and titanium (Ti) ), molybdenum (Mo), tungsten (W), etc., alloy materials such as indium tin, zinc titanium, zinc tin, indium zinc tin, and the like.
  • a second metal layer 5 of 50 to 300 nm thick is formed on the first metal layer 4.
  • the growth method is also performed by a DC magnetron sputtering method using a metal or alloy target, and the purity is ⁇ 99.99%, the sputtering pressure is between 0.3 and 2.5 Pa, and the gas is pure argon;
  • the second metal layer 5 is a metal material such as aluminum (Al), titanium (Ti), tantalum (Ta), hafnium (Hf), zirconium (Zr) or the like.
  • a channel region 6 is prepared at a position intermediate the first metal layer 4
  • a passivation region 7 is prepared at a position intermediate the second metal layer 5
  • a passivation region 7 is located at the channel region 6. The upper part.
  • the metal of the channel region 6 and the passivation region 7 is anodized at normal pressure and room temperature, and the anodization causes the first metal layer 4 to become a semiconductor metal oxide layer, and the second metal layer 5 becomes absolutely a metal oxide layer of a rim dielectric;
  • a semiconductor metal oxide layer is a channel layer of the thin film transistor of the present invention, and a metal oxide layer of the insulating medium serves as a passivation layer of the channel layer;
  • the channel region 6 and the passivation region 7 are prepared as follows: a 50 nm thick silicon nitride film is grown as a dielectric protective layer 51 on the second metal layer 5 by plasma enhanced chemical vapor deposition.
  • the protective layer 51 is coated with a photoresist 61, and the dielectric protective layer 51 is photolithographically and etched.
  • the passivation region 7 is exposed at a position intermediate the second metal layer 5, and the passivation region 7 corresponds to the first metal layer 4.
  • the upper region is the channel region 6, and the channel region 6 of the first metal layer 4 and the passivation region 7 of the second metal layer 5 are anodized to oxidize the metal to oxide; the rest is protected by the medium.
  • Layer 51 covers protection;
  • the method for anodizing the metal of the channel region 6 and the passivation region 7 is: a method of oxidizing in a constant voltage mode after first constant current mode oxidation, that is, a current density of 0.01 to 10 mA/cm 2 at a constant current.
  • first constant current mode oxidation that is, a current density of 0.01 to 10 mA/cm 2 at a constant current.
  • the metal oxide semiconductor layer may be indium oxide (In 2 O 3 ), zinc oxide (ZnO), tin oxide (SnO 2 ), stannous oxide (SnO), cuprous oxide (Cu 2 O), or nickel oxide (NiO).
  • titanium oxide (TiO 2 ), molybdenum oxide (MoO 3 ), tungsten oxide (WO 3 ), may also be a binary or multiple combination of the foregoing materials, such as indium tin oxide (InO 2 :Sn, referred to as ITO), indium oxide Zinc (IZO), zinc tin oxide (TZO), indium zinc tin oxide (TIZO), etc.
  • the metal oxide layer of the insulating medium may be aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ) cerium oxide (HfO 2 ) zirconia (ZrO 2 ), etc.;
  • the anodizing treatment used in the present invention is carried out at normal pressure and room temperature, it is a low-temperature process which is simple in operation and low in cost, and is suitable for mass production. Moreover, the variables involved in the anodization process are mainly oxidation voltage and oxidation current, thus improving the controllability and repeatability of the fabrication.
  • the source region 8 and the drain region 9 are formed to form an active region including the source region 8, the drain region 9, and the channel region 6; the source region 8 and the drain region 9 are located on both sides of the channel region 6. And connected to the channel region 6, the source region 8 and the drain region 9 are composed of a double metal of the first metal layer 4 and the second metal layer 5 which are not anodized;
  • the source region 8 and the drain region 9 are formed by removing the photoresist 61, and performing photolithography and etching on the dielectric protective layer 51 and the first metal layer 4 and the second metal layer 5 thereon to form the source region 8 .
  • FIG. 1.8 plasma enhanced chemical vapor deposition or magnetic control is applied to the active region.
  • a silicon nitride layer 10 is deposited by a sputtering method, the silicon nitride layer 10 covers the gate dielectric layer 3, and then photolithography is performed on the silicon nitride layer 10 on the source region 8 side and the drain region 9 side. Etching, forming two contact holes 11, 12 of the electrode; wherein the silicon nitride layer 10 has a thickness of 100 to 300 nm.
  • a metal aluminum film is deposited on the upper surface of the device by magnetron sputtering, and then lithographically and etched to form two metal contact electrodes 11, 12 of the thin film transistor electrode, metal The contact electrodes 11, 12 take out the respective electrodes of the thin film transistor to complete the preparation of the metal oxide thin film transistor; wherein the thickness of the metal aluminum film is 100 to 300 nm.
  • the substrate 1 may be a high temperature resistant substrate or a non-high temperature resistant flexible substrate, a high temperature resistant substrate such as a glass substrate, and a non-high temperature resistant flexible substrate such as a plastic substrate.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • the method for fabricating the metal oxide thin film transistor disclosed in this embodiment is similar to the method disclosed in the first embodiment, and the differences are as follows:
  • the channel region 6 and the passivation region 7 are prepared as follows: a 50 nm thick silicon nitride film is grown as a dielectric protective layer on the second metal layer 5 by plasma enhanced chemical vapor deposition. 51, and coating a photoresist 61 on the dielectric protective layer 51, then performing pattern exposure and development on the photoresist 61, opening a window on the dielectric protective layer 51, but not etching the dielectric protective layer 51, the window region Corresponding to the channel region 6 and the passivation region 7 of the transistor.
  • Embodiment 3 is a diagrammatic representation of Embodiment 3
  • the method for fabricating the metal oxide thin film transistor disclosed in this embodiment is similar to the method disclosed in the first embodiment, and the differences are as follows:
  • the channel region 6 and the passivation region 7 are prepared as follows: a photoresist 61 is coated on the second metal layer 5, and then the photoresist 61 is exposed and developed. The passivation region 7 on the second metal layer 5 is exposed, and the region on the first metal layer 4 corresponding to the passivation region 7 is the channel region 6, and the remaining portion is covered by the photoresist layer.
  • step 6 as shown in FIG. 3.6, the source region 8 and the drain region 9 are formed by removing the photoresist layer 61, and performing photolithography and etching on the first metal layer 4 and the second metal layer 5.
  • An active region including a source region 8, a drain region 9, and a channel region 6.
  • the present invention changes the channel region 6 and the passivation region 7 into a metal oxide by anodizing the channel region 6 and the passivation region 7.
  • the source region 8 and the drain region 9 of the thin film transistor are formed of a metal film which is not anodized, and no additional source/drain metal layer process steps are required, thereby simplifying the fabrication process of the thin film transistor.

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Abstract

提供了一种金属氧化物薄膜晶体管制备方法，其步骤：选取衬底（1），在衬底（1）制作栅电极（2）；在衬底（1）上生长一层绝缘介质或高介电常数介质，并覆盖在栅电极（2）上作为栅介质层（3）；在栅介质层（3）上生成一层第一金属层（4）；在第一金属层（4）上生成一层第二金属层（5）；在第一金属层（4）中间位置上制备沟道区（6），在第二金属层（5）中间位置上制备钝化区（7）；在常压和室温下对沟道区（6）和钝化区（7）的金属进行阳极氧化处理；制作源区（8）和漏区（9），形成包含源区（8）、漏区（9）和沟道区（6）的有源区；源区（8）和漏区（9）由未经过阳极氧化处理的第一金属层（4）和第二金属层（5）的双层金属组成；在有源区上淀积一层氮化硅层，制作电极的两个接触孔；法淀积一层金属铝膜，然后光刻和刻蚀制成两个金属接触电极。所提供的制备方法可以广泛在薄膜晶体管领域中应用。

Description

金属氧化物薄膜晶体管制备方法 技术领域
本发明涉及一种晶体管制备方法，特别是关于一种金属氧化物薄膜晶体管制备方法。
背景技术
薄膜晶体管一直是平板显示开关控制元件或周边驱动电路的集成元件。此外，薄膜晶体管还被广泛研究用于传感器，存储器，处理器等领域。目前被产业界广泛采用的薄膜晶体管主要是传统的硅基薄膜晶体管，如非晶硅薄膜晶体管和多晶硅薄膜晶体管。但是，随着显示技术的不断发展，这些硅基薄膜晶体管开始无法满足人们对平板显示技术越来越高的要求。在非晶硅薄膜晶体管中，主要存在迁移率低和性能易退化等缺点，在OLED像素驱动以及LCD和OLED周边驱动电路集成等方面的应用上受到了很大的限制。而多晶硅薄膜晶体管的工艺温度较高，制作成本高，器件性能的均匀性较差，因此不太适合大尺寸平板显示应用。因此为了平板显示技术的发展，金属氧化物薄膜晶体管就是近几年被广泛研究的一种新型薄膜晶体管技术。
金属氧化物薄膜晶体管具有低的工艺温度，低的工艺成本，高的载流子迁移率以及均匀且稳定的器件性能，不但汇集了非晶硅和多晶硅薄膜晶体管两者的优点，还具有可见光透过率高等优势，非常有希望应用于下一代大尺寸、高分辨率、高帧频透明显示中。金属氧化物薄膜晶体管采用的沟道层材料主要有氧化锌(ZnO)、氧化铟(In2O3)、氧化铟镓锌(GIZO)、氧化锌锡(ZTO)、氧化铟锌(IZO)、氧化铟锌锡(TIZO)、氧化锡(SnO2)，氧化亚锡(SnO)、氧化亚铜(Cu2O)等。
在底栅薄膜晶体管制作工艺中，钝化层通常是在沟道层和源漏形成之后淀积的一层不可缺少的，使沟道与大气隔绝的保护层，但钝化层的生长条件通常会影响器件的电学特性，如常用的等离子体增强化学汽相淀积(PECVD)长SiO2钝化层过程中，背沟道通常会遭受到等离子体的轰击，引入氢离子等，使得沟道层变得导电，阈值往负漂，器件特性退化，漏电增加等。这些有害的影响，使得钝化层的生长条件苛刻而难以把握。因此， 如何生长钝化层成为薄膜晶体管制作中一项需要突破的技术难点。另一方面，沟道层是低载流子浓度的高阻层，而源漏部分为了减小寄生电阻，需要另加一层低阻的金属层工艺，增加了制备工艺的复杂度。
发明内容
针对上述问题，本发明的目的是提供一种金属氧化物薄膜晶体管制备方法，该方法能使沟道背面免受等离子体轰击，避免背沟道造成损伤引起器件特性退化。
另一目的是，该方法工艺简单、节省了生产成本。
另一目的是，在阳极氧化双层金属中，底部金属由于受到上层金属的保护而不与溶液直接接触，因此，一些不耐酸不耐碱的金属及其氧化物也可能在上层金属的保护下实现阳极氧化。
为实现上述目的，本发明采取以下技术方案：一种金属氧化物薄膜晶体管制备方法，其包括以下步骤：1)选取衬底，在衬底上生长一层金属薄膜或者透明导电薄膜，然后在该金属薄膜或透明导电薄膜上采用光刻和刻蚀在衬底中心位置处形成栅电极；2)在衬底上生长一层绝缘介质或高介电常数介质，并覆盖在栅电极上作为栅介质层；3)在栅介质层上生成一层10～100纳米厚第一金属层，该生长方法采用直流磁控溅射的方法，使用金属或者合金靶，纯度≥99.99％，溅射气压为0.3～2.5Pa之间，气体为纯氩气；4)在第一金属层上生成一层50～300纳米厚第二金属层，该生长方法也采用直流磁控溅射的方法，使用金属或者合金靶，纯度≥99.99％，溅射气压为0.3～2.5Pa之间，气体为纯氩气；5)在第一金属层中间位置上制备沟道区，在第二金属层中间位置上制备钝化区，钝化区位于沟道区的上部；然后在常压和室温下对沟道区和钝化区的金属进行阳极氧化处理，阳极氧化使第一金属层为半导体金属氧化层，而使第二金属层成为绝缘介质的金属氧化物层；半导体金属氧化物层为薄膜晶体管的沟道层，而绝缘介质的金属氧化物层成为沟道层的钝化层；6)制作源区和漏区，形成包含源区、漏区和沟道区的有源区；源区及漏区位于沟道区两侧，并与沟道区相连，源区和漏区由未经过阳极氧化处理的第一金属层和第二金属层的双层金属组成；7)在有源区上采用等离子增强化学汽相淀积或磁控溅射方法淀积一层氮化硅层，该氮化硅层覆盖栅介质层，然后在 氮化硅层上位于源区一侧和漏区一侧都采用光刻和刻蚀，形成电极的两个接触孔；8)在整个器件上表面上采用磁控溅射方法淀积一层金属铝膜，然后光刻和刻蚀制成薄膜晶体管电极的两个金属接触电极，两个金属接触电极将薄膜晶体管的各电极引出，完成金属氧化物薄膜晶体管制备。
所述步骤5)中，所述沟道区和钝化区的制备方法如下：在所述第二金属层上采用等离子增强化学汽相淀积方法生长一层50纳米厚的氮化硅薄膜作为介质保护层，并在所述介质保护层上涂覆光刻胶，对所述介质保护层进行光刻和刻蚀，在所述第二金属层中间位置上露出所述钝化区，该钝化区对应的所述第一金属层上的区域即为所述沟道区。
所述步骤5)中，所述沟道区和钝化区的制备方法如下：在所述第二金属层上采用等离子增强化学汽相淀积方法生长一层50纳米厚的氮化硅薄膜作为介质保护层，并在所述介质保护层上涂覆光刻胶，然后对该光刻胶进行图形化曝光和显影，在所述介质保护层上开窗口，但不刻蚀所述介质保护层，该窗口区域对应晶体管的沟道区和钝化区。
所述步骤6)中，所述源区和漏区的制作方法为：去除所述光刻胶，对所述介质保护层和其下的所述第一金属层、第二金属层进行光刻和刻蚀，形成所述源区和漏区。
所述步骤5)中，所述沟道区和钝化区的制备方法如下：在所述第二金属层上涂覆光刻胶，然后对所述光刻胶进行曝光显影，使所述第二金属层上的钝化区露出，该钝化区对应的所述第一金属层上的区域即为沟道区，其余部分被光刻胶层覆盖保护。
所述步骤5)中，所述源区和漏区的制作方法为：去除所述光刻胶层，对所述第一金属层和第二金属层进行光刻和刻蚀，形成所述源区和漏区。
所述步骤1)中，所述衬底采用耐高温的玻璃衬底或非耐高温的柔性塑料衬底。
所述步骤1)中，所述金属薄膜采用磁控溅射或热蒸发方法生成，所述透明导电薄膜由磁控溅射方法生成。
所述步骤2)中，所述衬底上生长一层绝缘介质的方法如下：采用等离子增强化学汽相淀积方法在所述衬底上生长一层绝缘介质；在所述衬底上生长一层高介电常数介质的方法如下：采用磁控溅射或阳极氧化的方法在所述衬底上生长一层高介电常数介质。
所述步骤4)中，对所述沟道区和钝化区的金属进行阳极氧化处理方法为：采用先恒流模式氧化后恒压模式的氧化方法，即恒流时电流密度在0.01～10mA/cm2之间，当电压上升到预定值1～500V时转为恒压模式,在恒压模式下保持一小时左右，此时电流下降到小于0.01mA/cm2，阳极氧化过程完成。
本发明由于采取以上技术方案，其具有以下优点：1、本发明由于采用对第一金属层和第二金属层进行阳极氧化处理，使得第一金属层成为半导体的金属氧化层，而第二金属层成为绝缘介质的金属氧化物层。半导体金属氧化物层为沟道层，而绝缘介质的金属氧化物层成为沟道层的钝化层。采用此处理方法，避免了沟道区表面遭受等离子体的轰击。2、本发明由于薄膜晶体管的源区、漏区是由未进行阳极氧化处理的第一金属层和第二层金属层的双层金属形成，不需另加源漏金属层工艺步骤，因此简化了晶体管的制备工艺。3、本发明由于阳极氧化只需在常压、室温环境下进行，操作简单，实验设备简易，通过阳极氧化，不仅形成了沟道层和钝化层，同时也保证了源区、漏区为低阻的金属，简化了器件的工艺，节省了生产成本。同时，在阳极氧化双层金属中，底部金属由于受到上层金属的保护而不与溶液直接接触。因此，一些不耐酸不耐碱的金属及其氧化物也可能在上层金属的保护下实现阳极氧化。本发明可以广泛在薄膜晶体管领域中应用。
附图说明
图1.1是本发明实施例一中制作栅电极示意图；
图1.2是本发明实施例一中制作栅介质层示意图；
图1.3是本发明实施例一中制作第一金属层示意图；
图1.4是本发明实施例一中制作第二金属层示意图；
图1.5是本发明实施例一中制作介质保护层示意图；
图1.6是本发明实施例一中制作沟道区示意图；
图1.7是本发明实施例一中对介质保护层、第一金属层、第二金属层进行光刻和刻蚀，形成包含源区、漏区和沟道区的有源区以及位于沟道区之上的钝化区的示意图；
图1.8是本发明实施例一中制作钝化层和接触孔示意图；
图1.9是本发明实施例一中制成的金属氧化物薄膜晶体管剖面示意图；
图2.1是本发明实施例二中制作栅电极示意图；
图2.2是本发明实施例二中制作栅介质层示意图；
图2.3是本发明实施例二中制作第一金属层示意图；
图2.4是本发明实施例二中制作第二金属层示意图；
图2.5是本发明实施例二中制作介质保护层示意图；
图2.6是本发明实施例二中制作沟道区示意图；
图2.7是本发明实施例二中对介质保护层、第一金属层、第二金属层进行光刻和刻蚀，形成包含源区、漏区和沟道区的有源区以及位于沟道区之上的钝化区的示意图；
图2.8是本发明实施例二中制作钝化层和接触孔示意图；
图2.9是本发明实施例二中制成的金属氧化物薄膜晶体管剖面示意图；
图3.1是本发明实施例三中制作栅电极示意图；
图3.2是本发明实施例三中制作栅介质层示意图；
图3.3是本发明实施例三中制作第一金属层示意图；
图3.4是本发明实施例三中制作第二金属层示意图；
图3.5是本发明实施例三中制作沟道区示意图；
图3.6是本发明实施例三中制作包含源区、漏区和沟道区的有源区以及位于沟道区之上的钝化区示意图；
图3.7是本发明实施例三中制作钝化层和接触孔示意图；
图3.8是本发明实施例三中制成的金属氧化物薄膜晶体管剖面示意图。
本发明最佳实施方式
下面结合附图和实施例对本发明进行详细的描述。
实施例一：
如图1.1～图1.9所示，本发明提供一种金属氧化物薄膜晶体管制备方法，该方法利用阳极氧化双层金属同时形成沟道层及钝化层。其具体包括以下步骤：
1)如图1.1所示，选取衬底1，在衬底1上生长一层铬、钼、钛、铪、钽或铝等金属薄膜或者透明导电薄膜，然后在该金属薄膜或透明导电薄膜上采用光刻和刻蚀在衬底1中心位置处形成栅电极2；其中，
金属薄膜或者透明导电薄膜的厚度为100～300纳米；金属薄膜采用磁控溅射或热蒸发方法生成，透明导电薄膜例如氧化铟锡(ITO)等，由磁控溅射方法生成。
2)如图1.2所示，在衬底1上生长一层绝缘介质或高介电常数(high-k)介质，并覆盖在栅电极2上作为栅介质层3；其中，
在衬底1上生长一层绝缘介质的方法如下：采用等离子增强化学汽相淀积(PECVD)方法在衬底1上生长一层100～300纳米厚的绝缘介质，该绝缘介质为氮化硅或氧化硅等；
在衬底1上生长一层高介电常数介质的方法如下：采用磁控溅射或阳极氧化的方法在衬底1上生长一层100～300纳米厚的高介电常数介质，该高介电常数介质为氧化铪、氧化钽、氧化铝或由氧化铪、氧化钽、氧化铝及其他氧化物等构成的叠层等，即该高介电常数介质可以是单层、双层或多层材料组成。
3)如图1.3所示，在栅介质层3上生成一层10～100纳米厚第一金属层4，该生长方法可以采用直流磁控溅射的方法，使用金属或者合金靶，纯度≥99.99％，溅射气压为0.3～2.5Pa之间，气体为纯氩气；其中，
第一金属层4为金属材料，可以是单质材料也可以是合金材料，单质材料例如铟(In)、锌(Zn)、锡(Sn)、铜(Cu)、镍(Ni)、钛(Ti)、钼(Mo)、钨(W)等，合金材料例如铟锡、锌钛、锌锡、铟锌锡等。
4)如图1.4所示，在第一金属层4上生成一层50～300纳米厚第二金属层5，该生长方法也采用直流磁控溅射的方法，使用金属或者合金靶，纯度≥99.99％，溅射气压为0.3～2.5Pa之间，气体为纯氩气；其中，
第二金属层5为金属材料，例如铝(Al)、钛(Ti)、钽(Ta)、铪(Hf)、锆(Zr)等。
5)如图1.5和图1.6所示，在第一金属层4中间位置上制备沟道区6，在第二金属层5中间位置上制备钝化区7，钝化区7位于沟道区6的上部。然后在常压和室温下对沟道区6和钝化区7的金属进行阳极氧化处理，阳极氧化使第一金属层4成为半导体金属氧化层，而使第二金属层5成为绝 缘介质的金属氧化物层；半导体金属氧化物层为本发明薄膜晶体管的沟道层，而绝缘介质的金属氧化物层成为沟道层的钝化层；其中，
沟道区6和钝化区7的制备方法如下：在第二金属层5上采用等离子增强化学汽相淀积方法生长一层50纳米厚的氮化硅薄膜作为介质保护层51，并在介质保护层51上涂覆光刻胶61，对介质保护层51进行光刻和刻蚀，在第二金属层5中间位置上露出钝化区7，该钝化区7对应的第一金属层4上的区域即为沟道区6，需对第一金属层4的沟道区6和第二金属层5的钝化区7进行阳极氧化处理，使金属氧化成氧化物；其余部分被介质保护层51覆盖保护；
对沟道区6和钝化区7的金属进行阳极氧化处理方法为：采用先恒流模式氧化后恒压模式的氧化方法，即恒流时电流密度在0.01～10mA/cm2之间，当电压上升到预定值1～500V时转为恒压模式,在恒压模式下保持一小时左右，此时电流下降到小于0.01mA/cm2，阳极氧化过程完成；
金属氧化物半导体层可以为氧化铟(In2O3)、氧化锌(ZnO)、氧化锡(SnO2)、氧化亚锡(SnO)、氧化亚铜(Cu2O)、氧化镍(NiO)、氧化钛(TiO2)、氧化钼(MoO3)、氧化钨(WO3)，也可以为前述材料的二元或多元组合，例如氧化铟锡(InO2:Sn，简称ITO)、氧化铟锌(IZO)、氧化锌锡(TZO)、氧化铟锌锡(TIZO)等；绝缘介质的金属氧化物层可以为氧化铝(Al2O3)，氧化钛(TiO2)、氧化钽(Ta2O5)氧化铪(HfO2)氧化锆(ZrO2)等；
由于本发明采用的阳极氧化处理是在常压和室温下进行，是一种操作简单、低成本的低温工艺，适用于大批量生产。而且阳极氧化过程中涉及的变量主要是氧化电压和氧化电流，因此，提高了制作的可控性和可重复性。
6)如图1.7所示，制作源区8和漏区9，形成包含源区8、漏区9和沟道区6的有源区；源区8及漏区9位于沟道区6两侧，并与沟道区6相连，源区8和漏区9由未经过阳极氧化处理的第一金属层4和第二金属层5的双层金属组成；其中，
源区8和漏区9的制作方法为：去除光刻胶61，对介质保护层51和其下的第一金属层4、第二金属层5进行光刻和刻蚀，形成包含源区8、漏区9和沟道区6的有源区。
7)如图1.8所示，在有源区上采用等离子增强化学汽相淀积或磁控 溅射方法淀积一层氮化硅层10，该氮化硅层10覆盖栅介质层3，然后在氮化硅层10上位于源区8一侧和漏区9一侧都采用光刻和刻蚀，形成电极的两个接触孔11、12；其中，氮化硅层10的厚度为100～300纳米。
8)如图1.9所示，在整个器件上表面上采用磁控溅射方法淀积一层金属铝膜，然后光刻和刻蚀制成薄膜晶体管电极的两个金属接触电极11、12，金属接触电极11、12将薄膜晶体管的各电极引出，完成金属氧化物薄膜晶体管制备；其中，金属铝膜的厚度为100～300纳米。
上述步骤1)中，衬底1可以采用耐高温的衬底或非耐高温的柔性衬底，耐高温的衬底例如玻璃衬底，非耐高温的柔性衬底例如塑料衬底。
实施例二：
如图2.1～2.9所示，本实施例中公开的金属氧化物薄膜晶体管制作方法与实施例一中公开的方法类似，其不同之处如下：
步骤5)中，沟道区6和钝化区7的制备方法如下：在第二金属层5上采用等离子增强化学汽相淀积方法生长一层50纳米厚的氮化硅薄膜作为介质保护层51，并在介质保护层51上涂覆光刻胶61，然后对光刻胶61进行图形化曝光和显影，在介质保护层51上开窗口，但不刻蚀介质保护层51，该窗口区域对应晶体管的沟道区6和钝化区7。
实施例三：
如图3.1～图3.8所示，本实施例中公开的金属氧化物薄膜晶体管制作方法与实施例一中公开的方法类似，其不同之处如下：
步骤5)中，如图3.5所示，沟道区6和钝化区7的制备方法如下：在第二金属层5上涂覆光刻胶61，然后对光刻胶61进行曝光显影，使第二金属层5上的钝化区7露出，钝化区7对应的第一金属层4上的区域即为沟道区6，其余部分被光刻胶层覆盖保护。
步骤6)中，如图3.6所示，源区8和漏区9的制作方法为：去除光刻胶层61，对第一金属层4和第二金属层5进行光刻和刻蚀，形成包含源区8、漏区9和沟道区6的有源区。
上述各实施例中，本发明通过对沟道区6和钝化区7进行阳极氧化处理，使沟道区6和钝化区7变为金属氧化物。薄膜晶体管的源区8、漏区9是由未阳极氧化处理的金属薄膜形成，不需另加源漏金属层工艺步骤，因此简化了薄膜晶体管的制备工艺。
上述各实施例仅用于说明本发明，各部件的连接和结构都是可以有所变化的，在本发明技术方案的基础上，凡根据本发明原理对个别部件的连接和结构进行的改进和等同变换，均不应排除在本发明的保护范围之外。

Claims (10)

  1. 一种金属氧化物薄膜晶体管制备方法，其包括以下步骤：
    1)选取衬底，在衬底上生长一层金属薄膜或者透明导电薄膜，然后在该金属薄膜或透明导电薄膜上采用光刻和刻蚀在衬底中心位置处形成栅电极；
    2)在衬底上生长一层绝缘介质或高介电常数介质，并覆盖在栅电极上作为栅介质层；
    3)在栅介质层上生成一层10～100纳米厚第一金属层，该生长方法采用直流磁控溅射的方法，使用金属或者合金靶，纯度≥99.99％，溅射气压为0.3～2.5Pa之间，气体为纯氩气；
    4)在第一金属层上生成一层50～300纳米厚第二金属层，该生长方法也采用直流磁控溅射的方法，使用金属或者合金靶，纯度≥99.99％，溅射气压为0.3～2.5Pa之间，气体为纯氩气；
    5)在第一金属层中间位置上制备沟道区，在第二金属层中间位置上制备钝化区，钝化区位于沟道区的上部；然后在常压和室温下对沟道区和钝化区的金属进行阳极氧化处理，阳极氧化使第一金属层为半导体金属氧化层，而使第二金属层成为绝缘介质的金属氧化物层；半导体金属氧化物层为薄膜晶体管的沟道层，而绝缘介质的金属氧化物层成为沟道层的钝化层；
    6)制作源区和漏区，形成包含源区、漏区和沟道区的有源区；源区及漏区位于沟道区两侧，并与沟道区相连，源区和漏区由未经过阳极氧化处理的第一金属层和第二金属层的双层金属组成；
    7)在有源区上采用等离子增强化学汽相淀积或磁控溅射方法淀积一层氮化硅层，该氮化硅层覆盖栅介质层，然后在氮化硅层上位于源区一侧和漏区一侧都采用光刻和刻蚀，形成电极的两个接触孔；
    8)在整个器件上表面上采用磁控溅射方法淀积一层金属铝膜，然后光刻和刻蚀制成薄膜晶体管电极的两个金属接触电极，两个金属接触电极将薄膜晶体管的各电极引出，完成金属氧化物薄膜晶体管制备。
  2. 如权利要求1所述的金属氧化物薄膜晶体管制备方法，其特征在于：所述步骤5)中，所述沟道区和钝化区的制备方法如下：在所述第二金属层上采用等离子增强化学汽相淀积方法生长一层50纳米厚的氮化硅 薄膜作为介质保护层，并在所述介质保护层上涂覆光刻胶，对所述介质保护层进行光刻和刻蚀，在所述第二金属层中间位置上露出所述钝化区，该钝化区对应的所述第一金属层上的区域即为所述沟道区。
  3. 如权利要求1所述的金属氧化物薄膜晶体管制备方法，其特征在于：所述步骤5)中，所述沟道区和钝化区的制备方法如下：在所述第二金属层上采用等离子增强化学汽相淀积方法生长一层50纳米厚的氮化硅薄膜作为介质保护层，并在所述介质保护层上涂覆光刻胶，然后对该光刻胶进行图形化曝光和显影，在所述介质保护层上开窗口，但不刻蚀所述介质保护层，该窗口区域对应晶体管的沟道区和钝化区。
  4. 如权利要求2或3所述的金属氧化物薄膜晶体管制备方法，其特征在于：所述步骤6)中，所述源区和漏区的制作方法为：去除所述光刻胶，对所述介质保护层和其下的所述第一金属层、第二金属层进行光刻和刻蚀，形成所述源区和漏区。
  5. 如权利要求1所述的金属氧化物薄膜晶体管制备方法，其特征在于：所述步骤5)中，所述沟道区和钝化区的制备方法如下：在所述第二金属层上涂覆光刻胶，然后对所述光刻胶进行曝光显影，使所述第二金属层上的钝化区露出，该钝化区对应的所述第一金属层上的区域即为沟道区，其余部分被光刻胶层覆盖保护。
  6. 如权利要求5所述的金属氧化物薄膜晶体管制备方法，其特征在于：所述步骤5)中，所述源区和漏区的制作方法为：去除所述光刻胶层，对所述第一金属层和第二金属层进行光刻和刻蚀，形成所述源区和漏区。
  7. 如权利要求1或2或3或5或6所述的金属氧化物薄膜晶体管制备方法，其特征在于：所述步骤1)中，所述衬底采用耐高温的玻璃衬底或非耐高温的柔性塑料衬底。
  8. 如权利要求1或2或3或5或6所述的金属氧化物薄膜晶体管制备方法，其特征在于：所述步骤1)中，所述金属薄膜采用磁控溅射或热蒸发方法生成，所述透明导电薄膜由磁控溅射方法生成。
  9. 如权利要求1或2或3或5或6所述的金属氧化物薄膜晶体管制备方法，其特征在于：所述步骤2)中，所述衬底上生长一层绝缘介质的方法如下：采用等离子增强化学汽相淀积方法在所述衬底上生长一层绝缘介质；
    在所述衬底上生长一层高介电常数介质的方法如下：采用磁控溅射或 阳极氧化的方法在所述衬底上生长一层高介电常数介质。
  10. 如权利要求1或2或3或5或6所述的金属氧化物薄膜晶体管制备方法，其特征在于：所述步骤4)中，对所述沟道区和钝化区的金属进行阳极氧化处理方法为：采用先恒流模式氧化后恒压模式的氧化方法，即恒流时电流密度在0.01～10mA/cm2之间，当电压上升到预定值1～500V时转为恒压模式,在恒压模式下保持一小时左右，此时电流下降到小于0.01mA/cm2，阳极氧化过程完成。
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