WO2016061714A1 - 一种金属氧化物薄膜晶体管制作方法 - Google Patents

一种金属氧化物薄膜晶体管制作方法 Download PDF

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WO2016061714A1
WO2016061714A1 PCT/CN2014/000962 CN2014000962W WO2016061714A1 WO 2016061714 A1 WO2016061714 A1 WO 2016061714A1 CN 2014000962 W CN2014000962 W CN 2014000962W WO 2016061714 A1 WO2016061714 A1 WO 2016061714A1
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layer
metal
thin film
region
film transistor
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PCT/CN2014/000962
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French (fr)
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张盛东
邵阳
肖祥
贺鑫
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北京大学深圳研究生院
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Priority to US15/520,815 priority Critical patent/US9893173B2/en
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Definitions

  • the present invention relates to a method of fabricating a transistor, and more particularly to a method of fabricating a metal oxide thin film transistor.
  • Thin film transistors have always been an integrated component of flat panel display switch control elements or peripheral drive circuits.
  • thin film transistors are also widely studied in the fields of sensors, memories, and processors.
  • Thin film transistors currently widely used in the industry are mainly conventional silicon-based thin film transistors such as amorphous silicon thin film transistors and polysilicon thin film transistors.
  • silicon-based thin film transistors are beginning to fail to meet the increasing demands of flat panel display technology.
  • amorphous silicon thin film transistors there are mainly shortcomings such as low mobility and easy degradation of performance, and are greatly limited in applications such as OLED pixel driving and integration of LCD and OLED peripheral driving circuits.
  • the polysilicon thin film transistor has a high process temperature, high fabrication cost, and poor uniformity of device performance, so it is not suitable for large-size flat panel display applications. Therefore, in order to develop flat panel display technology, metal oxide thin film transistor is a new thin film transistor technology that has been widely studied in recent years.
  • Metal oxide thin film transistors have low process temperature, low process cost, high carrier mobility, and uniform and stable device performance, which not only combine the advantages of both amorphous silicon and polysilicon thin film transistors, but also have visible light transmission.
  • the high rate of over-rate is very promising for the next generation of large-size, high-resolution, high frame rate transparent display.
  • the channel layer material used in the metal oxide thin film transistor mainly includes zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium zinc oxide (GIZO), zinc tin oxide (ZTO), indium zinc oxide (IZO), Indium tin zinc tin (TIZO), tin oxide (SnO 2 ), stannous oxide (SnO), cuprous oxide (Cu 2 O), and the like.
  • a high resistance layer with a low carrier concentration is required for the channel layer, and a low resistance of a high carrier concentration is required in order to reduce parasitic resistance.
  • Layers, metal oxide transistors are different from polysilicon thin film transistors, and the resistance of the source and drain regions cannot be reduced by ion implantation. Therefore, the source and drain require an additional low-resistance metal layer process, which increases the complexity of the fabrication process.
  • an object of the present invention is to provide a method for fabricating a metal oxide thin film transistor by which a channel region is a high resistance metal oxide semiconductor, a source and drain region is a low resistance metal, and a channel region
  • the source and drain regions are formed by a one-step deposition process, which simplifies the fabrication process of the device and saves production costs.
  • a method for fabricating a metal oxide thin film transistor comprising the steps of: 1) selecting a substrate, growing a metal film or a transparent conductive film on the substrate, and then A gate electrode is formed on the metal film or the transparent conductive film by photolithography and etching at the center of the substrate; 2) an insulating medium or a high dielectric constant medium is grown on the substrate and covered on the gate electrode as a gate dielectric 3) A layer of 10 to 100 nm thick metal layer is grown on the gate dielectric layer by DC magnetron sputtering using a metal or alloy target with a purity of ⁇ 99.99% and a sputtering pressure of 0.3 to 2.5.
  • the gas is pure argon; 4) preparing a channel region at a position intermediate the metal layer, and then anodizing the metal in the channel region at normal pressure and room temperature to form a metal oxide semiconductor layer, the metal
  • the oxide semiconductor layer is a channel layer of the metal oxide thin film transistor; 5) forming a source region and a drain region to form an active region including a source region, a drain region, and a channel region; the source region and the drain region are not anodes
  • the metal of the oxidized metal layer is located at both ends of the channel region and connected to the channel region, both on the gate dielectric layer; 6) using a plasma enhanced chemical vapor deposition method or magnetron sputtering on the active region
  • the method deposits a silicon nitride layer, the silicon nitride layer covers the gate dielectric layer, and then lithography and etching are performed on the silicon nitride layer on one side of the source region and the drain region to form two electrodes.
  • the channel region is prepared as follows: a 50 nm thick silicon nitride film is grown on the metal layer by a plasma enhanced chemical vapor deposition method as a dielectric protective layer, and The dielectric protective layer is coated with a photoresist, and the dielectric protective layer is photolithographically and etched, and the exposed portion of the metal layer is the channel region.
  • the channel region is prepared as follows: a 50 nm thick silicon nitride film is grown on the metal layer by a plasma enhanced chemical vapor deposition method as a dielectric protective layer, and Coating a photoresist on the dielectric protective layer, then performing pattern exposure and development on the photoresist, opening a window on the dielectric protective layer, but not etching the dielectric protective layer, The area of the window corresponding to the metal layer is the channel area.
  • the source region and the drain region are formed by photolithography and etching the dielectric protective layer and the underlying metal layer to form the source region and the drain region.
  • the channel region is prepared by coating a photoresist on the metal layer, and then exposing and developing the photoresist to make a channel region on the metal layer. Exposed, the rest is covered by the photoresist.
  • the source region and the drain region are formed by photolithography and etching of the metal layer to form the source region and the drain region.
  • the substrate is made of a high temperature resistant glass substrate or a non-high temperature resistant flexible plastic substrate.
  • the metal thin film is formed by magnetron sputtering or thermal evaporation, and the transparent conductive film is formed by a magnetron sputtering method.
  • a method for growing an insulating medium on the substrate is as follows: a layer of insulating medium is grown on the substrate by a plasma enhanced chemical vapor deposition method; and a substrate is grown on the substrate
  • a method of laminating a high dielectric constant medium is as follows: a layer of high dielectric constant medium is grown on the substrate by magnetron sputtering or anodization.
  • the method for anodizing the metal in the channel region is: a method of oxidizing in a constant voltage mode after first constant current mode oxidation, that is, a current density at a constant current of between 0.01 and 10 mA/cm 2 ,
  • a current density at a constant current of between 0.01 and 10 mA/cm 2
  • the voltage rises to a predetermined value of 1 to 300 V it is switched to the constant voltage mode, and is kept in the constant voltage mode for several hours. At this time, the current drops to less than 0.01 mA/cm 2 , and the anodization process is completed.
  • the present invention has the following advantages due to the above technical solution: 1.
  • the metal layer is anodized, the metal layer is changed into a metal oxide semiconductor layer, and the metal oxide semiconductor layer is a channel layer of the device.
  • the source-drain metal layer process is not required, and the anodizing treatment process only needs to be carried out under normal pressure and room temperature environment, the equipment is cheap, the operation is simple, and the controllability is strong. Therefore, the fabrication process of the transistor is simplified, and the production cost is reduced.
  • the method of fabricating a thin film transistor of the present invention is to form a channel region according to an anodized metal.
  • the channel region is a high resistance metal oxide semiconductor
  • the source and drain regions are low resistance metals, channel regions and sources.
  • the region and the drain region are formed by a one-step deposition process, which simplifies the fabrication process of the device and saves production costs.
  • the invention can be widely applied in the field of thin film transistors.
  • Figure 1.1 is a schematic view showing the fabrication of a gate electrode on a substrate in the first embodiment of the present invention
  • Figure 1.2 is a schematic view showing the formation of a gate dielectric layer in the first embodiment of the present invention.
  • Figure 1.3 is a schematic view showing the fabrication of a metal layer in the first embodiment of the present invention.
  • Figure 1.4 is a schematic view showing the fabrication of a dielectric protective layer in the first embodiment of the present invention.
  • Figure 1.5 is a schematic view showing the fabrication of a channel region in the first embodiment of the present invention.
  • Figure 1.6 is a schematic view showing the source and drain regions in the first embodiment of the present invention.
  • Figure 1.7 is a schematic view showing a contact hole for fabricating an electrode in the first embodiment of the present invention.
  • Figure 1.8 is a schematic cross-sectional view showing a metal oxide thin film transistor formed in Embodiment 1 of the present invention.
  • Figure 2.1 is a schematic view showing the fabrication of a gate electrode on a substrate in the second embodiment of the present invention.
  • Figure 2.2 is a schematic view showing the formation of a gate dielectric layer in the second embodiment of the present invention.
  • Figure 2.3 is a schematic view showing the fabrication of a metal layer in the second embodiment of the present invention.
  • Figure 2.4 is a schematic view showing the fabrication of a dielectric protective layer in the second embodiment of the present invention.
  • Figure 2.5 is a schematic view showing a channel region formed in the second embodiment of the present invention.
  • Figure 2.6 is a schematic view showing the source and drain regions in the second embodiment of the present invention.
  • 2.7 is a schematic view showing a contact hole of an electrode fabricated in Embodiment 2 of the present invention.
  • FIG. 3.1 is a schematic view showing a gate electrode formed on a substrate in Embodiment 3 of the present invention.
  • Figure 3.2 is a schematic view showing a gate dielectric layer formed in Embodiment 3 of the present invention.
  • Figure 3.3 is a schematic view showing the fabrication of a metal layer in the third embodiment of the present invention.
  • 3.4 is a schematic diagram of a channel region formed in Embodiment 3 of the present invention.
  • Figure 3.5 is a schematic view showing the source and drain regions in the third embodiment of the present invention.
  • 3.6 is a schematic view showing a contact hole of an electrode fabricated in Embodiment 3 of the present invention.
  • Figure 3.7 is a schematic cross-sectional view showing a metal oxide thin film transistor formed in Embodiment 3 of the present invention.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • the present invention provides a method for fabricating a metal oxide thin film transistor, which uses anodization to form a metal oxide semiconductor channel layer, thereby producing a metal oxide thin film transistor, which specifically includes the following steps. :
  • the substrate 1 is selected, and a layer of chromium, molybdenum, titanium, tantalum is grown on the substrate 1.
  • a metal film such as tantalum or aluminum or a transparent conductive film, and then forming a gate electrode 2 at a central position of the substrate 1 by photolithography and etching on the metal film or the transparent conductive film; wherein the thickness of the metal film or the transparent conductive film is 100 to 300 nm; a metal film is formed by magnetron sputtering or thermal evaporation, and a transparent conductive film such as indium tin oxide (ITO) is formed by a magnetron sputtering method.
  • ITO indium tin oxide
  • an insulating medium or a high-k dielectric is grown on the substrate 1, and is overlaid on the gate electrode 2 as the gate dielectric layer 3;
  • a method of growing an insulating medium on the substrate 1 is as follows: a 100-300 nm thick insulating medium is grown on the substrate 1 by a plasma enhanced chemical vapor deposition (PECVD) method, and the insulating medium is silicon nitride. Or silicon oxide, etc.;
  • PECVD plasma enhanced chemical vapor deposition
  • a method of growing a high dielectric constant medium on the substrate 1 is as follows: a high dielectric constant medium having a thickness of 100 to 300 nm is grown on the substrate 1 by magnetron sputtering or anodization.
  • the electric constant medium is yttria or yttria or alumina or a laminate composed of yttria, yttria, alumina and other oxides, etc., that is, the high dielectric constant medium may be a single layer, a double layer or a plurality of layers. Material composition.
  • a 10 to 100 nm thick metal layer 4 is grown on the gate dielectric layer 3.
  • the growth method can be performed by DC magnetron sputtering using a metal or alloy target with a purity of ⁇ 99.99%.
  • the sputtering gas pressure is between 0.3 and 2.5 Pa, and the gas is pure argon gas;
  • the metal layer 4 is a metal material, and may be a single material or an alloy material, and a simple material such as indium (In), zinc (Zn), tin (Sn), copper (Cu), nickel (Ni), titanium (Ti), Molybdenum (Mo), tungsten (W), etc., alloy materials such as indium tin, zinc titanium, zinc tin, indium zinc tin, and the like.
  • the channel region 5 is prepared at a position intermediate the metal layer 4, and then the metal of the channel region 5 is anodized at normal pressure and room temperature to form a metal oxide semiconductor layer.
  • the metal oxide semiconductor layer is a channel layer of the transistor of the present invention.
  • the preparation method of the channel region 5 is as follows: a 50 nm thick silicon nitride film is deposited as a dielectric protective layer 41 on the metal layer 4 by a PECVD method, and a photoresist 51 is applied on the dielectric protective layer 41 to the medium.
  • the protective layer 41 is photolithographically and etched, the exposed portion of the metal layer 4 is the channel region 5, and the remaining portion is covered and protected by the dielectric protective layer 41;
  • the method for anodizing the metal of the channel region 5 is: a method of oxidizing in a constant voltage mode after first constant current mode oxidation, that is, a current density of 0.01 to 10 mA/cm 2 at a constant current, when the voltage rises to a predetermined value When it is 1 to 300V, it is changed to the constant voltage mode, and it is kept for several hours in the constant pressure mode. At this time, the current drops to less than 0.01 mA/cm 2 , and the anodization process is completed;
  • the metal oxide semiconductor layer may be indium oxide (In 2 O 3 ), zinc oxide (ZnO), tin oxide (SnO 2 ), stannous oxide (SnO), cuprous oxide (Cu 2 O), or nickel oxide (NiO).
  • titanium oxide (TiO 2 ), molybdenum oxide (MoO 3 ) or tungsten oxide (WO 3 ) may also be a binary or multiple combination of the foregoing materials, such as indium tin oxide (InO 2 :Sn, referred to as ITO), indium oxide Zinc (IZO), zinc tin oxide (TZO) or indium zinc tin oxide (TIZO).
  • the anodizing treatment used in the present invention is carried out at normal pressure and room temperature, it is a low-temperature process which is simple in operation and low in cost, and is suitable for mass production. Moreover, the variables involved in the anodization process are mainly oxidation voltage and oxidation current, thus improving the controllability and repeatability of the fabrication.
  • the source region 6 and the drain region 7 are formed to form an active region including the source region 6, the drain region 7, and the channel region 5; the source region 6 and the drain region 7 are not anodized.
  • the metal of the metal layer 4 is located at both ends of the channel region 5 and is connected to the channel region 5, and is located on the gate dielectric layer 3; wherein the source region 6 and the drain region 7 are formed by: the dielectric protective layer 41 and The underlying metal layer 4 is photolithographically and etched to form source regions 6 and drain regions 7.
  • a silicon nitride layer 8 is deposited on the active region by a PECVD method or a magnetron sputtering method, and the silicon nitride layer 8 covers the gate dielectric layer 3 and then is on the silicon nitride layer. 8 is located on the side of the source region 6 and the side of the drain region 7 by photolithography and etching to form two contact holes 9, 10 of the electrode; wherein the thickness of the silicon nitride layer 8 is 10 to 300 nm.
  • a metal aluminum film is deposited by magnetron sputtering on the upper surface of the entire device, and then lithographically and etched to form two metal contact electrodes 11, 12 of the thin film transistor electrode, in contact.
  • the electrodes 11, 12 lead the respective electrodes of the thin film transistor to complete the preparation of the metal oxide thin film transistor; wherein the thickness of the metal aluminum film is 10 to 300 nm.
  • the substrate 1 may be a high temperature resistant substrate or a non-high temperature resistant flexible substrate, a high temperature resistant substrate such as a glass substrate, and a non-high temperature resistant flexible substrate such as a plastic substrate.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • the method for fabricating the metal oxide thin film transistor disclosed in this embodiment is similar to the method disclosed in the first embodiment, and the differences are as follows:
  • the thickness of the metal thin film or the transparent conductive film is 10 to 300 nm.
  • this embodiment uses a layer of insulation grown on the substrate 1.
  • the dielectric method is: a plasma enhanced chemical vapor deposition (PECVD) method is used to grow a 10 to 300 nm thick insulating medium on the substrate 1, which is silicon nitride or silicon oxide.
  • PECVD plasma enhanced chemical vapor deposition
  • step 4 the preparation method of the channel region 5 is as follows: a 50 nm thick silicon nitride film is grown on the metal layer 4 by a PECVD method as the dielectric protective layer 41, and The dielectric protective layer 41 is coated with a photoresist 51, and then the photoresist 51 is subjected to pattern exposure and development to open a window on the dielectric protective layer 41, but the dielectric protective layer 41 is not etched, and the corresponding metal of the window region is The region on layer 4 is the channel region 5: the region on the metal layer 4 needs to be oxidized to oxidize the metal to an oxide to form the channel region 5.
  • the silicon nitride layer 8 has a thickness of 100 to 300 nm.
  • the thickness of the metal aluminum film is 100 to 300 nm.
  • Embodiment 3 is a diagrammatic representation of Embodiment 3
  • the method for fabricating the metal oxide thin film transistor disclosed in this embodiment is similar to the method disclosed in the first embodiment, and the differences are as follows:
  • the thickness of the metal thin film or the transparent conductive film is 10 to 300 nm.
  • step 2) as shown in FIG. 3.2, the present embodiment adopts a method of growing an insulating medium on the substrate 1 by using a plasma enhanced chemical vapor deposition method to grow a layer of 10 to 300 nm on the substrate 1.
  • a thick insulating medium such as silicon nitride or silicon oxide;
  • a method of growing a high dielectric constant medium on the substrate 1 is as follows: a high dielectric constant medium having a thickness of 10 to 300 nm is grown on the substrate 1 by magnetron sputtering or anodization.
  • the electric constant medium is cerium oxide or cerium oxide or aluminum oxide or a laminate composed of cerium oxide, cerium oxide, aluminum oxide, and other oxides.
  • the channel region 5 is prepared by coating a photoresist 51 on the metal layer 4, and then exposing and developing the photoresist 51 to the metal layer 4. The channel region 5 is exposed, and the remaining portion is covered by the photoresist 51 to protect it.
  • the method for anodizing the metal of the channel region 5 is: a method of oxidizing in a constant voltage mode after first constant current mode oxidation, that is, a current density of 0.01 to 10 mA/cm 2 at a constant current, when the voltage rises to a predetermined value When it is 1 to 300V, it is changed to the constant voltage mode, and it is kept for several hours in the constant pressure mode. At this time, the current drops to less than 0.01 mA/cm 2 , and the anodization process is completed.
  • step 5 as shown in FIG. 3.5, the source region 6 and the drain region 7 are formed by photolithography and etching of the metal layer 4 to form a source region 6 and a drain region 7.
  • the present invention changes the channel region 5 to a low-carrier concentration metal oxide semiconductor high-resistance region by anodizing the channel region 5.
  • the source region 6 and the drain region 7 of the thin film transistor are formed of a metal film which is not anodized, and no additional source/drain metal layer process steps are required, thereby simplifying the fabrication process of the transistor.

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Abstract

一种金属氧化物薄膜晶体管制作方法，其步骤为：选取衬底（1），在衬底上制作栅电极（2）；在衬底上生长一层绝缘介质或高介电常数介质，并覆盖在栅电极上作为栅介质层（3）；在栅介质层上生长一层金属层（4）；在金属层中间位置上制备沟道区（5），在常压和室温下对沟道区的金属进行阳极氧化处理，形成金属氧化物半导体层；制作包含源区（6）、漏区（7）和沟道区的有源区；在有源区上淀积一层氮化硅层（8），在氮化硅层上形成电极的两个接触孔（9、10）；淀积一层金属铝膜，制成薄膜晶体管电极的两个金属接触电极（11、12），完成金属氧化物薄膜晶体管制备。工艺简单、成本低，可以广泛在薄膜晶体管领域中应用。

Description

一种金属氧化物薄膜晶体管制作方法 技术领域
本发明涉及一种晶体管制作方法，特别是关于一种金属氧化物薄膜晶体管制作方法。
背景技术
薄膜晶体管一直是平板显示开关控制元件或周边驱动电路的集成元件。此外，薄膜晶体管还被广泛研究用于传感器、存储器和处理器等领域。目前被产业界广泛采用的薄膜晶体管主要是传统的硅基薄膜晶体管，如非晶硅薄膜晶体管和多晶硅薄膜晶体管。但是，随着显示技术的不断发展，这些硅基薄膜晶体管开始无法满足人们对平板显示技术越来越高的要求。在非晶硅薄膜晶体管中，主要存在迁移率低和性能易退化等缺点，在OLED像素驱动以及LCD和OLED周边驱动电路集成等方面的应用上受到了很大的限制。而多晶硅薄膜晶体管的工艺温度较高，制作成本高，器件性能的均匀性较差，因此不太适合大尺寸平板显示应用。因此为了平板显示技术的发展，金属氧化物薄膜晶体管就是近几年被广泛研究的一种新型薄膜晶体管技术。
金属氧化物薄膜晶体管具有低的工艺温度，低的工艺成本，高的载流子迁移率以及均匀且稳定的器件性能，不但汇集了非晶硅和多晶硅薄膜晶体管两者的优点，还具有可见光透过率高等优势，非常有希望应用于下一代大尺寸、高分辨率、高帧频透明显示中。金属氧化物薄膜晶体管采用的沟道层材料主要有氧化锌(ZnO)、氧化铟(In2O3)、氧化铟镓锌(GIZO)、氧化锌锡(ZTO)、氧化铟锌(IZO)、氧化铟锌锡(TIZO)、氧化锡(SnO2)，氧化亚锡(SnO)、氧化亚铜(Cu2O)等。
在金属氧化物薄膜晶体管制作工艺中，沟道层为了得到合适的阈值电压，需要低载流子浓度的高阻层，而源漏部分为了减小寄生电阻，需要高载流子浓度的低阻层，金属氧化物晶体管不同于多晶硅薄膜晶体管，无法通过离子注入等方式来降低源漏区的电阻，因此源漏需要另加一层低阻的金属层工艺，增加了制备工艺的复杂度。
发明内容
针对上述问题，本发明的目的是提供一种金属氧化物薄膜晶体管制作方法，通过该制作方法能使沟道区为高阻的金属氧化物半导体，源漏区为低阻的金属，沟道区和源漏区由一步淀积工艺形成，简化了器件的制作工艺，节省了生产成本。
为实现上述目的，本发明采取以下技术方案：一种金属氧化物薄膜晶体管制作方法，其包括以下步骤：1)选取衬底，在衬底上生长一层金属薄膜或透明导电薄膜，然后在该金属薄膜或透明导电薄膜上采用光刻和刻蚀在衬底中心位置处形成栅电极；2)在衬底上生长一层绝缘介质或高介电常数介质，并覆盖在栅电极上作为栅介质层；3)在栅介质层上生长一层10～100纳米厚金属层，该生长方法采用直流磁控溅射的方法，使用金属或者合金靶，纯度≥99.99％，溅射气压为0.3～2.5Pa之间，气体为纯氩气；4)在金属层中间位置上制备沟道区，然后在常压和室温下对沟道区的金属进行阳极氧化处理，形成金属氧化物半导体层，该金属氧化物半导体层即为金属氧化物薄膜晶体管的沟道层；5)制作源区和漏区，形成包含源区、漏区和沟道区的有源区；源区及漏区为未经阳极氧化处理的金属层的金属，位于沟道区的两端且与沟道区相连，都位于栅介质层上；6)在有源区上采用等离子增强化学汽相淀积方法或磁控溅射方法淀积一层氮化硅层，该氮化硅层覆盖栅介质层，然后在氮化硅层上位于源区一侧和漏区一侧都采用光刻和刻蚀，形成电极的两个接触孔；7)在整个器件的上表面采用磁控溅射方法淀积一层金属铝膜，然后光刻和刻蚀制成薄膜晶体管电极的两个金属接触电极，两个接触电极将薄膜晶体管的各电极引出，完成金属氧化物薄膜晶体管制备。
所述步骤4)中，所述沟道区的制备方法如下：在所述金属层上采用等离子增强化学汽相淀积方法生长一层50纳米厚的氮化硅薄膜作为介质保护层，并在所述介质保护层上涂覆光刻胶，对所述介质保护层进行光刻和刻蚀，所述金属层暴露在外的部分为所述沟道区。
所述步骤4)中，所述沟道区的制备方法如下：在所述金属层上采用等离子增强化学汽相淀积方法生长一层50纳米厚的氮化硅薄膜作为介质保护层，并在所述介质保护层上涂覆光刻胶，然后对所述光刻胶进行图形化曝光和显影，在所述介质保护层上开窗口，但不刻蚀所述介质保护层， 该窗口区域对应所述金属层上的区域即为所述沟道区。
所述步骤5)中，所述源区和漏区的制作方法为：对所述介质保护层和其下的所述金属层进行光刻和刻蚀，形成所述源区和漏区。
所述步骤4)中，所述沟道区的制备方法如下：在所述金属层上涂覆光刻胶，然后对所述光刻胶进行曝光显影，使所述金属层上的沟道区露出，其余部分被所述光刻胶覆盖保护。
所述步骤5)中，所述源区和漏区的制作方法为：对所述金属层进行光刻和刻蚀，形成所述源区和漏区。
所述步骤1)中，所述衬底采用耐高温的玻璃衬底或非耐高温的柔性塑料衬底。
所述步骤1)中，所述金属薄膜采用磁控溅射或热蒸发方法生成，所述透明导电薄膜由磁控溅射方法生成。
所述步骤2)中，所述衬底上生长一层绝缘介质的方法如下：采用等离子增强化学汽相淀积方法在所述衬底上生长一层绝缘介质；在所述衬底上生长一层高介电常数介质的方法如下：采用磁控溅射或阳极氧化的方法在所述衬底上生长一层高介电常数介质。
所述步骤4)中，对沟道区的金属进行阳极氧化处理方法为：采用先恒流模式氧化后恒压模式的氧化方法，即恒流时电流密度在0.01～10mA/cm2之间，当电压上升到预定值1～300V时转为恒压模式,在恒压模式下保持数小时，此时电流下降到小于0.01mA/cm2，阳极氧化过程完成。
本发明由于采取以上技术方案，其具有以下优点：1、本发明由于采用对金属层进行阳极氧化处理，使金属层变为金属氧化物半导体层，金属氧化物半导体层为器件的沟道层。采用此处理方法，不需要另加源漏金属层工艺，而阳极氧化处理工艺只需在常压、室温环境下进行，设备便宜，操作简单，可控性强。因此简化了晶体管的制备工艺，降低了生产成本。2、本发明的薄膜晶体管制作方法是根据阳极氧化金属形成沟道区，通过这种方法使沟道区为高阻的金属氧化物半导体，源漏区为低阻的金属，沟道区和源区、漏区由一步淀积工艺形成，简化了器件的制作工艺，节省了生产成本。本发明可以广泛在薄膜晶体管领域中应用。
附图说明
图1.1是本发明实施例一中在衬底上制作栅电极示意图；
图1.2是本发明实施例一中制作栅介质层示意图；
图1.3是本发明实施例一中制作金属层示意图；
图1.4是本发明实施例一中制作介质保护层示意图；
图1.5是本发明实施例一中制作沟道区示意图；
图1.6是本发明实施例一中制作源区和漏区示意图；
图1.7是本发明实施例一中制作电极的接触孔示意图；
图1.8是本发明实施例一中制成金属氧化物薄膜晶体管剖面示意图；
图2.1是本发明实施例二中在衬底上制作栅电极示意图；
图2.2是本发明实施例二中制作栅介质层示意图；
图2.3是本发明实施例二中制作金属层示意图；
图2.4是本发明实施例二中制作介质保护层示意图；
图2.5是本发明实施例二中制作沟道区示意图；
图2.6是本发明实施例二中制作源区和漏区示意图；
图2.7是本发明实施例二中制作电极的接触孔示意图；
图2.8是本发明实施例二中制成金属氧化物薄膜晶体管剖面示意图；
图3.1是本发明实施例三中在衬底上制作栅电极示意图；
图3.2是本发明实施例三中制作栅介质层示意图；
图3.3是本发明实施例三中制作金属层示意图；
图3.4是本发明实施例三中制作沟道区示意图；
图3.5是本发明实施例三中制作源区和漏区示意图；
图3.6是本发明实施例三中制作电极的接触孔示意图；
图3.7是本发明实施例三中制成金属氧化物薄膜晶体管剖面示意图。
本发明最佳实施方式
下面结合附图和实施例对本发明进行详细的描述。
实施例一：
如图1.1～图1.8所示，本发明提供一种金属氧化物薄膜晶体管制作方法，该方法利用阳极氧化形成金属氧化物半导体沟道层，进而制得金属氧化物薄膜晶体管，其具体包括以下步骤：
1)如图1.1所示，选取衬底1，在衬底1上生长一层铬、钼、钛、铪、 钽或铝等金属薄膜或者透明导电薄膜，然后在该金属薄膜或透明导电薄膜上采用光刻和刻蚀在衬底1中心位置处形成栅电极2；其中，金属薄膜或者透明导电薄膜的厚度为100～300纳米；金属薄膜采用磁控溅射或热蒸发方法生成，透明导电薄膜例如氧化铟锡(ITO)等，由磁控溅射方法生成。
2)如图1.2所示，在衬底1上生长一层绝缘介质或高介电常数(high-k)介质，并覆盖在栅电极2上作为栅介质层3；其中，
在衬底1上生长一层绝缘介质的方法如下：采用等离子增强化学汽相淀积(PECVD)方法在衬底1上生长一层100～300纳米厚的绝缘介质，该绝缘介质为氮化硅或氧化硅等；
在衬底1上生长一层高介电常数介质的方法如下：采用磁控溅射或阳极氧化的方法在衬底1上生长一层100～300纳米厚的高介电常数介质，该高介电常数介质为氧化铪或氧化钽或氧化铝或由氧化铪、氧化钽、氧化铝及其他氧化物等构成的叠层等，即该高介电常数介质可以是单层、双层或多层材料组成。
3)如图1.3所示，在栅介质层3上生长一层10～100纳米厚金属层4，该生长方法可以采用直流磁控溅射的方法，使用金属或者合金靶，纯度≥99.99％，溅射气压为0.3～2.5Pa之间，气体为纯氩气；其中，
金属层4为金属材料，可以是单质材料也可以是合金材料，单质材料例如铟(In)、锌(Zn)、锡(Sn)、铜(Cu)、镍(Ni)、钛(Ti)、钼(Mo)、钨(W)等，合金材料例如铟锡、锌钛、锌锡、铟锌锡等。
4)如图1.4、图1.5所示，在金属层4中间位置上制备沟道区5，然后在常压和室温下对沟道区5的金属进行阳极氧化处理，形成金属氧化物半导体层，该金属氧化物半导体层即为本发明晶体管的沟道层；其中，
沟道区5的制备方法如下：在金属层4上采用PECVD方法生长一层50纳米厚的氮化硅薄膜作为介质保护层41，并在介质保护层41上涂覆光刻胶51，对介质保护层41进行光刻和刻蚀，金属层4暴露在外的部分为沟道区5，其余部分被介质保护层41覆盖保护；
对沟道区5的金属进行阳极氧化处理方法为：采用先恒流模式氧化后恒压模式的氧化方法，即恒流时电流密度在0.01～10mA/cm2之间，当电压上升到预定值1～300V时转为恒压模式,在恒压模式下保持数小时，此时 电流下降到小于0.01mA/cm2，阳极氧化过程完成；
金属氧化物半导体层可以为氧化铟(In2O3)、氧化锌(ZnO)、氧化锡(SnO2)、氧化亚锡(SnO)、氧化亚铜(Cu2O)、氧化镍(NiO)、氧化钛(TiO2)、氧化钼(MoO3)或氧化钨(WO3)，也可以为前述材料的二元或多元组合，例如氧化铟锡(InO2:Sn，简称ITO)、氧化铟锌(IZO)、氧化锌锡(TZO)或氧化铟锌锡(TIZO)等。
由于本发明采用的阳极氧化处理是在常压和室温下进行，是一种操作简单、低成本的低温工艺，适用于大批量生产。而且阳极氧化过程中涉及的变量主要是氧化电压和氧化电流，因此，提高了制作的可控性和可重复性。
5)如图1.6所示，制作源区6和漏区7，形成包含源区6、漏区7和沟道区5的有源区；源区6及漏区7为未经阳极氧化处理的金属层4的金属，位于沟道区5的两端且与沟道区5相连，都位于栅介质层3上；其中，源区6和漏区7的制作方法为：对介质保护层41和其下的金属层4进行光刻和刻蚀，形成源区6和漏区7。
6)如图1.7所示，在有源区上采用PECVD方法或磁控溅射方法淀积一层氮化硅层8，该氮化硅层8覆盖栅介质层3，然后在氮化硅层8上位于源区6一侧和漏区7一侧都采用光刻和刻蚀，形成电极的两个接触孔9、10；其中，氮化硅层8的厚度为10～300纳米。
7)如图1.8所示，在整个器件的上表面采用磁控溅射方法淀积一层金属铝膜，然后光刻和刻蚀制成薄膜晶体管电极的两个金属接触电极11、12，接触电极11、12将薄膜晶体管的各电极引出，完成金属氧化物薄膜晶体管制备；其中，金属铝膜的厚度为10～300纳米。
上述步骤1)中，衬底1可以采用耐高温的衬底或非耐高温的柔性衬底，耐高温的衬底例如玻璃衬底，非耐高温的柔性衬底例如塑料衬底。
实施例二：
如图2.1～2.8所示，本实施例中公开的金属氧化物薄膜晶体管制作方法与实施例一中公开的方法类似，其不同之处如下：
步骤1)中，如图2.1所示，本实施例采用金属薄膜或者透明导电薄膜的厚度为10～300纳米。
步骤2)中，如图2.2所示，本实施例采用在衬底1上生长一层绝缘 介质的方法为：采用等离子增强化学汽相淀积(PECVD)方法在衬底1上生长一层10～300纳米厚的绝缘介质，该绝缘介质为氮化硅或氧化硅等。
步骤4)中，如图2.4、图2.5所示，沟道区5的制备方法如下：在金属层4上采用PECVD方法生长一层50纳米厚的氮化硅薄膜作为介质保护层41，并在介质保护层41上涂覆光刻胶51，然后对光刻胶51进行图形化曝光和显影，在介质保护层41上开窗口，但不刻蚀介质保护层41，对该窗口区域对应的金属层4上的区域即为沟道区5：需要对金属层4上的区域进行氧化处理，使金属氧化成氧化物，形成沟道区5。
步骤6)中，如图2.7所示，氮化硅层8的厚度为100～300纳米。
步骤7)中，如图2.8所示，金属铝膜的厚度为100～300纳米。
实施例三：
如图3.1～图3.7所示，本实施例中公开的金属氧化物薄膜晶体管制作方法与实施例一中公开的方法类似，其不同之处如下：
步骤1)中，如图3.1所示，本实施例采用金属薄膜或者透明导电薄膜的厚度为10～300纳米。
步骤2)中，如图3.2所示，本实施例采用在衬底1上生长一层绝缘介质的方法为：采用等离子增强化学汽相淀积方法在衬底1上生长一层10～300纳米厚的绝缘介质，该绝缘介质为氮化硅或氧化硅等；
在衬底1上生长一层高介电常数介质的方法如下：采用磁控溅射或阳极氧化的方法在衬底1上生长一层10～300纳米厚的高介电常数介质，该高介电常数介质为氧化铪或氧化钽或氧化铝或由氧化铪、氧化钽、氧化铝及其他氧化物等构成的叠层等。
步骤4)中，如图3.4、图3.5所示，沟道区5的制备方法如下：在金属层4上涂覆光刻胶51，然后对光刻胶51进行曝光显影，使金属层4上的沟道区5露出，其余部分被光刻胶51覆盖保护。对沟道区5的金属进行阳极氧化处理方法为：采用先恒流模式氧化后恒压模式的氧化方法，即恒流时电流密度在0.01～10mA/cm2之间，当电压上升到预定值1～300V时转为恒压模式,在恒压模式下保持数小时，此时电流下降到小于0.01mA/cm2，阳极氧化过程完成。
步骤5)中，如图3.5所示，源区6和漏区7的制作方法为：对金属层4进行光刻和刻蚀，形成源区6和漏区7。
上述各实施例中，本发明通过对沟道区5进行阳极氧化处理，使沟道区5变为低载流子浓度的金属氧化物半导体高阻区。薄膜晶体管的源区6、漏区7是由未阳极氧化处理的金属薄膜形成，不需另加源漏金属层工艺步骤，因此简化了晶体管的制备工艺。
上述各实施例仅用于说明本发明，各部件的连接和结构都是可以有所变化的，在本发明技术方案的基础上，凡根据本发明原理对个别部件的连接和结构进行的改进和等同变换，均不应排除在本发明的保护范围之外。

Claims (10)

  1. 一种金属氧化物薄膜晶体管制作方法，其包括以下步骤：
    1)选取衬底，在衬底上生长一层金属薄膜或透明导电薄膜，然后在该金属薄膜或透明导电薄膜上采用光刻和刻蚀在衬底中心位置处形成栅电极；
    2)在衬底上生长一层绝缘介质或高介电常数介质，并覆盖在栅电极上作为栅介质层；
    3)在栅介质层上生长一层10～100纳米厚金属层，该生长方法采用直流磁控溅射的方法，使用金属或者合金靶，纯度≥99.99％，溅射气压为0.3～2.5Pa之间，气体为纯氩气；
    4)在金属层中间位置上制备沟道区，然后在常压和室温下对沟道区的金属进行阳极氧化处理，形成金属氧化物半导体层，该金属氧化物半导体层即为金属氧化物薄膜晶体管的沟道层；
    5)制作源区和漏区，形成包含源区、漏区和沟道区的有源区；源区及漏区为未经阳极氧化处理的金属层的金属，位于沟道区的两端且与沟道区相连，都位于栅介质层上；
    6)在有源区上采用等离子增强化学汽相淀积方法或磁控溅射方法淀积一层氮化硅层，该氮化硅层覆盖栅介质层，然后在氮化硅层上位于源区一侧和漏区一侧都采用光刻和刻蚀，形成电极的两个接触孔；
    7)在整个器件的上表面采用磁控溅射方法淀积一层金属铝膜，然后光刻和刻蚀制成薄膜晶体管电极的两个金属接触电极，两个接触电极将薄膜晶体管的各电极引出，完成金属氧化物薄膜晶体管制备。
  2. 如权利要求1所述的一种金属氧化物薄膜晶体管制作方法，其特征在于：所述步骤4)中，所述沟道区的制备方法如下：在所述金属层上采用等离子增强化学汽相淀积方法生长一层50纳米厚的氮化硅薄膜作为介质保护层，并在所述介质保护层上涂覆光刻胶，对所述介质保护层进行光刻和刻蚀，所述金属层暴露在外的部分为所述沟道区。
  3. 如权利要求1所述的一种金属氧化物薄膜晶体管制作方法，其特征在于：所述步骤4)中，所述沟道区的制备方法如下：在所述金属层上采用等离子增强化学汽相淀积方法生长一层50纳米厚的氮化硅薄膜作为 介质保护层，并在所述介质保护层上涂覆光刻胶，然后对所述光刻胶进行图形化曝光和显影，在所述介质保护层上开窗口，但不刻蚀所述介质保护层，该窗口区域对应所述金属层上的区域即为所述沟道区。
  4. 如权利要求2或3所述的一种金属氧化物薄膜晶体管制作方法，其特征在于：所述步骤5)中，所述源区和漏区的制作方法为：对所述介质保护层和其下的所述金属层进行光刻和刻蚀，形成所述源区和漏区。
  5. 如权利要求1所述的一种金属氧化物薄膜晶体管制作方法，其特征在于：所述步骤4)中，所述沟道区的制备方法如下：在所述金属层上涂覆光刻胶，然后对所述光刻胶进行曝光显影，使所述金属层上的沟道区露出，其余部分被所述光刻胶覆盖保护。
  6. 如权利要求1或5所述的一种金属氧化物薄膜晶体管制作方法，其特征在于：所述步骤5)中，所述源区和漏区的制作方法为：对所述金属层进行光刻和刻蚀，形成所述源区和漏区。
  7. 如权利要求1或2或3或5所述的一种金属氧化物薄膜晶体管制作方法，其特征在于：所述步骤1)中，所述衬底采用耐高温的玻璃衬底或非耐高温的柔性塑料衬底。
  8. 如权利要求1或2或3或5所述的一种金属氧化物薄膜晶体管制作方法，其特征在于：所述步骤1)中，所述金属薄膜采用磁控溅射或热蒸发方法生成，所述透明导电薄膜由磁控溅射方法生成。
  9. 如权利要求1或2或3或5所述的一种金属氧化物薄膜晶体管制作方法，其特征在于：所述步骤2)中，所述衬底上生长一层绝缘介质的方法如下：采用等离子增强化学汽相淀积方法在所述衬底上生长一层绝缘介质；
    在所述衬底上生长一层高介电常数介质的方法如下：采用磁控溅射或阳极氧化的方法在所述衬底上生长一层高介电常数介质。
  10. 如权利要求1或2或3或5所述的一种金属氧化物薄膜晶体管制作方法，其特征在于：所述步骤4)中，对沟道区的金属进行阳极氧化处理方法为：采用先恒流模式氧化后恒压模式的氧化方法，即恒流时电流密度在0.01～10mA/cm2之间，当电压上升到预定值1～300V时转为恒压模式,在恒压模式下保持数小时，此时电流下降到小于0.01mA/cm2，阳极氧化过程完成。
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