WO2017152488A1 - 薄膜晶体管及其制造方法 - Google Patents

薄膜晶体管及其制造方法 Download PDF

Info

Publication number
WO2017152488A1
WO2017152488A1 PCT/CN2016/081784 CN2016081784W WO2017152488A1 WO 2017152488 A1 WO2017152488 A1 WO 2017152488A1 CN 2016081784 W CN2016081784 W CN 2016081784W WO 2017152488 A1 WO2017152488 A1 WO 2017152488A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
electrode
semiconductor layer
ohmic contact
gate electrode
Prior art date
Application number
PCT/CN2016/081784
Other languages
English (en)
French (fr)
Inventor
李金明
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US15/111,780 priority Critical patent/US20180108780A1/en
Publication of WO2017152488A1 publication Critical patent/WO2017152488A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/42—Bombardment with radiation
    • H01L21/423—Bombardment with radiation with high-energy radiation
    • H01L21/428—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/477—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the present invention relates to the technical field of semiconductor devices, and more particularly to a thin film transistor and a method of fabricating the same.
  • TFTs Thin film transistors
  • LCDs liquid crystal displays
  • OLED organic light emitting diode
  • PD plasma displays
  • EPD electrophoretic displays
  • EWD electrowetting. Display
  • a gate electrode is disposed on a substrate, a gate insulating layer is formed on the gate electrode, and a source electrode, a drain electrode, a semiconductor layer, and a pixel electrode layer are formed over the gate insulating layer, and the pixel electrode passes through the via hole and the drain electrode Extremely connected.
  • a plurality of masks are used and various layers in the TFT are formed by a complicated process. Therefore, the TFT is less efficient and costly to manufacture.
  • the exemplary embodiment provides a TFT having a pixel electrode formed by irradiation with light of a predetermined wavelength.
  • the exemplary embodiment provides a method of manufacturing a TFT capable of simplifying a process and reducing a used mask.
  • a thin film transistor including: a substrate; a gate electrode formed on the substrate; a gate insulating layer formed on the gate electrode; and a semiconductor layer formed on the gate insulating layer And corresponding to the gate electrode; the pixel electrode is disposed on the same layer as the semiconductor layer; the ohmic contact layer is formed on the same layer as the semiconductor layer and formed on the same layer as the pixel electrode; The source electrode and the drain electrode are disposed above the ohmic contact layer.
  • the pixel electrode may be connected to the drain electrode through an ohmic contact layer located under the drain electrode.
  • the ohmic contact layer under the drain electrode may be connected to the semiconductor layer.
  • the gate electrode may be formed of a metal and/or a metal alloy, and the semiconductor layer may be formed of an oxide semiconductor.
  • the thin film transistor may further include a passivation layer.
  • the passivation layer may cover the source electrode, the drain electrode, the semiconductor layer, and the pixel electrode.
  • a method of fabricating a thin film transistor comprising: forming a gate electrode on a substrate; forming a gate insulating layer on the gate electrode; forming a semiconductor layer on the gate insulating layer; Light having a predetermined wavelength is irradiated from the back such that a portion of the semiconductor layer not covered by the gate electrode becomes a pixel electrode and an ohmic contact layer, and a portion of the semiconductor layer that is hidden by the gate electrode maintains semiconductor characteristics; at the pixel electrode and the ohmic contact A source electrode and a drain electrode are formed over the layer.
  • the predetermined wavelength may range from 110 nm to 760 nm.
  • the light may be ultraviolet light.
  • the gate electrode may be formed of a metal and/or a metal alloy, and the semiconductor layer may be formed of an oxide semiconductor.
  • the pixel electrode may be connected to the drain electrode through an ohmic contact layer located under the drain electrode.
  • the ohmic contact layer under the drain electrode may be connected to the semiconductor layer.
  • the method may further include forming a passivation layer to cover the source electrode, the drain electrode, the semiconductor layer, and the pixel electrode.
  • the pixel electrode and the semiconductor layer are formed on the same layer, as compared with the prior art in which two separate masks are required to form the semiconductor layer and the pixel electrode, respectively.
  • the semiconductor layer and the pixel electrode are fabricated using only one mask, thereby reducing the number of masks and simplifying the process.
  • FIG. 1 shows a schematic cross-sectional view of a TFT according to an exemplary embodiment of the present invention.
  • FIGS. 2 to 7 illustrate schematic cross-sectional views of a method of fabricating a TFT according to an exemplary embodiment of the present invention.
  • an element or layer When an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer, the element or layer can be directly on the other element or layer, directly Connecting or joining to another element or layer, or an intermediate element or intermediate layer may be present. However, when an element or layer is referred to as “directly on,” “directly connected,” or “directly connected to” another element or layer, there is no intermediate element or intermediate layer.
  • the term “and/or” as used herein includes any and all combinations of one or more of the associated listed.
  • spatially relative terms such as “under”, “below”, “lower”, “above”, “upper”, etc., may be used herein, and The relationship between one element or feature shown in the other elements or features. Spatially relative terms are intended to encompass different orientations of the device in use or operation. For example, elements in the “following” or “below” other elements or features will be "being" Thus, the exemplary term “below” can include both “in” and “in”. Additionally, the device can be additionally positioned (e.g., rotated 90 degrees or at other orientations), so the spatially relative descriptors used herein are interpreted accordingly.
  • FIG. 1 shows a cross-sectional view of a TFT according to an exemplary embodiment of the present invention.
  • a TFT may include: a substrate 1; a gate electrode 2 formed on the substrate 1; a gate insulating layer 3 formed on the gate electrode 2; and a semiconductor layer 4 formed on the gate On the pole insulating layer 3 and corresponding to the gate electrode 2; the pixel electrode 5 is disposed on the same layer as the semiconductor layer 4; the ohmic contact layer 9 is formed on the same layer as the semiconductor layer 4 and is formed in the same manner as the pixel electrode 5 On the layer; the source electrode 6 and the drain electrode 7 are disposed above the ohmic contact layer 9.
  • the gate electrode 2 may be disposed on a substrate 1 including, for example, plastic, glass, or the like.
  • the substrate 1 can be rigid or flexible.
  • the gate electrode 2 may be formed of a metal and/or a metal alloy.
  • the gate electrode 2 may be made of an aluminum-based metal such as aluminum (Al) or an Al alloy, a silver-based metal (such as silver (Ag) or an Ag alloy), a copper-based metal (such as copper (Cu) or a Cu alloy).
  • the gate electrode 2 may include a multilayer structure including, for example, at least two conductive layers having different physical properties.
  • the gate electrode 2 may be a multilayer structure such as Mo/Al/Mo, Mo/Al, Mo/Cu, CuMn/Cu, and Ti/Cu.
  • the gate electrode 2 may be formed by a suitable process such as physical vapor deposition (PVD) or chemical vapor deposition (CVD).
  • the gate electrode 2 may have a pattern formed by, for example, a yellow light process, an etching process, or the like.
  • a buffer layer (not shown) may be formed on the substrate 1, and the gate electrode 2 may be formed on the buffer layer.
  • the buffer layer can be omitted as needed.
  • the thickness of the gate electrode 2 may be in the range of 2,000 to 5,500 angstroms.
  • a gate insulating layer 3 may be disposed on the gate electrode 2 to cover the gate electrode 2.
  • the gate insulating layer 3 may be a silicon oxide such as (SiO x), silicon nitride (SiN x), a monolayer or multilayer structure of silicon oxynitride (SiON) and the like of any suitable insulating material.
  • the gate insulating layer 3 can be formed by any suitable method such as plasma enhanced chemical vapor deposition (PECVD).
  • PECVD plasma enhanced chemical vapor deposition
  • the thickness of the gate insulating layer 3 may be in the range of 1,500 to 4,000 angstroms.
  • the semiconductor layer 4 may be formed on the gate insulating layer 3, and the position of the semiconductor layer 4 may be aligned with the gate The position of the electrode 2 corresponds.
  • the semiconductor layer 4 may be formed of an oxide semiconductor.
  • the oxide semiconductor may comprise any suitable metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti), etc. or any suitable metal (such as Zn, In, Any suitable oxide of a combination of Ga, Sn, Ti, etc.).
  • the semiconductor layer 4 is formed of indium gallium zinc oxide (IGZO), but is not limited thereto.
  • the semiconductor layer 4 may have a thickness of 400 to 1500 angstroms.
  • the semiconductor layer 4 can be formed by any suitable method such as PVD.
  • the semiconductor layer 4 may have a pattern formed by, for example, a yellow light process, an etching process, or the like.
  • the semiconductor layer 4 may have a pattern which is insulated from the source electrode 6 to be formed and connected to the drain electrode 7 to be formed by patterning, and therefore, the pixel electrode 5 and the source electrode 6 may not be connected by via holes.
  • the pixel electrode 5 may be formed on the same layer as the semiconductor layer 4, and may be formed on the same layer as the ohmic contact layer 9.
  • the ohmic contact layer 9 may be formed on the same layer as the semiconductor layer 4 and the pixel electrode 5.
  • the source electrode 6 and the drain electrode 7 may be formed over the ohmic contact layer 9. As shown in FIG. 1, the source electrode 6 and the drain electrode 7 may be formed on the ohmic contact layers 9 on both sides of the semiconductor layer 4, respectively. For example, the source electrode 6 may be formed over the ohmic contact layer 9 on the left side of the semiconductor layer 4, and the drain electrode 7 may be formed over the ohmic contact layer 9 on the right side of the semiconductor layer 4.
  • the pixel electrode 5 can be connected to the drain electrode 7 through an ohmic contact layer 9 located under the drain electrode 7. An ohmic contact layer 9 located under the drain electrode 7 may be connected to the semiconductor layer 4.
  • the pixel electrode 5 can be insulated from the source electrode 6.
  • Source electrode 6 and drain electrode 7 may be formed of any suitable electrically conductive material, such as Al-based metals, Ag-based metals, Cu-based metals, Mo-based metals, Cr-based metals, Ta-based metals, Ti-based metals. Metal, etc.
  • the source electrode 6 and the drain electrode 7 may be a multilayer structure such as Mo/Al/Mo, Mo/Al, Mo/Cu, CuMn/Cu, and Ti/Cu, but are not limited thereto.
  • the thickness of the source electrode 6 or the drain electrode 7 may be in the range of 200 to 6000 angstroms.
  • the source electrode 6 and the drain electrode 7 may have a pattern formed by, for example, a yellow light process, an etching process, or the like.
  • the TFT according to an exemplary embodiment of the present invention may further include a passivation layer 8.
  • the passivation layer 8 may cover the semiconductor layer 4, the pixel electrode 5, the source electrode 6, and the drain electrode 7.
  • the passivation layer 8 can be formed by, for example, a PECVD process.
  • the passivation layer 8 may be a single layer or a multilayer structure including any suitable material such as SiO x , SiN x , SiON, or the like.
  • the surface of the passivation layer 8 that is in contact with the semiconductor layer 4 may be oxygen-rich SiO x .
  • the thickness of the passivation layer 8 may be in the range of 1,500 to 4,000 angstroms.
  • FIG. 2 to 7 illustrate cross-sectional views of a method of manufacturing the TFT illustrated in Fig. 1 according to an exemplary embodiment of the present invention.
  • a method of manufacturing a TFT according to an exemplary embodiment of the present invention may include: forming a gate electrode 2 (S1) on a substrate 1; forming a gate insulating layer 3 (S2) on the gate electrode 2; on the gate insulating layer 3
  • the semiconductor layer 4 is formed (S3); light having a predetermined wavelength is irradiated from the back such that a portion of the semiconductor layer 4 not covered by the gate electrode becomes the pixel electrode 5 and the ohmic contact layer 9, and the semiconductor layer 4 is covered by the gate electrode
  • the portion retains the semiconductor characteristics (S4); the source electrode 6 and the drain electrode 7 are formed over the pixel electrode 5 and the ohmic contact layer 9 (S5).
  • the gate electrode 2 can be formed on the substrate 1 by a suitable method, and the gate electrode 2 can be patterned by, for example, a yellow light process, an etching process, or the like.
  • the gate electrode 2 can be deposited by a PVD or CVD process.
  • the gate electrode 2 can be formed using a metal and/or a metal alloy.
  • the gate electrode 2 may be made of an aluminum-based metal, a silver-based metal, a copper-based metal, a molybdenum-based metal, a chromium-based metal, a ruthenium-based metal, a titanium-based metal, or the like.
  • the gate electrode 2 may include a multilayer structure including, for example, at least two conductive layers having different physical properties.
  • the gate electrode 2 may be a multilayer structure such as Mo/Al/Mo, Mo/Al, Mo/Cu, CuMn/Cu, and Ti/Cu.
  • a buffer layer (not shown) may be formed on the substrate 1, and then the gate electrode 2 is formed on the buffer layer.
  • the thickness of the gate electrode 2 may be in the range of 2,000 to 5,500 angstroms.
  • a gate insulating layer 3 is formed on the gate electrode 2 to cover the gate electrode 2.
  • the gate insulating layer 3 can be formed by any suitable method such as PECVD.
  • the thickness of the gate insulating layer 3 may be in the range of 1,500 to 4,000 angstroms.
  • the gate insulating layer 3 may be a single layer or a multilayer structure including any suitable insulating material such as SiO x , SiN x , SiON, or the like.
  • a semiconductor layer 4 is formed on the gate insulating layer 3.
  • the semiconductor layer 4 can be deposited by any suitable method such as PVD.
  • the semiconductor layer 4 can be patterned by, for example, a yellow light process, an etching process, or the like.
  • the semiconductor layer 4 may have a pattern which is insulated from the source electrode 6 to be formed and connected to the drain electrode 7 to be formed by patterning, and therefore, the pixel electrode 5 and the source electrode 6 may not be connected by via holes.
  • the semiconductor layer 4 may be formed of an oxide semiconductor.
  • an oxide semiconductor can include Any suitable oxide of any suitable metal (such as Zn, In, Ga, Sn, Ti, etc.) or any suitable metal (such as Zn, In, Ga, Sn, Ti, etc.).
  • the semiconductor layer 4 is formed of IGZO, but is not limited thereto.
  • the semiconductor layer 4 may have a thickness of 400 to 1500 angstroms.
  • step S4 light having a predetermined wavelength is irradiated from the back such that a portion of the semiconductor layer 4 not covered by the gate electrode 2 becomes the pixel electrode 5 and the ohmic contact layer 9, and the gate electrode of the semiconductor layer 4 is The portion of the cover 2 maintains the semiconductor characteristics such that the pixel electrode 5 and the ohmic contact layer 9 can be formed on the same layer as the semiconductor layer 4.
  • the predetermined wavelength may range from 110 nm to 760 nm.
  • the predetermined wavelength ranges from 110 nm to 400 nm, 150 nm to 700 nm, or 200 nm to 450 nm, but is not limited thereto.
  • the light used for the illumination may be ultraviolet (UV) light.
  • the light used for illumination may be visible light.
  • the irradiation time may be 1 to 6 hours, for example, about 4 hours. The smaller the wavelength of the light used for the illumination, the shorter the irradiation time.
  • a carrier concentration and a Hall mobility of an oxide semiconductor such as IGZO can be increased by irradiation, and conductivity is improved, so that the semiconductor layer 4 is The portion not covered by the gate electrode 2 forms the pixel electrode 5 and the ohmic contact layer 9, and the portion of the semiconductor layer 4 that is hidden by the gate electrode 2 still maintains semiconductor characteristics.
  • the gate electrode 2 as a light shielding layer blocks light from being irradiated onto the semiconductor layer 4.
  • the conductivity is improved by 10 9 times, the Hall mobility reaches about 14.6 cm 2 /V, and the carrier concentration is irradiated by UV light. It is about 1.6 ⁇ 10 13 cm -2 and the electric resistance is about 4.6 ⁇ 10 -3 ⁇ ⁇ cm, so that the requirements of the pixel electrode can be satisfied. And after 4 weeks of aging experiments (in the air), there is almost no change in electrical properties, which indicates that UV light irradiation caused irreversible changes.
  • annealing may be performed at a temperature of 100 to 400 ° C after illumination to activate the semiconductor layer 4, thereby reducing defects.
  • a source electrode 6 and a drain electrode 7 are formed over the pixel electrode 5 and the ohmic contact layer 9.
  • the source electrode 6 and the drain electrode 7 may be formed on the ohmic contact layers 9 on both sides of the semiconductor layer 4, respectively.
  • the source electrode 6 may be formed over the ohmic contact layer 9 on the left side of the semiconductor layer 4, and the drain electrode 7 may be formed over the ohmic contact layer 9 on the right side of the semiconductor layer 4.
  • the pixel electrode 5 can be connected to the drain electrode 7 through an ohmic contact layer 9 located under the drain electrode 7.
  • An ohmic contact layer 9 located under the drain electrode 7 may be connected to the semiconductor layer 4.
  • the pixel electrode 5 can be insulated from the source electrode 6.
  • the source electrode 6 and the drain electrode 7 may be formed of any suitable conductive material, such as an Al-based metal, Ag-based metals, Cu-based metals, Mo-based metals, Cr-based metals, Ta-based metals, Ti-based metals, and the like.
  • the source electrode 6 and the drain electrode 7 may be a multilayer structure such as Mo/Al/Mo, Mo/Al, Mo/Cu, CuMn/Cu, and Ti/Cu, but are not limited thereto.
  • the source electrode 6 and the drain electrode 7 may be patterned by a yellow light process, an etching process, or the like.
  • the thickness of the source electrode 6 or the drain electrode 7 may be in the range of 200 to 6000 angstroms.
  • a method of fabricating a TFT according to an exemplary embodiment of the present invention may further include forming a passivation layer 8 (S6).
  • the passivation layer 8 may cover the semiconductor layer 4, the pixel electrode 5, the source electrode 6, and the drain electrode 7.
  • the passivation layer 8 can be formed by, for example, a PECVD process.
  • the passivation layer 8 may be a single layer or a multilayer structure including any suitable material such as SiO x , SiN x , SiON, or the like.
  • the surface of the passivation layer 8 that is in contact with the semiconductor layer 4 may be oxygen-rich SiO x .
  • the thickness of the passivation layer 8 may be in the range of 1,500 to 4,000 angstroms.
  • the pixel electrode and the semiconductor layer are formed on the same layer, as compared with the prior art in which two separate masks are required to form the semiconductor layer and the pixel electrode, respectively.
  • the semiconductor layer and the pixel electrode are fabricated using only one mask, thereby reducing the number of masks and simplifying the process.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

一种薄膜晶体管及其制造方法。所述晶体管包括：基底（1）；栅电极（2），形成在基底上；栅极绝缘层（3），形成在栅电极上；半导体层（4），形成在栅极绝缘层上且与栅电极对应；像素电极（5），与半导体层设置在相同的层上；欧姆接触层（9），与半导体层形成在相同的层上且与像素电极形成在相同的层上；源电极（6）和漏电极（7），设置在欧姆接触层上方。半导体层和像素电极形成在同一层上，可仅使用一道掩模来制造半导体层和像素电极，从而减少掩模的数量并且简化工艺。

Description

薄膜晶体管及其制造方法 技术领域
本发明属于半导体器件的技术领域，更具体地讲，涉及一种薄膜晶体管和制造该薄膜晶体管的方法。
背景技术
随着信息技术的发展，对于例如显示装置的各种电子装置的需求不断增长。薄膜晶体管(TFT)可作为开关和驱动元件应用于各种电子装置，例如，液晶显示器(LCD)、有机发光二极管(OLED)显示器、等离子体显示器(PD)、电泳显示器(EPD)和电润湿显示器(EWD)等。
在传统的TFT中，栅电极设置在基底上，栅极绝缘层形成在栅电极上，源电极、漏电极、半导体层和像素电极层形成在栅极绝缘层上方，像素电极通过通孔与漏电极连接。通常，使用多个掩模(mask)并通过复杂的工艺来形成TFT中的各个层。因此，制造TFT的效率较低且成本较高。
在背景技术部分中公开的以上信息仅为了增强对本发明的背景的理解，因此，它可能包含不构成在本国中本领域普通技术人员已知的现有技术的信息。
发明内容
示例性实施例提供了一种具有利用预定波长的光进行照射而形成的像素电极的TFT。
示例性实施例提供了一种能够简化工艺并减少使用的掩模的TFT的制造方法。
根据本发明的一方面，提供了一种薄膜晶体管，所述薄膜晶体管包括：基底；栅电极，形成在基底上；栅极绝缘层，形成在栅电极上；半导体层，形成在栅极绝缘层上且与栅电极对应；像素电极，与半导体层设置在相同的层上；欧姆接触层，与半导体层形成在相同的层上且与像素电极形成在相同的层上； 源电极和漏电极，设置在欧姆接触层上方。
根据本发明的示例性实施例，像素电极可以通过位于漏电极下方的欧姆接触层与漏电极连接。
根据本发明的示例性实施例，位于漏电极下方的欧姆接触层可以与半导体层连接。
根据本发明的示例性实施例，栅电极可以由金属和/或金属合金形成，半导体层可以由氧化物半导体形成。
根据本发明的示例性实施例，所述薄膜晶体管还可以包括钝化层。钝化层可以覆盖源电极、漏电极、半导体层和像素电极。
根据本发明的另一方面，提供了一种制造薄膜晶体管的方法，所述方法包括：在基底上形成栅电极；在栅电极上形成栅极绝缘层；在栅极绝缘层上形成半导体层；从背部照射具有预定波长的光，使得半导体层的未被栅电极遮住的部分成为像素电极和欧姆接触层，并且半导体层的被栅电极遮住的部分保持半导体特性；在像素电极和欧姆接触层上方形成源电极和漏电极。
根据本发明的示例性实施例，所述预定波长的范围可以为110nm～760nm。
根据本发明的示例性实施例，所述光可以为紫外光。
根据本发明的示例性实施例，栅电极可以由金属和/或金属合金形成，半导体层可以由氧化物半导体形成。
根据本发明的示例性实施例，像素电极可以通过位于漏电极下方的欧姆接触层与漏电极连接。
根据本发明的示例性实施例，位于漏电极下方的欧姆接触层可以与半导体层连接。
根据本发明的示例性实施例，所述方法还可以包括形成钝化层，以覆盖源电极、漏电极、半导体层和像素电极。
根据本发明的示例性实施例的TFT及其制造方法，像素电极和半导体层形成在同一层上，与需要两道单独的掩模来分别形成半导体层和像素电极的现有技术相比，可以仅使用一道掩模来制造半导体层和像素电极，从而减少掩模的数量并且简化工艺。
附图说明
图1示出了根据本发明的示例性实施例的TFT的示意性剖视图。
图2至图7示出了根据本发明的示例性实施例的制造TFT的方法的示意性剖视图。
具体实施方式
将在下文中参照附图更充分地描述示例性实施例，在附图中示出了本发明的示例性实施例。如本领域的技术人员将认识到的，在不脱离本发明的精神或范围的情况下，可以用各种不同方式修改所描述的实施例。
在附图中，为了清晰和描述的目的，可以夸大层、膜、板、区域等的尺寸和相对尺寸。另外，同样的附图标记始终表示同样的元件。
当元件或层被称作“在”另一元件或层“上”、“连接到”或“结合到”另一元件或层时，该元件或层可以直接在另一元件或层上、直接连接或结合到另一元件或层，或者可以存在中间元件或中间层。然而，当元件或层被称作“直接在”另一元件“上”、“直接连接到”或“直接结合到”另一元件或层时，不存在中间元件或中间层。如在这里使用的，术语“和/或”包括一个或多个相关所列项的任意组合和所有组合。
为了描述的目的，在这里可使用空间相对术语，如“在…之下”、“在…下方”、“下”、“在…上方”、“上”等，并由此来描述如在图中所示的一个元件或特征与其它元件或特征的关系。空间相对术语意在包含除了在图中描述的方位之外的装置在使用或操作中的不同方位。例如，如果附图中的装置被翻转，则描述为“在”其它元件或特征“下方”或“之下”的元件随后将被定位为“在”其它元件或特征“上方”。因而，示例性术语“在…下方”可包括“在…上方”和“在…下方”两种方位。另外，所述装置可被另外定位(例如，旋转90度或者在其它方位)，因此对在这里使用的空间相对描述符做出相应的解释。
这里使用的术语仅为了描述特定实施例的目的，而不意图是限制性的。另外，当在本说明书中使用术语“包含”和/或“包括”时，说明存在所述特征、整体、步骤、操作、元件和/或组件，但不排除存在或附加一个或多个其它特征、整体、步骤、操作、元件、组件和/或它们的组。
除非另有定义，否则这里使用的所有术语(包括技术术语和科学术语)具 有与本发明所属领域的普通技术人员所通常理解的意思相同的意思。除非这里明确定义，否则术语(诸如在通用字典中定义的术语)应该被解释为具有与相关领域的环境中它们的意思一致的意思，而将不以理想的或者过于正式的含义来解释它们。
图1示出了根据本发明的示例性实施例的TFT的剖视图。
参照图1，根据本发明的示例性实施例的TFT可以包括：基底1；栅电极2，形成在基底1上；栅极绝缘层3，形成在栅电极2上；半导体层4，形成在栅极绝缘层3上且与栅电极2对应；像素电极5，与半导体层4设置在相同的层上；欧姆接触层9，与半导体层4形成在相同的层上且与像素电极5形成在相同的层上；源电极6和漏电极7，设置在欧姆接触层9上方。
根据本发明的示例性实施例，栅电极2可设置在包括例如塑料、玻璃等的的基底1上。基底1可以是刚性或柔性的。栅电极2可以由金属和/或金属合金形成。例如，栅电极2可以由基于铝的金属(例如铝(Al)或Al合金)、基于银的金属(例如银(Ag)或Ag合金)、基于铜的金属(例如铜(Cu)或Cu合金)、基于钼的金属(例如钼(Mo)或Mo合金)、基于铬的金属(例如铬(Cr)或Cr合金)、基于钽的金属(例如钽(Ta)或Ta合金)、基于钛的金属(例如钛(Ti)或Ti合金)等制成。可选地，栅电极2可以包括多层结构，例如包括物理性质不同的至少两个导电层。例如，栅电极2可以是诸如Mo/Al/Mo、Mo/Al、Mo/Cu、CuMn/Cu和Ti/Cu的多层结构。
根据本发明的示例性实施例，栅电极2可通过合适的工艺形成，例如，物理气相沉积(PVD)或化学气相沉积(CVD)。栅电极2可以具有通过例如黄光工艺、蚀刻工艺等形成的图案。可选地，缓冲层(未示出)可形成在基底1上，并且栅电极2可形成在缓冲层上。根据需要，可以省略缓冲层。栅电极2的厚度可以在2000～5500埃的范围内。
栅极绝缘层3可以设置在栅电极2上以覆盖栅电极2。栅极绝缘层3可以是包括诸如氧化硅(SiOx)、氮化硅(SiNx)、氮氧化硅(SiON)等的任何合适的绝缘材料的单层或多层结构。栅极绝缘层3可以通过例如等离子体增强化学气相沉积(PECVD)的任何合适的方法来形成。栅极绝缘层3的厚度可以在1500～4000埃的范围内。
半导体层4可以形成在栅极绝缘层3上，并且半导体层4的位置可以与栅 电极2的位置对应。例如，半导体层4可以由氧化物半导体形成。例如，氧化物半导体可以包括任何合适的金属(诸如锌(Zn)、铟(In)、镓(Ga)、锡(Sn)、钛(Ti)等)或任何合适的金属(诸如Zn、In、Ga、Sn、Ti等)的组合的任何合适的氧化物。可选地，半导体层4由铟镓锌氧化物(IGZO)形成，但不限于此。半导体层4的厚度可以为400～1500埃。
半导体层4可以通过例如PVD的任何合适的方法形成。半导体层4可以具有通过例如黄光工艺、蚀刻工艺等形成的图案。半导体层4可以通过图案化而具有与将要形成的源电极6绝缘且与将要形成的漏电极7连接的图案，因此，像素电极5与源电极6可以不需要通孔连接。
如图1所示，像素电极5可以与半导体层4形成在同一层上，并且可以与欧姆接触层9形成在同一层上。欧姆接触层9可以与半导体层4和像素电极5形成在同一层上。
根据本发明的示例性实施例，源电极6和漏电极7可以形成在欧姆接触层9上方。如图1所示，源电极6和漏电极7可以分别形成在位于半导体层4的两侧的欧姆接触层9上。例如，源电极6可以形成在位于半导体层4左侧的欧姆接触层9的上方，漏电极7可以形成在位于半导体层4右侧的欧姆接触层9的上方。像素电极5可以通过位于漏电极7下方的欧姆接触层9与漏电极7连接。位于漏电极7下方的欧姆接触层9可以与半导体层4连接。像素电极5可以与源电极6绝缘。
虽然图1中示出了源电极6位于左侧且漏电极7位于右侧，但是源电极6和漏电极7的位置不限于此，例如可以互换。源电极6和漏电极7可以由任何合适的导电材料形成，例如基于Al的金属、基于Ag的金属、基于Cu的金属、基于Mo的金属、基于Cr的金属、基于Ta的金属、基于Ti的金属等。例如，源电极6和漏电极7可以是诸如Mo/Al/Mo、Mo/Al、Mo/Cu、CuMn/Cu和Ti/Cu的多层结构，但不限于此。源电极6或漏电极7的厚度可以在200～6000埃的范围内。源电极6和漏电极7可以具有通过例如黄光工艺、蚀刻工艺等形成的图案。
根据本发明的示例性实施例的TFT还可以包括钝化层8。钝化层8可以覆盖半导体层4、像素电极5、源电极6和漏电极7。钝化层8可以通过例如PECVD工艺形成。钝化层8可以是包括诸如SiOx、SiNx、SiON等的任何合适材料的单层或多层结构。可选地，钝化层8的与半导体层4接触的表面可以是富氧的SiOx。 钝化层8的厚度可以在1500～4000埃的范围内。
以下将参照图2至图7来详细描述根据本发明的示例性实施例的制造TFT的方法。
图2至图7示出了根据本发明的示例性实施例的制造图1中示出的TFT的方法的剖视图。
根据本发明的示例性实施例的制造TFT的方法可以包括：在基底1上形成栅电极2(S1)；在栅电极2上形成栅极绝缘层3(S2)；在栅极绝缘层3上形成半导体层4(S3)；从背部照射具有预定波长的光，使得半导体层4的未被栅电极遮住的部分成为像素电极5和欧姆接触层9，并且半导体层4的被栅电极遮住的部分保持半导体特性(S4)；在像素电极5和欧姆接触层9上方形成源电极6和漏电极7(S5)。
如图2所示，在步骤S1中，可以通过合适的方法在基底1上形成栅电极2，再利用例如黄光工艺、蚀刻工艺等使栅电极2图案化。例如，可以通过PVD或CVD工艺来沉积栅电极2。可以利用金属和/或金属合金形成栅电极2。例如，可以由基于铝的金属、基于银的金属、基于铜的金属、基于钼的金属、基于铬的金属、基于钽的金属、基于钛的金属等制成栅电极2。可选地，栅电极2可以包括多层结构，例如包括物理性质不同的至少两个导电层。例如，栅电极2可以是诸如Mo/Al/Mo、Mo/Al、Mo/Cu、CuMn/Cu和Ti/Cu的多层结构。可选地，可在基底1上形成缓冲层(未示出)，然后在缓冲层上形成栅电极2。栅电极2的厚度可以在2000～5500埃的范围内。
参照图3，在步骤S2中，在栅电极2上形成栅极绝缘层3，以覆盖栅电极2。可以通过例如PECVD的任何合适的方法来形成栅极绝缘层3。栅极绝缘层3的厚度可以在1500～4000埃的范围内。栅极绝缘层3可以是包括诸如SiOx、SiNx、SiON等的任何合适的绝缘材料的单层或多层结构。
参照图4，在步骤S3中，在栅极绝缘层3上形成半导体层4。可以通过例如PVD的任何合适的方法来沉积半导体层4。可以利用例如黄光工艺、蚀刻工艺等使半导体层4图案化。半导体层4可以通过图案化而具有与将要形成的源电极6绝缘且与将要形成的漏电极7连接的图案，因此，像素电极5与源电极6可以不需要通孔连接。
此外，可以由氧化物半导体形成半导体层4。例如，氧化物半导体可以包括 任何合适的金属(诸如Zn、In、Ga、Sn、Ti等)或任何合适的金属(诸如Zn、In、Ga、Sn、Ti等)的组合的任何合适的氧化物。可选地，由IGZO形成半导体层4，但不限于此。半导体层4的厚度可以为400～1500埃。
参照图5，在步骤S4中，从背部照射具有预定波长的光，使得半导体层4的未被栅电极2遮住的部分成为像素电极5和欧姆接触层9，并且半导体层4的被栅电极2遮住的部分保持半导体特性，使得像素电极5和欧姆接触层9可以与半导体层4形成在同一层上。根据本发明的示例性实施例，所述预定波长的范围可以是110nm～760nm。可选地，所述预定波长的范围是110nm～400nm、150nm～700nm或200nm～450nm，但不限于此。优选地，用于照射的光可以是紫外(UV)光。可选地，用于照射的光可以是可见光。根据本发明的示例性实施例，照射的时间可以是1～6小时，例如，大约4小时。用于照射的光的波长越小，照射的时间越短。
根据本发明的示例性实施例，通过照射可以使例如IGZO的氧化物半导体的载流子浓度(carrier concentration)和霍尔迁移率(Hall mobility)增大，并且导电性提高，使得半导体层4的未被栅电极2遮住的部分形成像素电极5和欧姆接触层9，而半导体层4的被栅电极2遮住的部分仍然保持半导体特性。换言之，作为遮光层的栅电极2阻挡了光照射到半导体层4。根据本发明的示例性实施例，在半导体层4由IGZO形成的情况下，经过UV光照射后，导电性提高了109倍，霍尔迁移率达到大约14.6cm2/V，载流子浓度为大约1.6×1013cm-2，电阻为大约4.6×10-3Ω·cm，因而可以满足像素电极的需求。并且经过4周的老化实验(空气中)，电性能基本没有变化，这说明UV光照射造成了不可逆的变化。
根据本发明的示例性实施例，可以在光照之后，在100～400℃的温度下进行退火，使得半导体层4活化，从而可减少缺陷。
如图6所示，在步骤S5中，在像素电极5和欧姆接触层9上方形成源电极6和漏电极7。根据本发明的示例性实施例，可以在位于半导体层4的两侧的欧姆接触层9上分别形成源电极6和漏电极7。例如，可以在位于半导体层4左侧的欧姆接触层9的上方形成源电极6，可以在位于半导体层4右侧的欧姆接触层9的上方形成漏电极7。像素电极5可以通过位于漏电极7下方的欧姆接触层9与漏电极7连接。位于漏电极7下方的欧姆接触层9可以与半导体层4连接。像素电极5可以与源电极6绝缘。
可以由任何合适的导电材料形成源电极6和漏电极7，例如基于Al的金属、 基于Ag的金属、基于Cu的金属、基于Mo的金属、基于Cr的金属、基于Ta的金属、基于Ti的金属等。例如，源电极6和漏电极7可以是诸如Mo/Al/Mo、Mo/Al、Mo/Cu、CuMn/Cu和Ti/Cu的多层结构，但不限于此。可以利用黄光工艺、蚀刻工艺等使源电极6和漏电极7图案化。源电极6或漏电极7的厚度可以在200～6000埃的范围内。
如图7所示，根据本发明的示例性实施例的制造TFT的方法还可以包括形成钝化层8(S6)。钝化层8可以覆盖半导体层4、像素电极5、源电极6和漏电极7。可以通过例如PECVD工艺形成钝化层8。钝化层8可以是包括诸如SiOx、SiNx、SiON等的任何合适材料的单层或多层结构。可选地，钝化层8的与半导体层4接触的表面可以是富氧的SiOx。钝化层8的厚度可以在1500～4000埃的范围内。
根据本发明的示例性实施例的TFT及其制造方法，像素电极和半导体层形成在同一层上，与需要两道单独的掩模来分别形成半导体层和像素电极的现有技术相比，可以仅使用一道掩模来制造半导体层和像素电极，从而减少掩模的数量并且简化工艺。
尽管已经参照其示例性实施例具体显示和描述了本发明，但是本领域的技术人员应该理解，在不脱离权利要求所限定的本发明的精神和范围的情况下，可以对其进行形式和细节上的各种改变。

Claims (10)

  1. 一种薄膜晶体管，其中，所述薄膜晶体管包括：
    基底；
    栅电极，形成在基底上；
    栅极绝缘层，形成在栅电极上；
    半导体层，形成在栅极绝缘层上且与栅电极对应；
    像素电极，与半导体层设置在相同的层上；
    欧姆接触层，与半导体层形成在相同的层上且与像素电极形成在相同的层上；
    源电极和漏电极，设置在欧姆接触层上方。
  2. 根据权利要求1所述的薄膜晶体管，其中，像素电极通过位于漏电极下方的欧姆接触层与漏电极连接。
  3. 根据权利要求2所述的薄膜晶体管，其中，位于漏电极下方的欧姆接触层与半导体层连接。
  4. 根据权利要求1所述的薄膜晶体管，其中，栅电极由金属和/或金属合金形成，半导体层由氧化物半导体形成。
  5. 一种制造薄膜晶体管的方法，其中，所述方法包括：
    在基底上形成栅电极；
    在栅电极上形成栅极绝缘层；
    在栅极绝缘层上形成半导体层；
    从背部照射具有预定波长的光，使得半导体层的未被栅电极遮住的部分成为像素电极和欧姆接触层，并且半导体层的被栅电极遮住的部分保持半导体特性；
    在像素电极和欧姆接触层上方形成源电极和漏电极。
  6. 根据权利要求5所述的方法，其中，所述预定波长的范围为110nm～760nm。
  7. 根据权利要求5所述的方法，其中，所述光为紫外光。
  8. 根据权利要求5所述的方法，其中，栅电极由金属和/或金属合金形成，半导体层由氧化物半导体形成。
  9. 根据权利要求5所述的方法，其中，像素电极通过位于漏电极下方的欧姆接触层与漏电极连接。
  10. 根据权利要求5所述的方法，其中，位于漏电极下方的欧姆接触层与半导体层连接。
PCT/CN2016/081784 2016-03-10 2016-05-12 薄膜晶体管及其制造方法 WO2017152488A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/111,780 US20180108780A1 (en) 2016-03-10 2016-05-12 Thin film transistor and manufacture method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610135630.9 2016-03-10
CN201610135630.9A CN105609563B (zh) 2016-03-10 2016-03-10 薄膜晶体管及其制造方法

Publications (1)

Publication Number Publication Date
WO2017152488A1 true WO2017152488A1 (zh) 2017-09-14

Family

ID=55989332

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/081784 WO2017152488A1 (zh) 2016-03-10 2016-05-12 薄膜晶体管及其制造方法

Country Status (3)

Country Link
US (1) US20180108780A1 (zh)
CN (1) CN105609563B (zh)
WO (1) WO2017152488A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180047551A (ko) * 2016-10-31 2018-05-10 엘지디스플레이 주식회사 액정표시장치
CN106920754A (zh) * 2017-02-17 2017-07-04 深圳市华星光电技术有限公司 一种薄膜晶体管及其制备方法
CN107564922B (zh) * 2017-09-19 2020-03-13 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置
CN107819039A (zh) * 2017-11-09 2018-03-20 深圳市华星光电半导体显示技术有限公司 薄膜晶体管、薄膜晶体管制造方法及液晶显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1627168A (zh) * 2003-12-08 2005-06-15 三星电子株式会社 薄膜晶体管阵列面板及其制造方法
CN101000896A (zh) * 2006-01-13 2007-07-18 中华映管股份有限公司 像素结构及其制造方法
CN101075584A (zh) * 2006-05-19 2007-11-21 三国电子有限会社 使用半色调曝光法的液晶显示装置的制造法
CN101078842A (zh) * 2006-05-23 2007-11-28 京东方科技集团股份有限公司 一种tft lcd阵列基板结构及其制造方法
CN102956691A (zh) * 2011-08-09 2013-03-06 乐金显示有限公司 薄膜晶体管及其制造方法和液晶显示装置及其制造方法
CN104269414A (zh) * 2014-09-25 2015-01-07 合肥京东方光电科技有限公司 一种阵列基板及其制作方法、显示装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101032027B (zh) * 2004-09-02 2010-10-13 卡西欧计算机株式会社 薄膜晶体管及其制造方法
US9048326B2 (en) * 2012-03-02 2015-06-02 Samsung Display Co., Ltd. Thin film transistor substrate and method of manufacturing the same
KR102075530B1 (ko) * 2013-09-11 2020-02-11 삼성디스플레이 주식회사 박막트랜지스터 어레이 기판 및 그 제조방법, 및 이를 포함하는 표시장치

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1627168A (zh) * 2003-12-08 2005-06-15 三星电子株式会社 薄膜晶体管阵列面板及其制造方法
CN101000896A (zh) * 2006-01-13 2007-07-18 中华映管股份有限公司 像素结构及其制造方法
CN101075584A (zh) * 2006-05-19 2007-11-21 三国电子有限会社 使用半色调曝光法的液晶显示装置的制造法
CN101078842A (zh) * 2006-05-23 2007-11-28 京东方科技集团股份有限公司 一种tft lcd阵列基板结构及其制造方法
CN102956691A (zh) * 2011-08-09 2013-03-06 乐金显示有限公司 薄膜晶体管及其制造方法和液晶显示装置及其制造方法
CN104269414A (zh) * 2014-09-25 2015-01-07 合肥京东方光电科技有限公司 一种阵列基板及其制作方法、显示装置

Also Published As

Publication number Publication date
CN105609563A (zh) 2016-05-25
US20180108780A1 (en) 2018-04-19
CN105609563B (zh) 2018-11-23

Similar Documents

Publication Publication Date Title
US10355025B2 (en) Thin film transistor array substrate and manufacturing method thereof
US20170154897A1 (en) Thin film transistor array panel and manufacturing method thereof
KR101814315B1 (ko) 박막 트랜지스터 및 그 제조 방법, 어레이 기판, 및 디스플레이 디바이스
US10043679B2 (en) Method of fabricating array substrate
KR102380647B1 (ko) 박막 트랜지스터 및 그 제조 방법
US9024311B2 (en) Thin film transistor, method for manufacturing same, active matrix substrate, display panel and display device
TWI515852B (zh) 主動元件基板與其之製作方法
JP2008219008A (ja) 薄膜トランジスタ及びその製造方法
WO2017152488A1 (zh) 薄膜晶体管及其制造方法
TW201405833A (zh) 顯示裝置及其製造方法
WO2015000267A1 (zh) 薄膜晶体管及其制作方法、阵列基板及显示器
US20160079285A1 (en) Double thin film transistor and method of manufacturing the same
WO2016061714A1 (zh) 一种金属氧化物薄膜晶体管制作方法
WO2013149463A1 (zh) 导电结构及制造方法、薄膜晶体管、阵列基板和显示装置
JP2013051328A (ja) アクティブマトリックス型表示素子およびその製造方法
US9831350B2 (en) Thin film transistor and method of manufacturing the same
WO2017219412A1 (zh) 顶栅型薄膜晶体管的制作方法
CN110112072B (zh) 阵列基板的制造方法和阵列基板
WO2017088272A1 (zh) 像素结构、阵列基板、液晶显示面板及像素结构制造方法
TW201115744A (en) Thin film transistor, method of manufacturing the thin film transistor and organic light emitting display device having the thin film transistor
US10861956B2 (en) Thin film transistor substrate and related display device
US8853698B1 (en) Oxide semiconductor thin film transistor substrate
KR20110106618A (ko) 박막 트랜지스터의 제조 방법
KR20080069439A (ko) 박막 트랜지스터 기판의 제조 방법

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15111780

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16893136

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 16893136

Country of ref document: EP

Kind code of ref document: A1