WO2015000267A1 - 薄膜晶体管及其制作方法、阵列基板及显示器 - Google Patents

薄膜晶体管及其制作方法、阵列基板及显示器 Download PDF

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Publication number
WO2015000267A1
WO2015000267A1 PCT/CN2013/089287 CN2013089287W WO2015000267A1 WO 2015000267 A1 WO2015000267 A1 WO 2015000267A1 CN 2013089287 W CN2013089287 W CN 2013089287W WO 2015000267 A1 WO2015000267 A1 WO 2015000267A1
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Prior art keywords
layer
drain
source
thin film
film transistor
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PCT/CN2013/089287
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English (en)
French (fr)
Inventor
阎长江
蒋晓纬
姜晓辉
谢振宇
陈旭
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/361,751 priority Critical patent/US10043911B2/en
Publication of WO2015000267A1 publication Critical patent/WO2015000267A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • Embodiments of the present invention relate to a thin film transistor and a method of fabricating the same, an array substrate, and a display. Background technique
  • the thin film transistor includes: a gate electrode 60 formed on a base substrate 10, a gate insulating layer 70, a source electrode 20, The drain 30, the semiconductor active layer 40, and the protective layer 90.
  • the array substrate including the thin film transistor further includes a passivation layer 50 and a pixel electrode 80.
  • the bottom gate type thin film transistor gate 60 can block the illumination of the backlight and prevent the semiconductor active layer 40 from being exposed to light from the backlight to cause leakage current of the thin film transistor.
  • a protective layer 90 is disposed over the semiconductor active layer 40, and the protective layer 90 can avoid active metal oxide semiconductors.
  • the layer 40 is affected by external water and oxygen, and the protective layer 90 in the structure is mostly non-metal, which causes leakage current of the thin film transistor.
  • 2 is a schematic structural view of a top-gate thin film transistor of the prior art.
  • the thin film transistor includes a drain electrode 200, a source electrode 300, an active layer 400, a gate insulating layer 500, and a gate electrode formed on a base substrate 100. 600.
  • the array substrate including the thin film transistor further includes a passivation layer 700 and a pixel electrode 800.
  • the gate 600 can block the influence of external illumination on the semiconductor active layer 400, and the drain 200 and the source 300 are disconnected, and the backlight light can pass through the transparent liner.
  • the base substrate 100 is irradiated to the semiconductor active layer 400, and the semiconductor active layer 400 is in contact with the drain electrode 200 while the semiconductor active layer 400 is in contact with the source electrode 300.
  • the semiconductor active layer 400 is turned on to turn on the drain 200 and the source 300, thereby causing leakage current to the thin film transistor.
  • the top gate type thin film transistor of the prior art is susceptible to a backlight and generates a leakage gram.
  • Embodiments of the present invention provide a thin film transistor, a method for fabricating the same, an array substrate, and a display.
  • the thin film transistor provided by the embodiment of the present invention can prevent the semiconductor active layer from being affected by illumination.
  • the thin film transistor generates a problem of leakage current.
  • a thin film transistor includes a source and a drain, a semiconductor active layer, a gate insulating layer and a gate, and a light shielding layer between the source and the drain, wherein the light shielding layer The source is separated from the drain, and the light shielding layer is located on a side of the semiconductor active layer remote from the gate.
  • An array substrate provided by an embodiment of the invention includes the thin film transistor.
  • a display provided by an embodiment of the invention includes the array substrate.
  • a method for fabricating a thin film transistor includes: fabricating a source, a drain, and a light shielding layer, wherein the light shielding layer is located between the source and the drain, and the source is Separating from the drain; fabricating a semiconductor active layer including both end portions overlapping the source and the drain and an intermediate portion corresponding to the light shielding layer; at the source and the drain A gate insulating layer and a gate are formed over the gate and the semiconductor active layer.
  • the thin film transistor and the manufacturing method thereof, the array substrate and the display of the embodiment of the invention includes a source and a drain, a semiconductor active layer, a gate insulating layer and a gate, and the thin film transistor further The method includes: a light shielding layer between the source and the drain, the light shielding layer blocks the source and the drain, and the light shielding layer is located on the incident light side of the semiconductor active layer, and is configured to block the incident light to the semiconductor active layer
  • the illumination can avoid the problem that the semiconductor active layer is affected by the illumination and cause leakage current of the thin film transistor, and effectively realize the high stability of the thin film transistor.
  • FIG. 1 is a schematic structural view of a bottom gate type thin film transistor in the prior art
  • FIG. 2 is a schematic structural view of a top gate type thin film transistor in the prior art
  • FIG. 3 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention.
  • FIG. 4 to FIG. 12 are respectively schematic structural diagrams of different stages of a thin film transistor in a manufacturing process according to an embodiment of the present invention. detailed description
  • Embodiments of the present invention provide a thin film transistor, a method for fabricating the same, an array substrate, and a display, which are used to prevent a semiconductor active layer from being affected by illumination to cause a leakage current of the thin film transistor.
  • a thin film transistor includes a source and a drain, a semiconductor active layer, a gate insulating layer and a gate, and the thin film transistor further includes: a light shielding layer between the source and the drain, The light shielding layer separates the source from the drain, and the light shielding layer is located on the incident light side of the semiconductor active layer to block the irradiation of the semiconductor active layer by the incident light. That is, the light shielding layer is located on a side of the semiconductor active layer remote from the gate.
  • a thin film transistor includes: a first drain layer 5 and a first source layer 7 on a base substrate 1, and a first drain layer 5 A second drain layer 8 and a second source layer 9, a semiconductor active layer 103, a gate insulating layer 11, and a gate electrode 12 on the first source layer 7.
  • the thin film transistor further includes: a light shielding layer 6 between the first drain layer 5 and the first source layer 7, and the light shielding layer 6 separates the first drain layer 5 from the first source layer 7, the light shielding layer 6 Located under the semiconductor active layer 103, the irradiation of the semiconductor active layer 103 by the incident light is blocked.
  • the array substrate including the thin film transistor further includes a passivation layer 13 and a pixel electrode 15.
  • the material of the light shielding layer 6 is an oxide of a metal titanium or an oxide of a metal aluminum.
  • the source and the drain are a two-layer structure or a multi-layer structure, and the source includes the first a source layer 7 and a second source layer 9; the drain includes a first drain layer 5 and a second drain layer 8.
  • the first source layer 7 and the first drain layer 5 are on the base substrate 1, and the second source layer 9 is on the first source layer 7 and covers the first source layer 7, and the second drain layer 8 is located.
  • the first drain layer 5 is covered on the first drain layer 5 and covers the first drain layer 5.
  • the second drain layer 8 includes a flat lower surface 8a and a sawtooth upper surface 8b which are in contact with the first drain layer 5, and the second source layer 9 includes a flat lower surface 9a which is in contact with the first source layer ⁇ and The serrated upper surface 9b.
  • the second source layer and/or the second drain layer are sawtooth protective layers, the sawtooth upper surface 8b in the second drain layer 8 and the zigzag upper surface 9b in the second source layer 9 It can reflect the outside light.
  • the second source layer 9 including the sawtooth upper surface may also be referred to as a reflective source 9
  • the second drain layer 8 including the sawtooth upper surface may also be referred to as a reflective drain 8
  • a second The specific shape of the drain layer 8 and the second source layer 9 may be directly flat without the need to form a sawtooth upper surface.
  • the specific shapes of the second drain layer 8 and the second source layer 9 may also be other shapes.
  • the material of the first source layer 7 is titanium Ti or aluminum A1 metal
  • the material of the first drain layer 5 is titanium Ti or aluminum A1 metal
  • the resistance of metal titanium or metal aluminum is low, low resistance.
  • the metal can also reduce the line width of the first source layer and the first drain layer while reducing the resistance of the thin film transistor.
  • the material of the second source layer 9 is molybdenum Mo or chromium Cr metal
  • the material of the second drain layer 8 is molybdenum Mo or chromium Cr metal
  • metal molybdenum or metal chromium is a metal that is difficult to oxidize, and is difficult to be oxidized.
  • the metal layer acts as a protective layer to protect the underlying metal from oxidation.
  • the source and the drain may also be designed as a multi-layer structure, and the source includes a first source layer on the bottom layer, a second source layer on the top layer, a first source layer and a second layer.
  • the other source layer between the source layers; the drain includes a first drain layer on the bottom layer, a second drain layer on the top layer, and other drain layers between the first drain layer and the second drain layer.
  • the second drain layer includes a sawtooth upper surface and the second source layer includes a serrated upper surface.
  • the materials of the second source layer and the second drain layer are preferably of a nature that is difficult to be oxidized, such as molybdenum Mo or chromium Cr, to protect other source layers and other drain layers located underneath.
  • the first source layer and other source layer materials are preferably metals having a low resistivity such as titanium Ti or aluminum Al.
  • the first drain layer and other drain layer materials are preferably metals having a low resistivity such as titanium Ti or aluminum Al.
  • the sawtooth upper surface of the second drain layer and the sawtooth upper surface of the second source layer can enhance reflection of external light and change the direction of light propagation.
  • the light shielding layer of the thin film transistor provided by the embodiment of the invention is located between the source and the drain and on the incident light side of the semiconductor active layer.
  • the light shielding layer can Separating the first source layer from the first drain layer from the first source layer and the first drain layer; the light shielding layer may also span the plurality of film layers, the first source layer and the first layer The drain layer is separated, and the second source layer and the second drain layer are also separated.
  • the thin film transistor provided by the embodiment of the present invention is a top gate type thin film transistor, as shown in FIG.
  • the thin film transistor of the present invention may also be a thin film transistor of another structure such as a bottom gate type.
  • the thin film transistor includes a light shielding layer on a side of the semiconductor active layer away from the gate to block external light from illuminating the semiconductor active layer. Not here - repeat.
  • a light shielding layer may be disposed on a side of the semiconductor active layer remote from the gate.
  • the semiconductor active layer is disposed between the gate and the light shielding layer; and the gate insulating layer is disposed between the semiconductor active layer and the gate. Therefore, one side of the semiconductor active layer can block light through the gate, and the other side can block light through the light shielding layer. Therefore, the semiconductor active layer can be protected from light, whether it is a bottom gate type thin film transistor or a top gate type thin film transistor.
  • the light shielding layer is obtained by oxidizing a metal for forming a source drain, that is, the light shielding layer is formed of an oxide of a metal for forming a source and a drain. This allows the preparation process to be carried out without adding too many additional processes to form the light shielding layer.
  • An array substrate provided by an embodiment of the invention includes the thin film transistor.
  • a display provided by an embodiment of the invention includes the array substrate.
  • the display is a liquid crystal display, and may be other types of displays.
  • a method for fabricating a thin film transistor according to an embodiment of the present invention includes: fabricating a source, a drain, and a light shielding layer, wherein the light shielding layer is located between the source and the drain, and the source The pole is separated from the drain;
  • the light shielding layer being located on the incident light side of the semiconductor active layer, blocking the irradiation of the semiconductor active layer by the incident light;
  • a gate insulating layer and a gate are formed over the source, drain, and semiconductor active layers.
  • the method of fabricating a source, a drain, and a light shielding layer includes:
  • a metal layer is deposited on the base substrate, and the two ends of the metal layer are respectively formed into a source layer and a drain layer, and a region of the intermediate portion of the metal layer is oxidized to obtain a light shielding layer.
  • the fabricating the source, the drain, and the light shielding layer including forming the second source layer and the second drain layer includes:
  • the photoresist coated on the second source layer and the second drain layer is made into a sawtooth photoresist by a gray scale or a half-order exposure technique, and then a second method is performed by dry etching or wet etching. a source layer and a second drain layer.
  • a metal titanium Ti film layer 2 is deposited on the base substrate 1 by magnetron sputtering, and a metal molybdenum Mo film layer 3 is further deposited on the metal titanium Ti film layer 2, and the metal titanium film layer 2
  • the total thickness of the metal molybdenum film layer 3 ranges from 1400 to 3400 A, and the thickness range can be adjusted at will, and can be adjusted according to the resistance of the product.
  • a photoresist is coated on the metal molybdenum thin film layer 3 and exposed by a gray scale or a half-step exposure technique, and the pattern of the photoresist 4 obtained after development is as shown in FIG.
  • the metal titanium thin film layer 2 and the metal molybdenum thin film layer 3 can also be formed by electron beam evaporation or the like.
  • the deposited titanium metal film layer 2 and the metal molybdenum film layer 3 are wet-etched, and the metal titanium film layer 2 and the metal molybdenum film layer are covered by the photoresist 4 during the etching process. 3
  • the metal titanium film layer and the metal molybdenum film layer, which are left without the photoresist, are etched away to expose the substrate 1.
  • the thickness of the photoresist 4 in FIG. 5 is different.
  • the photoresist in the thin region of the photoresist is completely removed, and the metal molybdenum thin film layer 3 is exposed, and the metal molybdenum is in a place where the photoresist is thick.
  • the film layer 3 is still covered by the photoresist 4.
  • a thin region of photoresist corresponds to a region between the source and the drain. Then, a dry etching process is performed.
  • the metal molybdenum film layer not covered by the photoresist is etched away to expose the metal titanium film layer 2, and the metal molybdenum film layer 3 covered by the photoresist 4 is Reserved. Then, an oxidation process is performed, and the exposed titanium metal thin film layer 2 is oxidized to obtain a TiO x insulating layer, and at the same time, the photoresist coated on the metal molybdenum thin film layer 3 can be completely removed by oxidation. Referring to FIG. 6, the insulating layer obtained by oxidation can be used as the light shielding layer 6.
  • the main function of the light shielding layer 6 is to reflect the backlight illumination on the side of the substrate substrate 1, thereby preventing the semiconductor active layer from being exposed to light and causing leakage of the thin film transistor.
  • Current The titanium metal thin film layer 2 shown in FIG. 5 is formed by oxidizing a light shielding layer 6 to form a first drain layer 5 and a first source layer 7, respectively. Similarly, the metal molybdenum film is completely removed. After the photoresist is covered on the layer 3, the metal molybdenum thin film layer 3 shown in FIG. 5 forms the second drain layer 8 and the second source layer 9.
  • a semiconductor active layer such as a metal oxide indium gallium oxide IGZO or an indium oxide oxide IZO is deposited by a magnetron sputtering method.
  • a metal oxide IGZO semiconductor active layer is taken as an example to illustrate the deposition of the obtained metal oxide.
  • the IGZO semiconductor active layer includes three regions of 101, 102, and 103, wherein a metal oxide IGZO semiconductor active layer 101 region is located on the base substrate 1, and a metal oxide IGZO semiconductor active layer 102 region is located at the second drain layer 8.
  • the metal oxide IGZO semiconductor active layer 103 region is located above the light shielding layer 6, and the metal oxide IGZO semiconductor active layer 103 region covers the light shielding layer 6.
  • a photoresist is coated on the deposited metal oxide IGZO semiconductor active layer, and exposed by a gray scale or a half-order exposure technique.
  • the photoresist pattern obtained after development is as shown in FIG. 7 , and the metal oxide IGZO semiconductor has The photoresist layer 42 is not covered on the region of the source layer 101, and the photoresist 42 covering the region of the metal oxide IGZO semiconductor active layer 103 is flat.
  • the photoresist 41 covered on the region of the metal oxide IGZO semiconductor active layer 102 is a zigzag pattern in which the 1020 region of the metal oxide IGZO semiconductor active layer 102 region on the second drain layer 8 is not covered with a photoresist, so that the second drain layer 8 formed under the subsequent etching is formed.
  • the upper surface is flat, and the second drain layer 8 of the flat upper surface has better contact with the subsequently formed pixel electrode.
  • the semiconductor active layer such as metal oxide IGZO or IZO can also be prepared by electron beam evaporation or the like, and the semiconductor active layer can also be an amorphous silicon active layer (a-Si), a polysilicon active layer (poly-Si). ) Wait.
  • the active layer of the metal oxide IGZO semiconductor without the photoresist covering region is completely etched by dry etching, and the thickness of the photoresist is performed as the dry etching progresses. Also in the corresponding thinning, the photoresist 41 covered on the metal oxide IGZO semiconductor active layer 102 region is thinner, and the photoresist 42 covered on the metal oxide IGZO semiconductor active layer 103 region is thicker, when the metal is oxidized.
  • the metal oxide IGZO semiconductor active layer 102 is continued when dry etching is continued.
  • the metal oxide IGZO semiconductor active layer of the region functions as the sawtooth photoresist 41 in the drawing, and the metal oxide IGZO semiconductor active layer of the metal oxide IGZO semiconductor active layer 102 region can serve as the second
  • the sawtooth photoresist on the source layer 9 and the second drain layer 8 continues to be dry etched such that the metal oxide IGZO semiconductor active layer above the second source layer 9 and the second drain layer 8 When completely etched away
  • the second source layer 9 forms a sawtooth upper surface 9b
  • the second drain layer 8 also forms a sawtooth upper surface 8b, as shown in FIG. 8, and ensures metal oxide IGZO throughout the dry etching process.
  • the photoresist 42 covered on the region is not etched away, and the photoresist covered on the region of the metal oxide IGZO semiconductor active layer 103 is removed after the completion of the dry etching to obtain the metal oxide IGZO semiconductor active layer 103.
  • the obtained metal oxide IGZO semiconductor active layer 103 is annealed.
  • the resulting reflective drain 8 and reflective source 9 can be used as the first drain layer 5 and the first source layer 7.
  • the first drain layer 5 and the first source layer 7 below it are oxidized by the outside oxygen.
  • the exposure dose of the photoresist coated on the active layer of the metal oxide IGZO semiconductor is increased by using gray scale or half-order exposure technology, and the metal oxide IGZO semiconductor in FIG. 7 obtained after development has
  • the photoresist 41 covering the region of the source layer 102 is thinner, wherein the thinnest portion of the photoresist 41 is exposed to the underlying metal oxide IGZO semiconductor active layer, and the metal oxide IGZO semiconductor active layer 103 is covered on the region.
  • the photoresist 42 is thicker. In the embodiment of the present invention, the thickness of the photoresist 41 is about 5000 to 800 ⁇ , and the thickness of the photoresist 42 is about 15000 to 2500 ⁇ .
  • the thickness of the photoresists 41 and 42 is not limited to the implementation of the present invention.
  • wet etching is performed to completely etch away the metal oxide IGZO semiconductor active layer without the photoresist covering region, wet etching, immersion, and the etching liquid continuously flows, and the wet method The etching is performed in all directions. As the wet etching progresses, the adjacent etching positions on the active layer 102 of the metal oxide IGZO semiconductor are gradually connected, and the flowing wet etching can be adjacent.
  • a thin isolated photoresist is etched away at the etched position, and a sawtooth shape is initially formed, and the wet etching is continued, at this time, the metal oxide IGZO semiconductor active layer 102 region of the metal oxide IGZO semiconductor active layer The effect is the same as that of the sawtooth photoresist 41 in FIG. 7, and the metal oxide IGZO semiconductor active layer of the metal oxide IGZO semiconductor active layer 102 region can serve as the second source layer 9 and the second drain layer 8.
  • the sawtooth photoresist when the metal oxide IGZO semiconductor active layer over the second source layer 9 and the second drain layer 8 is completely etched away, the second source layer 9 forms a sawtooth upper surface 9b, the second drain layer 8 is formed in a zigzag shape
  • the upper surface 8b ensures that the photoresist 42 covered on the metal oxide IGZO semiconductor active layer 103 region is not etched away during the entire wet etching process, after the entire wet etching is completed.
  • the photoresist covered on the region of the metal oxide IGZO semiconductor active layer 103 is removed to obtain a metal oxide IGZO semiconductor active layer 103.
  • the obtained metal oxide IGZO semiconductor active layer 103 is annealed.
  • the obtained reflective drain 8 and reflective source 9 can serve as a protective layer of the first drain layer 5 and the first source layer 7, respectively, and the reflective drain 8 and the reflective source 9 can reflect external illumination. It is also possible to avoid the first drain layer 5 and the first source layer below it 7 is oxidized by external oxygen.
  • the flat lower surface 8a of the second drain layer 8 can effectively reflect the illumination of the backlight from the substrate substrate side; the sawtooth upper surface 8b of the second drain layer 8 can reflect the cause The liquid crystal rotates or confuses the scattered light, so that the second drain layer 8 including the sawtooth upper surface 8b and the flat lower surface 8a can better avoid light from generating leakage current.
  • the serrated upper surface 9b and the flat lower surface 9a of the second source layer 9 can also better avoid light from generating leakage current.
  • the formed semiconductor active layer includes both end portions overlapping the source and drain electrodes and an intermediate portion corresponding to the light shielding layer.
  • the resin layer 11 is coated on the basis of the structure shown in FIG. 8, and the resin layer 11 is thermally cured.
  • the conditions of the heat curing treatment include: heating by an electromagnetic induction furnace at a heating temperature of 250 ° C The heating temperature is lower than the melting point of the resin material, and an argon (Ar) gas shielding gas is introduced, and the soft resin material is thermally cured, and the resin layer 11 after the heat curing treatment is hardened, and the resin layer after the heat curing treatment 11 can be used as a gate insulating layer.
  • the present invention forms a gate insulating layer by a resin layer having a higher transmittance than an inorganic silicon nitride or silicon oxide material.
  • the resin has a good planarization effect.
  • the gate insulating layer according to the embodiment of the present invention is not limited to the resin layer, and any other suitable gate insulating layer material may be employed.
  • a metal Mo layer is deposited by magnetron sputtering on the basis of FIG. 9.
  • the thickness of the metal Mo layer is 1400-3400 A, and a photoresist is coated on the deposited metal Mo layer.
  • the overlying photoresist is exposed, developed, and then wet etched, the metal Mo layer without the photoresist overlying region is etched away, and the photoresist is removed to obtain the gate layer 12.
  • the gate layer 12 is located above the metal oxide IGZO semiconductor active layer 103 and can be used to block external incident light from illuminating the metal oxide IGZO semiconductor active layer 103.
  • the metal Mo layer can also be prepared by electron beam evaporation or the like.
  • the gate layer 12 may also be a double-layer metal or a multi-layer metal such as aluminum A1/molybdenum Mo, or may be other types of metals such as titanium Ti, copper Cu or the like.
  • a silicon nitride SiN x is deposited by chemical vapor deposition on the basis of FIG.
  • the film, SiN film is deposited to a thickness of 2500-6000A, and a photoresist is coated on the deposited silicon nitride SiN x film, and the coated photoresist is exposed and developed, followed by dry etching and etching.
  • the silicon nitride SiN x film without the photoresist overlying region is removed, and the via hole 14 is etched to remove the photoresist to obtain the passivation layer 13.
  • the passivation layer 13 and the resin layer 11 are simultaneously etched away, and the second drain layer 8 is exposed through the formed via hole 14.
  • the passivation layer 13 is an insulating material and may be silicon nitride, silicon oxide or an insulating polymer material.
  • an ITO film is deposited by magnetron sputtering on the basis of FIG. 11, and the thickness of the ITO film is 400-600 A.
  • a photoresist is coated on the deposited ITO film to coat the light.
  • the adhesive is exposed and developed, and then the wet etching is used to etch away the ITO film without the photoresist covering region, and the photoresist is removed to obtain the pixel electrode 15.
  • the pixel electrode 15 is in contact with the second drain layer 8 through the via hole 14.
  • the ITO film can also be prepared by electron beam evaporation or the like.
  • the source and the drain of the thin film transistor prepared in the embodiment of the present invention are two-layer metal, and one of the two-layer metal may be made of metal titanium Ti, or a low-resistance metal such as metal aluminum A1, and a low-resistance metal. Reducing the resistance of the thin film transistor can also reduce the line width of the source and the drain; in addition to the metal molybdenum Mo, the other metal in the double layer metal can also be a metal that is difficult to oxidize such as metal chromium Cr, a metal that is difficult to oxidize.
  • the layer acts as a protective layer to protect the underlying metal from oxidation.
  • the source and drain of the thin film transistor prepared in the embodiment of the present invention are not limited to a double layer metal, and may be a single layer metal or a multilayer metal of two or more layers.
  • the thin film transistor includes a source and a drain, a semiconductor active layer, a gate insulating layer and a gate.
  • the thin film transistor further includes: a light shielding layer between the source and the drain, the light shielding layer is a source and a The drain is separated, and the light shielding layer is located on the incident light side of the semiconductor active layer to block the incident light from illuminating the semiconductor active layer, thereby avoiding the problem that the semiconductor active layer is affected by the light and causing leakage current of the thin film transistor, thereby effectively implementing the problem.
  • Highly stable thin film transistor characteristics are.

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Abstract

一种薄膜晶体管及其制作方法、阵列基板及显示器。所述薄膜晶体管包括源极（7，9）和漏极（5，8）、半导体有源层（103）、栅极绝缘层（11）和栅极（12），该薄膜晶体管还包括：位于源极（7，9）与漏极（5，8）之间的遮光板（6），所述遮光板（6）将源极（7，9）与漏极（5，8）阻断，并且该遮光板（6）位于半导体有源层（103）的入射光侧，用于阻挡入射光对半导体有源层（103）的照射。

Description

薄膜晶体管及其制作方法、 阵列基板及显示器 技术领域
本发明的实施例涉及一种薄膜晶体管及其制作方法、阵列基板和显示器。 背景技术
图 1为现有技术中底栅型薄膜晶体管（Thin Film Transistor, TFT )的结 构示意图， 该薄膜晶体管包括： 形成于衬底基板 10上的栅极 60、 栅极绝缘 层 70、 源极 20、 漏极 30、 半导体有源层 40和保护层 90。 包含薄膜晶体管的 阵列基板还包括钝化层 50和像素电极 80。底栅型的薄膜晶体管栅极 60可以 阻挡背光源的光照，避免半导体有源层 40受背光源的光照而导致薄膜晶体管 产生漏电流。 该结构的薄膜晶体管为了避免外界环境中水及氧气等对半导体 有源层 40的影响， 在半导体有源层 40的上方设置了一层保护层 90, 保护层 90可以避免金属氧化物半导体有源层 40受外界水及氧气的影响， 而该结构 中的保护层 90多为非金属，会导致薄膜晶体管产生漏电流。 图 2为现有技术 的顶栅型薄膜晶体管的结构示意图，该薄膜晶体管包括：形成于衬底基板 100 上的漏极 200、 源极 300、 有源层 400、 栅极绝缘层 500、 栅极 600。 包含薄 膜晶体管的阵列基板还包含钝化层 700和像素电极 800。 在图 2所示的顶栅 型薄膜晶体管中， 栅极 600可以阻挡外界光照对半导体有源层 400的影响， 漏极 200与源极 300之间断开， 背光源的光可以穿过透明的衬底基板 100照 射到半导体有源层 400, 而半导体有源层 400与漏极 200相接触， 同时半导 体有源层 400与源极 300相接触。半导体有源层 400受到光照后会将漏极 200 和源极 300导通， 从而导致薄膜晶体管产生漏电流。
综上所述， 现有技术中的顶栅型的薄膜晶体管容易受到背光源影响而产 生漏电克。 发明内容
本发明实施例提供了一种薄膜晶体管及其制作方法、阵列基板及显示器， 本发明实施例提供的薄膜晶体管可以避免半导体有源层受到光照影响而导致 薄膜晶体管产生漏电流的问题。
本发明实施例提供的一种薄膜晶体管， 包括源极和漏极、半导体有源层、 栅极绝缘层和栅极、 以及位于源极与漏极之间的遮光层， 其中所述遮光层将 源极与漏极分隔，所述遮光层位于所述半导体有源层的远离所述栅极的一侧。
本发明实施例提供的一种阵列基板， 包括所述的薄膜晶体管。
本发明实施例提供的一种显示器， 包括所述的阵列基板。
本发明实施例提供的一种薄膜晶体管制作方法，该方法包括：制作源极、 漏极和遮光层， 其中， 所述遮光层位于所述源极与所述漏极之间， 并将源极 与漏极分隔； 制作半导体有源层， 所述半导体有源层包括与所述源极和所述 漏极交叠的两端部分以及与所述遮光层对应的中间部分； 在源极、 漏极和半 导体有源层上方制作栅极绝缘层和栅极。
综上所述， 本发明实施例的薄膜晶体管及其制作方法、 阵列基板及显示 器， 所述薄膜晶体管包括源极和漏极、 半导体有源层、 栅极绝缘层和栅极， 该薄膜晶体管还包括： 位于源极与漏极之间的遮光层， 所述遮光层将源极与 漏极阻断， 并且该遮光层位于半导体有源层入射光侧， 用于阻挡入射光对半 导体有源层的照射， 从而可以避免半导体有源层受到光照影响而导致薄膜晶 体管产生漏电流的问题， 有效的实现了高稳定的薄膜晶体管特性。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为现有技术中底栅型薄膜晶体管的结构示意图；
图 2为现有技术中顶栅型薄膜晶体管的结构示意图；
图 3为本发明实施例提供的一种薄膜晶体管的结构示意图；
图 4-图 12分别为本发明实施例提供的一种薄膜晶体管在制作过程中的 不同阶段的结构示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
本发明实施例提供了一种薄膜晶体管及其制作方法、阵列基板及显示器， 用以避免半导体有源层受到光照影响而导致薄膜晶体管产生漏电流的问题。
本发明实施例提供的一种薄膜晶体管， 包括源极和漏极、半导体有源层、 栅极绝缘层和栅极， 该薄膜晶体管还包括： 位于源极与漏极之间的遮光层， 所述遮光层将源极与漏极分隔， 该遮光层位于半导体有源层入射光侧， 阻挡 入射光对半导体有源层的照射。 也就是说， 遮光层位于半导体有源层的远离 栅极的一侧。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的 "第一" 、 "第二" 以及类似的词语并不表示任何顺序、 数量或者重要性， 而只是用来区分不同的组成部分。 同样， "一个" 、 "一" 或者 "该"等类似词语也不表示数量限制， 而是表示存在至少一个。 "包括" 或者 "包含" 等类似的词语意指出现该词前面的元件或者物件涵盖出现在该 词后面列举的元件或者物件及其等同， 而不排除其他元件或者物件。 "上" 、 "下" 、 "左" 、 "右" 、 "底" 、 "顶" 等仅用于表示相对位置关系， 当 被描述对象的绝对位置改变后， 则该相对位置关系也可能相应地改变。
下面结合具体实施例进行说明。
如图 3所示， 本发明实施例提供的一种薄膜晶体管， 包括： 位于衬底基 板 1上的第一漏极层 5和第一源极层 7、位于第一漏极层 5上的第二漏极层 8 和位于第一源极层 7上的第二源极层 9、 半导体有源层 103、 栅极绝缘层 11 和栅极 12。 该薄膜晶体管还包括： 位于第一漏极层 5与第一源极层 7之间的 遮光层 6, 遮光层 6将第一漏极层 5与第一源极层 7分隔， 该遮光层 6位于 半导体有源层 103下方， 阻挡入射光对半导体有源层 103的照射。 包含该薄 膜晶体管的阵列基板还包含钝化层 13和像素电极 15。
例如， 所述遮光层 6的材料为金属钛的氧化物或金属铝的氧化物。
例如， 所述源极和所述漏极为双层结构或多层结构， 所述源极包括第一 源极层 7和第二源极层 9;所述漏极包括第一漏极层 5和第二漏极层 8。第一 源极层 7和第一漏极层 5位于衬底基板 1上， 第二源极层 9位于第一源极层 7上并覆盖第一源极层 7,第二漏极层 8位于第一漏极层 5上并覆盖第一漏极 层 5。 第二漏极层 8包括与第一漏极层 5接触的平坦状下表面 8a和锯齿状上 表面 8b, 第二源极层 9包括与第一源极层 Ί接触的平坦状下表面 9a和锯齿 状上表面 9b。
例如， 所述第二源极层和 /或第二漏极层为锯齿状保护层， 第二漏极层 8 中的锯齿状上表面 8b和第二源极层 9中的锯齿状上表面 9b可以反射外界的 光照。 包括有锯齿状上表面的第二源极层 9也可以称为反射性源极 9, 包括 有锯齿状上表面的第二漏极层 8也可以称为反射性漏极 8 , 另外， 第二漏极 层 8和第二源极层 9的具体形状可以直接为平坦状而不需要形成锯齿状的上 表面。 当然， 第二漏极层 8和第二源极层 9的具体形状也可以为其它形状。
例如， 所述第一源极层 7的材料为钛 Ti或铝 A1金属， 所述第一漏极层 5的材料为钛 Ti或铝 A1金属， 金属钛或金属铝的电阻较低， 低电阻的金属 在减小薄膜晶体管电阻的同时还可以减小第一源极层和第一漏极层的线宽。
例如， 所述第二源极层 9的材料为钼 Mo或铬 Cr金属，所述第二漏极层 8的材料为钼 Mo或铬 Cr金属， 金属钼或金属铬为难氧化的金属， 难氧化的 金属层可以充当保护层的作用， 保护其下面的金属不被氧化。
本发明实施例提供的薄膜晶体管中源极和漏极也可以设计为多层结构， 源极包括位于底层第一源极层、 位于顶层第二源极层、 位于第一源极层和第 二源极层之间的其他源极层； 漏极包括位于底层第一漏极层、 位于顶层第二 漏极层、 位于第一漏极层和第二漏极层之间的其他漏极层。 例如， 第二漏极 层包括锯齿状上表面， 第二源极层包括锯齿状上表面。 第二源极层和第二漏 极层的材料优选性质稳定， 难于被氧化的金属， 如钼 Mo或铬 Cr, 以保护位 于其下方的其他源极层和其他漏极层。 第一源极层和其他源极层材料优选电 阻率低的金属， 如钛 Ti或铝 Al。 第一漏极层和其他漏极层材料优选电阻率 低的金属， 如钛 Ti或铝 Al。 第二漏极层的锯齿状上表面、 第二源极层的锯 齿状上表面可以加强反射外界光线， 改变光的传播方向。
本发明实施例提供的薄膜晶体管的遮光层位于源极和漏极之间且位于半 导体有源层的入射光侧。 源极和漏极为双层结构或多层结构时， 遮光层可以 与第一源极层、第一漏极层处于同一膜层，将第一源极层和第一漏极层分隔； 遮光层也可以跨越多个膜层， 将第一源极层和第一漏极层分隔， 也将第二源 极层和第二漏极层分隔。
本发明实施例提供的薄膜晶体管为顶栅型薄膜晶体管， 如图 3所示。 本 发明的薄膜晶体管也可以为其他结构的薄膜晶体管， 如底栅型。 薄膜晶体管 包括遮光层， 遮光层位于半导体有源层远离栅极的一侧， 阻挡外界光线对于 半导体有源层的照射。 在此不——赘述。
实际上， 不论是底栅型薄膜晶体管还是顶栅型薄膜晶体管， 遮光层均可 以设置在半导体有源层的远离栅极的一侧。 这样， 半导体有源层设置在栅极 和遮光层之间； 栅极绝缘层设置在半导体有源层和栅极之间。 因此， 半导体 有源层的一侧可以通过栅极遮挡光线， 而另一侧可以通过遮光层遮挡光线。 因此， 无论是底栅型薄膜晶体管还是顶栅型薄膜晶体管， 其半导体有源层均 可以免受光线的照射。
另夕卜，本发明中遮光层通过氧化用于形成源漏极的金属得到，也就是说， 遮光层是由用于形成源漏极的金属的氧化物形成。 这样可以筒化制备工艺， 不必增加过多额外的工艺来形成遮光层。
本发明实施例提供的一种阵列基板， 包括所述的薄膜晶体管。
本发明实施例提供的一种显示器， 包括所述的阵列基板。
例如， 所述显示器为液晶显示器， 也可以是其它类型的显示器。
本发明实施例提供的一种薄膜晶体管的制作方法， 该方法包括： 制作源极、 漏极和遮光层， 其中， 所述遮光层位于所述源极与所述漏极 之间， 并将源极与漏极分隔；
制作半导体有源层， 所述遮光层位于半导体有源层的入射光侧， 阻挡入 射光对半导体有源层的照射；
在源极、 漏极和半导体有源层上方制作栅极绝缘层和栅极。
例如， 所述制作源极、 漏极和遮光层的方法包括：
在衬底基板上沉积一层金属层， 将该金属层的两端分别制作成源极层与 漏极层， 对金属层中间部分的区域进行氧化处理， 制作得到遮光层。
例如， 所述制作源极、 漏极和遮光层包括制作第二源极层和第二漏极层 包括： 采用灰阶或半阶曝光技术曝光使得第二源极层和第二漏极层上方覆盖的 光刻胶为锯齿状光刻胶， 之后采用干法刻蚀或湿法刻蚀的方法制作第二源极 层和第二漏极层。
下面结合具体实施例进行说明。
如图 4所示， 首先在衬底基板 1上采用磁控溅射的方法沉积金属钛 Ti 薄膜层 2, 在金属钛 Ti薄膜层 2上继续沉积金属钼 Mo薄膜层 3, 金属钛薄 膜层 2和金属钼薄膜层 3的总厚度范围为 1400-3400A,该厚度范围可随意调 节， 可根据产品要求的电阻大小来调节。 在金属钼薄膜层 3上涂覆光刻胶并 采用灰阶或半阶曝光技术曝光， 显影后得到的光刻胶 4的图案如图 4所示。 金属钛薄膜层 2和金属钼薄膜层 3也可以采用电子束蒸发等方法进行形成。
如图 5所示， 对沉积得到的金属钛薄膜层 2和金属钼薄膜层 3进行湿法 刻蚀， 刻蚀过程中， 有光刻胶 4覆盖的区域金属钛薄膜层 2和金属钼薄膜层 3 被保留， 无光刻胶覆盖的区域金属钛薄膜层和金属钼薄膜层被刻蚀掉， 露 出衬底基板 1。
图 5中光刻胶 4的厚度不一样， 进行灰化去胶工艺时， 将光刻胶薄的区 域的光刻胶全部去掉， 露出金属钼薄膜层 3, 光刻胶厚的地方处金属钼薄膜 层 3仍被光刻胶 4覆盖。 例如， 光刻胶薄的区域对应于源极和漏极之间的区 域。 接着进行干法刻蚀处理， 刻蚀过程中， 无光刻胶覆盖的区域金属钼薄膜 层被刻蚀掉， 露出金属钛薄膜层 2, 有光刻胶 4覆盖的区域金属钼薄膜层 3 被保留。接着进行氧化工艺处理,暴露出的金属钛薄膜层 2被氧化而得到 TiOx 绝缘层， 同时， 也可氧化完全去除掉金属钼薄膜层 3上覆盖的光刻胶。 参见 图 6, 氧化后得到的 1¾ 绝缘层可以作为遮光层 6, 遮光层 6的主要作用是 反射衬底基板 1侧的背光源光照， 从而可以避免半导体有源层受光照而导致 薄膜晶体管产生漏电流。 图 5中所示的金属钛薄膜层 2除了一部分经氧化形 成遮光层 6之外， 另外两部分分别形成第一漏极层 5和第一源极层 7; 同理， 完全去除掉金属钼薄膜层 3上覆盖的光刻胶后， 图 5所示的金属钼薄膜层 3 形成第二漏极层 8和第二源极层 9。
如图 7所示， 在图 6所示结构的基础上， 使用磁控溅射方法沉积金属氧 化物铟镓辞氧化物 IGZO或者铟辞氧化物 IZO等半导体有源层。 本发明实施 例中以金属氧化物 IGZO 半导体有源层为例说明， 沉积得到的金属氧化物 IGZO半导体有源层包括 101、 102和 103三个区域， 其中金属氧化物 IGZO 半导体有源层 101区域位于衬底基板 1上， 金属氧化物 IGZO半导体有源层 102区域位于第二漏极层 8和第二源极层 9上， 金属氧化物 IGZO半导体有 源层 103区域位于遮光层 6上方， 金属氧化物 IGZO半导体有源层 103区域 覆盖遮光层 6。 在沉积得到的金属氧化物 IGZO半导体有源层上涂覆光刻胶， 采用灰阶或半阶曝光技术进行曝光， 显影后得到的光刻胶图案如图 7所示， 金属氧化物 IGZO 半导体有源层 101 区域上没有覆盖光刻胶， 金属氧化物 IGZO半导体有源层 103区域上覆盖的光刻胶 42为平坦状,金属氧化物 IGZO 半导体有源层 102区域上覆盖的光刻胶 41为锯齿状，其中第二漏极层 8上的 金属氧化物 IGZO半导体有源层 102区域中的 1020区域上没有覆盖光刻胶， 以便在后续刻蚀后在其下方形成的第二漏极层 8的上表面为平坦状， 而平坦 状上表面的第二漏极层 8与后续形成的像素电极有更好的接触。 另外， 金属 氧化物 IGZO或者 IZO等半导体有源层还可以采用电子束蒸发等方法制备得 到， 半导体有源层也可以是非晶硅有源层（a-Si ) , 多晶硅有源层 (poly-Si) 等。
在制备反射性源极、 反射性漏极和金属氧化物 IGZO半导体有源层的具 体实施例中， 包含下面两种实施方案：
方案一， 在图 7的基础上， 采用干法刻蚀将没有光刻胶覆盖区域的金属 氧化物 IGZO半导体有源层全部刻蚀掉， 随着干法刻蚀的进行， 光刻胶的厚 度也在相应减薄， 金属氧化物 IGZO半导体有源层 102区域上覆盖的光刻胶 41较薄， 金属氧化物 IGZO半导体有源层 103区域上覆盖的光刻胶 42厚度 较厚， 当金属氧化物 IGZO半导体有源层 102区域上覆盖的光刻胶完全被刻 蚀掉而露出金属氧化物 IGZO半导体有源层时， 此时继续进行干法刻蚀时， 金属氧化物 IGZO半导体有源层 102区域的金属氧化物 IGZO半导体有源层 的作用与图 Ί中的锯齿状光刻胶 41的作用相同，金属氧化物 IGZO半导体有 源层 102区域的金属氧化物 IGZO半导体有源层可以充当第二源极层 9和第 二漏极层 8上的锯齿状光刻胶， 继续进行干法刻蚀， 使得第二源极层 9和第 二漏极层 8上方的金属氧化物 IGZO半导体有源层完全被刻蚀掉时， 第二源 极层 9形成锯齿状的上表面 9b,第二漏极层 8也形成锯齿状的上表面 8b,如 图 8所示，而在整个干法刻蚀过程中保证金属氧化物 IGZO半导体有源层 103 区域上覆盖的光刻胶 42 不被刻蚀掉， 整个干法刻蚀结束后去除金属氧化物 IGZO半导体有源层 103区域上覆盖的光刻胶， 得到金属氧化物 IGZO半导 体有源层 103。 对得到的金属氧化物 IGZO半导体有源层 103进行退火处理。 得到的反射性漏极 8和反射性源极 9可以作为第一漏极层 5和第一源极层 7 其下面的第一漏极层 5和第一源极层 7被外界氧气氧化。
方案二， 采用灰阶或半阶曝光技术对金属氧化物 IGZO半导体有源层上 涂覆的光刻胶进行曝光时要加大曝光剂量， 显影后得到的图 7中的金属氧化 物 IGZO半导体有源层 102区域上覆盖的光刻胶 41较薄， 其中光刻胶 41最 薄的地方要暴露出其下面的金属氧化物 IGZO 半导体有源层， 金属氧化物 IGZO半导体有源层 103区域上覆盖的光刻胶 42较厚， 本发明实施例中光刻 胶 41的厚度约为 5000~800θΑ, 光刻胶 42的厚度约为 15000~2500θΑ, 光刻 胶 41与 42的厚度不限于本发明实施例中的厚度值。 接着进行湿法刻蚀， 将 没有光刻胶覆盖区域的金属氧化物 IGZO半导体有源层全部刻蚀掉， 湿刻液 喷淋， 浸泡， 此时的刻蚀液体不停的流动， 且湿法刻蚀是各个方向都在刻蚀， 随着湿刻的进行， 金属氧化物 IGZO半导体有源层 102区域上相邻的刻蚀位 置就会逐渐相连起来， 流动的湿刻液可以将相邻的刻蚀位置处薄薄的孤立的 光刻胶沖走， 初步形成了锯齿形状， 继续进行湿法刻蚀， 此时金属氧化物 IGZO半导体有源层 102区域的金属氧化物 IGZO半导体有源层的作用与图 7 中锯齿状光刻胶 41的作用相同，金属氧化物 IGZO半导体有源层 102区域的 金属氧化物 IGZO半导体有源层可以充当第二源极层 9和第二漏极层 8上的 锯齿状光刻胶， 当第二源极层 9和第二漏极层 8上方的金属氧化物 IGZO半 导体有源层完全被刻蚀掉时， 第二源极层 9形成锯齿状的上表面 9b, 第二漏 极层 8形成锯齿状的上表面 8b, 如图 8所示， 在整个湿法刻蚀过程中保证金 属氧化物 IGZO半导体有源层 103区域上覆盖的光刻胶 42不被刻蚀掉，整个 湿法刻蚀结束后去除金属氧化物 IGZO半导体有源层 103区域上覆盖的光刻 胶， 得到金属氧化物 IGZO半导体有源层 103。 对得到的金属氧化物 IGZO 半导体有源层 103进行退火处理。 得到的反射性漏极 8和反射性源极 9可以 分别作为第一漏极层 5和第一源极层 7的保护层， 反射性漏极 8和反射性源 极 9可以反射外界的光照， 也可以避免其下面的第一漏极层 5和第一源极层 7被外界氧气氧化。
如图 8所示，第二漏极层 8中的平坦状下表面 8a可以有效的反射背光源 从衬底基板侧入射的光照；第二漏极层 8中的锯齿状上表面 8b可以反射因液 晶旋转或混乱而散射的光， 因此包含有锯齿状上表面 8b和平坦状下表面 8a 的第二漏极层 8可以更好的避免光照而产生漏电流。 同样地， 第二源极层 9 中的锯齿状上表面 9b和平坦状下表面 9a也可以更好的避免光照而产生漏电 流。 如图 8所示， 形成的半导体有源层包括与源极和漏极交叠的两端部分以 及与遮光层对应的中间部分。
如图 9所示， 在图 8所示结构的基础上涂覆树脂层 11 , 并对树脂层 11 进行热固化处理， 热固化处理的条件包括： 采用电磁感应炉加热， 加热温度 为 250°C, 加热温度要低于树脂材料的熔点， 同时通入氩（Ar )气保护气体， 将柔软的树脂材料进行热固化处理，热固化处理后的树脂层 11变硬，热固化 处理后的树脂层 11可以作为栅极绝缘层。 另外， 图 9仅为树脂层 11的示意 图， 实际树脂层 11的截面结构也为锯齿状结构，本发明具体实施例中的金属 锯齿状结构再加上非金属的树脂层锯齿状结构， 对于避免光照而产生漏电流 为锯齿状结构， 相比于平坦的薄膜， 锯齿状结构的薄膜增大了薄膜的反射面 积， 理论上来说， 效果更好。 本发明通过树脂层形成栅极绝缘层， 相对于无 机氮化硅或氧化硅材料具有更高的透射率。 此外， 树脂具有良好的平坦化作 用。 当然， 根据本发明实施例的栅极绝缘层也并不限于树脂层， 也可以采用 其他任何合适的栅极绝缘层材料。
如图 10所示，在图 9的基础上采用磁控溅射的方法沉积金属 Mo层，金 属 Mo层的厚度为 1400-3400A, 在沉积得到的金属 Mo层上涂覆光刻胶， 对 涂覆的光刻胶进行曝光、 显影， 之后采用湿法刻蚀， 刻蚀掉没有光刻胶覆盖 区域的金属 Mo层， 再去除掉光刻胶得到栅极层 12。 栅极层 12位于金属氧 化物 IGZO半导体有源层 103上方， 可以用于阻挡外界入射光对金属氧化物 IGZO半导体有源层 103的照射。 金属 Mo层还可以采用电子束蒸发等方法 制备得到。 另外， 栅极层 12还可以是双层金属或多层金属， 如铝 A1/钼 Mo, 还可以是其它类型的金属， 如钛 Ti、 铜 Cu等金属。
如图 11所示， 在图 10的基础上采用化学气相沉积方法沉积氮化硅 SiNx 薄膜， SiN^ 膜沉积厚度为 2500-6000A, 在沉积得到的氮化硅 SiNx薄膜上 涂覆光刻胶， 对涂覆的光刻胶进行曝光、 显影， 之后采用干法刻蚀， 刻蚀掉 没有光刻胶覆盖区域的氮化硅 SiNx薄膜， 并刻蚀形成过孔 14, 去除掉光刻 胶，得到钝化层 13。 干法刻蚀形成过孔 14时， 需要将钝化层 13与树脂层 11 同时刻蚀掉， 且第二漏极层 8通过形成的过孔 14暴露出来。 钝化层 13为绝 缘材料， 可以为氮化硅、 氧化硅或绝缘高分子材料。
如图 12所示，在图 11的基础上采用磁控溅射的方法沉积 ITO薄膜， ITO 薄膜的厚度为 400-600A,在沉积得到的 ITO薄膜上涂覆光刻胶，对涂覆的光 刻胶进行曝光、显影，之后采用湿法刻蚀，刻蚀掉没有光刻胶覆盖区域的 ITO 薄膜， 去除掉光刻胶， 得到像素电极 15。 像素电极 15通过过孔 14与第二漏 极层 8接触。 ITO薄膜还可以采用电子束蒸发等方法制备得到。
本发明实施例中制备得到的薄膜晶体管的源极和漏极为双层金属， 双层 金属中其中一层金属除了采用金属钛 Ti, 还可以采用金属铝 A1等低电阻金 属， 低电阻的金属在减小薄膜晶体管电阻的同时还可以减小源极和漏极的线 宽； 双层金属中另一层金属除了采用金属钼 Mo, 还可以采用金属铬 Cr等难 氧化的金属， 难氧化的金属层可以充当保护层的作用， 保护其下面的金属不 被氧化。 另外， 本发明实施例中制备得到的薄膜晶体管的源极和漏极不限于 采用双层金属， 也可以是单层金属或两层以上的多层金属。
综上所述， 本发明实施例的薄膜晶体管及其制作方法、 阵列基板及显示 器。 所述薄膜晶体管包括源极和漏极、 半导体有源层、 栅极绝缘层和栅极， 该薄膜晶体管还包括： 位于源极与漏极之间的遮光层， 所述遮光层将源极与 漏极分隔， 遮光层位于半导体有源层入射光侧， 阻挡入射光对半导体有源层 的照射， 从而可以避免半导体有源层受到光照影响而导致薄膜晶体管产生漏 电流的问题， 有效的实现了高稳定的薄膜晶体管特性。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种薄膜晶体管， 包括源极和漏极、 半导体有源层、栅极绝缘层和栅 极、 以及位于源极与漏极之间的遮光层， 其中
所述遮光层将源极与漏极分隔， 所述遮光层位于所述半导体有源层的远 离所述栅极的一侧。
2、根据权利要求 1所述的薄膜晶体管， 其中， 所述遮光层的材料为金属 钛的氧化物或金属铝的氧化物。
3、根据权利要求 1或 2所述的薄膜晶体管， 其中， 所述源极和所述漏极 为双层结构或多层结构， 所述源极至少包括位于底层的第一源极层和位于顶 层的第二源极层； 所述漏极至少包括位于底层的第一漏极层和位于顶层的第 二漏极层。
4、 根据权利要求 3所述的薄膜晶体管， 其中， 所述第二源极层和 /或第 二漏极层为锯齿状保护层。
5、根据权利要求 3或 4所述的薄膜晶体管， 其中， 所述第一源极层的材 料为钛 Ti或铝 A1金属； 所述第一漏极层的材料为钛 Ti或铝 A1金属。
6、 根据权利要求 3-5任一项所述的薄膜晶体管， 其中， 所述第二源极层 的材料为钼 Mo或铬 Cr金属；所述第二漏极层的材料为钼 Mo或铬 Cr金属。
7、 根据权利要求 3-6任一项所述的薄膜晶体管， 其中， 所述遮光层的材 料为用于所述第一源极层和所述第一漏极层的材料的氧化物， 所述遮光层与 所述第一源极层和所述第一漏极层位于同一层。
8、 根据权利要求 1-7任一项所述的薄膜晶体管， 其中， 所述半导体有源 层设置在所述栅极和所述遮光层之间； 所述栅极绝缘层设置在所述半导体有 源层和所述栅极之间。
9、 根据权利要求 1-8任一项所述的薄膜晶体管， 其中， 所述栅极绝缘层 为树脂层。
10、 一种阵列基板， 包括权利要求 1-9任一权项所述的薄膜晶体管。
11、 一种显示器， 包括权利要求 10所述的阵列基板。
12、 一种薄膜晶体管的制作方法， 包括：
制作源极、 漏极和遮光层， 其中， 所述遮光层位于所述源极与所述漏极 之间， 并将源极与漏极分隔；
制作半导体有源层， 所述半导体有源层包括与所述源极和所述漏极交叠 的两端部分以及与所述遮光层对应的中间部分；
在源极、 漏极和半导体有源层上方制作栅极绝缘层和栅极。
13、根据权利要求 12所述的薄膜晶体管的制作方法， 其中， 所述制作源 极、 漏极和遮光层的方法包括：
在衬底基板上沉积一层金属层， 将该金属层的两端分别制作成源极层与 漏极层， 对金属层中间部分的区域进行氧化处理， 制作得到遮光层。
14、根据权利要求 13所述的薄膜晶体管的制作方法， 其中， 所述源极和 漏极包括具有锯齿状表面结构的顶层， 制作所述顶层包括：
采用灰阶或半阶曝光技术曝光使得用于形成源极和漏极的金属层上方覆 盖的光刻胶为锯齿状光刻胶， 之后采用干法刻蚀或湿法刻蚀进行独刻以形成 所述具有锯齿状表面结构的顶层。
PCT/CN2013/089287 2013-07-01 2013-12-12 薄膜晶体管及其制作方法、阵列基板及显示器 WO2015000267A1 (zh)

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