WO2015182658A1 - 電力用半導体素子の駆動回路 - Google Patents

電力用半導体素子の駆動回路 Download PDF

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Publication number
WO2015182658A1
WO2015182658A1 PCT/JP2015/065257 JP2015065257W WO2015182658A1 WO 2015182658 A1 WO2015182658 A1 WO 2015182658A1 JP 2015065257 W JP2015065257 W JP 2015065257W WO 2015182658 A1 WO2015182658 A1 WO 2015182658A1
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Prior art keywords
voltage
terminal
negative
semiconductor element
power semiconductor
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PCT/JP2015/065257
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English (en)
French (fr)
Japanese (ja)
Inventor
公輔 中野
佳祐 岩澤
隆義 三木
中武 浩
Original Assignee
三菱電機株式会社
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to US15/303,149 priority Critical patent/US10038438B2/en
Priority to EP15800653.6A priority patent/EP3151402B1/en
Priority to JP2015558273A priority patent/JP5989265B2/ja
Priority to CN201580015507.7A priority patent/CN106104993B/zh
Publication of WO2015182658A1 publication Critical patent/WO2015182658A1/ja

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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/08Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1602Diamond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003Nitride compounds
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/32Means for protecting converters other than automatic disconnection
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • H02M7/53875Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with analogue control of three-phase output
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/04Modifications for accelerating switching
    • H03K17/041Modifications for accelerating switching without feedback from the output circuit to the control circuit
    • H03K17/0412Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit
    • H03K17/04123Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit in field-effect transistor switches
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/06Modifications for ensuring a fully conducting state
    • H03K17/063Modifications for ensuring a fully conducting state in field-effect transistor switches
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
    • H03K17/0812Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
    • H03K17/08122Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit in field-effect transistor switches
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/20Modifications for resetting core switching units to a predetermined state
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/567Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/06Modifications for ensuring a fully conducting state
    • H03K2017/066Maximizing the OFF-resistance instead of minimizing the ON-resistance

Definitions

  • the present invention relates to a drive circuit for driving a power semiconductor element, and more particularly to a drive circuit having a function of preventing destruction due to malfunction of the power semiconductor element due to voltage fluctuation dv / dt.
  • a self-extinguishing power semiconductor element such as Si (silicon) IGBT (Insulated Gate Bipolar Transistor)
  • Si silicon
  • IGBT Insulated Gate Bipolar Transistor
  • the collector of the off-state power semiconductor element When the voltage variation dv / dt occurs between the emitter terminals, the gate voltage increases due to the parasitic capacitance associated with the gate of the power semiconductor element. If the gate voltage exceeds a predetermined threshold voltage, the power semiconductor element in the off state is erroneously turned on, causing an arm short circuit in a power converter such as an inverter, and destroying the power semiconductor element. It was. In order to avoid this problem, there is a method in which a negative bias voltage is applied between the gate and emitter terminals when the power semiconductor element is in an off state.
  • the driving power of the power semiconductor element is often supplied from the power supply of the main circuit, and the negative bias voltage applied to the power semiconductor element is established between the gate and emitter terminals before the power semiconductor element is established. Voltage fluctuations occur, the gate voltage rises, and malfunctions may occur.
  • MOSFET Metal-Oxide-Semiconductor Field-Effect-Transistor
  • voltage fluctuation occurs between the drain and source terminals before the negative bias voltage applied to the power semiconductor element is established. Then, the gate voltage rises, and malfunction may occur.
  • Patent Document 1 describes a circuit (drive circuit) for driving a semiconductor element having a low threshold voltage.
  • a normally-on FET (Field-Effect-Transistor) 132 is connected to the gate terminal and the source terminal 144 of the switching element 130 and the power source of the drive pulse generation circuit 118 is turned off, the gate ⁇ The source terminals were short-circuited.
  • Japanese Patent No. 45528321 (0053 to 0063 stages, FIG. 5)
  • the present invention has been made in order to solve the above-described problems, and prevents voltage fluctuations without applying a reverse voltage between the main terminals of a switching element that prevents malfunction of an off-state power semiconductor element.
  • An object of the present invention is to prevent the power semiconductor element from being erroneously turned on (erroneously turned on) due to dv / dt, and to prevent the power semiconductor element from being destroyed by this malfunction.
  • the power semiconductor element driving circuit includes a positive voltage supply power source that supplies a positive bias voltage between a control terminal and a reference terminal of the power semiconductor element, and a positive electrode side connected to a negative electrode side of the positive voltage supply power source.
  • a negative voltage supply power source that supplies a negative bias voltage between a control terminal and a reference terminal of the power semiconductor element, a positive bias voltage that turns on the power semiconductor element, and a negative voltage that turns off the power semiconductor element.
  • a gate drive circuit that supplies any one of the bias voltages between the control terminal and the reference terminal of the power semiconductor element based on a control signal of the control circuit, a total voltage of the positive bias voltage and the negative bias voltage, and a negative bias Connected to the voltage detection unit that detects the detection target voltage, which is either voltage or positive bias voltage, the control terminal of the power semiconductor element, and the negative side of the negative voltage supply power source And and a switching element.
  • the voltage detection unit detects whether the detection target voltage value is lower than the set voltage value or between the control terminal and the reference terminal of the power semiconductor element when the detection target voltage value is lower than the set voltage value. When the voltage rises, the switching element is turned on, and a voltage of zero V or less is supplied between the control terminal and the reference terminal in the power semiconductor element.
  • the switching element connected to the control terminal of the power semiconductor element and the negative side of the negative voltage supply power source is provided, so that the voltage fluctuation dv / dt is applied.
  • FIG. 3 is a circuit diagram showing a first drive circuit according to the first embodiment of the present invention. It is a figure which shows the insulated power supply which supplies electric power to the drive circuit of FIG.
  • FIG. 3 is a circuit diagram showing a drive circuit of a comparative example with respect to the drive circuit of FIG. 2.
  • FIG. 3 is a circuit diagram showing a second drive circuit according to the first embodiment of the present invention. It is a circuit diagram which shows the 3rd drive circuit by Embodiment 1 of this invention. It is a circuit diagram which shows the 4th drive circuit by Embodiment 1 of this invention. It is a circuit diagram which shows the drive circuit by Embodiment 2 of this invention.
  • FIG. 6 is a circuit diagram showing a third drive circuit according to a third embodiment of the present invention. It is a circuit diagram which shows the drive circuit by Embodiment 4 of this invention. It is a circuit diagram which shows the drive circuit of the comparative example with respect to the drive circuit of FIG.
  • FIG. FIG. 1 is a schematic diagram of an electric drive system according to Embodiment 1 of the present invention.
  • FIG. 2 is a circuit diagram showing a first drive circuit according to the first embodiment of the present invention
  • FIG. 3 is a diagram showing an isolated power supply for supplying power to the drive circuit of FIG.
  • an n-type MOSFET will be used for the power semiconductor element of the main circuit of the electric drive system 10.
  • the electric drive system 10 includes a DC power source 1, a smoothing capacitor 2, an electric motor drive device 3, an electric motor drive control circuit 4, and an electric motor 5.
  • the DC power supply 1 is used for the power supply of the main circuit, but the present invention is not limited to this.
  • the AC power supply may be rectified and used as a DC power supply.
  • the voltage from the DC power source 1 is smoothed by the smoothing capacitor 2, converted into a three-phase AC by the motor driving device 3, and supplied to the motor 5.
  • the motor drive control circuit 4 controls the operation of the motor drive device 3 in order to control the rotation speed and torque of the motor 5.
  • the electric motor driving device 3 corresponds to each phase of the U phase, the V phase, and the W phase.
  • the high potential side semiconductor elements (upper arms) 31u, 31v, 31w switch between the high potential side bus 21 which is the high potential side and the phase lines of U phase, V phase and W phase.
  • the potential side semiconductor elements (lower arms) 32u, 32v, 32w switch between the low potential side bus 22 which is the low potential side and each of the above phase lines.
  • the high potential side semiconductor element is referred to as an upper arm
  • the low potential side semiconductor element is referred to as a lower arm.
  • the electric motor drive device 3 includes high-potential side drive circuits 33u, 33v, 33w corresponding to the upper arms 31u, 31v, 31w, and low-potential side drive circuits 34u, 34v corresponding to the lower arms 32u, 32v, 32w. , 34w.
  • the motor drive control circuit 4 outputs a control signal sig4u to the high potential side drive circuit 33u and the low potential side drive circuit 34u.
  • the high potential side drive circuit 33u and the low potential side drive circuit 34u operate in a complementary manner. That is, when the high potential side drive circuit 33u turns on the upper arm 31u, the low potential side drive circuit 34u turns off the lower arm 32u. When the high potential side drive circuit 33u turns off the upper arm 31u, the low potential side drive circuit 34u turns on the lower arm 32u.
  • the motor drive control circuit 4 outputs the control signal sig4v to the high potential side drive circuit 33v and the low potential side drive circuit 34v, and outputs the control signal sig4w to the high potential side drive circuit 33w and the low potential side drive circuit 34w. To do.
  • the gate drive power supply for supplying power to the high potential side drive circuits 33u, 33v, 33w and the low potential side drive circuits 34u, 34v, 34w is derived from the voltage charged in the smoothing capacitor 2.
  • 3 is produced via an insulated power source 6 as shown in FIG.
  • the insulated power supply 6 includes, for example, a semiconductor element 23, a transformer 11, two diodes 12, and two smoothing capacitors 13.
  • the insulated power supply 6 can change the voltage according to the ON time of the semiconductor element 23 and the turn ratio of the transformer 11.
  • the drive circuit of the first embodiment will be described with reference to FIG. Since the upper arms 31u, 31v, 31w and the lower arms 32u, 32v, 32w are common, the details of the drive circuit will be described with the low-potential side drive circuit 34u as a representative.
  • the reference numeral 34 for the low-potential side drive circuit is generally used, and 34u, 34v, and 34w are used for distinction.
  • the reference numeral of the high-potential side drive circuit is generally 33, and 33u, 33v, and 33w are used for distinction. Further, since the circuit configurations of the low potential side drive circuit 34 and the high potential side drive circuit 33 are the same, the low potential side drive circuit 34 is simply referred to as a drive circuit 34 as appropriate.
  • the low potential side drive circuit 34 u includes a second DC power supply 61, a third DC power supply 62, a low threshold countermeasure circuit 36, a gate drive circuit 35, and a buffer circuit 75.
  • the second DC power supply 61 corresponds to the upper smoothing capacitor 13 in the insulated power supply 6 in FIG. 3
  • the third DC power supply 62 corresponds to the lower smoothing capacitor 13 in the insulated power supply 6 in FIG.
  • the second DC power supply 61 has a positive bias voltage between the gate terminal (control terminal) and the source terminal (reference terminal) in the power semiconductor element that is the upper arm 31u, 31v, 31w or the lower arm 32u, 32v, 32w. Is a positive voltage supply power source.
  • the third DC power supply 62 has a negative bias voltage between the gate terminal (control terminal) and the source terminal (reference terminal) in the power semiconductor element that is the upper arms 31u, 31v, 31w and the lower arms 32u, 32v, 32w. Is a negative voltage supply power source.
  • a connection point 65 where the negative electrode side of the second DC power supply 61 and the positive electrode side of the third DC power supply 62 are connected is connected to the source terminal side of the lower arm 32u of the main circuit, that is, the low potential bus 22 in FIG. Yes.
  • the gate drive circuit 35 includes an FET 71, a resistor 72, a resistor 73, and an FET 74 connected in series.
  • the FET 71 is a positive side transistor
  • the FET 74 is a negative side transistor.
  • the low threshold value countermeasure circuit 36 includes transistors 78 and 81 and resistors 76, 77, 79 and 80.
  • the positive side of the second DC power supply 61 is connected to the drain terminal of the FET 71 constituting the gate drive circuit 35, and the connection point is connected to one end of the resistor 76 of the low threshold value countermeasure circuit 36.
  • the other end of the resistor 76 is connected to one end of the resistor 77, and the other end of the resistor 77 is connected to the negative electrode side of the third DC power supply 62.
  • the triangular mark attached to the negative electrode side of the third DC power supply 62 indicates the same potential. This triangle mark is the same in other drawings.
  • the source terminal of the FET 71 is connected to one end of the resistor 72, the other end of the resistor 72 is connected to one end of the resistor 73, and the connection point 66 is connected to the gate terminal of the lower arm 32u.
  • the other end of the resistor 73 is connected to the drain terminal of the FET 74, and the source terminal of the FET 74 is connected to the negative side of the third DC power supply.
  • the gate terminals of the FET 71 and FET 74 are connected to the buffer circuit 75.
  • the buffer circuit 75 transmits the control signal sig4u from the electric motor drive control circuit 4 to the FET 71 and the FET 74.
  • connection point 67 between the resistor 76 and the resistor 77 is connected to the base terminal of the transistor 78.
  • the emitter terminal of the transistor 78 is connected to the negative electrode side of the third DC power supply 62.
  • One end of the resistor 79 and one end of the resistor 80 are connected, and the connection point 68 is connected to the base terminal of the transistor 81 and the collector terminal of the transistor 78.
  • the other end of the resistor 79 and the collector terminal of the transistor 81 are connected to the gate terminal of the lower arm 32u.
  • the emitter terminal of the transistor 81 and the other end of the resistor 80 are connected to the negative electrode side of the third DC power supply 62.
  • the resistors 76 and 77 and the transistor 78 constitute a voltage detection circuit 37.
  • the voltage detection circuit 37 in FIG. 2 detects the total voltage of the second DC power supply 61 and the third DC power supply 62.
  • the total voltage value of the second DC power supply 61 and the third DC power supply 62 is charged to a predetermined value or more. Even when the voltage fluctuation dv / dt is applied between the drain and source terminals of the lower arm 32u by the recovery operation of the diode 26, the negative bias voltage is continuously applied between the gate and source of the lower arm 32u. Since a negative bias voltage is applied between the gate and source of the lower arm 32u, even if the voltage between the gate and source terminals of the lower arm 32u rises, the voltage rise is suppressed quickly. The gate-source voltage is suppressed below the threshold voltage of the lower arm 32u, and the lower arm 32u can be kept off.
  • the resistance values R76 and R77 of the resistors 76 and 77 are selected so that the transistor 78 is turned on when the sum of the voltage V61 and the voltage V62 is equal to or greater than a predetermined value.
  • the transistor 78 is turned on, zero V is applied between the base and emitter terminals of the transistor 81, so that the transistor 81 is turned off and the transistor 81 is turned off.
  • the gate terminal of the lower arm 32u is controlled by the gate drive circuit 35 and does not affect the switching operation of the lower arm 32u.
  • the operation of the drive circuit in an abnormal state that is, a state in which the total voltage of the second DC power supply 61 and the third DC power supply 62 has dropped below a predetermined value due to a power failure or the like will be described.
  • the transistor 78 of the low threshold value countermeasure circuit 36 decreases, the transistor 78 is turned off.
  • the transistor 78 is off, a voltage obtained by resistance-dividing the voltage between the connection point 66 and the negative electrode side of the third DC power supply 62 is applied between the base and emitter terminals of the transistor 81. Therefore, in the case where the lower arm 32u is in an off state, zero V is applied between the base and emitter terminals of the transistor 81.
  • the resistor 79 When the lower arm 32u is in the off state and the transistor 78 is in the off state, when the voltage between the gate and source terminals rises due to the voltage fluctuation dv / dt between the drain and source terminals of the lower arm 32u, the resistor 79 The voltage is applied to the connection point 66 side, which is the high potential side, and the negative side of the third DC power supply 62, which is the low potential side of the resistor 80.
  • the resistance value of the resistor 79 is very small compared to the resistance value of the resistor 80 (resistance value of the resistor 79 ⁇ resistance value of the resistor 80)
  • most of the increased voltage is the base-emitter of the transistor 81. Applied between the terminals, the transistor 81 is turned on.
  • the path A is a path of the gate terminal of the lower arm 32u, the transistor 81, the negative side of the third DC power source 62, the positive side of the third DC power source 62, and the source terminal of the lower arm 32u.
  • the path A is formed, so that the gate-source terminal of the lower arm 32u of the main circuit can be maintained in a negative voltage applied state or can be brought to approximately zero V state. .
  • a negative voltage can be applied if the voltage of the third DC power supply 62 remains, and a negative voltage is applied between the gate and source terminals of the lower arm 32u. Can be maintained in a state. Further, when the transistor 81 is turned on and the path A is formed, when the third DC power supply 62 is zero V, zero V is applied between the gate and the source terminal of the lower arm 32u, and the gate of the lower arm 32u -Zero V state between source terminals.
  • FIG. 4 is a circuit diagram showing a driving circuit of a comparative example with respect to the driving circuit of FIG.
  • the emitter terminal of the transistor 81 is connected to the source terminal of the lower arm 32u.
  • the drive circuit 34 according to the first embodiment can apply a negative voltage between the gate and the source terminal of the lower arm 32u when the transistor 81 is turned on. The discharge limit voltage in the voltage between the source terminals can be lowered.
  • the drive circuit 34 of the first embodiment is applied with the voltage fluctuation dv / dt in an abnormal state in which the total voltage value of the second DC power supply 61 and the third DC power supply 62 is lower than a predetermined value. Also, the rise in the gate voltage of the lower arm 32u is suppressed, and it is possible to prevent the lower arm 32u from malfunctioning. In the drive circuit 34 of the first embodiment, the rise of the voltage between the gate and source terminals of the lower arm 32u is suppressed by the operation of the low threshold countermeasure circuit 36, and the transistor 81 is turned off when the voltage value is recovered.
  • the drive circuit 34 is configured to perform initial charging. It is also effective at times.
  • the emitter terminal of the transistor 81 is connected to the negative terminal of the third DC power supply 62, a negative voltage is applied to the gate terminal of the lower arm 32u. In this case, a reverse voltage is not applied between the collector and emitter terminals, which are between the main terminals of the transistor 81. Therefore, there is no need to insert a diode in series with the transistor 81. When the diode is inserted, the forward voltage of the diode is generated between the gate and the source of the lower arm 32u, so that the discharge limit voltage between the gate and the source terminal of the lower arm 32u is increased. On the other hand, since the drive circuit 34 according to the first embodiment does not have a diode connected in series to the transistor 81, the discharge limit voltage between the gate and source terminals of the lower arm 32u can be lowered.
  • the low threshold value countermeasure circuit 36 for preventing the lower arm 32u from erroneously turning on shown in the first embodiment is an example, and satisfies the function of preventing the lower arm 32u from being erroneously turned on induced by the voltage fluctuation dv / dt. It is sufficient that the resistor 81 is connected to the drain or source terminal of the transistor 81 so that the lower arm 32u is not broken due to erroneous firing even when the transistor 81 is used in multiple parallels or when the voltage variation dv / dt is applied for current limiting. You may do it.
  • the drive circuit 34 does not require a reverse breakdown voltage by connecting the transistor 81 as a switching element between the gate terminal of the lower arm 32 u and the negative side of the third DC power supply 62. While using the switching element, it is possible to prevent a malfunction of power semiconductor elements such as the lower arm 32u and the upper arm 31u, and to realize a function of preventing destruction of the power semiconductor element due to malfunction.
  • the drive circuit 34 preferably has a diode 63 connected in antiparallel with the third DC power source 62 as shown in FIG.
  • FIG. 5 is a circuit diagram showing a second drive circuit according to the first embodiment of the present invention.
  • the diode 63 is preferably a diode with a small voltage drop, and SBD (Schottky Barrier Diode) is suitable.
  • SBD Schottky Barrier Diode
  • the transistor 78 when the voltage of the second DC power supply 61 or the voltage of the third DC power supply 62 becomes abnormal, the transistor 78 is turned off, and the lower arm 32u is turned off between the drain and source terminals. For example, when the voltage variation dv / dt occurs and the voltage between the gate and the source of the lower arm 32u increases, the transistor 81 is turned on. In such an abnormal state, a path A is formed of the gate of the lower arm 32u, the transistor 81, the negative terminal of the third DC power source 62, the positive terminal of the third DC power source 62, and the source terminal of the lower arm 32u.
  • FIG. 6 is a circuit diagram showing a third drive circuit according to the first embodiment of the present invention.
  • one end of the resistor 76 is connected to the positive electrode side of the second DC power supply 61, but as shown in FIG. 6, one end of the resistor 76 is connected to the second DC power source. Only the voltage value of the third DC power supply 62 may be detected by connecting to the connection point 65 between the negative side of the power supply and the positive side of the third DC power supply 62.
  • the resistors 76 and 77 Since it is possible to reduce the power loss in the resistors 76 and 77 by detecting only the voltage value of the third DC power supply, in the third example of the drive circuit 34 of the first embodiment, the resistor The effect that 76 and the resistor 77 can be reduced in size can be obtained.
  • FIG. 7 is a circuit diagram showing a fourth drive circuit according to the first embodiment of the present invention.
  • a resistor 85 may be inserted between the gate and source terminals of the lower arm 32u.
  • the resistor 85 discharges the residual charge of the parasitic capacitance of the lower arm 32u, so that the discharge limit voltage is zero. It can be lowered to V.
  • the resistor 85 is connected between the gate terminal and the source terminal of the lower arm 32u to lower the discharge limit voltage when the low threshold countermeasure circuit 36 is operated. The effect that can be obtained.
  • the drive circuit 34 of the first embodiment may be another modified example.
  • a resistor may be inserted between the connection point 67 of the resistor 76 and the resistor 77 in the voltage detection circuit 37 and the base terminal of the transistor 78.
  • a resistor may be inserted between the connection point 68 of the resistor 79 and the resistor 80 in the low threshold value countermeasure circuit 36 and the base terminal of the transistor 81.
  • a capacitor may be inserted between the base terminal and the emitter terminal of the transistor 78.
  • a capacitor may be inserted between the base terminal and the emitter terminal of the transistor 81.
  • the structure of the semiconductor element shown here is an example, and the present invention is not limited to this.
  • the transistors 78 and 81 used in the low threshold value countermeasure circuit 36 may be replaced with FETs, and the FETs 71 and 74 of the gate drive circuit 35 may be replaced with bipolar transistors.
  • a bipolar transistor or IGBT may be used as long as it has a switching function.
  • the diode 26 connected in reverse parallel to the semiconductor element 25 is shown as a body diode of MOSFET, it is not limited to this.
  • the diode 26 only needs to have a function of flowing current in the reverse direction, and an SBD or a PN junction diode may be used in parallel with the MOSFET, or synchronous rectification of the MOSFET may be used.
  • the semiconductor element shown as the semiconductor element 25 and the diode 26 can use the thing using Si semiconductor, the thing using the wide band gap semiconductor whose semiconductor material is a wide band gap semiconductor material is used. It is also possible.
  • wide band gap semiconductor materials include gallium nitride materials and diamond. Since the wide band gap semiconductor can operate at a high temperature, a cooling system such as a heat sink can be simplified, and the device can be downsized. By using a wide band gap semiconductor, a power semiconductor element having a low on-resistance can be used, and a low-loss power converter can be configured.
  • the drive circuit 34 includes the positive voltage supply power source (second DC power source) that supplies a positive bias voltage between the control terminal and the reference terminal in the power semiconductor element (lower arm 32u). 61) and the positive side of the positive voltage supply power source (second DC power source 61) are connected to the positive side, and a negative bias voltage is applied between the control terminal and the reference terminal of the power semiconductor element (lower arm 32u).
  • second DC power source the positive voltage supply power source
  • any of a negative voltage supply power supply (third DC power supply 62) to be supplied, a positive bias voltage for turning on the power semiconductor element (lower arm 32u), and a negative bias voltage for turning off the power semiconductor element (lower arm 32u) Is driven between the control terminal and the reference terminal of the power semiconductor element (lower arm 32u) based on the control signal sig4u of the control circuit (motor drive control circuit 4).
  • a voltage detection unit (voltage detection circuit 37) that detects a detection target voltage that is one of a total voltage of a positive bias voltage and a negative bias voltage, a negative bias voltage, and a positive bias voltage, and a power semiconductor element ( A control terminal of the lower arm 32u) and a switching element (transistor 81) connected to the negative side of the negative voltage supply power source (third DC power source 62).
  • the voltage detection unit (voltage detection circuit 37) in the drive circuit 34 according to the first embodiment has a control terminal and a reference terminal in the power semiconductor element (lower arm 32u) in a state where the value of the detection target voltage is lower than the set voltage value.
  • the switching element (transistor 81) When the voltage between the switching element (transistor 81) increases, the switching element (transistor 81) is turned on, and a voltage of zero V or less is supplied between the control terminal and the reference terminal in the power semiconductor element (lower arm 32u). As a characteristic, even when a voltage fluctuation dv / dt is applied, the switching element (transistor 81) is turned on without applying a reverse voltage between the main terminals (between the collector and emitter terminals) of the switching element (transistor 81). As a result, the power semiconductor element in the off state (lower) can be obtained without using an element having a reverse breakdown voltage for the switching element (transistor 81).
  • the on-drive voltage of the power semiconductor element is in the range of approximately + 10V to + 20V, and is typically + 15V.
  • the off drive voltage is in the range of approximately -5V to -20V, typically -10V.
  • the component needs to have a reverse breakdown voltage capable of withstanding at least ⁇ 5V, and in some cases, a reverse breakdown voltage capable of withstanding ⁇ 20V.
  • FIG. FIG. 8 is a circuit diagram showing a drive circuit according to the second embodiment of the present invention.
  • the power semiconductor element drive circuit 34 according to the second embodiment includes a temperature characteristic of the transistor 78 that detects whether or not the total voltage value of the second DC power supply 61 and the third DC power supply 62 is below a predetermined value. This is an example in which The driving circuit 34 according to the second embodiment is different from the first embodiment in that the variation in operation of the transistor 78 due to the temperature characteristics of the transistor 78 can be reduced or substantially eliminated.
  • a Zener diode 82 which is a constant voltage element is used as an alternative to the resistor 76 shown in FIG.
  • the voltage detection circuit 37 according to the second embodiment includes a Zener diode 82, a transistor 78, and resistors 77 and 83.
  • the positive side of the second DC power supply 61 and the cathode terminal of the Zener diode 82 are connected, and the anode terminal of the Zener diode 82 is connected to one end of the resistor 77.
  • One end of the resistor 83 is connected to a connection point 67 between the anode terminal of the Zener diode 82 and the resistor 77, and the other end of the resistor 83 is connected to the base terminal of the transistor 78.
  • the resistor 83 may be replaced with a wiring resistance.
  • the voltage applied to the transistor 78 is dominantly determined by the Zener voltage of the Zener diode 82, and the influence of the temperature characteristics between the base and the emitter of the transistor 78 is suppressed or eliminated. Can do. This will be described in detail below.
  • FIG. 9 is a diagram showing the Vbe-ib characteristics of the bipolar transistor, and is a schematic diagram showing the relationship between the base-emitter voltage Vbe and the base current ib of the transistor 78 which is a bipolar transistor.
  • the horizontal axis is the base-emitter voltage Vbe, and the vertical axis is the base current ib.
  • three characteristics 90, 91, and 92 are shown, which change from the right characteristic 90 to the left characteristics 91 and 92 as the temperature increases. From FIG. 9, the base current ib flows with a lower base-emitter voltage as the temperature increases.
  • the base current ib flows when the base-emitter voltage is about 0.6 V, and a change of about ⁇ 0.2 V to +0.2 V occurs within the guaranteed operation range of the transistor 78.
  • the change may affect the operation of the low threshold countermeasure circuit 36. Below, it demonstrates in detail using numerical formula.
  • the base current ib when the configuration shown in FIG. 2, that is, the resistor 76 is used is obtained. Assuming that the current flowing through the resistor 77 is ir77 and the base current of the transistor 78 is ib78, equations (2) and (3) are established.
  • Equation (3) is expressed using the base-emitter voltage Vbe78 of the transistor 78.
  • ib78 ⁇ (V61 + V62) -A1 * Vbe78 ⁇ / R76 (4)
  • A1 of Formula (4) is 1 + R76 / R77.
  • the sum of the voltages of the second DC power supply 61 and the third DC power supply 62 (V61 + V62) is the sum of the Zener voltage Vz82 and the base-emitter voltage Vbe78 of the transistor 78 (Vz82 + Vbe78).
  • the base current ib78 does not flow. Therefore, when the condition 1 is satisfied, the transistor 78 does not operate.
  • the base current ib78 starts to flow.
  • the Vbe 78 changes depending on the temperature characteristics, but since the value of Vz82 is generally larger than the value of Vbe78, the change of Vbe78 can be ignored with respect to the value of Vz82.
  • ib78 changes little with respect to the change of Vbe78 by Formula (6). Therefore, since the drive circuit 34 of the second embodiment is configured using the Zener diode 82 for the voltage detection circuit 37, the change in operation of the transistor 78 due to the temperature characteristics of the transistor 78 can be made smaller than that of the first embodiment. .
  • the Zener voltage Vz82 of the Zener diode 82 also has a temperature characteristic. However, by selecting the values of Vz82 and Vbe78 so that the temperature characteristic of the transistor 78 can be ignored with respect to the Zener diode 82 as described above, or approximately. The temperature characteristic of ib78 can be reduced or zero. For this reason, the low threshold value countermeasure circuit 36 of the second embodiment can suppress variation in operating conditions more than that of the first embodiment.
  • the Zener diode 82 is composed of one element, but this is not a limitation. A plurality of the same zener diodes may be connected in series or in parallel, or a plurality of different zener diodes may be connected in series or in parallel.
  • the drive circuit 34 according to the second embodiment uses the Zener diode 82 in the voltage detection circuit 37 that detects the total voltage state of the voltages of the second DC power supply 61 and the third DC power supply 62.
  • the drive circuit 34 according to the second embodiment can suppress the variation in the operation of the transistor 78 due to the temperature characteristics of the transistor 78. Therefore, even if there is a temperature change, the power semiconductor element can be used with higher accuracy than the first embodiment. Can be protected.
  • the drive circuit 34 of the second embodiment reverses between the main terminals (between the collector and the emitter terminal) of the switching element (transistor 81) when the voltage fluctuation dv / dt occurs even when the operating temperature is changed.
  • the switching element (transistor 81) By turning on the switching element (transistor 81) without applying a voltage, the power semiconductor element (lower arm 32u) in the off state can be used without using an element having a reverse breakdown voltage for the switching element (transistor 81).
  • FIG. 10 is a circuit diagram showing a first drive circuit according to the third embodiment of the present invention.
  • the power semiconductor element drive circuit 34 according to the third embodiment is different from the first and second embodiments in that a normally-on type relay 84 is used in the low threshold countermeasure circuit 36.
  • 10, components that are the same as or equivalent to those shown in FIG. 2 are given the same reference numerals. Here, the description will be focused on the portion related to the third embodiment.
  • the normally-on type relay 84 is a four-terminal device including a primary terminal pair composed of primary terminals 43 and 44 and a secondary terminal pair composed of secondary terminals 45 and 46. In a state where current or voltage is not sufficiently supplied to the primary side terminal pair, the secondary side terminal pair is in a low resistance state, and is called normally-on type because it is on. In a state where current or voltage is sufficiently supplied to the primary side terminal pair, the secondary side terminal pair is in a high resistance state and is turned off.
  • a normally-on type relay 84 in which the primary side is the light emitting diode 41 and the secondary side is constituted by the optical MOSFET 42 will be described.
  • the primary side light emitting diode 41 corresponds to the voltage detection circuit 37 in the first and second embodiments
  • the secondary side optical MOSFET 42 corresponds to the transistor 81 in the first and second embodiments.
  • the drive circuit 34 of the third embodiment using the normally-on type relay 84 has a voltage detection unit (light emission) when the value of the detection target voltage, which is the voltage between the primary side terminal pair, is lower than the set voltage value.
  • the diode 41) turns on the switching element (optical MOSFET 42), and supplies a voltage of zero V or less between the control terminal and the reference terminal in the power semiconductor element (lower arm 32u).
  • the normally-on type relay 84 may be a mechanical relay in which the primary side is a coil and the secondary side is constituted by a metal piece contact.
  • the primary side terminal 43 of the normally-on type relay 84 is connected to the positive side of the second DC power supply 61, and the primary side terminal 44 is connected to the negative side of the third DC power supply 62.
  • a resistor is placed in the middle of the wiring between the primary side terminal 43 of the normally-on type relay 84 and the positive side of the second DC power supply 61 and the wiring between the primary side terminal 44 and the negative side of the third DC power supply 62. It may be inserted. By inserting a resistor in the middle of the wiring, excess current passing through the primary terminal pair can be suppressed. In FIG. 10, an example in which no resistor is inserted will be described.
  • the secondary terminal 45 of the normally-on type relay 84 is connected to the gate terminal of the lower arm 32u, and the secondary terminal 46 is connected to the negative electrode side of the third DC power supply 62. Insert a resistor in the middle of the wiring between the secondary terminal 45 of the normally-on type relay 84 and the gate terminal of the lower arm 32u and the wiring between the secondary terminal 46 and the negative side of the third DC power supply 62. Also good. By inserting a resistor in the middle of the wiring, an excessive current passing through the secondary terminal pair can be suppressed. In FIG. 10, an example in which no resistor is inserted will be described.
  • the drive circuit 34 of the third embodiment has a simple circuit configuration in which the normally-on type relay 84 is connected between the gate terminal of the lower arm 32u and the negative side of the third DC power supply 62. Even if an element having a reverse withstand voltage is not used in the optical MOSFET 42 of the normally-on type relay 84, a function of preventing the power semiconductor element (lower arm 32u) from being damaged by erroneous firing can be realized.
  • the drive circuit 34 according to the third embodiment applies a reverse voltage between the main terminals (between the drain and source terminals) of the switching element (the optical MOSFET 42 of the normally-on relay 84) when the voltage fluctuation dv / dt occurs.
  • the switching element (the optical MOSFET 42 of the normally-on type relay 84) is turned on without being switched on, so that the switching element (the optical MOSFET 42 of the normally-on type relay 84) is turned off without using an element having a reverse breakdown voltage. This prevents a positive bias voltage from being charged between the gate and source of the power semiconductor element in the state (lower arm 32u) and malfunctions, and damages to the power semiconductor elements such as the lower arm 32u and the upper arm 31u due to malfunction. Can be prevented.
  • FIG. 11 is a circuit diagram showing a second drive circuit according to the third embodiment of the present invention.
  • the primary side terminal 43 is connected to the positive side of the second DC power supply 61
  • the primary side terminal 44 is connected to the negative side of the second DC power supply 61.
  • the normally-on type relay 84 in FIG. 11 is configured to monitor the voltage of the second DC power supply 61.
  • FIG. 12 is a circuit diagram showing a third drive circuit according to the third embodiment of the present invention.
  • the primary side terminal 43 is connected to the positive side of the third DC power supply 62, and the primary side terminal 44 is connected to the negative side.
  • the normally-on type relay 84 in FIG. 12 is configured to monitor the third DC power supply 62.
  • the drive circuit 34 has a positive voltage supply power source (second DC power source) that supplies a positive bias voltage between the control terminal and the reference terminal in the power semiconductor element (lower arm 32u). 61) and the positive side of the positive voltage supply power source (second DC power source 61) are connected to the positive side, and a negative bias voltage is applied between the control terminal and the reference terminal of the power semiconductor element (lower arm 32u).
  • second DC power source positive voltage supply power source
  • any of a negative voltage supply power supply (third DC power supply 62) to be supplied, a positive bias voltage for turning on the power semiconductor element (lower arm 32u), and a negative bias voltage for turning off the power semiconductor element (lower arm 32u) Is driven between the control terminal and the reference terminal of the power semiconductor element (lower arm 32u) based on the control signal sig4u of the control circuit (motor drive control circuit 4).
  • a voltage detector (a light-emitting diode 41 of a normally-on type relay 84) that detects a path 35, a sum of positive bias voltage and negative bias voltage, or a detection target voltage that is a negative bias voltage, and a power semiconductor element (
  • the switching device (the optical MOSFET 42 of the normally-on relay 84) connected to the control terminal of the lower arm 32u) and the negative side of the negative voltage supply power source (third DC power source 62).
  • the voltage detection unit (the light emitting diode 41 of the normally-on type relay 84) in the drive circuit 34 according to the third embodiment has a switching element (normally-on type relay) when the value of the detection target voltage is lower than the set voltage value.
  • the switching element the optical MOSFET 42 of the normally-on type relay 84
  • the reverse voltage is not applied between the main terminals (between the drain and source terminals) of the switching element (the optical MOSFET 42 of the normally-on type relay 84). Is turned on, the reverse resistance is applied to the switching element (the optical MOSFET 42 of the normally-on type relay 84).
  • Embodiment 4 FIG.
  • any power source in which the primary terminal pair exists in the drive circuit 34 is used. Can be connected to.
  • a connection destination of the primary side terminal pair of the normally-on type relay 84 a power source that is the slowest starting, a power source that is the fastest in power outage, or a power source that has the largest voltage fluctuation range at the time of abnormality is selected.
  • FIG. 13 is a circuit diagram showing a drive circuit according to the fourth embodiment of the present invention.
  • the drive circuit 34 according to the fourth embodiment is different from the third embodiment in that the buffer circuit 75 includes a UVLO unit 86.
  • the second DC power supply 61 or the third DC power supply 62 may become abnormal. If the buffer circuit 75 turns on the FET 71, a positive bias voltage is charged in the input capacitance between the gate and source terminals of the lower arm 32u from the second DC power supply 61 via the resistor 72. When the second DC power supply 61 or the third DC power supply 62 is abnormal, the low threshold countermeasure circuit 36 is in a low resistance state between the secondary terminal pairs, but the gate voltage generated by the low threshold countermeasure circuit 36 is low. Is suppressed by the ON operation of the FET 71.
  • the UVLO unit 86 monitors the power supply voltage of the buffer circuit 75. When the UVLO unit 86 detects that the power supply voltage of the buffer circuit 75 is low, the UVLO unit 86 prohibits the FET circuit 71 from turning on, and the buffer circuit 75 turns on the FET 74. Switch to. When the UVLO unit 86 detects that the power supply voltage of the buffer circuit 75 is low, the buffer circuit 75 turns on the FET 74 regardless of the on instruction and the off instruction from the motor drive control circuit 4. Therefore, even when the second DC power supply 61 or the third DC power supply 62 becomes abnormal, it is possible to obtain an effect that the gate voltage increase suppressing operation by the low threshold value countermeasure circuit 36 is not hindered. Such a function of the UVLO unit 86 may be referred to as an undervoltage lockout function.
  • FIG. 14 is a circuit diagram showing a drive circuit of a comparative example with respect to the drive circuit of FIG.
  • the drive circuit 101 of the comparative example of FIG. 14 is different from the drive circuit 34 of FIG. 13 in that the primary side terminal 44 and the secondary side terminal 46 of the normally-on type relay 84 are connected to the source terminal of the lower arm 32u. Different.
  • the gate terminal and the source terminal of the lower arm 32u are electrically connected.
  • the ON operation of the FET 74 occurs by the ULVO unit 86.
  • paths are formed on the positive side of the third DC power source 62, the source terminal of the lower arm, the gate terminal of the lower arm 32u, the resistor 73, the FET 74, and the negative side of the third DC power source 62.
  • the resistor 73 receives the energy of the third DC power supply 62 and may heat up abnormally.
  • the drive circuit 101 is activated, the voltage increase of the third DC power supply 62 is hindered, and the activation may be delayed.
  • the secondary terminal 45 of the normally-on type relay 84 is connected to the gate terminal of the lower arm 32u, and the secondary terminal 46 is the third DC power supply 62. Is connected to the negative electrode side.
  • the normally-on type relay 84 operates, and the gate of the lower arm 32u and the negative electrode side of the third DC power supply 62 are electrically connected. Even when the FET 74 is turned on by the UVLO unit 86, a path passing through the positive electrode side and the negative electrode side of the third DC power supply 62 and through the FET 74 is not formed.
  • the drive circuit 34 of the fourth embodiment there is no possibility that the resistor 73 is abnormally heated. Further, the drive circuit 34 according to the fourth embodiment does not have a risk of preventing the voltage increase of the third DC power supply 62 even at the time of startup. As described above, the drive circuit 34 according to the fourth embodiment has a feature that an unfavorable problem that occurs in the drive circuit of Patent Document 1 does not occur while enjoying the effect of including the UVLO unit 86.
  • the drive circuit 34 according to the fourth embodiment can include the UVLO unit 86. Even when the second DC power supply 61 or the third DC power supply 62 is abnormal, the normally-on type relay 84 is provided. Even if an element having a reverse withstand voltage is not used for the optical MOSFET 42 of the present invention, there is no abnormal heating of the resistor 73, and the power semiconductor element (lower arm 32u) is prevented from being erroneously turned on. The destruction of power semiconductor elements such as 31u can be prevented.
  • the drive circuit 34 according to the first and second embodiments can also include the UVLO unit 86.
  • the drive circuit 34 according to the first and second embodiments including the UVLO unit 86 does not have an undesired problem that occurs in the drive circuit disclosed in Patent Document 1, while enjoying the effects provided by the UVLO unit 86.
  • the drive circuit 34 according to the first to fourth embodiments is not limited to the electric drive system that operates the electric motor 5 by converting DC power to AC power, and can also be applied to the case of converting AC power to DC power. Further, within the scope of the invention, the present invention can be freely combined with each other, or can be appropriately modified or omitted.
  • Electric motor drive control circuit 31u, 31v, 31w ... Upper arm (power semiconductor element), 32u, 32v, 32w ... Lower arm (power semiconductor element), 34, 34u, 34v, 34w ... Low potential side drive circuit (Drive circuit), 35 ... gate drive circuit, 37 ... voltage detection circuit (voltage detection unit), 43 ... primary side terminal, 44 ... primary side terminal, 45 ... secondary side terminal, 46 ... secondary side terminal, 61 ... Second DC power source, 62 ... Third DC power source, 63 ... Diode, 67 ... Connection point, 71 ... FET (positive side transistor), 74 ... FET (negative side transistor), 75 ... Buffer circuit, 76 ... Resistor, 77 ...

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PCT/JP2015/065257 2014-05-30 2015-05-27 電力用半導体素子の駆動回路 WO2015182658A1 (ja)

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EP15800653.6A EP3151402B1 (en) 2014-05-30 2015-05-27 Power-semiconductor element driving circuit
JP2015558273A JP5989265B2 (ja) 2014-05-30 2015-05-27 電力用半導体素子の駆動回路
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JP2019193406A (ja) * 2018-04-24 2019-10-31 株式会社日立製作所 ゲート駆動回路およびゲート駆動方法
CN111971884A (zh) * 2018-04-24 2020-11-20 株式会社日立制作所 栅极驱动电路和栅极驱动方法
JP2019213445A (ja) * 2018-05-30 2019-12-12 富士電機株式会社 電圧駆動型半導体スイッチング素子のゲート駆動装置、該ゲート駆動装置を備える電力変換装置
JP7259430B2 (ja) 2018-05-30 2023-04-18 富士電機株式会社 電圧駆動型半導体スイッチング素子のゲート駆動装置、該ゲート駆動装置を備える電力変換装置
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