WO2015132926A1 - 半導体装置、及び、その試験方法 - Google Patents
半導体装置、及び、その試験方法 Download PDFInfo
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- WO2015132926A1 WO2015132926A1 PCT/JP2014/055719 JP2014055719W WO2015132926A1 WO 2015132926 A1 WO2015132926 A1 WO 2015132926A1 JP 2014055719 W JP2014055719 W JP 2014055719W WO 2015132926 A1 WO2015132926 A1 WO 2015132926A1
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- semiconductor device
- protective film
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- semiconductor
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- G01R31/26—Testing of individual semiconductor devices
- G01R31/2644—Adaptations of individual semiconductor devices to facilitate the testing thereof
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Definitions
- the present invention relates to a semiconductor device including an electrode pad, and a test method for evaluating electrical characteristics of the semiconductor device by inputting and outputting electricity to the electrode pad.
- a test method for evaluating the electrical characteristics of an object to be measured by bringing a contact probe into contact with an electrode pad of the object to be measured such as a semiconductor wafer or a semiconductor device and then inputting and outputting electricity to the electrode pad is known. It has been. In recent years, the number of pins in contact probes has been increased due to demands for large electric currents input to and output from electrode pads, application of high voltage, and the like.
- Patent Documents 1 and 2 propose techniques for suppressing partial discharge.
- breakage or the like is detected from the upper or lower surface of an object to be measured during electrical evaluation by the OBIRCH method using infrared irradiation of metal, photoemission microscopy using emission detection, infrared spectroscopy, or the like.
- Failure analysis has been proposed (for example, Patent Documents 3 and 4).
- Patent Document 1 With the technique of inspecting in an insulating liquid disclosed in Patent Document 1, it is possible to suppress the discharge that occurs during the characteristic inspection of electronic components. However, there is a problem that an expensive prober is required and the evaluation is performed in a liquid, so that the time required for the evaluation process increases and the cost is not reduced. Further, when the object to be measured is a semiconductor element in a wafer test or a chip test, it has been difficult to completely remove the insulating liquid from the semiconductor element after the evaluation.
- Patent Document 2 With the technique for inspecting in a closed space filled with an inert gas disclosed in Patent Document 2, it is possible to suppress the electric discharge that occurs during the characteristic inspection of the electronic component. However, there is a problem that the configuration of the evaluation apparatus is complicated, the cost is not reduced, and the time for the evaluation process increases.
- the present invention has been made in view of the above-described problems, and an object thereof is to provide a technique capable of suppressing discharge at the time of evaluation.
- a semiconductor device includes a semiconductor substrate having an element region and a termination region adjacent to each other in a plan view, and a plurality of elements disposed on a region separated from the termination region among the element regions of the semiconductor substrate.
- each of the conductive layers extends to the termination region or the vicinity thereof.
- the test method of the semiconductor device includes (a) a step of bringing a plurality of probes into contact with portions near the termination region of the plurality of conductive layers, and (b) after the step (a), And a step of inputting / outputting electricity to / from the plurality of electrode pads via the plurality of probes and the plurality of conductive layers.
- the distance between the probes can be increased, discharge during electrical evaluation can be suppressed.
- 1 is a plan view showing a schematic configuration of a semiconductor device according to a first embodiment.
- 1 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a first embodiment.
- 1 is a plan view showing a schematic configuration of part of a semiconductor device according to a first embodiment;
- 1 is a plan view showing a schematic configuration of part of a semiconductor device according to a first embodiment;
- 1 is a side view showing a schematic configuration of a semiconductor evaluation apparatus according to a first embodiment.
- 6 is a plan view for explaining the semiconductor device testing method according to the first embodiment;
- FIG. FIG. 6 is a plan view showing a schematic configuration of a semiconductor device according to a second embodiment.
- FIG. 6 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a second embodiment.
- FIG. 10 is a plan view for explaining the semiconductor device testing method according to the second embodiment;
- FIG. 6 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a third embodiment.
- FIG. 6 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a third embodiment.
- FIG. 1 is a plan view showing a schematic configuration of a semiconductor device 1 according to the first embodiment of the present invention
- FIG. 2 is a cross-sectional view taken along the line AA in FIG.
- the semiconductor device 1 a semiconductor device having a vertical structure that turns on or off a large current flowing in the out-of-plane direction of FIG. 1, that is, the vertical direction (Z direction) of FIG.
- An IGBT Insulated Gate Bipolar Transistor
- the semiconductor device 1 according to the present embodiment is not limited to this, and may be, for example, a semiconductor device other than an IGBT, or a horizontal structure semiconductor device provided along the horizontal direction. May be.
- FIG. 1 and 2 includes a semiconductor substrate 11, a plurality of electrode pads 12 (two emitter electrodes 12a and one gate electrode 12b) indicated by a two-dot chain line in FIG. 1 includes an insulating protective film 13 provided with an opening 13a indicated by a broken line in FIG. 1, a plurality of conductive layers 14, and a collector electrode 15 shown in FIG.
- FIG. 3 is a plan view showing the semiconductor substrate 11 and the plurality of electrode pads 12.
- the semiconductor substrate 11 has an element region 11a and a termination region 11b that are adjacent to each other in plan view.
- the element region 11a is an inner region from the broken line in FIG. 3
- the termination region 11b is an outer region from the broken line in FIG.
- the element region 11a is a region in which a desired semiconductor element (here, IGBT) including a plurality of electrode pads 12 and an impurity region (not shown) is formed.
- the termination region 11b is a region for maintaining the breakdown voltage of the semiconductor element or the like, and is formed so as to surround the element region 11a in plan view. Here, the termination region 11b will be described as being formed at the peripheral edge of the semiconductor substrate 11.
- a plurality of electrode pads 12 (emitter electrode 12a and gate electrode 12b) and a collector electrode 15 are provided on the front and back surfaces of the element region 11a of the semiconductor substrate 11 so that electrical input / output with the outside can be performed. It has been. Note that the positions and the number of the electrode pads 12 (emitter electrode 12a and gate electrode 12b) and the collector electrodes 15 are not limited to the configuration shown in FIG.
- Each electrode pad 12 (emitter electrode 12a and gate electrode 12b) is disposed on a region of the element region 11a of the semiconductor substrate 11 that is separated from the termination region 11b.
- each electrode pad 12 is made of a transparent conductive film.
- each conductive layer 14 is also composed of a transparent conductive film.
- the transparent conductive film includes zinc oxide having a thickness of about 3 ⁇ m to 5 ⁇ m, for example. According to such a configuration, the process can be shortened and facilitated.
- the transparent conductive film is not limited to this, and may include, for example, ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), SnO 2 , and the like.
- FIG. 4 is a plan view showing a configuration in which an insulating protective film 13 is provided in the configuration shown in FIG.
- the outline of the electrode pad 12 hidden by the protective film 13 is indicated by a two-dot chain line.
- the boundary line between the element region 11 a and the termination region 11 b is omitted.
- the protective film 13 is provided with one opening 13a on each electrode pad 12, and the protective film 13 is arranged on the entire surface of the semiconductor substrate 11 except for the opening 13a. It is installed. That is, the surface of the electrode pad 12 is exposed from the protective film 13 in the opening 13a.
- a material of the protective film 13 a material having a certain degree of transparency, being thermally and chemically stable, and having an excellent insulating performance is used at the time of electrical evaluation.
- a sheet member such as polyimide such as Kapton (registered trademark), polyphenylsilsesquiosaline, or polyvinylsilsesquiosaline, or a photoresist is applied.
- materials other than these may be applied to the material of the protective film 13.
- the protective film 13 is partially removed or stripped to form a pattern, and the post-process is advanced.
- the protective film 13 When the protective film 13 is formed from a photoresist, pattern formation is performed using an ashing process in which the photoresist is partially decomposed and removed, and cleaning is performed as necessary. As described above, when the photoresist is applied to the protective film 13, the protective film 13 can be formed relatively easily using a general semiconductor process, so that the process can be shortened and the cost can be reduced. In addition, the protective film 13 can be provided with a certain degree of transparency.
- the protective film 13 is formed from a polyimide sheet (polyimide sheet member), basically, the polyimide sheet is partially peeled off and removed.
- the protective film 13 can be formed relatively easily, so that the process can be shortened and the cost can be reduced, and the protective film can be realized. 13 can be provided with a certain degree of transparency.
- the adhesive layer is provided in the polyimide sheet, attachment / detachment of the protective film 13 can be made easy.
- the protective film 13 may be composed of a plurality of layers made of different materials or the same material.
- FIG. 1 shows a configuration in which a plurality of conductive layers 14 are arranged in the configuration shown in FIG.
- the opening 13a hidden by the conductive layer 14 is indicated by a broken line.
- the outline of the electrode pad 12 is indicated by a two-dot chain line, and the boundary line (broken line in FIG. 3) between the element region 11a and the termination region 11b is omitted.
- each conductive layer 14 extends to the termination region 11b or the vicinity thereof. In plan view, the conductive layer 14 extends to the vicinity of the termination region 11b.
- the distance between the conductive layer 14 and the termination region 11b is an electrode pad that is electrically connected to the conductive layer 14. It means that the distance between 12 and the termination region 11b is short.
- the conductive layer 14 extends to the termination region 11b.
- the conductive layer 14 extends to the boundary between the element region 11a and the termination region 11b. 2 includes a configuration in which the conductive layer 14 extends beyond the boundary to the inside of the termination region 11b.
- each conductive layer 14 extends to the boundary between the element region 11a and the termination region 11b in plan view. According to such a configuration, the distance between the conductive layer 14 and the other electrode via the end face of the semiconductor device 1 (side face of the semiconductor substrate 11) can be separated to some extent, so that electrical evaluation is possible. The discharge and short circuit between them in time can be suppressed.
- each contact probe probe
- electricity is input to each electrode pad 12 via each contact probe and each conductive layer 14.
- Output A test for evaluating the electrical characteristics of the semiconductor device 1 is performed by such input / output of electricity.
- the conductive layer 14 is made of a transparent conductive film such as zinc oxide having a thickness of about 3 ⁇ m to 5 ⁇ m, but is not limited to this.
- a transparent conductive film such as zinc oxide having a thickness of about 3 ⁇ m to 5 ⁇ m, but is not limited to this.
- ITO, IZO may be constructed from a transparent conductive film such as SnO 2.
- the material may be composed of a plurality of layers of the same kind or different kinds. In such a structure, it can be expected to ensure electrical conductivity and suppress heat generation by reducing the current density.
- the transparent conductive film to be the conductive layer 14 is formed by using, for example, sputtering.
- a photoresist When a photoresist is applied to the protective film 13, it is considered difficult to perform sputtering of the conductive layer 14 using a photoresist capable of forming a fine pattern as a mask.
- the conductive layer 14 is selectively formed by sputtering using a metal mask that can form a pattern to some extent without using a photoresist. It is possible. If a fine pattern needs to be formed on the conductive layer 14, a sheet member may be applied to the protective film 13, and the conductive layer 14 may be formed by sputtering using a photoresist as a mask.
- the upper surface of the electrode pad 12 may be roughened and roughened. Thereby, the adhesiveness and contact property between the electrode pad 12 and the conductive layer 14 can be ensured.
- a roughening method for example, light etching for the electrode pad 12 or short-time sandblasting can be applied.
- FIG. 5 is a side view showing a schematic configuration of the semiconductor evaluation device 5 for evaluating the electrical characteristics of the semiconductor device 1 having the vertical structure described above. Here, it is assumed that the semiconductor evaluation device 5 evaluates the electrical characteristics of a plurality of semiconductor devices 1 formed on one wafer 1 a for each semiconductor device 1.
- the semiconductor evaluation apparatus 5 includes a chuck stage 51 which is a pedestal for fixing the wafer 1a in contact with the installation surface of the wafer 1a (here, the back surface on which the collector electrode 15 is disposed).
- a chuck stage 51 which is a pedestal for fixing the wafer 1a in contact with the installation surface of the wafer 1a (here, the back surface on which the collector electrode 15 is disposed).
- vacuum suction is applied to the fixing means (holding means) of the chuck stage 51.
- the fixing means is not limited to vacuum suction, and for example, electrostatic suction or the like may be applied.
- the electrode that contacts the electrode pad 12 when evaluating the electrical characteristics of the semiconductor device 1 is a contact probe 52.
- a plurality of contact probes 52 are provided on the assumption that a large current is applied.
- the contact probe 52 is provided on a probe base 53, and the probe base 53 includes an insulating base 54 and a connection portion 55 a in addition to the contact probe 52.
- the contact probe 52 is mechanically connected to the insulating base 54, and a connecting portion 55 a is disposed on the insulating base 54.
- metal wiring (not shown) is formed on the insulating base 54, and the contact probe 52 is electrically connected to the connection portion 55a via the metal wiring.
- the connection part 55a is electrically connected to the evaluation part (control part) 57 through the signal line 56a. According to the above configuration, the contact probe 52 is electrically connected to the evaluation unit 57 through the metal wiring provided on the insulating base 54, the connection unit 55a, and the signal line 56a. .
- the semiconductor evaluation device 5 includes an electrode (not shown) formed on the upper surface of the chuck stage 51 as an electrode that contacts the collector electrode 15 when the electrical characteristics of the semiconductor device 1 are evaluated.
- the electrode is electrically connected to a connection portion 55 b provided on the side surface of the chuck stage 51.
- the connection part 55b is electrically connected to the evaluation part (control part) 57 through the signal line 56b.
- the electrode formed on the upper surface of the chuck stage 51 is electrically connected to the evaluation unit 57 via the connection unit 55b and the signal line 56b.
- connection portion 55a that defines the connection position between the signal line 56a and the insulating base 54 and the connection portion 55b provided on the side surface of the chuck stage 51 is substantially the same through any contact probe 52.
- the arrangement positions of the connecting portions 55a and 55b are designed. According to such a configuration, the current density applied to each contact probe 52 can be substantially matched.
- the probe base 53 including the contact probe 52, the insulating base 54, and the connection portion 55a can be moved in any direction by the moving arm 58.
- the wafer 1a that is, the chuck stage 51 side may be moved.
- the plurality of contact probes 52 can come into contact with the plurality of electrode pads 12 of the semiconductor device 1 on the chuck stage 51.
- a through-hole 54a is provided in the insulating base 54 (probe base 53), and a detector / camera 59 used for analysis is installed on the top. According to such a configuration, it is possible to perform failure analysis for detecting breakage from the upper surface of the semiconductor device 1 (measurement object) by means of a photo emission microscope, infrared spectroscopy, or the like during electrical evaluation.
- FIG. 6 is a top view for explaining the test method of the semiconductor device 1 according to the first embodiment.
- the electrical characteristics of a plurality of semiconductor devices 1 formed on one wafer 1a are evaluated for each semiconductor device 1.
- each contact probe 52 is brought into contact with a portion of each conductive layer 14 closer to the termination region 11b than the electrode pad 12 electrically connected thereto.
- a test for evaluating the electrical characteristics of the semiconductor device 1 by inputting / outputting electricity to / from the plurality of electrode pads 12 via the plurality of contact probes 52 and the plurality of conductive layers I do.
- a large current can be applied by bringing a plurality of contact probes 52 into contact with one conductive layer 14.
- the conductive layer 14 and the electrode layer 12 can be compared to the distance between the contact probes 52 when the electrode pads 12 and the contact probes 52 are brought into contact.
- the distance between the contact probes 52 when the contact probes 52 are brought into contact with each other is longer. Therefore, since the distance between the contact probes 52 can be increased, discharge during electrical evaluation can be suppressed.
- the distance between any two conductive layers 14 is greater than the distance between two electrode pads 12 electrically connected to the two conductive layers 14. It is preferable to increase the size. According to such a configuration, since the distance between the two electrode pads 12 can be substantially increased, discharge during electrical evaluation can be suppressed.
- the two emitter electrodes 12a are configured such that two conductive layers 14 that are separated from each other are electrically connected to each other. That is, the emitter electrode 12a and the conductive layer 14 are configured in a one-to-one relationship.
- the two emitter electrodes 12 a are basically at the same potential, the two emitter electrodes 12 a (several predetermined electrode pads 12) are electrically connected to each other by one conductive layer 14 ( Connected). According to such a configuration, the selectivity of the region is facilitated and the simplification of the process can be expected. Moreover, the current concentration at the time of electrical evaluation, and the effect of suppressing heat generation can also be expected.
- the electrical characteristics of the plurality of semiconductor devices 1 formed on one wafer 1 a are evaluated for each semiconductor device 1.
- the present invention is not limited to this, and after the contact process of the contact probe 52 is uniformly performed on a plurality of semiconductor devices 1 (for example, all the semiconductor devices 1) formed on one wafer 1a, An electric input / output process may be uniformly performed on the semiconductor device 1. According to such a configuration, it is possible to shorten the process, improve the throughput, and reduce the test cost.
- the semiconductor device 1 includes at least one of a first barrier metal (not shown) disposed under the electrode pad 12 and a second barrier metal (not shown) disposed under the conductive layer 14.
- a first barrier metal (not shown) disposed under the electrode pad 12
- a second barrier metal (not shown) disposed under the conductive layer 14.
- One may be further provided. According to such a structure, it can suppress that electrode materials, such as a transparent conductive film, grow to the deep part of the element area
- the first and second barrier metals may be tungsten silicide (WSi) members having a thickness of, for example, about 50 nm to 200 nm. According to such a configuration, the effect of the barrier metal can be enhanced.
- WSi tungsten silicide
- the semiconductor device 1 has a configuration in which the protective film 13 is finally left.
- the protective film 13 may be present at the time of evaluation, and may be removed by ashing or peeling after the evaluation.
- an electrode pad (not shown) may be formed using a non-transparent metal as a component after removing the transparent conductive film. As a result, long-term stability can be realized and post-processing can be facilitated.
- FIG. 7 is a plan view showing a schematic configuration of the semiconductor device 1 according to the second embodiment of the present invention
- FIG. 8 is a cross-sectional view taken along the line AA of FIG. Note that in the semiconductor device 1 according to the second embodiment, the same or similar components as those described above are denoted by the same reference numerals, and different portions will be mainly described.
- a plurality (three in this case) of openings 13a are provided in the protective film 13 corresponding to each electrode pad 12 (here, each emitter electrode 12a). Yes. Further, one conductive layer 14 is provided corresponding to each of a plurality (all three in this case) of openings 13 a provided corresponding to one electrode pad 12.
- FIG. 9 is a top view for explaining the test method of the semiconductor device 1 according to the second embodiment. As shown in FIG. 9, in the second embodiment, it is possible to apply a large current by bringing the contact probes 52 into one-to-one contact with the conductive layer 14.
- the semiconductor device 1 and the test method thereof according to the second embodiment as described above not only can the same effect as the first embodiment be obtained, but also the current concentration during electrical evaluation can be suppressed. Therefore, heat generation due to the current can be suppressed.
- three openings 13a and three conductive layers 14 are provided in order to input and output electricity to one emitter electrode 12a via three contact probes 52.
- the number of the openings 13a and the conductive layers 14 is not limited to this.
- the number of the electrode pads 12 made of a transparent conductive film, the input / output current, and the number of the contact probes 52 are matched.
- the number of openings 13a and conductive layers 14 may be increased or decreased.
- the semiconductor device 1 includes the protective film 13 composed of one layer.
- the semiconductor device 1 includes an insulating property composed of a plurality of layers. It has a protective film.
- FIG. 10 is a sectional view showing a schematic configuration of the semiconductor device 1 according to the third embodiment of the present invention.
- the same or similar components as those described above are denoted by the same reference numerals, and different portions are mainly described.
- the semiconductor device according to the third embodiment also includes the conductive layer 14, but the conductive layer 14 is not shown in FIG. 10 for the sake of simplicity.
- a protective film 13-2 of an insulating layer is laminated on the insulating protective film 13-1.
- the materials of the protective films 13-1 and 13-2 may be the same or different.
- the above-described sheet member may be applied to the protective film 13-1, and a photoresist may be applied to the protective film 13-2.
- the opening 13a-1 of the lower protective film 13-1 is formed larger than the opening 13a-2 of the upper protective film 13-2, and electrical evaluation is performed. Later, only the upper protective film 13-2 may be removed, and the lower protective film 13-1 may be left to perform a post-process. Thereby, the wire bond which requires a comparatively big opening part can be easily performed in a post process, for example.
- the protective film 13-1 formed in the previous process is covered with the protective film 13-2 formed in the subsequent process. If comprised in this way, an excessive level
- the same effect as that of the first embodiment can be enhanced by the protective film composed of a plurality of layers. Further, the efficiency of partial removal of the protective film can be improved.
- the partial discharge occurs not only in the element region 11a (the central portion of the semiconductor device 1) as the active region, which is in contact with the contact probe 52, but also in the vicinity of the outer peripheral portion where the termination region 11b is formed. It is known. For this reason, as shown in FIG. 11, a protective film composed of the protective film 13-1 and the protective film 13-2 thereon may be formed only in the vicinity of the termination region 11b. According to such a configuration, the distance between the conductive layer 14 and the other electrode via the end face of the semiconductor device 1 (side face of the semiconductor substrate 11) can be separated to some extent, so that electrical evaluation is possible. The discharge and short circuit between them in time can be suppressed.
- the protective film has been described as having two layers (protective films 13-1 and 13-2). However, the protective film may have three or more layers.
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Abstract
Description
<半導体装置の構成>
図1は、本発明の実施の形態1に係る半導体装置1の概略構成を示す平面図であり、図2は、図1のA-A線に沿った断面図である。ここでは、半導体装置1として、図1の面外方向、つまり図2の縦方向(Z方向)に流れる大きな電流をオンまたはオフする縦型構造の半導体装置を例にして説明し、特に縦型構造の半導体装置として、IGBT(Insulated Gate Bipolar Transistor)を例にして説明する。しかし、本実施の形態に係る半導体装置1は、これに限るものではなく、例えば、IGBT以外の半導体装置であってもよいし、水平方向に沿って設けられた横型構造の半導体装置などであってもよい。
図5は、以上に説明した縦型構造の半導体装置1の電気的特性の評価を行う半導体評価装置5の概略構成を示す側面図である。ここでは、半導体評価装置5は、一つのウェハ1aに形成された複数の半導体装置1の電気的特性の評価を、一つの半導体装置1ごとに行うものとする。
図6は、本実施の形態1に係る半導体装置1の試験方法を説明するための上面図である。なお、本実施の形態1では、上述したように、一つのウェハ1aに形成された複数の半導体装置1の電気的特性の評価を、一つの半導体装置1ごとに行うものとする。
以上のような本実施の形態1に係る半導体装置及びその試験方法によれば、電極パッド12とコンタクトプローブ52とを接触させた場合のコンタクトプローブ52同士の間の距離よりも、導電層14とコンタクトプローブ52とを接触させた場合のコンタクトプローブ52同士の間の距離のほうが長くなっている。したがって、コンタクトプローブ52同士の間の距離を長くすることができるので、電気的な評価時における放電を抑制することができる。
本実施の形態1では、二つのエミッタ電極12aには、互いに離間する二つの導電層14がそれぞれ電気的に接続されているように構成されている。つまり、エミッタ電極12aと導電層14とが一対一で構成されている。しかし、二つのエミッタ電極12aが基本的に同電位となる場合には、二つのエミッタ電極12a(予め定められたいくつかの電極パッド12)が、一つの導電層14によって互いに電気的に接続(連結)されてもよい。このような構成によれば、領域の選択性が容易となり、工程の容易化が期待できる。また、電気的な評価時における電流集中ひいては発熱の抑制効果も期待できる。
図7は、本発明の実施の形態2に係る半導体装置1の概略構成を示す平面図であり、図8は、図7のA-A線に沿った断面図である。なお、本実施の形態2に係る半導体装置1において、以上で説明した構成要素と同一または類似するものについては同じ参照符号を付し、異なる部分について主に説明する。
これまでの実施の形態では、半導体装置1は、1層から構成された保護膜13を備えたが、本発明の実施の形態3では、半導体装置1は、複数の層から構成された絶縁性の保護膜を備えている。
Claims (15)
- 平面視において互いに隣接する素子領域及び終端領域を有する半導体基体と、
前記半導体基体の前記素子領域のうち、前記終端領域から離間した領域上に配設された複数の電極パッドと、
前記半導体基体の前記素子領域及び前記終端領域上に配設され、各前記電極パッド上に開口部が設けられた絶縁性の保護膜と、
前記保護膜上に配設され、前記開口部を介して前記複数の電極パッドとそれぞれ電気的に接続された複数の導電層と
を備え、
平面視において、各前記導電層は前記終端領域またはその近傍まで延設されている、半導体装置。 - 請求項1に記載の半導体装置であって、
各前記電極パッドに対応して、複数の前記開口部が前記保護膜に設けられた、半導体装置。 - 請求項2に記載の半導体装置であって、
一つの前記電極パッドに対応して設けられた複数の前記開口部のそれぞれに対応して、前記導電層が一つずつ配設された、半導体装置。 - 請求項1または請求項2に記載の半導体装置であって、
予め定められたいくつかの前記電極パッドが、一つの導電層によって互いに電気的に接続されている、半導体装置。 - 請求項1または請求項2に記載の半導体装置であって、
平面視において、各前記導電層は前記素子領域及び前記終端領域の境界まで延設している、半導体装置。 - 請求項1または請求項2に記載の半導体装置であって、
平面視において、任意の二つの前記導電層の間の距離は、当該二つの導電層にそれぞれ電気的に接続された二つの前記電極パッドの間の距離よりも大きい、半導体装置。 - 請求項1または請求項2に記載の半導体装置であって、
前記電極パッド及び前記導電層は、透明導電膜から構成される、半導体装置。 - 請求項7に記載の半導体装置であって、
前記透明導電膜は酸化亜鉛を含む、半導体装置。 - 請求項1または請求項2に記載の半導体装置であって、
前記保護膜は、材料が異種または同種である複数の層から構成される、半導体装置。 - 請求項1または請求項2に記載の半導体装置であって、
前記保護膜は、フォトレジストまたはポリイミドシートを含む、半導体装置。 - 請求項10に記載の半導体装置であって、
前記保護膜がポリイミドシートを含む場合に、前記ポリイミドシートには接着層が設けられている、半導体装置。 - 請求項1または請求項2に記載の半導体装置であって、
前記電極パッド下に配設された第1バリアメタル、及び、前記導電層下に配設された第2バリアメタルの少なくともいずれか一つをさらに備える、半導体装置。 - 請求項12に記載の半導体装置であって、
前記第1及び第2バリアメタルは、タングステンシリサイド(WSi)を含む、半導体装置。 - 請求項1に記載の半導体装置を試験する試験方法であって、
(a)前記複数の導電層の前記終端領域近傍の部分にそれぞれ複数のプローブを接触させる工程と、
(b)前記工程(a)の後、前記複数のプローブ及び前記複数の導電層を介して、前記複数の電極パッドに電気の入出力を行う工程と
を備える、半導体装置の試験方法。 - 請求項14に記載の半導体装置の試験方法であって、
一つのウェハに形成された複数の前記半導体装置に対して一律に前記工程(a)が行われた後に、前記複数の半導体装置に対して一律に前記工程(b)が行われる、半導体装置の試験方法。
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DE112014006442T5 (de) | 2016-11-24 |
KR20160113718A (ko) | 2016-09-30 |
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