JP2009087998A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2009087998A JP2009087998A JP2007252201A JP2007252201A JP2009087998A JP 2009087998 A JP2009087998 A JP 2009087998A JP 2007252201 A JP2007252201 A JP 2007252201A JP 2007252201 A JP2007252201 A JP 2007252201A JP 2009087998 A JP2009087998 A JP 2009087998A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 160
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 230000005684 electric field Effects 0.000 abstract description 11
- 239000012141 concentrate Substances 0.000 abstract description 3
- 230000037430 deletion Effects 0.000 abstract 1
- 238000012217 deletion Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 124
- 230000015556 catabolic process Effects 0.000 description 9
- 239000012535 impurity Substances 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 238000005530 etching Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 230000002093 peripheral effect Effects 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 210000000746 body region Anatomy 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
【解決手段】 超接合構造を有する半導体領域の端部に、素子領域を囲む絶縁領域を設ける。素子領域の空乏層は絶縁領域で終端するので、素子領域の端部が曲面形状とならない。つまり、空乏層に内部電界が集中する曲面が存在しないので、終端領域を設けて空乏層の水平方向の広がりを促進する手段をとる必要がない。終端領域は不要となるので、チップサイズの小型化が実現する。あるいは、素子領域の面積を拡大できる。
【選択図】 図1
Description
2 半導体領域
21、211 n型半導体層
22、221、22n p型半導体層
3 チャネル層
6 トレンチ
7 ゲート絶縁膜
8 ゲート電極
9 ソース領域
10 ボディ領域
16 層間絶縁膜
17 ソース電極
18 ゲート配線
19 ドレイン電極
30 絶縁領域
31 凹部
32 絶縁膜
50 空乏層
51 トレンチ
100 MOSFET
101 n+型基板
102 p型半導体層
103 p型ベース層
104 n型ソース拡散層
105 n型半導体層
107 ソース電極
110 p型コンタクト層
SB 基板
E 素子領域
T 終端領域
W1 絶縁領域幅
W2 トレンチ幅
W3 終端領域幅
Wd ダイシングブレード幅
Claims (2)
- 一導電型半導体基板と、
該一導電型半導体基板上に設けられ、一導電型半導体層と逆導電型半導体層を互いに当接して交互に配置し、前記一導電型半導体基板に対して垂直方向に複数のpn接合を形成した半導体領域と、
該半導体領域の表面に設けられた素子領域と、
前記素子領域の外周を囲んで設けられた絶縁領域と、を具備し、
前記絶縁領域は、前記半導体領域の表面から前記半導体基板に達して設けられ、前記絶縁領域の側面が露出するように前記半導体領域の端部に設けられることを特徴とする半導体装置。 - 前記素子領域は、絶縁ゲート型半導体素子が設けられることを特徴とする請求項1に記載の半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007252201A JP2009087998A (ja) | 2007-09-27 | 2007-09-27 | 半導体装置 |
CN2008101617906A CN101399286B (zh) | 2007-09-27 | 2008-09-26 | 半导体装置 |
US12/239,368 US7777316B2 (en) | 2007-09-27 | 2008-09-26 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007252201A JP2009087998A (ja) | 2007-09-27 | 2007-09-27 | 半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2009087998A true JP2009087998A (ja) | 2009-04-23 |
Family
ID=40517685
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007252201A Pending JP2009087998A (ja) | 2007-09-27 | 2007-09-27 | 半導体装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7777316B2 (ja) |
JP (1) | JP2009087998A (ja) |
CN (1) | CN101399286B (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9312331B2 (en) | 2014-09-16 | 2016-04-12 | Kabushiki Kaisha Toshiba | Semiconductor device |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011204935A (ja) * | 2010-03-26 | 2011-10-13 | Mitsubishi Electric Corp | 半導体装置とその製造方法 |
JP5659558B2 (ja) * | 2010-05-20 | 2015-01-28 | 富士電機株式会社 | 超接合半導体装置の製造方法 |
JP2012074441A (ja) | 2010-09-28 | 2012-04-12 | Toshiba Corp | 電力用半導体装置 |
TWI463666B (zh) * | 2012-10-05 | 2014-12-01 | Vanguard Int Semiconduct Corp | 半導體裝置及其製造方法 |
GB201314655D0 (en) * | 2013-08-16 | 2013-10-02 | Cambridge Display Tech Ltd | Hydrophobic bank |
CN106104780B (zh) * | 2014-03-06 | 2018-12-21 | 三菱电机株式会社 | 半导体装置以及其试验方法 |
US9773863B2 (en) * | 2014-05-14 | 2017-09-26 | Infineon Technologies Austria Ag | VDMOS having a non-depletable extension zone formed between an active area and side surface of semiconductor body |
US10468479B2 (en) | 2014-05-14 | 2019-11-05 | Infineon Technologies Austria Ag | VDMOS having a drift zone with a compensation structure |
CN105428397B (zh) * | 2015-11-17 | 2019-07-02 | 深圳尚阳通科技有限公司 | 超结器件及其制造方法 |
CN111951721B (zh) * | 2020-08-24 | 2021-11-02 | 上海天马微电子有限公司 | 驱动背板、发光面板、显示装置以及成型方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003332588A (ja) * | 2002-05-09 | 2003-11-21 | Nippon Inter Electronics Corp | 半導体素子 |
JP2005317828A (ja) * | 2004-04-30 | 2005-11-10 | Sumitomo Electric Ind Ltd | 高電圧車載電力変換用半導体装置の製造方法と高電圧車載電力変換用半導体装置 |
JP2009004547A (ja) * | 2007-06-21 | 2009-01-08 | Toshiba Corp | 半導体装置 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5177028A (en) * | 1991-10-22 | 1993-01-05 | Micron Technology, Inc. | Trench isolation method having a double polysilicon gate formed on mesas |
JP2003101022A (ja) | 2001-09-27 | 2003-04-04 | Toshiba Corp | 電力用半導体素子 |
JP2004342660A (ja) * | 2003-05-13 | 2004-12-02 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2006313892A (ja) | 2005-04-07 | 2006-11-16 | Toshiba Corp | 半導体素子 |
-
2007
- 2007-09-27 JP JP2007252201A patent/JP2009087998A/ja active Pending
-
2008
- 2008-09-26 US US12/239,368 patent/US7777316B2/en active Active
- 2008-09-26 CN CN2008101617906A patent/CN101399286B/zh not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003332588A (ja) * | 2002-05-09 | 2003-11-21 | Nippon Inter Electronics Corp | 半導体素子 |
JP2005317828A (ja) * | 2004-04-30 | 2005-11-10 | Sumitomo Electric Ind Ltd | 高電圧車載電力変換用半導体装置の製造方法と高電圧車載電力変換用半導体装置 |
JP2009004547A (ja) * | 2007-06-21 | 2009-01-08 | Toshiba Corp | 半導体装置 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9312331B2 (en) | 2014-09-16 | 2016-04-12 | Kabushiki Kaisha Toshiba | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
CN101399286A (zh) | 2009-04-01 |
US20090096030A1 (en) | 2009-04-16 |
US7777316B2 (en) | 2010-08-17 |
CN101399286B (zh) | 2011-06-22 |
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