WO2015089917A1 - 用于平板显示的goa电路及显示装置 - Google Patents

用于平板显示的goa电路及显示装置 Download PDF

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Publication number
WO2015089917A1
WO2015089917A1 PCT/CN2014/070120 CN2014070120W WO2015089917A1 WO 2015089917 A1 WO2015089917 A1 WO 2015089917A1 CN 2014070120 W CN2014070120 W CN 2014070120W WO 2015089917 A1 WO2015089917 A1 WO 2015089917A1
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WIPO (PCT)
Prior art keywords
circuit
gate
drain
thin film
film transistor
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PCT/CN2014/070120
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English (en)
French (fr)
Inventor
虞晓江
李文英
李长晔
赖梓杰
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深圳市华星光电技术有限公司
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Priority to US14/241,079 priority Critical patent/US9530371B2/en
Publication of WO2015089917A1 publication Critical patent/WO2015089917A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/188—Organisation of a multiplicity of shift registers, e.g. regeneration, timing or input-output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0204—Compensation of DC component across the pixels in flat panels

Definitions

  • the driving of the horizontal scanning line of the active flat panel display panel is mainly completed by the external IC of the panel, and the external IC can control the stepwise charging and discharging of the horizontal scanning lines connected to the pixel (pixel) of the panel.
  • the GO A technology that is, the Gate Driver on Array technology, can use the original process of the flat panel display panel to make the horizontal scan line driving circuit on the substrate around the display area, so that it can be replaced by an external IC.
  • GOA technology simplifies the manufacturing process of the display panel, eliminating the IC bonding process in the horizontal scanning line direction, which has the opportunity to increase productivity and reduce costs, and can improve the integration of flat panel display panels to make it more suitable for narrow borders or A borderless display product.
  • the existing GOA circuit usually includes a plurality of cascaded GOA units, and each level of the GOA unit corresponds to driving a level one horizontal scanning line.
  • the main structure of the GOA unit includes a Pui-up part, a pull-up ccmtroi part, a Transfer Part, a Key Pull-down Part, and Next; fiii down Holding Part, and the bootstrap (Boast) capacitor responsible for potential uplift.
  • the pull-up circuit is mainly responsible for outputting the clock signal (Clock) as a gate signal;
  • the pull-up control circuit is responsible for controlling the opening time of the pull-up circuit, and generally connecting the downlink signal or the Gate signal transmitted by the GOA circuit of the previous stage;
  • the circuit is responsible for pulling Gate low to low level at the first time, that is, turning off the Gate signal;
  • the pull-down sustain circuit is responsible for maintaining the Gate output signal and the Gate signal of the pull-up circuit (commonly referred to as Q point) in the off state (Holding). That is, the negative potential), usually two pull-down maintenance modules alternate;
  • the bootstrap capacitor (C boast) is responsible for the secondary rise of the Q point, which is beneficial to the G (N) output of the pull-up circuit.
  • the purpose of the GOA circuit is to output the scan waveform output from the integrated circuit through circuit operation, so that the pixel switch is turned on to input a data signal to the indium tin oxide (ITO) electrode. After the data signal is input, the data signal content is held until the next frame is turned on.
  • ITO indium tin oxide
  • the scanning circuit is turned off (hold) for a much longer time than the scanning time, and the specific requirements for the stability of the thin film transistor in the GOA circuit are high.
  • the high temperature stability of GOA circuits is affecting the application of GOA technology. One of the important factors. At high temperatures, the leakage of the thin film transistor that makes up the G0A circuit becomes large, and the output waveform of the GOA circuit may be abnormal. Summary of the invention
  • Another object of the present invention is to provide a display device using the above GOA circuit, which reduces the influence of thin film transistor leakage on the output of the GOA circuit at a high temperature, and improves the high temperature performance of the GOA circuit output.
  • the present invention provides a GOA circuit for flat panel display, comprising a plurality of cascaded GOA units, and controlling charging of an nth horizontal scanning line of a display area according to a level II GOA unit, the nth stage
  • the GOA unit includes a pull-up circuit, a pull-down circuit, a pull-down sustain circuit, a pull-up control circuit, a downlink circuit, and a bootstrap capacitor; the pull-up circuit, the pull-down circuit, the pull-down sustain circuit, and the bootstrap capacitor respectively correspond to the cabinet signal point and the a second horizontal scanning line is connected, and the pull-up control circuit and the lower transmission circuit are respectively connected to the gate signal point;
  • the downlink circuit includes:
  • a first thin film transistor having a gate connected to the gate signal point, and a drain and a source respectively inputting an nth-level clock signal and an output start signal;
  • the upper control circuit includes ':
  • a second thin film transistor having a gate inputting an activation signal from the n-th stage GOA unit, and a drain and a source respectively connected to the 11-2th level flat scan line and the gate signal point;
  • the third thin film transistor has a gate connected to the n-th level horizontal scanning line, and a drain and a source respectively connected to the n-1th horizontal scanning line and the drain signal point.
  • the pull-down maintaining circuit comprises:
  • a fourth thin film transistor having a gate connected to the first circuit point, a drain and a source respectively connected to the nth horizontal scanning line and an input first DC low voltage
  • a fifth thin film transistor having a gate connected to a second circuit point, a drain and a source respectively connected to the nth horizontal scanning line and inputting the first DC low voltage
  • a sixth thin film transistor having a gate connected to the first circuit point, and a drain and a source respectively connected to the nth- ith horizontal scan line and the gate signal point;
  • a seventh thin film transistor having a gate connected to the second circuit point, and a drain and a source respectively connected to the n-1th horizontal scanning line and the gate signal point;
  • An eighth thin film transistor having a gate connected to the gate signal point, and a drain and a source respectively connected to the gate a first circuit point and inputting the first DC low voltage;
  • a ninth thin film transistor having a tree pole connected to the * pole signal point, a drain and a source respectively connected to the second circuit point and inputting the first DC low voltage;
  • a tenth thin film transistor having a gate inputting a first clock signal, a drain and a source respectively inputting the first clock signal and connecting the first circuit point;
  • the eleventh thin film transistor has a gate inputting a second clock signal, and the drain and the source respectively input the first clock signal and are connected to the first circuit point;
  • a twelfth thin film transistor having a drain inputting the second clock signal, a drain and a source respectively inputting the second clock signal and connecting the second circuit point;
  • a thirteenth thin film transistor wherein a first-pole signal is input to the first-pole, and a drain and a source are respectively input to the second clock signal and connected to the second circuit point;
  • the first clock signal and the second clock signal have a lower frequency than the nth-level clock signal, and the first circuit point and the second circuit point are alternately subjected to the first clock signal and the second clock signal Charging is at a high potential.
  • the pull-up circuit comprises: a fourteenth thin film transistor, the cabinet is connected to the cabinet signal point, and the drain and the source respectively input the nth-level clock signal and connect the n-th horizontal scanning line.
  • the pull-down circuit comprises: a fifteenth thin film transistor having a gate connected to the n++2 horizontal scanning line, a drain and a source respectively connected to the nth horizontal scanning line and inputting the DC low voltage; A thin film transistor having a gate connected to the n+2th horizontal scan line, a drain and a source respectively connected to the gate signal point and inputting the DC low voltage.
  • the duty ratio of the nth-level clock signal is less than 50%.
  • the duty ratio of the nth-level clock signal is 40%.
  • the first clock signal is input to the cascaded plurality of GOA units through a common metal line.
  • the second clock signal is input to the cascaded plurality of GOA units through a common metal line.
  • the DC low voltage is input to the cascaded plurality of GOA units through a common metal line.
  • the present invention further provides a GOA circuit for flat panel display, comprising a plurality of cascaded GOA units, and controlling charging of the n-th horizontal scanning line of the display area according to the n-th stage GOA unit, the n-th level GOA unit including Pull-up circuit, pull-down circuit, pull-down sustain circuit, pull-up control circuit, down-transmission circuit and bootstrap capacitor; the pull-up circuit, pull-down circuit.
  • a pull-down sustaining circuit and a bootstrap capacitor are respectively connected to the gate signal point and the n-th horizontal scanning line, and the pull-up control circuit and the lower transmission circuit are respectively connected to the gate signal point;
  • the downlink circuit includes:
  • a first thin film transistor having a tree pole connected to the * pole signal point, and a drain and a source respectively inputting an nth stage clock signal and an output start signal;
  • the pull-up control circuit includes:
  • a second thin film transistor having a gate input signal from an nth-stage GOA unit, and a drain and a source respectively connected to the n-2th horizontal scan line and the gate signal point;
  • a third thin film transistor having a gate connected to the n-1th horizontal scanning line, and a drain and a source respectively connected to the n-1th horizontal scanning line and the gate. signal point;
  • the pull-down maintaining circuit comprises:
  • a fourth thin film transistor having a bridge connected to the first circuit point, a drain and a source respectively connected to the nth horizontal scan line and an input first DC low voltage;
  • a fifth thin film transistor having a gate connected to the second circuit point, a drain and a source respectively connected to the nth horizontal scanning line and inputting the first DC low voltage
  • a sixth thin film transistor having a tree pole connected to the first circuit point, and a drain and a source respectively connected to the n-1th horizontal scan line and the gate signal point;
  • a seventh thin film transistor having a gate connected to the second circuit point, and a drain and a source respectively connected to the n-ith horizontal scan line and the gate signal point;
  • An eighth thin film transistor having a gate connected to the gate signal point, a drain and a source respectively connected to the first circuit point and inputting the first DC low voltage;
  • a ninth thin film transistor having a gate connected to the gate signal point, a drain and a source respectively connected to the second circuit point and inputting the first DC low voltage
  • a tenth thin film transistor having a gate inputting a first clock signal, a drain and a source respectively inputting the first clock signal and connecting the first circuit point;
  • the eleventh thin film transistor has a gate inputting a second clock signal, and the drain and the source respectively input the first clock signal and are connected to the first circuit point;
  • a twelfth thin film transistor having a gate inputting the second clock signal, a drain and a source respectively inputting the second clock signal and connecting the second circuit point;
  • a thirteenth thin film transistor having a gate inputting the first clock signal, a drain and a source respectively inputting the second clock signal and connecting the second circuit point;
  • the first clock signal and the second clock signal have a lower frequency than the nth-level clock signal, and the first circuit point and the second circuit point are alternately subjected to the first clock signal and the second clock signal Charging and being at a high potential;
  • the pull-up circuit includes: a fourteenth thin film transistor, the sump and the pole are connected to the bridge signal point, and the drain and the source respectively input the nth-level clock signal and are connected to the second-level horizontal scan line;
  • the pull-down circuit includes: a fifteenth thin film transistor having a drain connected to the n+2th horizontal scan line, a drain and a source respectively connected to the nth horizontal scan line and inputting the DC low voltage; a thin film transistor having a gate connected to the ⁇ +2 horizontal scanning line, a drain and a source respectively connected to the gate signal point and inputting the DC low voltage;
  • the duty ratio of the nth stage clock signal is less than 50%.
  • the duty ratio of the nth-level clock signal is 40%.
  • the first clock signal is input to the cascaded plurality of GOA units through a common metal line.
  • the second clock signal is input to the plurality of cascaded GOA units via a common metal line.
  • the DC low voltage is input to the cascaded plurality of GOA units through a common metal line.
  • the present invention also provides a display device comprising the above-described flat panel display
  • the GOA circuit for flat panel display of the present invention can improve the stability of the GOA circuit and related display device at high temperatures and reduce the RC delay of the GOA charging signal.
  • a low-cost narrow-frame or borderless flat panel display product can be fabricated using the GOA circuit of the present invention.
  • FIG. 1 is a circuit diagram of an embodiment of a GOA circuit (single stage) for flat panel display of the present invention
  • FIG. 2 is a schematic diagram of an output waveform of a GOA circuit for flat panel display at 80 ° C according to the present invention
  • FIG. 3 is a schematic diagram of a multi-level architecture of a GOA circuit for flat panel display according to the present invention.
  • Fig. 4 is a view showing the configuration of a flat panel display device to which the GOA. circuit for flat panel display of the present invention is applied. detailed description
  • the GOA circuit of the present invention may include a plurality of cascaded GOA units, and control the n-th horizontal scanning line G(n) of the display area according to the n-th stage GOA unit control, the n-th stage GOA unit including the pull-up circuit 100, Circuit 200, pull-down sustain circuit 300, pull-up control circuit 400, down-conversion circuit 500 and bootstrap capacitor Cb; pull-up circuit 100, pull-down circuit 200, lower
  • the pull-up maintaining circuit 300 and the bootstrap capacitor Cb are respectively connected to the tree-pole signal point Q ( ⁇ ) and the n-th horizontal scanning line G(n), and the pull-up control circuit 400 and the down-converting circuit 500 respectively and the gate signal Point Q (n) is connected.
  • the pull-up circuit 100 includes: a thin film transistor T21 that directly controls charging of the nth horizontal scanning line G(n) of the display region, the ⁇ -pole connecting the gate signal point (Q( ⁇ )), the drain of the T21 And inputting the n-th clock signal CK(n) and the potential connected to the n-th horizontal scanning line G(n), and the potential of the gate Q(n) of T21 can directly affect CK(n) to G(ii) Charging.
  • a thin film transistor T21 that directly controls charging of the nth horizontal scanning line G(n) of the display region, the ⁇ -pole connecting the gate signal point (Q( ⁇ )), the drain of the T21 And inputting the n-th clock signal CK(n) and the potential connected to the n-th horizontal scanning line G(n), and the potential of the gate Q(n) of T21 can directly affect CK(n) to G(ii) Charging.
  • the pull-down circuit 200 includes a group of thin film transistors that discharge at the end of G(n) charging, including T31 that discharges G(n) and T41 that discharges Q(ii); T31 gates connect to n+ Level 2 horizontal scanning line G (n+2), the drain and source are respectively connected to the nth horizontal scanning line G (II) and the input DC low voltage VSS; T41 is connected to the n+2 level horizontal scanning Line G (n+2), the drain and source are connected to the gate signal point Q (n) and the input DC low voltage VSS, respectively; T31 and T41 can be turned on and discharged when G(n+2) is at a high potential.
  • the down circuit 500 includes a thin film transistor T22, the drain of which is connected to the gate signal point Q (11), and the drain and the source respectively input the 11th stage clock signal CK(n) and the output start signal ST(n);
  • the pull-up control circuit 400 includes: a thin film transistor T11 whose gate input is an start signal ST(n-2) from the 1st to 2nd stage GOA unit, and the drain and the source are respectively connected to the n-th level horizontal scanning line (G (n-2) :) and the gate signal point (Q (n) ); the thin film transistor T12 has a gate connected to the n-1th horizontal scanning line G (n-1 ), and the drain and the source are respectively connected The n-1th horizontal scanning line G (n-1) and the bridge signal point Q(II).
  • one thin film transistor T12 is added to charge Q(n) to compensate for the leakage of Q(n) before bootstrap, so that Q(n) can be maintained before bootstrapping at high temperature. More stable.
  • the thin film transistors Tli, T12 and T22 can control the transfer signal ST of the pre-stage GOA circuit to the GOA circuit of the present stage, so that the GOA circuit can be charged and discharged step by step.
  • a capacitor Cb with a bootstrap function connected between Q(n) and G(ri) can increase the Q(n) potential by the coupling effect of Cb when the G(n) potential is raised, thereby obtaining a higher Q. (n) Potential and smaller RC delay of the GOA charging signal.
  • the pull-down sustain circuit (300) includes a set of thin film transistors that can maintain the low potential of G(n) and Q(n) during the non-charging period of the GOA circuit.
  • the pull-down maintaining circuit (300) comprises: a thin film transistor T32 having a pole connected to the first circuit point P, a drain and a source respectively connected to G(n) and an input first DC low voltage VSS; a thin film transistor T33, the gate thereof The pole is connected to the second circuit point ⁇ , the drain and the source are respectively connected to G ( ⁇ ) and the input first DC low voltage VSS; the thin film transistor ⁇ 42 has a gate connected to the first circuit point ⁇ , and the drain and the source are respectively connected G (n-1 ) and gate signal point Q (n); thin film transistor T43, the drain of which is connected to the second circuit point ⁇ , the drain and the source are respectively connected to G ( ⁇ - 1 ) and the drain signal point Q ( ⁇ ); the thin film transistor ⁇ 52 has a gate connection gate
  • the frequencies of the low frequency clock signal ECK and the low frequency clock signal EXCK are lower than the high frequency clock signal CK(n), and the first circuit point P and the second circuit point K are alternately subjected to the low frequency clock signal ECK and the low frequency clock signal EXCK.
  • Charging is at a high potential, thereby alternately controlling the opening of the thin film transistors T32 & T42 or T33 & T43 to maintain the low potential of G(n) or Q(n) during the non-charging period.
  • the thin film transistors T54 and T64 can be alternately turned on according to the potentials of the low frequency clock signals EXCK and ECK to discharge the P point or the K point, which can better ensure the alternate operation of the T32&T42 and T33&T43, so as to avoid the long-term exposure of the thin film transistor to the gate voltage.
  • the effect of stress increases the operational life of the GOA circuit.
  • the thin film transistor T52 is connected to the P point and the DC low voltage Vss
  • the thin film transistor T62 is connected to the K point and the DC low voltage Vss
  • the T52 and T62 can be turned on when the Q(n) is at a high potential, and the T32, ⁇ 42, ⁇ 33, and ⁇ 43 are turned off. Does not affect Q(n) and G(n) charging.
  • the GOA circuit of the present invention can make the Q(n) voltage of the gate of the thin film transistor controlling the charging of the horizontal scanning line become more stable before the bootstrap at a high temperature, so there is an opportunity to improve the high temperature stability of the GOA circuit and reduce the GOA charging signal.
  • Resistor delay (C delay ) Resistor delay . Specifically: 1. The connection method of the thin film transistors T42 and T43 for maintaining the potential of Q(n) in the non-charging period can reduce the leakage of Q(n) before bootstrap at high temperature; 2. Increase in the GOA circuits at all levels The thin film transistor charges Q(ii) to compensate for the leakage of Q(n) before bootstrap.
  • FIG. 2 is a schematic diagram of an output waveform of the GOA circuit for flat panel display at 801:, wherein the duty ratio of the high frequency clock signal CK(n) is less than 50%, specifically 40%.
  • tl ⁇ i:4 is the preparation time before G(n) charging
  • i.4 ⁇ t5 is the charging time of G(n)
  • G(n) is discharged after t5.
  • the low frequency clock signal ECK and the low frequency clock signal EXCK can be selected to have the same frequency and opposite phases.
  • Figure 2 can be understood in conjunction with Figure 1.
  • the potential of CK(n 2) starts to rise, and the potentials of G(n-2) and ST(n-2) also start to rise, and the thin film transistor Tl i Turn on Q(n) charging.
  • the potential of CK(n-i) starts to rise, and the thin film transistor T12 is also turned on to charge Q(n).
  • the thin film transistors T52 and T62 can be turned on, thereby turning off T32, ⁇ 42 ⁇ 33, and ⁇ 43 so as not to affect Q(n) and G(n) charging.
  • the potential of CK.(n-2) begins to decrease, the potentials of G(n-2) and ST(n2) decrease, and the thin film transistor T11 has a certain leakage.
  • the transistor transistors T21 and T22 are turned on, Q(n) is bootstrapped to a higher potential and T21 is charged to charge G(n) and T22 is charged to ST(ii). Since the initial rise time of the G(n-) potential: 2 is earlier than the initial rise time t4 of the G(n) potential, the circuit structure connecting the drains of T42 and T43 to G(n 1) is relative to the T42 and The circuit structure of the drain of T43 connected to the second DC low voltage Vss2 (not shown) can reduce the leakage of Q(n) through the thin film transistors T42 and T43 before bootstrap.
  • T52 and T62 are turned off, T32&T42 or T33&T43 can be alternately turned on to maintain the low potential of G(n) or Q(n) during the non-charging period.
  • the present invention enables the GOA circuit Q(n The voltage before bootstrap is more stable at high temperatures, so there is a chance to obtain a higher charge period Q(n) voltage and a smaller GOA charge signal RC delay.
  • FIG 3 there is shown a multi-level architectural schematic of a GOA circuit for flat panel display of the present invention.
  • Figure 3 shows a multi-level connection method of the GOA circuit of the present invention.
  • the low-frequency clock signals ECK and EXCK, the DC low-voltage Vss, and the CK1-CK4 four high-frequency clock signals are placed on the GOA circuits of each stage. Peripheral, GOA circuits at all levels (see Figure i for internal connections).
  • connection method shown in Fig. 3 ensures that the start signal ST(n) of the GO A circuit can be transferred step by step, so that the horizontal scanning lines of each level can be charged and discharged step by step.
  • the input activation signal can be used instead of the missing signal input.
  • the GOA circuit of the present invention can be fabricated on the substrate around the display area by using the original process of the flat panel display panel, so that it can replace the external IC to complete the horizontal scanning line driving of the flat panel display panel.
  • the invention is particularly suitable for making flat-panel display products with narrow borders or no borders.
  • FIG. 4 it is a flat panel display of a GOA circuit for flat panel display to which the present invention is applied.
  • the flat panel display device has a display substrate 10, and the drive control panel 20 above the display substrate 10 provides driving and control signals for the display substrate 10.
  • the left side of the display substrate 10, the region 30 and the right region 40 are fabricated with GOA circuits, which are available from the left side.
  • the horizontal scanning line of the display area 50 is driven in the right direction.
  • the GOA circuit accepts the input signal of the drive control board 20 and generates a control signal of the horizontal scan line step by step, and can control the pixels in the display area 50 to be turned on line by line.
  • the present invention can improve the stability of the GOA circuit (using a high frequency clock signal with a duty ratio less than 50%) and the related display device at a high temperature, and reduce the RC delay of the GOA charging signal.
  • the low-cost narrow-frame or borderless flat panel display product can be produced by using the GOA circuit of the present invention.

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Abstract

一种用于平板显示的GOA电路及显示装置。该GOA电路包括级联的多个GOA单元，GOA单元包括上拉控制电路(400)及下传电路(500)。下传电路(500)包括第一薄膜晶体管(T22)，其栅极连接栅极信号点(Q(n))，漏极和源极分别输入时钟信号(CK(n))和输出开动信号(ST(n))。上拉控制电路(400)包括：第二薄膜晶体管(T11)，其栅极输入开动信号(ST(n-2))，漏极和源极分别连接水平扫描线(G(n-2))和栅极信号点(Q(n))；第三薄膜晶体管(T12)，其栅极连接水平扫描线(G(n-1))，漏极和源极分别连接水平扫描线(G(n-1))和栅极信号点(Q(n))。该GOA电路及相应显示装置具有在高温下的稳定性。

Description

于平板显示的 GO A电路及显示装置
GOA
Figure imgf000003_0001
( Gate Driver on Array, ί^·歹| * ) 电路及显示装置。 背景;
目前主动式平板显示面板水平扫描线的驱动主要由面板外接的 IC 来 完成， 外接 IC 可以控制面板各级像素 （pixel )相连的水平扫描线的逐级 充电和放电。 而 GO A技术， 即 Gate Driver on Array (阵列基板行驱动） 技术， 可以运用平板显示面板的原有制程将水平扫描线的驱动电路制作在 显示区周围的基板上， 使之代替外接 IC 来完成水平扫描线的驱动。 GOA 技术能简化显示面板的制作工序， 省去水平扫描线方向的 IC 绑定 ( bonding ) 工艺， 有机会提升产能并降低成本， 并且可以提升平板显示面 板的集成度使之更适合制作窄边框或无边框的显示产品。
现有的 GOA电路， 通常包括级联的多个 GOA单元， 每一级 GOA单 元对应驱动一级水平扫描线。 GOA单元的主要结构包括上拉电路（Puii- up part ) , 上 4立控制电各（ Pull- up ccmtroi part ) ， 下传电路 (Transfer Part), 下 ii电珞 ( Key Pull-down Part ) 和下； f.i维 电 i¾- ( Puii down Holding Part ) ， 以及负责电位抬升的自举（ Boast ) 电容。 上拉电路主要负责将时 钟信号 （Clock )输出为柵极（Gate )信号； 上拉控制电路负责控制上拉电 路的打开时间， 一般连接前面级 GOA 电路传递过来的下传信号或者 Gate 信号； 下拉电路负责在第一时间将 Gate 拉低为低电位， 即关闭 Gate 信 号； 下拉维持电路則负责将 Gate输出信号和上拉电路的 Gate信号 （通常 称为 Q点） 维持（Holding )在关闭状态 （即负电位） ， 通常有两个下拉 维持模块交替作用； 自举电容（ C boast )则负责 Q点的二次抬升， 这样有 利于上拉电路的 G(N)输出。
GOA 电路的目的就是将集成电路输出的扫描波形通过电路操作的方 式输出， 使像素开关打开从而可以向氧化铟锡 （ITO ) 电极输入数据信 号。 数据信号输入完后将数据信号内容保持住直到下一帧的开启。 在电路 操作过程中， 因一条扫描电路打开过后在一帧剩余的时间里都是关闭的， 扫描电路关闭 （保持） 时间比扫描时间长很多， 对 GOA 电路中的薄膜晶 体管稳定特定要求很高。 GOA电路的高温稳定性是影响 GOA技术应用的 重要因素之一。 高温下， 组成 G0A 电路的薄膜晶体管的漏电变大， GOA 电路的输出波形可能出现异常。 发明内容
因此， 本发明的目的在于提供一种用于平板显示的 GOA 电路， 减少 高温下薄膜晶体管漏电对 GOA电路输出的影响， 提升 GO A电路输出的高 温稳定性。
本发明的另一目的在于提供一种应用上述 GOA 电路的显示装置， 减 少高温下薄膜晶体管漏电对 GOA电路输出的影响， 提升 GOA电路输出的 高温 定性。
为实现上述目的， 本发明提供了一种用于平板显示的 GOA 电路， 包 括级联的多个 GOA单元， 按照第 II级 GOA单元控制对显示区域第 n级水 平扫描线充电， 该第 n级 GOA单元包括上拉电路， 下拉电路， 下拉维持 电路， 上拉控制电路， 下传电路及自举电容； 该上拉电路、 下拉电路、 下 拉维持电路及自举电容分别与櫥极信号点和该第 Ώ级水平扫描线连接， 该 上拉控制电路和下传电路分别与该柵极信号点连接；
该下传电路包括：
第一薄膜晶体管， 其栅极连接该栅极信号点， 漏极和源极分别输入第 n級时钟信号和输出开动信号；
该上 ^控制电路包括'：
第二薄膜晶体管， 其柵极输入来自第 n- 2 级 GOA单元的开动信号， 漏极和源极分别连接第 11-2级氷平扫描线和该栅极信号点；
第三薄膜晶体管， 其栅极连接第 n- 1 级水平扫描线， 漏极和源极分别 连接该第 n- 1级水平扫描线和该槲极信号点。
其中， 该下拉维持电路包括：
第四薄膜晶体管， 其栅极连接第一电路点， 漏极和源极分别连接该第 n级水平扫描线和输入第一直流低电压；
第五薄膜晶体管， 其柵极连接第二电路点， 漏极和源极分别连接该第 n级水平扫描线和输入该第一直流低电压；
第六薄膜晶体管， 其栅极连接该第一电路点， 漏极和源极分别连接该 第 n»i级水平扫描线和该栅极信号点；
第七薄膜晶体管， 其柵极连接该第二电路点， 漏极和源极分别连接该 第 n-1级水平扫描线和该栅极信号点;
第八薄膜晶体管， 其柵极连接该柵极信号点， 漏极和源极分别连接该 第一电路点和输入该第一直流低电压；
第九薄膜晶体管， 其树极连接该 *极信号点， 漏极和源极分别连接该 第二电路点和输入该第一直流低电压；
第十薄膜晶体管， 其柵极输入第一时钟信号， 漏极和源极分别输入该 第一时钟信号和连接该第一电路点；
第十一薄膜晶体管， 其柵极输入第二时钟信号， 漏极和源极分别输入 该第一时钟信号和连接该第一电路点；
第十二薄膜晶体管， 其槲极输入该第二时钟信号， 漏极和源极分别输 入该第二时钟信号和连接该第二电路点；
第十三薄膜晶体管， 其楣-极输入该第一时钟信号， 漏极和源极分别输 入该第二时钟信号和连接该第二电路点；
工作时, 该第一时钟信号和该第二时钟信号的频率低于该第 n级时钟 信号， 并且该第一电路点和该第二电路点交替受该第一时钟信号和该第二 时钟信号充电而处于高电位。
其中， 该上拉电路包括'： 第十四薄膜晶体管， 其櫥极连接该橱极信号 点， 漏极和源极分别输入该第 n级时钟信号和连接该第 n级水平扫描线。
其中， 该下拉电路包括： 第十五薄膜晶体管， 其柵极连接第 η+·2级水 平扫描线， 漏极和源极分别连接该第 η级水平扫描线和输入该直流低电 压； 第十六薄膜晶体管， 其栅极连接该第 η+2级水平扫描线， 漏极和源极 分别连接该栅极信号点和输入该直流低电压。
其中， 该第 η级时钟信号的占空比小于 50%。
其中， 该第 η级时钟信号的占空比为 40%。
其中， 该第一时钟信号通过公共的金属线输入所述级联的多个 GOA 单元。
其中, 该第二时钟信号通过公共的金属线输入所述级联的多个 GOA 单元。
其中， 该直流低电压通过公共的金属线输入所述级联的多个 GOA单 元。
本发明还提^ Γ—种用于平板显示的 GOA电路， 包括级联的多个 GOA 单元, 按照第 η级 GOA单元控制对显示区域第 η级水平扫描线充电， 该 第 η级 GOA单元包括上拉电路， 下拉电路， 下拉维持电路， 上拉控制电 路， 下传电路及自举电容； 该上拉电路、 下拉电路.。 下拉维持电路及自举 电容分别与栅 信号点和该第 η级水平扫描线连接， 该上拉控制电路和下 传电路分别与该柵极信号点连接； 该下传电路包括：
第一薄膜晶体管， 其树极连接该 *极信号点， 漏极和源极分别输入第 n级时钟信号和输出开动信号；
该上拉控制电路包括：
第二薄膜晶体管， 其棚 ·极输入来自第 n- 2 级 GOA单元的开动信号， 漏极和源极分别连接第 n-2级水平扫描线和该栅极信号点;
第三薄膜晶体管， 其栅极.连接第 n-1 级水平扫描线， 漏极和源极分别 连.接该第 n- 1级水平扫描线和该栅极.信号点；
其中， 该下拉维持电路包括：
第四薄膜晶体管， 其橋极连接第一电路点， 漏极和源极分别连接该第 η级水平扫描线和输入第一直流低电压；
第五薄膜晶体管， 其栅极连接第二电路点， 漏极和源极分别连接该第 η级水平扫描线和输入该第一直流低电压；
第六薄膜晶体管， 其树极连接该第一电路点， 漏极和源极分别连接该 第 η-1级水平扫描线和该栅极信号点；
第七薄膜晶体管， 其柵极连接该第二电路点， 漏极和源极分别连接该 第 n-i级水平扫描线和该栅极信号点；
第八薄膜晶体管， 其栅极连接该栅极信号点， 漏极和源极分别连接该 第一电路点和输入该第一直流低电压；
第九薄膜晶体管， 其柵极连接该栅极信号点， 漏极和源极分别连接该 第二电路点和输入该第一直流低电压；
第十薄膜晶体管， 其栅极输入第一时钟信号， 漏极和源极分别输入该 第一时钟信号和连接该第一电路点;
第十一薄膜晶体管， 其栅极输入第二时钟信号， 漏极和源极分别输入 该第一时钟信号和连接该第一电路点;
第十二薄膜晶体管， 其栅极输入该第二时钟信号， 漏极和源极分别输 入该第二时钟信号和连接该第二电路点；
第十三薄膜晶体管， 其柵极输入该第一时钟信号， 漏极和源极分别输 入该第二时钟信号和连接该第二电路点;
工作时， 该第一时钟信号和该第二时钟信号的频率低于该第 η级时钟 信号， 并且该第一电路点和该第二电路点交替受该第一时钟信号和该第二 时钟信号充电而处于高电位；
其中， 该上拉电路包括： 第十四薄膜晶体管， 其棚 ·极连接该橋极信号 点， 漏极和源极分别输入该第 η级时钟信号和连接该第 II级水平扫描线； 其中， 该下拉电路包括： 第十五薄膜晶体管， 其櫪极连接第 n+2级水 平扫描线， 漏极和源极分别连接该第 n 级水平扫描线和输入该直流低电 压； 第十六薄膜晶体管， 其柵极连接该第 Ώ+2级水平扫描线， 漏极和源极 分别连接该栅极信号点和输入该直流低电压；
其中， 该第 n级时钟信号的占空比小于 50%。
该第 η级时钟信号的占空比为 40%。
该第一时钟信号通过公共的金属线输入所述级联的多个 GOA单元。 该第二时钟信号通过^共的金属线输入所述级联的多个 GOA单元„ 该直流低电压通过公共的金属线输入所述级联的多个 GOA单元。
本发明还提供了一种显示装置， 其包括如上所述的用于平板显示的
GO Α电路。
本发明用于平板显示的 GOA电路可以提升 GOA电路及相关显示装置 在高温下的稳定性， 并减小 GOA 充电信号的阻容延迟（RC delay ) 。 运 用本发明的 GOA 电路可以制作低成本的窄边框或无边框的平板显示产 品 附图说明
下面结合附图， 通过对本发明的具体实施方式详细描述， 将使本发明 的技术方案及其他有益效果显而易见。
附图中，
图 为本发明用于平板显示的 GOA 电路（单级） 一实施例的电路 图；
图 2 为本发明用于平板显示的 GOA 电路在 80 °C时的输出波形示意 图；
图 3为本发明用于平板显示的 GOA电路的多级架构示意图；
图 4为应用了本发明用于平板显示的 GOA. 电路的平板显示装置的结 构示意图。 具体实施方式
参见图 1 , 其为本发明用于平板显示的 GOA 电路（单级）一实施例 的电路图。 本发明的 GOA电路可以包括级联的多个 GOA单元， 按照第 n 级 GOA单元控制对显示区域第 n级水平扫描线 G(n)充电, 该第 n级 GOA 单元包括上拉电路 100, 下拉电路 200， 下拉维持电路 300， 上拉控制电路 400, 下传电路 500及自举电容 Cb; 该上拉电路 100、 下拉电路 200、 下 拉维持电路 300及自举电容 Cb分别与树极信号点 Q (ιι)和该第 n级水平 扫描线 G (n)连接， 该上拉控制电路 400和下传电路 500分别与该栅极 信号点 Q (n)连.接。
该上拉电路 100包括： 直接控制给显示区域第 n级水平扫描线 G(n)进 行充电的薄膜晶体管 T21， 其楣-极连接该栅极信号点 （Q (η) ) ， T21 的 漏极和源极分别输入该第 η级时钟信号 CK (η)和连接该第 η级水平扫描 线 G ( η ) , T21栅极 Q(n)的电位可直接影响 CK(n)对 G(ii)充电。
下拉电路 200包含在 G(n)充电结束时进行放电的一组薄膜晶体管， 包 括对 G(n)进行放电的 T31和对 Q(ii)进行放电的 T41; T31栅极连.接第 n+2 级水平扫描线 G ( n+2 ) ， 漏极和源极分别连接该第 n级水平扫描线 G ( II ) 和输入直流低电压 VSS; T41 棚'极连接该第 n+2 级水平扫描线 G (n+2 ) ， 漏极和源极分别连接栅极信号点 Q (n) 和输入直流低电压 VSS; T31和 T41可以在 G(n+2)处于高电位时打开进行放电。
下传电路 500 包括薄膜晶体管 T22， 其槲极连接该栅极信号点 Q ( 11 ) , 漏极和源极分别输入第 11 級时钟信号 CK ( η ) 和输出开动信号 ST(n);
上拉控制电路 400包括： 薄膜晶体管 T11, 其栅极输入来自第 11-2级 GOA单元的开动信号 ST(n- 2), 漏极和源极分别连接第 n- 2级水平扫描线 (G (n-2) ：)和该柵极信号点 （Q (n) ) ； 薄膜晶体管 T12, 其栅极连接 第 n-1级水平扫描线 G (n-1 ) ， 漏极和源极分别连接该第 n-1级水平扫描 线 G ( n-1 )和该橋极信号点 Q ( II ) 。 本发明的各级 GOA电路中增加了 1 颗薄膜晶体管 T12给 Q(n)充电， 用以弥补 Q(n)在自举前的漏电， 能使 Q(n) 在高温下自举前保持得较为稳定。
薄膜晶体管 Tli、 T12和 T22可以控制将前级 GOA电路的开动信号 ST传递给本级 GOA电路， 使 GOA电路可以逐级充放电。
Q(n)和 G(ri)之间所连接的有自举功能的电容 Cb, 可在 G(n)电位提升 时通过 Cb的耦合效应使 Q(n)电位提升， 从而获得更高的 Q(n)电位及更小 的 GOA充电信号的阻容延迟 ( RC delay ) 。
下拉维持电路（300) 包括的一组薄膜晶体管可以在 GOA电路非充电 时期保持 G(n)和 Q(n)的低电位。 该下拉维持电路（300) 包括： 薄膜晶体 管 T32, 其极极连接第一电路点 P, 漏极和源极分别连接 G (n)和输入第 一直流低电压 VSS; 薄膜晶体管 T33， 其柵极连接第二电路点 Κ, 漏极和 源极分别连接 G (η)和输入第一直流低电压 VSS; 薄膜晶体管 Τ42, 其 柵极连接第一电路点 Ρ, 漏极和源极分别连接 G (n-1 )和柵极信号点 Q ( n ) ； 薄膜晶体管 T43， 其槲极连接第二电路点 Κ, 漏极和源极分别连接 G ( η- 1 )和槲极信号点 Q ( η ) ； 薄膜晶体管 Τ52 , 其栅极连接柵极信号点 Q ( η ) ， 漏极和源极分别连接第一电路点 Ρ和输入第一直流低电压 VSS; 薄膜晶体管 Τ62， 其楣 ·极连接楣-极信号点 Q ( η ) ， 漏极和源极分别连接第 二电路点 Κ和输入第一直流低电压 VSS ; 薄膜晶体管 Τ53 , 其柵极输入低 频时钟信号 ECK, 漏极和源极分别输入低频时钟信号 ECK和连接第一电 路点 Ρ; 薄膜晶体管 Τ54 , 其 *极输入低频时钟信号 EXCK， 漏极和源极 分别输入低频时钟信号 ECK和连接第一电路点 P; 薄膜晶体管 T63 , 其櫥 极输入该低频时钟信号 EXCK, 漏极和源极分别输入低频时钟信号 EXCK 和连接第二电路点 K; 薄膜晶体管 T64 , 其柵极输入低频时钟信号 ECK， 漏极和源极分别输入低频时钟信号 EXCK和连接第二电路点 K;
工作时， 低频时钟信号 ECK和低频时钟信号 EXCK的频率低于高频 时钟信号 CK ( n ) ， 并且该第一电路点 P和该第二电路点 K交替受低频 时钟信号 ECK和低频时钟信号 EXCK充电而处于高电位， 从而交替控制 薄膜晶体管 T32&T42或 T33&T43的打开， 以维持 G(n)或 Q(n)在非充电时 期的低电位。 薄膜晶体管 T54和 T64能根据低频时钟信号 EXCK和 ECK 的电位来交替打开以便给 P点或 K点放电， 可以更好的保证 T32&T42及 T33&T43 的交替工作， 用以避免薄膜晶体管长时间受栅极电压应力的影 响， 提高 GOA电路的操作寿命。 薄膜晶体管 T52连接 P点和直流低电压 Vss, 薄膜晶体管 T62连接 K点和直流低电压 Vss, T52和 T62可在 Q(n) 处于高电位时打开而关闭 T32、 Τ42、 Τ33和 Τ43 , 使之不影响 Q(n)和 G(n) 充电。
本发明的 GOA 电路可以使控制给水平扫描线充电的薄膜晶体管柵极 的 Q(n)电压在高温下自举前变得更加稳定， 因此有机会提升 GOA 电路的 高温稳定性并减少 GOA 充电信号的阻容延迟 ( C delay ) 。 具体来讲: 1 , 对于维持 Q(n)在非充电时期电位的薄膜晶体管 T42和 T43的连接方法 可以减少 Q(n)在高温下自举前的漏电； 2、 在各级 GOA电路中增加了 】颗 薄膜晶体管给 Q(ii)充电， 用以弥补 Q(n)在自举前的漏电。
参见图 2 , 其为本发明用于平板显示的 GOA电路在 801：时的输出波 形示意图， 其中高频时钟信号 CK(n)的占空比 （duty ratio ) 小于 50% , 具 体为 40%。 图 2中， tl〜i:4为 G(n)充电前的准备时闾， i.4〜t5为 G(n)的充电 时间， t5后 G(n)被放电。 低频时钟信号 ECK和低频时钟信号 EXCK可以 选择为频率相同， 相位相反。 可结合图 1来理解图 2， ti时， CK(n 2)的电 位开始抬升， G(n- 2)和 ST(n- 2)的电位也跟着开始抬升， 薄膜晶体管 Tl i打 开给 Q(n)充电。 t2 时， CK(n- i)的电位开始抬升， 薄膜晶体管 T12也打开 给 Q(n)充电。 Q(n)电位抬升后， 可打开薄膜晶体管 T52和 T62 , 从而关闭 T32、 Τ42 Τ33和 Τ43， 使之不影响 Q(n)和 G(n)充电。 t3 时， CK.(n- 2)的 电位开始下降， G(n- 2)和 ST(n 2)的电位跟着下降， 薄膜晶体管 T11会有一 定漏电
了
Figure imgf000010_0001
膜晶体管 T21和 T22打开， Q(n)自举到更高电位并控制 T21给 G(n)充电及 T22给 ST(ii)充电。 由于 G(n- )电位的起始抬升时间 :2要早于 G(n)电位的 始抬升时间 t4， 将 T42及 T43的漏极连接至 G(n 1)的电路结构相对于将 T42及 T43的漏极连接至第二直流低电压 Vss2 (图未示 ) 的电路结构可减 低 Q(n)在自举前通过薄膜晶体管 T42和 T43的漏电。 Q(n)自举后 , P点和 K点电位已被拉低， T42和 T43 已被关闭， Q(n)漏电可得到有效控制。 t5 时， CK(n)开始下降， Q(ri)电位并未立即被拉低， 薄膜晶体管 T21 和 T22 在 :5 后的短时间内仍保持导通， 将 G(ri)和 ST(n)电位拉低。 这之后， G(n+2)电位抬升， 薄膜晶体管 T31 和 T41 打开， 确保 G(n)和 Q(n)被拉至 氐电位。 这之 -后， T52和 T62关闭， T32&T42或 T33&T43可交替打开， 以维持 G(n)或 Q(n)在非充电时期的低电位„ 综上所述， 本发明能使 GOA 电路 Q(n)在高温下自举前的电压更稳定， 因此有机会获得更高的充电时期 的 Q(n)电压以及更小的 GOA充电信号的阻容延迟 ( RC delay ) 。
参见图 3， 其为本发明用于平板显示的 GOA 电路的多级架构示意 图。 图 3给出了本发明的 GOA 电路的一种多级连接方法， 低频时钟信号 ECK和 EXCK, 直流低电压 Vss、 CK1-CK4的 4个高频时钟信号的金属 线放置于各級 GOA电路的周边， 各级 GOA电路（其内部连接参见图 i ) 连接 CK1-CK4中的 1个 CK信号、 第 Ώ-2级 GOA电路产生的 G(n-2)和 ST(n- 2)、 第 (n- 1)级 GOA电路产生的 G(n 1)、 第（n+2)级 GOA电路产生的 G(n+2) , 并产生 G(n)和 ST'(n)信号。 图 3所示的连接方法可保证 GO A电路 的开动信号 ST(n)能逐级传递， 使得各级水平扫描线可以被逐级充电和放 电。 对于首、 末端级联的 GOA单元可以采用输入激活信号的方式来代替 缺少的信号输入。
本发明的 GOA 电路可以运用平板显示面板的原有制程制作在显示区 周围的基板上， 使之能替代外接 IC 来完成平板显示面板各级水平扫描线 的驱动。 本发明尤其适合制作窄边框或无边框的平板显示产品。
参见图 4 , 其为应用了本发明用于平板显示的 GOA 电路的平板显示 装置的结构示意图。 图 4 中， 平板显示装置具有显示基板 10， 显示基板 10 上方的驱动控制板 20 为显示基板 10提供驱动和控制信号， 显示基板 10左边.区域 30和右边区域 40制作了 GOA电路， 可从左边和右边两个方 向驱动显示区域 50 的水平扫描线。 GOA 电路接受驱动控制板 20 的输入 信号并逐级产生水平扫描线的控制信号， 可以控制显示区域 50 中的像素 逐行打开。
综上所述， 本发明可以提升 GOA电路（采用 duty ratio小于 50%的高 频时钟信号）及相关显示器件在高温下的稳定性， 并减小 GOA 充电信号 的阻容延迟（RC delay ) 。 运用本发明的 GOA 电路可以制作低成本的窄 边框或无边框的平板显示产品。
以上所述， 对于本领域的普通技术人员来说， 可以根据本发明的技术 方案和技术构思作出其他各种相应的改变和变形， 而所有这些改变和变形 都应属于本发明后附的权利要求的保护范围。

Claims

权 利 要 求
】、 一种用于平板显示的 G0A电路， 包括级联的多个 GOA单元， 按 照第 n级 GOA单元控制对显示区域第 n级水平扫描线充电， 该第 n级 GOA 单元包括上拉电路， 下拉电路， 下拉维持电路， 上拉控制电路， 下 传电路及自举电容； 该上拉电路、 下拉电路、 下拉维持电路及自举电容分 别与树极信号点和该第 n级水平扫描线连接， 该上拉控制电路和下传电路 分别与该櫥极信号点连接；
该下传电路包括：
第一薄膜晶体管， 其柵极连接该柵极信号点， 漏极和源极分别输入第 n级时钟信号和输出开动信号；
该上 4ϊ控制电路包 4舌：
第二薄膜晶体管， 其櫪极输入来自第 n- 2 级 GOA单元的开动信号， 漏极和源极分别连.接第 n 2级水平扫描线和该栅极信号点；
第三薄膜晶体管， 其栅极连接第 n— 1 级水平扫描线， 漏极和源极分别 连接该第 n 1级水平扫描线和该柵极信号点。
1、 如权利要求 1所述的用于平板显示的 GOA电路， 其中, 该下拉维 持电路包括：
第四薄膜晶体管， 其柵极连接第一电路点， 漏极和源极分别连接该第 n级水平扫描线和输入第一直流低电压;
第五薄膜晶体管， 其栅极连接第二电路点， 漏极和源极分别连接该第 n级水平扫描线和输入该第一直流低电压；
第六薄膜晶体管， 其树极连接该第一电路点， 漏极和源极分别连接该 第 11-1级水平扫描线和该栅极信号点；
第七薄膜晶体管， 其栅极连接该第二电路点, 漏极和源极分别连接该 第 n- 1级水平扫描线和该栅极信号点；
第八薄膜晶体管， 其柵极连接该栅极信号点， 漏极和源极分别连接该 第一电路点和输入该第一直流低电压；
第九薄膜晶体管， 其栅极连接该栅极信号点， 漏极和源极分别连接该 第二电路点和输入该第一直流低电压；
第十薄膜晶体管， 其柵极输入第一时钟信号， 漏极和源极分别输入该 第一时钟信号和连接该第一电路点；
第十一薄膜晶体管， 其柵极输入第二时钟信号， 漏极和源极分别输入 该第一时钟信号和连接该第一电路点；
第十二薄膜晶体管， 其栅极输入该第二时钟信号， 漏极和源极分别输
Figure imgf000013_0001
时钟信号充电而处于高电位。
3、 如权利要求 1所述的用于平板显示的 GOA电路， 其中， 该上拉电 路包括： 第十 薄膜晶体管， 其棚 ·极连接该棚 ·极信号点， 漏极和源极分别 输入该第 n级时钟信号和连接该第 ri级水平扫描线。
4、 如权利要求 I所述的用于平板显示的 GOA电路， 其中， 该下拉电 路包括： 第十五薄膜晶体管， 其栅极连接第 級水平扫描线， 漏极和源 极分别连接该第 n级水平扫描线和输入该直流低电压； 第十六薄膜晶体 管， 其栅极连接该第 n+2级水平扫描线， 漏极和源极分别连.接该栅极信号 点和输入该直流低电压。
5、 如权利要求 1所述的用于平板显示的 GOA电路， 其中 该第 11级 时钟信号的占空比小于 50%。
6、 如权利要求 5所述的用于平板显示的 GOA电路， 其中
时钟信号的占空比为 40%。
7、 如权利要求 1所述的用于平板显示的 GOA电路， 其中
Figure imgf000013_0002
钟信号通过公共的金属线输入所述级联的多个 GOA单元
8、 如权利要求 1所述的用于平板显示的 GOA电路， 其中 该第二时 钟信号通过公共的金属线输入所述级联的多个 GOA单元
9、 如权利要求 所述的用于平板显示的 GOA电路， —流低 电压通过公共的金属线输入所述级联的多个 GQA单元。
10、 一种用于平板显示的 GOA电路， 包括级联的多个 GOA单元， 按 照第 η级 GOA单元控制对显示区域第 η级水平扫描线充电， 该第 η级 GOA 单元包括上拉电路， 下拉电路， 下拉维持电路， 上拉控制电路， 下 传电路及自举电容； 该上拉电路、 下拉电路、 下拉维持电路及自举电容分 别与柵极信号点和该第 η级水平扫描线连.接， 该上拉控制电路和下传电路 与该柵极信号点连接；
该下传电路包括：
第一薄膜晶体管， 其柵极连接该柵极信号点， 漏极和源极分别输入第 n级时钟信号和输出开动信号；
该上拉控制电路包括：
第二薄膜晶体管， 其柵极输入来自第 n-2 级 GOA单元的开动信号， 漏极和源极分别连接第 n-2级水平扫描线和该栅极信号点;
第三薄膜晶体管， 其柵极连接第 n— 1 级水平扫描线， 漏极和源极分別 连接该第 α-l级水平扫描线和该柵极信号点;
其中， 该下拉维持电路包括：
第四薄膜晶体管， 其栅极连接第一电路点， 漏极和源极分别连接该第 η级水平扫描线和输入第一直流低电压;
第五薄膜晶体管， 其橋极连接第二电路点， 漏极和源极分别连接该第 η级水平扫描线和输入该第一直流低电压;
第六薄膜晶体管、 其柵极连接该第一电路点， 漏极和源极分别连接该 第 η— 1级水平扫描线和该柵极信号点；
第七薄膜晶体管、 其栅极连接该第二电路点， 漏极和源极分别连接该 第 η- 1级水平扫描线和该栅极信号点；
第八薄膜晶体管， 其柵极连接该柵极信号点， 漏极和源极分别连接该 第一电路点和输入该第一直流低电压；
第九薄膜晶体管， 其栅极连接该栅极信号点， 漏极和源极分别连接该 第二电路点和输入该第一直流低电压；
第十薄膜晶体管， 其柵极输入第一时钟信号， 漏极和源极分别输入该 第一时钟信号和连接该第一电路点；
第十一薄膜晶体管， 其柵极输入第二时钟信号、 漏极和源极分別输入 该第一时钟信号和连接该第一电路点；
第十二薄膜晶体管， 其栅极输入该第二时钟信号， 漏极和源极分别输 入该第二时钟信号和连接该第二电路点;
第十三薄膜晶体管， 其栅极输入该第一时钟信号， 漏极和源极分别输 入该第二时钟信号和连接该第二电路点；
工作时， 该第一时钟信号和该第二时钟信号的频率低于该第 η级时钟 信号， 并且该第一电路点和该第二电路点交替受该第一时钟信号和该第二 时钟信号充电而处于高电位；
其中， 该上拉电路包括： 第十四薄膜晶体管， 其柵极连接该柵极信号 点， 漏极和源极分别输入该第 η级时钟信号和连接该第 η级水平扫描线； 其中， 该下拉电路包括： 第十五薄膜晶体管， 其棚.极连接第 η+2级水 平扫描线， 漏极和源极分别连接该第 η 级水平扫描线和输入该直流低电 压； 第十六薄膜晶体管， 其槲极连接该第 n+2级水平扫描线， 漏极.和源极 分别连接该栅极信号点和输入该直流低电压；
其中， 该第 n级时钟信号的占空比小于 50%。
】1、 如权利要求 10所述的用于平板显示的 GOA电路， 其中， 该第 n 级时钟信号的占空比为 40%。
12、 如权利要求 10所述的用于平板显示的 GOA电路， 其中， 该第一 时钟信号通过^^共的金属线输入所述级联的多个 GOA单元„
13、 如权利要求 10所述的用于平板显示的 GOA电路， 其中， 该第二 时钟信号通过.公共的金属线输入所述级联的多个 GOA单元。
14、 如权利要求 10所述的用于平板显示的 GOA电路， 其中， 该直流 低电压通过公共的金属线输入所述级联的多个 GOA单元。
15、 —种显示装置， 包括如权利要求 i 所述的用于平板显示的 GOA 电路。
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