WO2015029951A1 - 実装基板用ウエハ、多層セラミックス基板、実装基板、チップモジュール、及び実装基板用ウエハの製造方法 - Google Patents
実装基板用ウエハ、多層セラミックス基板、実装基板、チップモジュール、及び実装基板用ウエハの製造方法 Download PDFInfo
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- WO2015029951A1 WO2015029951A1 PCT/JP2014/072175 JP2014072175W WO2015029951A1 WO 2015029951 A1 WO2015029951 A1 WO 2015029951A1 JP 2014072175 W JP2014072175 W JP 2014072175W WO 2015029951 A1 WO2015029951 A1 WO 2015029951A1
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H01L21/486—Via connections through the substrate with or without pins
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- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Definitions
- the present disclosure relates to a mounting substrate wafer, a multilayer ceramic substrate, a mounting substrate, a chip module, and a manufacturing method of the mounting substrate wafer.
- semiconductor integrated circuit elements As the degree of integration of semiconductor integrated circuit elements (hereinafter referred to as “semiconductor chips”) increases, there is a large difference in the arrangement pitch (distance between electrode centers) of each electrode terminal between the semiconductor chip and the main substrate. Has arisen. For this reason, when mounting a semiconductor chip on a main board, an “interposer” that relays the electrical connection between the two is drawing attention.
- Patent Document 1 discloses a semiconductor chip mounting wiring board that can function as an “interposer”.
- This mounting board has a configuration in which a glass epoxy rigid board having one layer of wiring and a flexible board having two layers of wiring are combined.
- the wiring of the rigid substrate has a structure that can be connected to the narrow pitch electrodes of the semiconductor chip.
- the wiring of the flexible substrate has a structure that can be mounted on the main substrate (motherboard).
- Patent Document 2 discloses a wiring board with a built-in silicon interposer in which a first unit wiring board and a second unit wiring board formed of glass cloth epoxy resin and a silicon substrate are combined.
- Patent Document 3 discloses a wiring board in which a silicon substrate having a fine wiring pattern and a multilayer ceramic substrate are combined. Each of the multilayer ceramic substrate and the silicon substrate has a plurality of internal electrodes penetrating the substrate.
- Patent Document 4 discloses a ceramic polycrystalline substrate and a glass multilayer ceramic substrate having high smoothness.
- the arrangement pitch of bump electrodes connected to a semiconductor chip is 50 ⁇ m or less.
- the arrangement pitch of the electrodes mounted on the main board such as a printed board is about 500 ⁇ m to 1 mm.
- the wiring structure on the surface side on which a highly integrated semiconductor chip is mounted is formed on a silicon substrate.
- the embodiment of the present disclosure can provide a mounting substrate wafer, a multilayer ceramic substrate, a mounting substrate, a chip module, and a manufacturing method of the mounting substrate wafer that can realize an interposer that does not include a silicon substrate.
- a mounting substrate wafer has a front surface and a back surface, a front surface ceramic layer positioned on the front surface, a back surface ceramic layer positioned on the back surface, a plurality of front surface electrodes penetrating the surface ceramic layer, and the back surface Intermediate ceramics in which a plurality of back electrodes penetrating a ceramic layer and a plurality of internal electrodes that are electrically connected between the plurality of surface electrodes and the plurality of back electrodes inside the multilayer ceramic substrate
- the distance between the plurality of back electrodes is smaller than the distance between the electrode centers, and the multilayer ceramic substrate is 20 mm
- the surface is such that the SF
- SBIR Site Back Surface Referenced
- the surface is flattened so that (Ideal Ranges) is 2 ⁇ m or less.
- the surface of the multilayer ceramic substrate is flattened so that GBIR (Global Back Ideal Ranges) is 2 ⁇ m or less.
- an insulating layer is provided between the surface of the multilayer ceramic substrate and the wiring pattern, and the insulating layer electrically connects each of the plurality of surface electrodes to the wiring pattern.
- a plurality of openings are provided, and the plurality of surface electrodes are aligned with the plurality of openings, respectively.
- the distance from the center position of each of the plurality of surface electrodes to one corresponding center position of the plurality of openings is equal to or less than the radius of the surface electrode.
- the positions of the plurality of openings are defined by a photolithography process.
- the positions of the plurality of wiring patterns are defined by a photolithography process.
- a multilayer ceramic substrate according to the present disclosure is a multilayer ceramic substrate for any one of the above mounting substrate wafers, having a front surface and a back surface, a front surface ceramic layer positioned on the front surface, and a back surface ceramic positioned on the back surface
- a mounting substrate is a mounting substrate on which a semiconductor chip is mounted, and includes a front surface ceramic layer positioned on a front surface, a back surface ceramic layer positioned on a back surface, a plurality of front surface electrodes penetrating the surface ceramic layer, A plurality of back electrodes penetrating the back ceramic layer, and a plurality of internal electrodes that are electrically connected between the plurality of surface electrodes and the plurality of back electrodes inside the multilayer ceramic substrate
- a plurality of surface electrode electrodes comprising: a ceramic chip substrate having a ceramic layer; and a wiring pattern formed on the surface of the ceramic chip substrate and having a minimum wiring width of 2 ⁇ m or less and a minimum wiring interval of 2 ⁇ m or less.
- the center-to-center distance is smaller than the distance between the electrode centers of the plurality of back electrodes, and the ceramic chip substrate is The surface is flattened so that SFQR (Site Front Last Squares Ranges) in a 20 mm square region is 2 ⁇ m or less.
- SFQR Site Front Last Squares Ranges
- the surface of the ceramic chip substrate is flattened so that SBIR (Site Back Surface Recommended Ranges) in a 20 mm square region is 2 ⁇ m or less.
- a plurality of bump electrodes formed on the wiring pattern are provided.
- the distance between the electrode centers of the plurality of bump electrodes is 1/10 or less of the distance between the electrode centers of the back electrode.
- an insulating layer is provided between the surface of the ceramic chip substrate and the wiring pattern, and the insulating layer electrically connects each of the plurality of surface electrodes to the wiring pattern.
- a plurality of openings are provided, and the plurality of surface electrodes are aligned with the plurality of openings, respectively.
- the distance from the center position of each of the plurality of surface electrodes to one corresponding center position of the plurality of openings is equal to or less than the radius of the surface electrode.
- the positions of the plurality of openings are defined by a photolithography process.
- the positions of the plurality of wiring patterns are defined by a photolithography process.
- a chip module according to the present disclosure includes any of the mounting boards described above and a plurality of semiconductor chips mounted on the mounting board.
- the mounting substrate according to the present disclosure is a mounting substrate cut out from any one of the above mounting substrate wafers, and includes a plurality of bump electrodes formed on the wiring pattern.
- the distance between the electrode centers of the plurality of bump electrodes is 1/10 or less of the distance between the electrode centers of the back electrode.
- the chip module of the present disclosure includes any one of the mounting substrates described above and a plurality of semiconductor chips mounted on the mounting substrate.
- a method for manufacturing a wafer for a mounting substrate includes a front surface ceramic layer positioned on a front surface, a back surface ceramic layer positioned on a back surface, a plurality of front surface electrodes penetrating the surface ceramic layer, and a plurality of holes penetrating the back surface ceramic layer A back surface electrode, and an intermediate ceramic layer that forms a plurality of internal electrodes that are electrically connected between the plurality of front surface electrodes and the plurality of back surface electrodes inside the multilayer ceramic substrate, And a step of preparing a multilayer ceramic substrate in which the distance between the electrode centers of the plurality of front surface electrodes is smaller than the distance between the electrode centers of the plurality of back surface electrodes, and the multilayer ceramic substrate in a plurality of evaluation regions in units of 20 mm square.
- SFQR Si in the evaluation area of 20 mm square in at least 50% of the plurality of evaluation areas.
- e At least the surface of the multilayer ceramic substrate is flattened so that the Front Last Squares Ranges is 2 ⁇ m or less, and a wiring pattern having a minimum wiring width of 2 ⁇ m or less and a minimum wiring interval of 2 ⁇ m or less is formed by photolithography.
- Forming on the front surface of the multilayer ceramic substrate, and the step of preparing the multilayer ceramic substrate includes: a first green sheet that forms the front surface ceramic layer; and a second green sheet that forms the back surface ceramic layer.
- a laminated green sheet body is formed by laminating and pressing, and the laminated green sheet body is fired to form a ceramic fired body having an internal electrode that connects the front surface and the back surface, a front electrode, and a back electrode. Including the step of.
- the multilayer ceramic substrate shrinks by a distance of 1% or less in the in-plane direction.
- a method of manufacturing a wafer for a mounting substrate includes forming a plurality of electrode vias on a ceramic green sheet, filling the electrode vias with electrode paste from at least one surface of the green sheet, and forming a green sheet with electrodes Laminating the electrodes between the plurality of green sheets with electrodes to be electrically connected, and forming a laminated green sheet body integrated by pressure bonding, and the laminated green sheet body.
- a ceramic fired body having an internal electrode that connects the front surface and the back surface, a surface electrode, and a back electrode, and processing at least the surface of the ceramic fired body, a unit of 20 mm square
- the evaluation area is divided into a plurality of evaluation areas, at least 50% of the plurality of evaluation areas includes a 20 mm square evaluation area.
- the step of forming the wiring pattern includes a step of forming an insulating layer on at least the surface and forming at least one or more through holes for exposing the electrode on the surface in a part of the insulating layer.
- the step of forming the wiring pattern includes a step of forming an insulating layer on at least the surface and forming at least one or more through holes for exposing the electrode on the surface in a part of the insulating layer. And a step of applying a photoresist on the insulating layer and the through hole; a step of exposing the photoresist using an exposure apparatus; and developing the exposed photoresist to remove a part of the photoresist A step of obtaining a resist pattern, a step of forming a metal layer by a vacuum film forming method on the photoresist pattern, the insulating layer and the through hole, and a deposition on the photoresist pattern by removing the photoresist pattern The removed metal is removed (lifted off), leaving only the metal deposited on the insulating layer and the through hole. And a step of obtaining a pattern.
- the surface ceramic layer and the back ceramic layer of the ceramic fired body are planarized one by one.
- the front surface ceramic layer and the back surface ceramic layer of the ceramic fired body are simultaneously planarized.
- the step of obtaining the multilayer ceramic substrate includes a step of processing at least the surface of the surface ceramic layer using CMP (Chemical Mechanical Polishing).
- CMP Chemical Mechanical Polishing
- the embodiment of the present disclosure can provide a mounting substrate and a chip module that do not require a silicon interposer. Also provided are a mounting substrate wafer, a multilayer ceramic substrate, and a manufacturing method of the mounting substrate wafer that can be used for manufacturing such a mounting substrate.
- FIG. 2 is a schematic cross-sectional view of a laminated green sheet body after firing and a multilayer ceramic substrate after polishing.
- FIG. 5 is a schematic perspective view illustrating an example of a method for forming an electrode via 16 on the green sheet 15 according to the first embodiment of the present disclosure.
- FIG. FIG. 4 is a schematic perspective view showing an example of a method for filling an electrode via 16 with an electrode material 18. It is a typical perspective view which shows an example of the method of forming the lamination
- 5 is a schematic perspective view showing an example of a method for processing a ceramic fired body 23.
- FIG. (A) is a typical perspective view which shows the multilayer ceramic substrate in which the insulating layer 5 was formed in the surface
- (b) is typical sectional drawing of the multilayer ceramic substrate shown to (a).
- (A) is a typical perspective view which shows the multilayer ceramic substrate by which the through-hole 27 was formed in the insulating layer 5, (b) is typical sectional drawing of the multilayer ceramic substrate shown to (a). .
- (A) is a typical perspective view which shows the multilayer ceramic substrate by which the metal base film 28 and the photoresist 29 were sequentially provided on the insulating layer 5 and the through hole 27, (b) is shown to (a). It is typical sectional drawing of a multilayer ceramic substrate, (c) is a figure which expands and shows a part of cross section of the multilayer ceramic substrate shown to (b).
- FIG. (A) is a perspective view which shows typically the multilayer ceramic substrate after formation of the photoresist pattern 30, (b) is typical sectional drawing of the multilayer ceramic substrate shown to (a).
- (A) is a typical perspective view which shows the multilayer ceramic substrate of the state which deposited the plating layer 31 on the metal base film 28, (b) is typical sectional drawing of the multilayer ceramic substrate shown to (a).
- FIG. (A) is a typical perspective view which shows the multilayer ceramic substrate of the state which removed the photoresist pattern 30 and the metal base film 28, (b) is typical sectional drawing of the multilayer ceramic substrate shown to (a).
- FIG. (A) is a typical perspective view which shows the multilayer ceramic substrate of the state in which the photoresist pattern for forming the wiring pattern 6 was formed on the insulating layer 5, (b) is (a). It is typical sectional drawing of the multilayer ceramic substrate shown.
- (A) is a typical perspective view which shows the multilayer ceramic substrate of the state which formed the metal layer 32 on the photoresist pattern 30,
- (b) is typical sectional drawing of the multilayer ceramic substrate shown to (a).
- FIG. (A) is a typical perspective view which shows the multilayer ceramic substrate of the state which removed the metal layer 32 by lift-off
- (b) is typical sectional drawing of the multilayer ceramic substrate shown to (a).
- FIG. 3 is a schematic cross-sectional view of a mounting substrate 4a having an insulating layer 5 between a surface 3x of a multilayer ceramic substrate 3 and a wiring pattern 6.
- FIG. It is a graph which shows the relationship between a focus shift
- the “multilayer ceramic substrate” is a laminated body of a plurality of ceramic layers and is a constituent element of a “wafer for mounting substrate” described below.
- the “multilayer ceramic substrate” has, for example, a flat plate shape with a rectangular upper surface, but may be processed into a disk shape.
- the shape of the “multilayer ceramic substrate” is not limited to the examples in the embodiments described below.
- the “mounting substrate wafer” includes a multilayer ceramic substrate and a wiring pattern formed on the surface of the multilayer ceramic substrate as constituent elements.
- the mounting substrate wafer typically has a generally disk shape, but the shape of the mounting substrate wafer is not limited to the disk shape.
- the above multilayer ceramic substrate and mounting substrate wafer are in a state before being divided into a plurality of small pieces.
- the “mounting substrate” is a small piece portion cut out from the mounting substrate wafer, and is obtained by dividing the mounting substrate wafer into a plurality of small piece portions.
- the mounting substrate includes, as a base, a small piece portion of a multilayer ceramic substrate included in the mounting substrate wafer. This small piece portion is referred to as a “ceramic chip substrate” and is distinguished from the “multilayer ceramic substrate” before being divided.
- the “ceramic chip substrate” may be called a “split multilayer ceramic substrate”.
- Chip module includes a mounting substrate and a semiconductor chip mounted on the mounting substrate as components.
- the mounting board is a small piece cut out from the mounting board wafer, the structure of the ceramic chip board included in the mounting board matches the local structure of the multilayer ceramic board. For this reason, the structure, shape, and size of the electrode or wiring pattern described for the ceramic chip substrate are also valid for the structure, shape, and size of the electrode or wiring pattern of the multilayer ceramic substrate.
- This mounting board is one of a plurality of mounting boards cut out from the mounting board wafer.
- Each mounting substrate forms a chip module by mounting a semiconductor chip on the surface thereof.
- the chip module can be used by being mounted on a main board (mother board).
- the semiconductor chip is typically a semiconductor element in which a large-scale integrated circuit is formed, but may be a semiconductor element in which a communication circuit or a power circuit is formed.
- the semiconductor constituting the chip is not limited to single crystal silicon, and may be a wide band gap semiconductor such as silicon carbide and gallium nitride.
- the main board may typically be a printed wiring board.
- the main substrate on which the chip module is mounted can be used for various apparatuses or devices such as portable terminals, information devices, home appliances, automobile parts, and industrial machines.
- FIG. 1 an example of the basic configuration of the mounting board of the present disclosure will be described.
- the illustrated mounting substrate 4 includes a ceramic chip substrate (divided multilayer ceramic substrate) 300 having a front surface 3x and a back surface 3y.
- the ceramic chip substrate 300 includes a front surface ceramic layer 3a located on the front surface 3x, a back surface ceramic layer 3b located on the back surface 3y, and at least one intermediate ceramic layer 3c sandwiched between the front surface ceramic layer 3a and the back surface ceramic layer 3b.
- the boundary of the ceramic layer is divided by a dotted line, which is shown for explaining the front surface ceramic layer 3a, the back surface ceramic layer 3b, and the intermediate ceramic layer 3c.
- the boundary of each ceramic layer is not clear, and the boundary part is continuous so that it cannot be distinguished, or has a boundary in which internal electrodes are formed in each ceramic layer. It may be configured.
- the multilayer ceramic substrate 3 is electrically connected between the plurality of front surface electrodes 7 in the front surface ceramic layer 3a, the plurality of back surface electrodes 9 in the back surface ceramic layer 3b, and the plurality of front surface electrodes 7 and the plurality of back surface electrodes 9. It has the some internal electrode 8 which performs.
- the intermediate ceramic layer 3c is one layer, but the multilayer ceramic substrate 3 may include a plurality of intermediate ceramic layers 3c.
- the ceramic layers 3a, 3b, 3c constituting the ceramic chip substrate 300 are described as having substantially the same thickness, but the actual thickness is not limited to such an example. .
- the size of each element in the drawing does not necessarily reflect the actual scale and ratio.
- the mounting substrate 4 has a wiring pattern 6 formed on the surface 3x of the ceramic chip substrate 300.
- the wiring pattern 6 has a minimum wiring width of 2 ⁇ m or less and a minimum wiring interval of 2 ⁇ m or less. A part of the wiring pattern 6 may have a wiring width exceeding 2 ⁇ m. Moreover, the wiring interval in the wiring pattern 6 may partially exceed 2 ⁇ m.
- FIG. 33 shows the correlation between the deviation from the optimum focus value and the dimensions of the photoresist.
- the area where SFQR is measured is, for example, a 20 mm square area.
- the 20 mm square area is merely an example of an arbitrary area for convenience, and may be set to an arbitrary numerical value according to the measuring apparatus. For example, a 15 mm square may be sufficient and a 25 mm square may be sufficient.
- SFQR tends to be smaller, and inevitably satisfies 2 ⁇ m or less.
- an evaluation area of 20 mm square is selected from the area, and SFQR may be 2 ⁇ m or less.
- the evaluation area since there is a possibility of taking various sizes and shapes depending on the product, the evaluation area may be different in size and shape from the area to be actually exposed, and the mounting substrate wafer is further cut and divided. The size and shape may be different from the unit chip area.
- a plurality of bump electrodes 13 are provided on the wiring pattern 6.
- the bump electrode 13 can be connected in electrical contact with a semiconductor chip mounted on the mounting substrate 4.
- FIG. 2A shows a configuration example of the chip module 40.
- the illustrated chip module 40 includes a mounting substrate 4 having the same configuration as that shown in FIG. 1 and a plurality of semiconductor chips 41 mounted on the mounting substrate 4.
- the semiconductor chips 41 in the chip module 40 can be electrically connected to each other via wiring patterns, electrodes, or internal circuits of the mounting substrate 4.
- a plurality of semiconductor chips are mounted on the mounting substrate 4, and the semiconductor chips are mainly electrically connected by a wiring pattern 6 formed on the surface 3 x of the ceramic chip substrate 300 of the mounting substrate 4 to transmit signals.
- a wiring pattern 6 formed on the surface 3 x of the ceramic chip substrate 300 of the mounting substrate 4 to transmit signals.
- pads having a diameter of 25 ⁇ m connected to the wiring pattern 6 are arranged with a minimum pitch of 55 ⁇ m.
- the wiring patterns 6 (8 to 11) corresponding to the required number of channels are arranged so as to pass between the pads, the minimum wiring width and the minimum wiring interval of the wiring are required to be 2 ⁇ m or less.
- FIG. 2B and 2C are plan views schematically showing a part of the arrangement example of the front surface electrode 7 and a part of the arrangement example of the back surface electrode 9, respectively.
- the distance between the electrode centers of the surface electrode 7 is indicated by “Px”.
- the electrode center distance of the back electrode 9 is indicated by “Py”.
- the distance Px between the electrode centers of the surface electrode 7 can take a plurality of values on the same ceramic chip substrate. For this reason, the minimum value among these plural values is defined as “distance between electrode centers of surface electrodes”.
- the distance Py between the electrode centers of the back surface electrode 9 can take a plurality of values in the same ceramic chip substrate, the minimum value among the plurality of values is “the distance between the electrode centers of the back surface electrodes”. It is defined as
- the distance between the electrode centers of the front electrode 7 is smaller than the distance between the electrode centers of the back electrode 9. Since the internal electrode 8 of the ceramic chip substrate 300 has a conductor layer extending in the in-plane direction of the substrate, even if the arrangement of the front electrode 7 and the arrangement of the back electrode 9 are different, the front electrode 7 The electrode 9 can be properly connected.
- the distance between electrode centers is the length of a line segment connecting the centers of the two electrodes adjacent to each other on the front or back surface of the ceramic chip substrate.
- the “electrode center” is the center of gravity of the cross section of the electrode on the front or back surface of the ceramic chip substrate.
- the cross sections of the electrodes illustrated in FIGS. 2B and 2C are circular, but the cross sectional shape of each electrode is not limited to a circular shape, and may be an ellipse or a polygon such as a rectangle. The cross-sectional size of each electrode need not be the same.
- the surface 3x of the ceramic chip substrate 300 is flattened so that SFQR (Site Front Last Squares Ranges) in a 20 mm square region is 2 ⁇ m or less.
- the surface 3x of the ceramic chip substrate 300 is flattened so that the SBIR in a 20 mm square region is 2 ⁇ m or less.
- the surface 3x of the multilayer ceramic substrate 3 is flattened so that GBIR is 2 ⁇ m or less.
- an insulating layer (not shown in FIG. 1) is provided between the surface 3x of the ceramic chip substrate or the multilayer ceramic substrate 3 and the wiring pattern 6.
- This insulating layer has a plurality of openings that electrically connect each of the plurality of surface electrodes 7 to the wiring pattern 6.
- the plurality of surface electrodes 7 are aligned with the plurality of openings, respectively.
- FIG. 3 is a top view of a part of the insulating layer 5 having a plurality of openings 5a.
- four openings 5 a are formed in the insulating layer 5, and each opening 5 a is aligned with the surface electrode 7 on the surface 3 x of the multilayer ceramic substrate 3.
- the wiring pattern 6 and the bump electrode 13 are not shown in FIG. Actually, the surface electrode 7 is electrically connected to the wiring pattern 6 through each opening 5a.
- the shape and position of the opening 5a are defined by the photolithography process in the same manner as the shape and position of the wiring pattern formed thereon.
- a multilayer ceramic substrate is manufactured by firing a structure in which ceramic green sheets are laminated. For this reason, the multilayer ceramic substrate is deformed due to shrinkage due to drying of the solvent inside the green sheet prior to the firing step, expansion due to pressure bonding during lamination, and the in-plane direction and thickness of the substrate before and after the firing step. Shrink in the direction. Since it is difficult to control the degree of these deformations, the surface of the multilayer ceramic substrate loses flatness, making it difficult to form a fine structure by a photolithography process. Specifically, due to the deformation in the in-plane direction of the substrate, the positions in the in-plane direction of the plurality of surface electrodes 7 are easily shifted from the target position (design reference position).
- FIG. 4A is a top view showing a state where the center position of the surface electrode 7 is shifted from the target position.
- the radius on the upper surface of the surface electrode 7 is R ⁇ m
- the distance from the electrode center of the surface electrode 7 to the center of the opening 5a of the insulating layer is about R ⁇ m.
- misalignment can have an effect when a fine structure is formed on the multilayer ceramic substrate by photolithography.
- the fine structure is not limited to the opening of the insulating layer.
- a wiring pattern can be formed without providing an insulating layer on the surface of the multilayer ceramic substrate, or only a necessary part can be covered with the insulating layer. Or can be formed by crossing. In such a case, according to the prior art, misalignment may occur between the wiring pattern or the insulating layer coating and the surface electrode 7.
- the flatness of the multilayer ceramic substrate is improved, the fine structure can be formed by photolithography, and the above-described index such as SFQR is adjusted to an appropriate range. Further, the shrinkage in the in-plane direction of the multilayer ceramic substrate is suppressed to 1% or less, thereby making it easier to bring the position of the surface electrode 7 closer to the target value. Further, by improving the flatness on the surface of the multilayer ceramic substrate, it is possible to connect the fine structure formed by photolithography to the surface electrode 7 with high accuracy. In a specific embodiment to be described later, the distance from the center position of each surface electrode 7 to the center position of the corresponding opening 5a is equal to or less than the radius of the surface electrode.
- FIG. 4B is a top view showing an example in which the surface electrode 7 and the opening 5a of the insulating layer 5 are aligned.
- the radius on the upper surface of the surface electrode 7 is R ⁇ m
- the distance from the electrode center of the surface electrode 7 to the center of the opening 5a of the insulating layer is shorter than R ⁇ m.
- the radius on the upper surface of the surface electrode 7 is about 40 ⁇ m
- the surface electrode 7 and the opening 5a of the insulating layer 5 are aligned with each other. Is suppressed to 30 ⁇ m or less.
- the radius on the upper surface of the surface electrode 7 is R ⁇ m
- the distance from the electrode center of the surface electrode 7 to the center of the opening 5a of the insulating layer is preferably shorter than R / 2 ⁇ m.
- the target of the photolithography process is a multilayer ceramic substrate.
- the multilayer ceramic substrate includes a surface ceramic layer located on the front surface, a back surface ceramic layer located on the back surface, a plurality of surface electrodes in the surface ceramic layer, a plurality of back surface electrodes in the back surface ceramic layer, a plurality of surface electrodes and the plurality A plurality of internal electrodes that make electrical connection with the back electrode of the other.
- the distance between the electrode centers of the plurality of front surface electrodes is smaller than the distance between the electrode centers of the plurality of back surface electrodes.
- step S10 a plurality of green sheets for forming the front surface ceramic layer and the back surface ceramic layer of the multilayer ceramic substrate are prepared.
- Each green sheet may have a thickness of 100 ⁇ m to 200 ⁇ m, for example.
- step S12 two or more green sheets are stacked and temporarily pressed to form a green sheet laminate in order to form each of the front surface ceramic layer and the back surface ceramic layer.
- the temporary pressure bonding can be performed while pressing the green sheet laminate in the thickness direction.
- the green sheet laminate can be heated to about 60 to 80 ° C., for example.
- the thickness of the green sheet laminate in the temporarily pressed state can be, for example, 300 ⁇ m to 500 ⁇ m.
- the thickness of the green sheet laminate is determined assuming the thickness of the surface layer to be removed by subsequent planarization.
- step S14 aging is performed on each of the green sheet laminates.
- Aging is a treatment performed to relieve stress accumulated in the green sheet. Aging can include various processes in which stress relaxation is achieved.
- As the aging process a process of leaving at room temperature for a long time (for example, 24 hours or more) may be performed, or a heat treatment for raising the temperature may be performed.
- the temperature of the heat treatment can be about 60 to 100 ° C., for example.
- the heat treatment time can be set to about 30 to 320 minutes, for example. Then, you may process at room temperature for about 24 hours, for example.
- An aging process is performed in order to suppress that a 1st and 2nd green sheet deform
- step S20 at least one or more green sheets (third green sheets) different from the first and second green sheets are prepared.
- the third green sheet forms at least one internal ceramic layer located between the front surface ceramic layer and the back surface ceramic layer in the multilayer ceramic substrate.
- the first green sheet and the second green sheet produced in step S14 are a step of preparing a plurality of green sheets each having a thickness substantially equal to the thickness of the third green sheet; And laminating each of the first green sheet and the second green sheet.
- the first and second green sheets and the third green sheet can be obtained using the same thickness green sheets manufactured by the same method.
- each of the first and second green sheets is manufactured by stacking three layers of green sheets each having a thickness of 150 ⁇ m
- each of the first and second green sheets is, for example, 450 ⁇ m, although it varies slightly depending on pressure or the like. It has a thickness of about.
- the thickness of each third green sheet is 150 ⁇ m.
- the first and second green sheets may be manufactured using a green sheet that is thicker than the third green sheet from the beginning.
- a plurality of openings are formed in the first, second and third green sheets. These openings define the shape and position of the front electrode, back electrode and internal electrode.
- the opening can be formed by irradiating each of the first, second and third green sheets with a laser.
- the opening may have a diameter of 30 to 150 ⁇ m, for example.
- mJ millijoules
- a plurality of openings in the first, second and third green sheets are filled with a conductive material.
- the filling of the conductive material can be performed by a printing method. If the through hole has a diameter of about 80 ⁇ m, the conductive material can be densely filled even if the depth is about 450 ⁇ m. After firing, the conductive material functions as an electrode.
- a conductive pattern can be formed on the green sheet by applying a conductive material on the main surface of the green sheet.
- a printing method can be used to form the conductive pattern.
- a conductive pattern is formed on one main surface of the third green sheet along with filling of the conductive material into the opening provided in the third green sheet (see FIG. 7 described later). The formation of the conductive pattern may be performed before or after filling the opening with the conductive material.
- An electrode that electrically connects the front surface electrode and the back surface electrode, such as a conductive pattern and a conductive material, is an internal electrode.
- the “internal electrode” can include all conductors that electrically connect the front surface electrode and the back surface electrode.
- the internal electrode, the surface electrode, and the back electrode are formed of the same material, since they are integrally coupled, it is not necessary to distinguish the internal electrode from the front electrode and the back electrode.
- the term “internal electrode” in the present specification when used in the broadest sense, may have the same meaning as a conductive material located inside a multilayer ceramic substrate.
- FIG. 6 shows an example of a cross section of the first and second green sheets after being filled with a conductive material.
- the first green sheet 21a and the second green sheet 21b are each formed by laminating three layers of green sheets.
- the opening 16a provided in the first green sheet 21a and the opening 16b provided in the second green sheet 21b are filled with a conductive electrode material 18.
- the distance between the centers of the openings 16a of the first green sheet 21a is smaller than the distance between the centers of the openings 16b of the second green sheet 21b.
- FIG. 7 shows an example of a cross section of the third green sheet after being filled with the conductive material.
- the third green sheet 21c does not have a laminated structure.
- the third green sheet 21c shown in FIG. 7 has a conductive pattern 18p on its upper surface.
- the opening 16c provided in the third green sheet 21c is filled with an electrode material 18.
- the opening 16c has the same arrangement as the opening 16b of the second green sheet 21b.
- the conductive pattern 18p has a portion overlapping the opening 16c.
- the conductive pattern 18p may be provided on the upper surface of the second green sheet 21b.
- a laminated green sheet body is formed by laminating the first to third green sheets so that the third green sheet is sandwiched between the first green sheet and the second green sheet. At this time, it is preferable to restrain the upper surface and the lower surface of the laminated green sheet body by contacting, for example, another base material that is not fired at the same temperature as the green sheet as a constraining layer.
- FIG. 8 shows a cross section in a state where the first green sheet 21a and the second green sheet 21b shown in FIG. 6 and the third green sheet 21c shown in FIG. 7 are laminated.
- the third green sheet 21c includes a first green sheet 21a and a second green sheet 21b such that the main surface on which the conductive pattern 18p is provided faces the first green sheet 21a. It is sandwiched between.
- the electrode material 18 in the opening part 16a of the 1st green sheet 21a and the conductive pattern 18p on the 3rd green sheet 21c contact.
- the opening part 16c of the 3rd green sheet 21c and the opening part 16b of the 2nd green sheet 21b have the same arrangement
- step S22 the laminated green sheet body that is constrained by the base material is loaded into the frame body, and the main pressure bonding is performed on the laminated green sheet body.
- step S24 the laminated green sheet body is fired. Firing can be performed, for example, at a temperature of 900 ° C. over 2 hours. In firing, it is preferable to press the upper and lower surfaces of the laminated green sheet body with a flat plate-like setter.
- FIG. 9 shows a cross section of the ceramic fired body, and the lower part is a cross sectional view schematically showing the multilayer ceramic substrate after polishing.
- a fired body having a structure in which the front surface ceramic layer 3a, the intermediate ceramic layer 3c, and the back surface ceramic layer 3b are laminated is obtained.
- the conductive material contained in the electrode material 18 and the conductive pattern 18p is also densified.
- a plurality of front surface electrodes 7 in the front surface ceramic layer 3a, a plurality of back surface electrodes 9 in the back surface ceramic layer 3b, and a plurality of internal electrodes 8 are formed.
- a conductor pattern 18p see FIG.
- the internal electrode 8 in advance on the main surface of the third green sheet 21c, the internal electrode 8 having a conductor layer extending in the in-plane direction of the intermediate ceramic layer 3c can be formed. . As shown in the figure, the internal electrode 8 has a connection portion with the front electrode 7 and the back electrode 9. As a result, the front electrode 7 and the corresponding back electrode 9 are electrically connected via the internal electrode 8.
- the broken line portion shown in the upper part of FIG. 9 is removed, and as shown in the lower part of FIG. 9, a multilayer ceramic substrate 3 having a flattened front surface and back surface is obtained. Since the ceramic sintered body has the internal electrode 8 inside, even if the arrangement of the surface electrode 7 and the arrangement of the back electrode 9 of the multilayer ceramic substrate 3 is different, the surface electrode 7 and the corresponding back electrode 9 are mutually connected. Can be connected to.
- step S26 the ceramic fired body is processed into a disk shape by, for example, a laser (shape processing step). Thereby, a disk-shaped multilayer ceramic substrate is obtained.
- the multilayer ceramic substrate shrinks only by a distance of 1% or less in the in-plane direction. Deviation from the target value at the position in the inward direction can be reduced.
- FIG. 10 is a graph plotting the deviation of the surface electrode from the target position.
- the measurement result of the shift amount from the target value of the surface electrode in the disk-shaped multilayer ceramic substrate (diameter: 150 mm) is shown.
- 20 ⁇ 20 surface electrodes (diameter: 80 ⁇ m) are formed in a square region having a side of 3 mm arranged at a predetermined pitch.
- the result of measuring 16 surface electrodes extracted symmetrically with respect to the origin with the center of the multilayer ceramic substrate as the origin is shown.
- Each measurement point is the position of four vertices in a square shape.
- the positional deviation of the surface electrode due to contraction is in the range of 30 ⁇ m or less.
- 3 ⁇ in the X direction is 29 ⁇ m
- 3 ⁇ in the Y direction is 15 ⁇ m.
- step S28 a flattening process of the multilayer ceramic substrate is executed.
- the planarization of the multilayer ceramic substrate is typically performed by grinding, lapping, CMP (chemical mechanical polishing), or the like.
- CMP chemical mechanical polishing
- SFQR Site Front Last Squares Ranges
- SBIR Site Back Surface Referenced Ranges
- the condition that SFQR or SBIR in a 20 mm square region is 2 ⁇ m or less need not be achieved in any part of the front surface (or back surface) of the multilayer ceramic substrate.
- the condition that the SFQR in the 20 mm square region is 2 ⁇ m or less in at least 50% or more of the plurality of regions may be achieved.
- the condition that the SBIR in the 20 mm square region is 2 ⁇ m or less may be satisfied.
- the thickness of the front surface ceramic layer and the back surface ceramic layer can be reduced to, for example, about half of the original value by processing both surfaces of the multilayer ceramic substrate.
- the thickness of the first and second green sheets is set sufficiently large in consideration of the thickness of the portion removed by polishing, so that the front ceramic layer and the back ceramic layer do not disappear. (Fig. 9)
- step S30 a fine structure such as a wiring pattern is formed by lithography on the flattened surface of the multilayer ceramic substrate (lithography process). Specifically, a wiring pattern having a minimum wiring width of 2 ⁇ m or less and a minimum wiring interval of 2 ⁇ m or less is formed on the surface of the multilayer ceramic substrate by photolithography. Thus, the mounting substrate wafer in the embodiment of the present disclosure is manufactured. A bump electrode can be provided on the wiring pattern by a known method.
- the multilayer ceramic substrate produced in step S28 may be sold before the wiring pattern is formed. Since the surface of the multilayer ceramic substrate according to the present disclosure is smooth, it is easy to form a wiring pattern by photolithography.
- FIG. 11 is a top view of the mounting substrate wafer of the present disclosure.
- a mounting substrate wafer 1 shown in FIG. 11 has a multilayer ceramic substrate 3.
- a plurality of chip areas 2 are gathered on the surface of the multilayer ceramic substrate 3.
- a plurality of mounting substrates can be obtained by dividing the mounting substrate wafer 1 by cutting the mounting substrate wafer 1 so as to include the chip area.
- the shape of the mounting substrate wafer 1 may be, for example, a disk shape having a diameter of 150 mm or more so that a conventional Si wafer processing process can be applied.
- the shape of the mounting substrate wafer 1 may be other than a disk shape.
- the chip area 2 it is beneficial to arrange the chip area 2 so that many mounting substrates can be obtained from one mounting substrate wafer 1, and the shape of the mounting substrate wafer 1 can be arbitrarily designed according to the size of the chip area 2.
- the chip area 2 it is beneficial not to arrange the chip area 2 in this range.
- the mounting substrate 4 including the chip area 2 has an insulating layer 5 on the surface of the multilayer ceramic substrate 3, and a wiring pattern 6 is formed on the upper surface thereof.
- One end of the wiring pattern 6 is connected to the surface electrode 7 of the multilayer ceramic substrate 3, and the surface electrode 7 is electrically connected to the back electrode 9 through the internal electrode 8 of the multilayer ceramic substrate 3.
- the multilayer ceramic substrate 3 includes a dielectric mainly composed of Al 2 O 3 and SiO 2 , an internal electrode 8, a front electrode 7, and a back electrode 9.
- the internal electrode 8, the front electrode 7 and the back electrode 9 are made of, for example, Ag.
- the multilayer ceramic substrate 3 can have an insulating layer 5, a wiring pattern 6, and the like in the chip area 2 on the surface thereof.
- the wiring pattern 6 electrically connects the semiconductor chips.
- the wiring pattern 6 can be arbitrarily designed according to the specifications of the semiconductor chip mounted on the mounting substrate 4.
- An element such as a varistor for preventing excessive current may be formed in the middle of the pattern.
- the width of the narrowest portion of the wiring pattern 6 is defined as the minimum wiring width (in FIG. 12).
- the width of the portion where the distance between the patterns is the narrowest is called the minimum wiring space (the space shown by the arrow p1 in FIG. 12).
- the minimum wiring width s1 in the wiring pattern 6 is 2 ⁇ m or less, and the minimum wiring interval p1 is greater than 0 ⁇ m and 2 ⁇ m or less.
- the thickness of the wiring pattern 6 can be arbitrarily designed according to the electrical resistance specification and the like. However, it is beneficial that the thickness of the wiring pattern 6 is 2 ⁇ m or less, which is the same as the minimum wiring width, from the viewpoint of suppressing the occurrence of disconnection.
- the SFQR in the 20 mm square evaluation region is 2 ⁇ m or less on the surface of the multilayer ceramic substrate 3, the minimum wiring width s1 is 2 ⁇ m or less and the minimum wiring interval p1 is 2 ⁇ m or less.
- a mounting substrate having such a fine wiring pattern 6 can be produced.
- the SFQR is more preferably 1 ⁇ m or less.
- the SFQR on the back surface of the multilayer ceramic substrate 3 may be 2 ⁇ m or less.
- SFQR is an abbreviation for Site Front Last Squares Ranges, and is used as an index indicating local flatness.
- FIG. 14 the opposite surface 10 to be measured of the multilayer ceramic substrate 3 is sucked and fixed to a flat surface.
- the reference plane 12 is calculated based on the shape of the surface in the evaluation region in a certain range (for example, a range of 20 mm square (a square having a side of 20 mm)) using the least square method with the opposite surface 10 being flat.
- An arrow 11 in FIG. 14 schematically represents the length of one side in the square evaluation region.
- SFQR is the sum of the distance from the reference plane 12 to the highest point on the site surface and the distance to the lowest point on the site surface (the distance indicated by the arrow t SFQR in FIG. 14).
- SFQR is 2 ⁇ m or less, and a fine processing technique by photolithography using a stepper can be applied.
- the SFQR in the conventional multilayer ceramic substrate generally does not satisfy the condition that the SFQR is 2 ⁇ m or less.
- the SFQR when the multilayer ceramic substrate 3 is divided into a plurality of evaluation regions in units of 20 mm square, the SFQR can satisfy the condition of 2 ⁇ m or less in at least 50% region. Lithographic processing can be easily applied. Further, it is more preferable that SFQR satisfies the condition of 1 ⁇ m or less in at least 80% evaluation region. Thereby, a fine wiring pattern can be realized by applying photolithography.
- a stepper for performing exposure there is a stepper having a function of correcting the inclination of the multilayer ceramic substrate for each pattern (also referred to as a shot) to be exposed.
- a stepper having a function of correcting the inclination of the multilayer ceramic substrate for each pattern (also referred to as a shot) to be exposed.
- the SFQR is 2 ⁇ m or less
- SBIR can be used as an index of local flatness.
- SBIR is an abbreviation for Site Back Surface Referred Ideal Ranges. In the SBIR measurement, as shown in FIG.
- the opposite surface 10 of the multilayer ceramic substrate 3 is flattened by adsorbing and fixing the opposite surface 10 to the flat surface.
- the SBIR is the difference between the height of the highest point and the lowest point on the site surface relative to the opposite surface 10 in an evaluation region of a certain range (for example, a range of 20 mm square (a square having a side of 20 mm)) ( In FIG. 15, the difference in height indicated by the arrow tSBIR ). As the SBIR is 2 ⁇ m or less and the value is smaller, the focusing accuracy can be improved.
- the SBIR is more preferably 1 ⁇ m or less.
- the SBIR when the multilayer ceramic substrate 3 is divided into a plurality of evaluation regions in units of 20 mm square, the SBIR can satisfy the condition of 2 ⁇ m or less in at least 50% region. Lithographic processing can be easily applied. Further, it is more preferable that the SBIR satisfies the condition of 1 ⁇ m or less in the evaluation region of at least 80%. Thereby, a fine wiring pattern can be realized by applying photolithography.
- GBIR can also be used as an index of flatness.
- GBIR is an abbreviation for Global Back Ideal Ranges, and indicates the flatness of the entire wafer surface.
- the opposite surface 10 of the multilayer ceramic substrate 3 is flattened by adsorbing and fixing the opposite surface 10 to the flat surface.
- GBIR is the difference between the height of the highest point and the height of the lowest point on the wafer surface with respect to the opposite surface 10 on the entire wafer surface (the difference in height indicated by the arrow t GBIR in FIG. 16).
- the focusing accuracy can be improved as GBIR is 2 ⁇ m or less and the value is smaller.
- GBIR is more preferably 1 ⁇ m or less.
- the minimum wiring width is 2 ⁇ m.
- a fine wiring pattern in which the minimum wiring interval is larger than 0 ⁇ m and not larger than 2 ⁇ m can be realized. If such a wiring pattern can be formed, bump electrodes can be arranged on the wiring pattern corresponding to the fine electrode pitch of the semiconductor chip. As a result, the silicon substrate interposer, which has been conventionally required, can be eliminated. Which index to use, SFQR, SBIR, and GBIR, may be selected as appropriate according to the function of the exposure apparatus.
- SFQR is an effective index for exposure with a stepper having a substrate surface tilt correction function
- SBIR is an effective index for exposure with a stepper having no substrate surface tilt correction function.
- GBIR is an effective index for the case where an aligner that exposes the entire surface of the substrate at once is used. It is not necessary to satisfy the above conditions for all the indices of SFQR, SBIR, and GBIR, and any item may be selected according to the exposure apparatus to be used. However, it can be said that SFQR is usually satisfied when the SBIR index is used, and that both SBIR and SFQR are satisfied when the GBIR index is used.
- the mounting substrate 4 may have bump electrodes 13 (see FIG. 1).
- the bump electrodes 13 may be formed in advance on the mounting substrate wafer 1 in advance, or may be formed after the mounting substrate wafer 1 is divided. Examples of the material of the bump electrode 13 are Cu, Au, Sn, and the like.
- the bump electrode 13 may include a two-layer structure or a three-layer structure such as Cu / Sn or Cu / Ni / Au. Depending on the design of the electrode pitch for mounting the semiconductor chip 41 on the mounting substrate 4, the pitch of the bump electrodes 13 is required to be 50 ⁇ m or less.
- the pitch p2 of the bump electrode 13 and the height t1 of the bump electrode 13 are shown in FIG.
- one end portion (for example, Sn in Cu / Sn) of the bump electrode 13 on the surface that has been flattened and warped is melted, whereby the semiconductor chip 41 is melted.
- Variation in the height of the bump electrode 13 facing the electrode 42 can be absorbed.
- the distance to the highest point on the surface of the multilayer ceramic substrate 3 measured from the global best-fit reference surface 14 when not attracted This is the sum (the distance indicated by the arrow t SORI in FIG. 18) with the distance to the lowest point on the surface of the ceramic substrate 3.
- the global best fit reference surface 14 is a reference surface calculated by the least square method based on the shape of the surface of the entire wafer surface where the opposite surface to be measured is not attracted to the flat surface.
- the electrode pitch of the back electrode 9 may be about 500 ⁇ m to 1 mm.
- a bump may be formed by forming a metal film called UBM (Under Bump Metal) on the back electrode 9 and mounting a solder ball thereon.
- the UBM may have a laminated structure such as Ni / Au or Ni / Pd / Au.
- the solder ball material is, for example, lead-free solder such as Sn—Ag—Cu.
- a green sheet obtained by forming ceramic powder into a sheet is prepared.
- a low-temperature sintered ceramic material that can be fired simultaneously with a conductive paste such as Ag, Cu, Au, or so-called LTCC (Low Temperature Co-Fired Ceramics) ceramics can be used.
- LTCC Low Temperature Co-Fired Ceramics
- Al, Si, Sr and Ti as main components are converted into Al 2 O 3 , SiO 2 , SrO and TiO 2 , respectively, 10 to 60% by mass in terms of Al 2 O 3 and in terms of SiO 2
- a mixture of 25 to 60% by mass, 7.5 to 50% by mass in terms of SrO, and 20% by mass or less (including 0) in terms of TiO 2 is used.
- the mixture has at least one selected from the group consisting of Bi, Na, K and Co as subcomponents in an amount of 0.1 to 10% by weight in terms of Bi 2 O 3 and 100% by weight of Na 2. It may be contained in an amount of 0.1 to 5% by mass in terms of O, 0.1 to 5% by mass in terms of K 2 O, and 0.1 to 5% by mass in terms of CoO.
- the mixture may further contain at least one selected from the group consisting of Cu, Mn, and Ag.
- the mixing ratio of Cu and Mn at this time can be 0.01 to 5% by mass in terms of CuO and 0.01 to 5% by mass in terms of MnO 2 , respectively.
- the mixing ratio of Ag may be 0.01 to 5% by mass.
- the low-temperature sintered ceramic material may contain other inevitable impurities.
- the above mixture is calcined at 700 ° C. to 850 ° C. and pulverized to obtain a dielectric ceramic composition composed of finely pulverized particles having an average particle size of 0.6 to 2 ⁇ m.
- This dielectric ceramic composition is mixed with an organic binder and a plasticizer to obtain a ceramic slurry. After applying the ceramic slurry on a carrier film such as a polyethylene terephthalate film with a uniform thickness by the doctor blade method, etc., the ceramic slurry is dried to obtain a green sheet having a thickness of several tens to several hundreds of ⁇ m. obtain.
- first and second green sheets two laminates (first and second green sheets) in which three green sheets are previously stacked are prepared.
- one or more green sheets (third green sheets) sandwiched between the first green sheet and the second green sheet are prepared.
- an aging process is performed on the first and second green sheets under the above-described conditions.
- the third green sheet may also be subjected to an aging process in order to increase the positional accuracy.
- a plurality of electrode vias 16 are formed in the green sheet 15.
- the illustrated green sheet 15 corresponds to any of the first, second, and third green sheets described above. Since the green sheet 15 contains a lot of organic binder, the electrode via 16 can be easily formed. From the viewpoint of position accuracy, processing accuracy, and processing speed, it is beneficial to form the electrode via 16 with a laser. For example, carbon dioxide laser 17 is used to form electrode via 16 having a diameter of 60 ⁇ m to 80 ⁇ m that penetrates green sheet 15. The arrangement of the electrode vias 16 formed in at least one of the first, second and third green sheets is different from the arrangement of the electrode vias 16 formed in other green sheets.
- the electrode vias 16 formed on the first and second green sheets define front and back electrodes
- the electrode vias 16 formed on the third green sheet define internal electrodes.
- the arrangement of the electrode vias 16 in the second and third green sheets is common.
- the interval between the center positions of the electrode vias 16 in the first green sheet is made smaller than the interval between the center positions of the electrode vias 16 in the second and third green sheets.
- a paste-like electrode material 18 is filled into the electrode via 16 by screen printing using a mask 19 and a squeegee 20.
- the electrode material 18 for example, a conductive paste whose main component is a conductive material such as Ag, Cu, or Au can be used.
- alignment marks may be formed in at least two places of the green sheet 15. In this case, an alignment mark is also formed on the mask 19 at a position corresponding to the mark on the green sheet 15, and alignment is performed using an image recognition function when the two are overlapped.
- a circuit pattern for internal wiring is formed on the surface of the green sheet 15 by a screen printing method using a conductive paste.
- a circuit pattern for internal wiring is formed on one main surface of the third green sheet. This circuit pattern functions as an internal electrode that electrically connects at least the front electrode and the back electrode after firing the green sheet.
- This step may be performed after the step of filling the electrode via 18 with the electrode material 18 or may be performed before.
- the mask 19 and the squeegee 20 may be used simultaneously with the filling of the electrode material 18 into the electrode via 16.
- the electrode material 18 filling the electrode via 16 and the electrode material for forming a circuit pattern on the surface of the green sheet 15 may be the same material, or an electrode material suitable for each process may be selected.
- the third green sheet can be formed by stacking a plurality of green sheets 15.
- the shape and arrangement of the electrode via 16 of each green sheet and the circuit pattern for internal wiring may be different for each sheet.
- the material composition of the ceramic powder constituting the green sheet 15 may be different for each sheet.
- a capacitor can be formed by forming an electrode pattern so as to sandwich a green sheet containing a high dielectric constant material, or an inductor can be formed by forming a spiral electrode pattern.
- the multilayer ceramic substrate is formed by laminating green sheets. Therefore, the shape and / or circuit pattern can be changed for each green sheet, and a complicated three-dimensional structure can be obtained both in terms of structure and circuit.
- a plurality of green sheets with electrodes 21 obtained by filling the electrode vias 16 of the green sheets 15 with the electrode material 18 are stacked, and the stacked green sheets are bonded by pressure bonding.
- Form body 22 the lamination is performed so that the third green sheet is disposed between the first green sheet and the second green sheet.
- a plurality of electrodes are connected so that the electrode of one sheet and the corresponding electrode of the other sheet or the circuit pattern for internal wiring are electrically connected between the adjacent green sheets with electrodes 21.
- the attached green sheets 21 are stacked.
- a through hole for positioning is provided in at least two places of the green sheet with electrodes, and a stacking jig having pins at corresponding positions is prepared.
- a plurality of green sheets with electrodes can be positioned by passing pins through through holes for positioning formed in the green sheets with electrodes.
- the diameter of the positioning through hole in the electrode-equipped green sheet is larger than the diameter of the pin. For this reason, the alignment using the image recognition function generally gives higher positioning accuracy.
- a laminated green sheet body 22 is obtained by pressing and integrating a plurality of green sheets 21 with electrodes.
- the electrode-attached green sheet 21 can be bonded using, for example, a hydraulic hand press, a uniaxial pressure molding machine, a CIP (cold isostatic molding machine), or the like.
- CIP cold isostatic molding machine
- Use of CIP is advantageous because the green sheet 21 with electrodes can be pressed isotropically and bonded with a uniform pressure.
- the laminated green sheet body 22 is placed in a firing furnace and fired.
- the temperature in firing is determined based on the material composition of the ceramic powder selected according to the composition of the electrode material 18. For example, a ceramic material that can be fired at about 900 ° C. or lower when using Ag as the electrode material 18, about 1000 ° C. or lower when using Au or Cu, and about 1400 ° C. or lower when using Ni or the like is selected.
- the Since Ag and Cu have low electric resistance, the size of the front electrode 7, the back electrode 9, and the internal electrode 8 (see FIG. 1) can be reduced by selecting Ag or Cu as the electrode material 18. Therefore, when Ag or Cu is selected as the electrode material 18, LTCC ceramics that can be fired simultaneously with the electrode material at 1000 ° C. or lower may be used as the ceramic powder material.
- the laminated green sheet body 22 is fired by using a non-shrinkage method of firing while suppressing dimensional change.
- the non-shrinking method used here is that the constraining layer formed from a material (for example, Al 2 O 3 ) that is not fired at the firing temperature of the green sheet (here, the laminated green sheet body 22) is previously applied to the front and back surfaces of the laminated green sheet body. This is a technique in which firing is performed at the firing temperature of the green sheet.
- a ceramic fired body in which the shrinkage in the in-plane direction of the laminated green sheet body 22 is suppressed to 1% or less is obtained.
- the electrode material 18 is also densified simultaneously with the firing of the LTCC material.
- the front electrode 7 and the back electrode 9, and the internal electrode 8 which electrically connects between these can be formed (for example, refer FIG. 13).
- the firing of the laminated green sheet body 22 is performed, for example, in a state where the laminated green sheet body 22 is disposed between members called setters. It is advantageous that the material composition of the setter contains a material contained as a main component in the green sheet to be fired.
- a setter obtained by firing a material containing Al 2 O 3 , mullite, ZrO 2 or the like as a main component is used.
- the laminated green sheet body 22 is fired, the laminated green sheet body 22 is placed on the setter, and the upper surface of the laminated green sheet body 22 is formed of the same material as the setter on which the laminated green sheet body 22 is placed. Place a setter.
- the thermal profiles on the upper surface and the lower surface of the laminated green sheet body 22 during firing are substantially the same. Can be adjusted. Thereby, the temperature gradient between the upper surface and lower surface of the lamination
- the green sheet tends to shrink in the in-plane direction of the sheet. Therefore, if the green sheet is simply fired by placing setters on the upper and lower surfaces of the green sheet, the isotropic shrinkage of the green sheet is hindered by the friction that occurs partially between the green sheet and the setter. In addition, the distortion in the obtained fired body becomes large.
- the constraining layers provided on the upper and lower surfaces of the laminated green sheet body 22 suppress the shrinkage in the in-plane direction of the sheet. It is possible to obtain a ceramic fired body with less warping even if fired while contacting a setter.
- a ceramic fired body with suppressed surface shrinkage and warpage can be obtained.
- the SFQR of the multilayer ceramic substrate it is beneficial that the SFQR of the ceramic fired body is 50 ⁇ m or less and the SORI amount is 50 ⁇ m or less.
- the ceramic laminated body which has SFQR of 2 micrometers or less is obtained.
- the processing method of the main surface of the ceramic fired body 23 may be appropriately selected according to the hardness of the ceramic fired body 23.
- the main surface of the ceramic fired body 23 can be ground or polished using the abrasive grains 24. After roughing the main surface of the ceramic fired body 23 one by one using surface grinding or a large-diameter abrasive grinder, both main surfaces of the ceramic fired body 23 are respectively formed using a small-diameter abrasive grinder. It may be polished.
- SFQR can be reduced to 2 ⁇ m or less in a relatively short time.
- the surface grinding may be performed only on one of the main surfaces of the ceramic fired body 23.
- the processing time can be further reduced.
- surface roughness can be reduced by using CMP (Chemical Mechanical Polishing). Reducing the surface roughness is beneficial because the thickness of the insulating layer described later can be reduced.
- CMP Chemical Mechanical Polishing
- the outer shape of the ceramic fired body 23 may be made circular using a laser 25 or the like, or a notch or an orientation flat may be formed on the outer edge of the ceramic fired body 23.
- the outer shape of the ceramic fired body 23 is circular, so that the disk-shaped multilayer ceramic substrate 3 is obtained.
- an identification mark 26 may be given to the ceramic fired body 23 using a laser or the like.
- the outer shape of the multilayer ceramic substrate 3, the presence / absence of the identification mark 26, and the like can be arbitrarily selected according to the specifications of an apparatus used in photolithography in a later process.
- the multilayer ceramic substrate 3 which has several electrodes (surface electrode and back electrode) on the surface and back surface of a board
- the multilayer ceramic substrate 3 is divided into a plurality of evaluation regions each having a 20 mm square, at least 50% of the plurality of evaluation regions has an SFQR in the 20 mm square evaluation region of 2 ⁇ m or less.
- the evaluation region is typically defined on the surface excluding 1 mm from the outer edge of the multilayer ceramic substrate 3.
- the SFQR is 2 ⁇ m or less in at least 50% evaluation areas. Lithography can be applied. Accordingly, it is possible to form an arbitrarily designed fine wiring pattern on the surface of the multilayer ceramic substrate.
- the insulating layer 5 is formed on the surface of the multilayer ceramic substrate 3.
- a film of polyimide, siloxane polymer, or the like is formed on the surface of the multilayer ceramic substrate 3 by spin coating, dip coating, spray coating, or the like.
- a film having a flat surface that does not follow the fine irregularities on the surface of the multilayer ceramic substrate 3 can be formed.
- a liquid material by, for example, a spin coating method, a film having a substantially uniform thickness is formed on the surface of the multilayer ceramic substrate 3. Therefore, the flatness of the film formed on the surface of the multilayer ceramic substrate 3 reflects the flatness of the surface of the multilayer ceramic substrate 3.
- an inorganic insulating film such as a SiO 2 film may be formed by applying a sputtering method, a CVD (Chemical Vapor Deposition) method, or the like.
- a film having a substantially uniform thickness can be formed on the surface of the multilayer ceramic substrate 3. Therefore, even when an inorganic insulating film is formed, the flatness of the film formed on the surface of the multilayer ceramic substrate 3 reflects the flatness of the surface of the multilayer ceramic substrate 3.
- a through hole 27 is formed in the insulating layer 5 by removing a part of the insulating layer 5. By forming the through hole 27, at least a part of each of the surface electrodes 7 is exposed. If the insulating layer 5 is formed of polyimide, a through hole photoresist pattern is formed on the insulating layer 5 using photolithography, and the polyimide film is etched using a chemical etching solution or the like. 27 can be formed. If a film of photosensitive polyimide or the like is formed on the multilayer ceramic substrate 3, the through hole 27 can be formed by removing unnecessary portions after the film on the multilayer ceramic substrate 3 is exposed.
- the through-hole 27 can be formed by applying dry etching using plasma using a gas containing gas.
- the through hole 27 is formed so as to be aligned with the surface electrode 7 of the multilayer ceramic substrate 3. Thereby, each of the surface electrodes 7 of the multilayer ceramic substrate 3 and a wiring pattern to be described later can be electrically connected through the through hole 27.
- the through hole 27 is formed by using a photolithography technique. At this time, for example, the position of the surface electrode 7 of the multilayer ceramic substrate 3 is confirmed by visual detection or detection by image recognition, and the through-hole forming mask is aligned with reference to the position of the surface electrode 7.
- An alignment pattern or the like may be formed on the multilayer ceramic substrate 3. Thus, it is possible to use an arbitrary pattern formed in advance for alignment.
- the multilayer ceramic substrate 3 is manufactured by applying a non-shrinkage method capable of suppressing shrinkage in the in-plane direction. Therefore, the position shift from the target position (design reference position) in the surface electrode 7 is sufficiently small to allow photolithography to be applied to the formation of the through hole 27.
- a wiring pattern is formed on the upper surface of the insulating layer 5.
- a wiring pattern is formed using a material having low resistivity including Al, Cu, etc.
- a method for easily forming a wiring pattern a method for forming a Cu film by applying an electrolytic plating method is known. According to the electrolytic plating method, the plating layer can be selectively grown in the region where the underlayer is formed. Further, the growth rate of the plating layer can be adjusted by adjusting the current density.
- a metal base film 28 is formed on the insulating layer 5 by, for example, a sputtering method.
- the metal underlayer 28 may be a two-layer film in which, for example, a Cr film having a film thickness of 0.02 ⁇ m is formed and a Cu film having a film thickness of 0.08 ⁇ m is further formed on the surface thereof.
- a Cr film or a Ti film so as to be in contact with the insulating layer 5, the adhesion of the metal base film 28 to the insulating layer 5 can be improved.
- the metal underlayer 28 functions as a power supply layer that supplies a current necessary for electrolytic plating.
- the composition and structure of the metal underlayer 28 are not limited to the above example.
- a photoresist 29 is applied on the metal base film 28 as shown in FIGS.
- Examples of the method for applying the photoresist 29 include spin coating, dip coating, spray coating, and slit coating.
- the method for applying the photoresist 29 may be appropriately selected according to the viscosity of the photoresist, the dimensions of the multilayer ceramic substrate 3, and the like.
- a spin coating method is used for applying the photoresist.
- the film thickness of the photoresist 29 is set to a thickness larger than the thickness of the plating film to be formed.
- the plating film may be formed across the pattern of the photoresist 29, and adjacent wirings in the wiring pattern may be short-circuited. For example, when a plating film having a thickness of 2.0 ⁇ m is formed, a photoresist having a thickness of about 2.2 to 2.6 ⁇ m may be formed.
- the photoresist 29 is exposed and developed to remove unnecessary portions of the photoresist 29, thereby forming a photoresist pattern 30 (see FIGS. 26A and 26B).
- an exposure apparatus is selected according to the required resolution. For example, when the wiring width of a wiring pattern to be formed is 1 ⁇ m to 2 ⁇ m, a reduction projection exposure apparatus (stepper) including a light source that emits g-line (wavelength 436 nm), h-line (wavelength 405 nm), or i-line (wavelength 365 nm) Can be used.
- the light beam emitted from the light source is converged by the lens, and the pattern of the photomask is imaged on the photoresist 29.
- the resolution in the photoresist pattern 30 depends on the magnitude of the focus shift at this time.
- a Cr film (film thickness 0.02 ⁇ m) and a Cu film (film thickness 0.08 ⁇ m) are sequentially formed on a silicon substrate by sputtering, and then a positive photoresist is applied by spin coating.
- the data for the sample exposed with the i-line stepper is plotted.
- the photoresist was developed using an alkaline developer for 120 seconds by the paddle method.
- the horizontal axis of the graph shown in FIG. 33 indicates the amount of deviation from the optimum focus value.
- the sign of the shift amount is positive when the focus position shifts upward when the exposure surface of the substrate is raised, and negative when the focus position shifts downward.
- the vertical axis (photoresist dimension) of the graph indicates the width (line interval) of the portion where the photoresist is removed at the approximate center of the shot, and this photoresist dimension corresponds to the width of the wiring to be formed later. To do. It can be seen from FIG. 33 that the wiring width increases when the focus deviates from the optimum value. If the deviation amount based on the optimum value is ⁇ 1 ⁇ m or less or +1 ⁇ m or more, the photoresist pattern is destroyed (see FIG.
- the wiring width becomes too wide. Therefore, from the viewpoint of obtaining a photoresist pattern having a line width (line width) or line spacing of about 2 ⁇ m, the range of deviation from the optimum focus value is within 2 ⁇ m (within the range of ⁇ 1 ⁇ m centered on the optimum focus value). It is beneficial to have it.
- Stepper performs exposure of the entire photoresist by repeating exposure in units of a certain range (shot).
- a shot is typically an area of about 10 mm square to 20 mm square.
- the stepper generally measures the height of the substrate surface inside the apparatus prior to exposure in units of shots. Thereby, a focus reference plane is calculated for each shot, and an exposure operation is performed. Therefore, it can be said that there is no focus shift if exposure is performed on an ideal photoresist on a substrate with no variation in surface height.
- a substrate provided with a photoresist has variations in the height of its surface.
- the surface height measured for each shot is a representative value of the surface height in the shot, and the stepper corrects the surface height variation in the shot even though it can correct the surface height variation between shots. It is not possible. For this reason, if the surface height varies in the shot, a focus shift may occur partially in the shot. A focus shift within a shot can cause a reduction in the resolution of the photoresist pattern.
- formation of fine wiring as shown in FIG. 35 can be realized by suppressing the height variation in the shot during exposure to within 2 ⁇ m.
- the specific specifications required for the substrate on which the wiring pattern 6 is to be formed vary depending on the functions provided in the exposure apparatus.
- SFQR is preferably 2 ⁇ m or less.
- SBIR is preferably 2 ⁇ m or less.
- GBIR is preferably 2 ⁇ m or less.
- a plating layer 31 is deposited on the metal base film 28 by electrolytic plating.
- the wiring pattern 6 can be selectively formed in a region where no photoresist exists.
- the metal constituting the plating layer 31 are Cu, Ag, Au, Ni, Al, etc., which have a small electrical resistance. If the surface of the metal base film 28 is the same kind of metal as the metal constituting the plating layer 31, it is beneficial because the adhesion of the plating layer 31 to the metal base film 28 can be improved.
- the photoresist pattern 30 is removed by a known method. Thereafter, the metal base film 28 in a region other than the region where the plating layer 31 is formed is removed by a known method (see FIGS. 28A and 28B). Thereby, the wiring pattern 6 is obtained on the surface of the multilayer ceramic substrate 3 on the surface electrode 7 side. As shown in FIG. 28B, the wiring pattern 6 is electrically connected to the surface electrode 7 through the through hole 27 of the insulating layer 5.
- the wiring pattern 6 on the multilayer ceramic substrate 3 may be formed using a vacuum film forming method.
- the multilayer ceramic substrate 3 can be obtained in the same manner as in the first embodiment. Therefore, below, description of the process for producing the multilayer ceramic substrate 3 is abbreviate
- the multilayer ceramic substrate 3 has a plurality of electrodes (a front electrode and a back electrode) on the front surface and the back surface, and the front electrode and the back electrode are electrically connected via an internal electrode. Has a structured.
- the multilayer ceramic substrate used here has an area where SFQR in an evaluation area of 20 mm square is 2 ⁇ m or less on the surface excluding 1 mm from the outer edge.
- SFQR in an evaluation area of 20 mm square is 2 ⁇ m or less on the surface excluding 1 mm from the outer edge.
- a resin layer such as polyimide or an inorganic material layer is formed on the surface of the multilayer ceramic substrate 3. Thereafter, a through hole 27 is formed in the insulating layer 5. Next, a photoresist is applied on the insulating layer 5 and the through hole 27. At this time, the thickness of the photoresist is adjusted so as to be thicker than the thickness of the wiring pattern to be formed. Next, the photoresist is exposed and developed using, for example, a stepper, and unnecessary portions of the photoresist are removed. Thus, a photoresist pattern 30 is formed on the insulating layer 5 as shown in FIGS. 29 (a) and 29 (b).
- a metal layer 32 is formed on the photoresist pattern 30 by using a vacuum film forming method.
- the vacuum film forming method include a sputtering method and a vacuum deposition method.
- the metal deposited on the photoresist pattern 30 are Cu, Ag, Au, Ni, Al, etc., which have a low electrical resistance.
- the metal layer 32 is formed not only on the photoresist but also on the insulating layer 5 and on the portion of the surface electrode 7 that overlaps the through hole 27.
- the photoresist pattern 30 is removed by a known method (see FIGS. 31A and 31B).
- the metal on the photoresist pattern 30 in the metal layer 32 is removed together with the photoresist pattern 30 (lift-off).
- the metal is left only in the region that was not masked by the photoresist pattern 30.
- the wiring pattern 6 can be formed.
- the manufacturing method according to the second embodiment since an electrolytic solution necessary for electrolytic plating is not used, there are metal options for forming the wiring pattern 6 as compared with the case where the electrolytic plating method is applied. To increase.
- FIG. 32 shows a cross section of the mounting board according to the third embodiment.
- a mounting substrate 4 a shown in FIG. 32 has an insulating layer 5 between the surface 3 x of the ceramic chip substrate 300 and the wiring pattern 6.
- the mounting substrate 4 a has bump electrodes 13 on the wiring pattern 6.
- the mounting substrate 4a is formed by forming the bump electrodes 13 on the wiring pattern 6 of the mounting substrate wafer obtained by the method described in the first or second embodiment, and then cutting and dividing the mounting substrate wafer. Can be produced.
- the formation of the bump electrodes 13 may be performed after the mounting substrate wafer is cut and divided.
- the bump electrode 13 may have a laminated structure of a plurality of metal layers.
- an electrode pad having a Ni / Au laminated structure is formed by using photolithography at a position where the bump electrode 13 is to be formed in the wiring pattern 6 of the mounting substrate wafer.
- a protective layer of a wiring pattern may be formed in a region other than the portion where the bump electrode 13 is formed. This protective layer is formed from an insulating material.
- an Sn layer is formed on the electrode pad. Thereby, a bump electrode capable of physically and electrically connecting the electrode (for example, Cu electrode) on the semiconductor chip side and the wiring pattern 6 is obtained.
- the Sn layer can be formed efficiently.
- the formation method of Sn layer is not limited to a specific method, For example, an electrolytic plating method, a sputtering method, etc. can be used. If the Sn layer has a thickness of about 15 ⁇ m, it is beneficial because sufficient bonding strength to the semiconductor chip can be obtained. From the viewpoint of depositing Sn to a thickness of 15 ⁇ m, it is advantageous to apply an electrolytic plating method to the formation of the Sn layer.
- a ceramic material that takes into consideration the melting point of the electrode material formed on the multilayer ceramic substrate is used as the green sheet material.
- the green sheet material For example, at least one of various oxides of Al, Si, Sr, and Ti as main components, and various oxides of Bi, Na, K, and Co as subcomponents, and at least of various oxides of Cu, Mn, and Ag
- a mixture containing one or more and other inevitable impurities is calcined at 700 ° C. to 850 ° C. and pulverized to obtain finely pulverized particles having an average particle size of 0.6 to 2 ⁇ m.
- a green sheet is obtained by forming a slurry obtained by adding various additives such as an organic binder, a plasticizer, and a solvent into the obtained finely pulverized particles into a sheet shape by a doctor blade method or the like.
- various additives such as an organic binder, a plasticizer, and a solvent
- changes in dimensions and shape during firing can be suppressed.
- Use of a ceramic material that can form a fired body having a thermal expansion coefficient close to that of Si is advantageous because it can reduce the difference in thermal expansion between the semiconductor chip and the ceramic chip substrate. By reducing the difference in thermal expansion between the semiconductor chip and the ceramic chip substrate, it is possible to suppress the influence of warp caused by the thermal expansion difference due to the heat treatment at the time of mounting the semiconductor chip.
- the circuit pattern for the internal electrode and / or the internal wiring can be easily formed in the process of manufacturing the multilayer ceramic substrate. Therefore, for example, by forming a green sheet using a ceramic material capable of realizing a high dielectric constant, a circuit incorporating the function of a capacitor can be formed inside the multilayer ceramic substrate. Further, for example, a material having varistor characteristics may be used as the ceramic material. As a result, the circuit formed inside the multilayer ceramic substrate can have a function of preventing overcurrent. Furthermore, by using a material having high thermal conductivity, heat generated in a semiconductor chip or the like can be released to the multilayer ceramic substrate.
- Example 1 Using a method similar to the manufacturing method described in the first embodiment, a mounting substrate wafer having a diameter of 150 mm was manufactured.
- the flattening process of the ceramic fired body was performed by placing the processed surface of the front surface ceramic layer or the back surface ceramic layer directly on the surface plate for polishing so that the substrate was not deformed. Since the work surface (for example, the surface) is used as the polishing reference surface as it is, foreign objects such as unevenness of the substrate and adhesive members, or particles entering from the polishing process are not affected by the work surface. The flatness after processing is improved.
- Table 1 shows the results of measuring SFQR by dividing the obtained multilayer ceramic substrate into 20 mm square evaluation regions.
- the obtained multilayer ceramic substrate achieved SFQR of 2 ⁇ m or less in 100% of the plurality of evaluation regions, and achieved SFQR of 1 ⁇ m or less in 97%.
- the chip area size of each mounting substrate wafer was 15 mm ⁇ 15 mm, and 60 chip areas were formed on one wafer.
- a photoresist for forming a wiring pattern a positive photoresist THMR-iP5700 (viscosity: 0.025 Pa ⁇ s) manufactured by Tokyo Ohka Kogyo Co., Ltd. was used.
- a spin coating method (rotation speed: 3000 rpm) was used for applying the photoresist.
- the thickness of the photoresist was 2.3 ⁇ m.
- a Nikon i-line stepper NSR-2205i12 was used for exposure of the photoresist.
- the line pitch in the photomask for forming the photoresist pattern was 2 ⁇ m.
- Example 2 Example 1 except that one surface (for example, the back surface) is fixed to a flat surface (for example, a lap plate) by applying a load and the surface to be processed (for example, the surface) is polished in the planarization processing of the ceramic fired body.
- a mounting substrate wafer was produced under the same conditions as those described above.
- Table 1 shows the results of measuring SFQR by dividing the multilayer ceramic substrate into 20 mm square evaluation regions. Of the plurality of evaluation regions, the obtained multilayer ceramic substrate achieved SFQR of 2 ⁇ m or less in 78% and SFQR of 1 ⁇ m or less in 59%.
- Example 3 Two mounting substrate wafers were produced using the same method as in Example 1, and cut and divided according to the chip area to obtain a plurality of cut pieces. Among the obtained cut pieces, a cut piece having an SFQR of 2 ⁇ m or less of the ceramic chip substrate was extracted to obtain a mounting board of Example 3. In one mounting substrate wafer, 60 of the 60 cut pieces cut out have an SFQR of the ceramic chip substrate of 2 ⁇ m or less, and in the other mounting substrate wafer, 60 cut out pieces. Of 54 pieces, the SFQR of the ceramic chip substrate was 2 ⁇ m or less. The line width of the formed wiring pattern was 0.5 to 1.5 ⁇ m, and the line interval was 0.5 to 1.5 ⁇ m.
- Table 2 shows the results of confirming the wiring pattern on the mounting board of Example 3. As shown in Table 2, in the mounting substrate of Example 3, the minimum wiring width of 2 ⁇ m or less was achieved in all the mounting substrates. The minimum wiring interval was larger than 0 ⁇ m and 2 ⁇ m or less.
- Comparative Example 1 Of the cut pieces obtained by cutting and dividing the mounting substrate wafer according to the chip area, cut pieces having an SFQR of 2 ⁇ m or more of the ceramic chip substrate were extracted, and these were used as the mounting substrate of Comparative Example 1. Table 2 shows the result of confirming the wiring pattern on the mounting substrate of Comparative Example 1. In all the mounting boards of Comparative Example 1, the minimum wiring width exceeded 2 ⁇ m or the minimum wiring interval did not exceed 0 ⁇ m. That is, the wiring pattern collapsed.
- Example 4 A mounting substrate of Example 4 was produced in the same manner as in Example 1 except that exposure was performed without correcting the tilt of the substrate using a stepper (manufactured by NIKON, NSR-2205i12). In the obtained mounting substrate wafer, it was confirmed that SBIR was 2 ⁇ m or less in at least 50% or more of the evaluation region. Further, the minimum wiring interval of the wiring pattern formed on the mounting substrate is greater than 0 ⁇ m and 2 ⁇ m or less, and the minimum wiring width is 2 ⁇ m or less.
- Example 5 A mounting substrate of Example 5 was produced in the same manner as in Example 1 except that the aligner (manufactured by SUSS, MA-6) was used instead of the stepper to perform batch exposure. In the obtained wafer for mounting substrates, it was confirmed that GBIR was 2 ⁇ m or less. Further, the minimum wiring interval of the wiring pattern formed on the mounting substrate is greater than 0 ⁇ m and 2 ⁇ m or less, and the minimum wiring width is 2 ⁇ m or less.
- a mounting substrate that facilitates mounting a highly integrated semiconductor chip on a main substrate and the like, and a mounting substrate wafer for manufacturing the mounting substrate are provided.
- Embodiments of the present disclosure can be applied to, for example, an interposer that can be used in the fabrication of semiconductor packages, mobile device circuits, and the like.
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Abstract
Description
まず、複数の半導体チップを実装するための本開示における実装基板の基本構成例を説明する。この実装基板は、実装基板用ウエハから切り出された複数の実装基板の1つである。各実装基板は、その表面に半導体チップが実装されることにより、チップモジュールを形成する。チップモジュールは、メイン基板(マザーボード)に実装されて使用され得る。半導体チップとは、典型的には、大規模集積回路が形成された半導体素子であるが、通信回路または電力回路が形成された半導体素子であってもよい。チップを構成する半導体は、単結晶シリコンに限定されず、炭化ケイ素および窒化ガリウムなどのワイドバンドギャップ半導体であってもよい。一方、メイン基板は、典型的には、プリント配線基板であり得る。チップモジュールが実装されたメイン基板は、携帯端末、情報機器、家電機器、自動車部品、および産業用機械など種々の装置または機器に使用され得る。
本開示によれば、収縮を抑制した多層セラミックス基板を用い、その表面にフォトリソグラフィによって微細加工を実行する必要がある。フォトリソグラフィ工程の対象は、多層セラミックス基板である。多層セラミックス基板は、表面に位置する表面セラミックス層、裏面に位置する裏面セラミックス層、表面セラミックス層内の複数の表面電極、裏面セラミックス層内の複数の裏面電極、および、複数の表面電極と前記複数の裏面電極との間で電気的接続を行う複数の内部電極を有する。複数の表面電極の電極中心間距離は複数の裏面電極の電極中心間距離よりも小さい。
図11は、本開示の実装基板用ウエハの上面図である。図11に示す実装基板用ウエハ1は、多層セラミックス基板3を有する。多層セラミックス基板3の表面上に、複数個のチップエリア2が集約されている。チップエリアを含むように実装基板用ウエハ1を切断して実装基板用ウエハ1を分割することにより、複数個の実装基板を得られる。実装基板用ウエハ1の形状は、従来のSiウエハの加工プロセスを適用できるように、例えば、直径が150mm以上の円盤状であっても良い。実装基板用ウエハ1の形状は、円盤状以外の形状であっても構わない。1枚の実装基板用ウエハ1から多くの実装基板を得られるようにチップエリア2を配置すると有益であり、実装基板用ウエハ1の形状は、チップエリア2のサイズに応じて任意に設計できる。ただし、多層セラミックス基板3の外縁部から1mmのエリアはハンドリング時に異物が付着しやすい。そのため、この範囲にはチップエリア2を配置しないことが有益である。
多層セラミックス基板3上の配線パターン6は、真空成膜法を用いて形成しても良い。
図32は、第3の実施形態による実装基板の断面を示す。図32に示す実装基板4aは、セラミックスチップ基板300の表面3xと配線パターン6との間に絶縁層5を有している。また、実装基板4aは、配線パターン6上にバンプ電極13を有している。実装基板4aは、例えば、第1または第2の実施形態において説明した方法により得られる実装基板用ウエハの配線パターン6上にバンプ電極13を形成した後、実装基板用ウエハを切断および分割することによって作製することができる。なお、バンプ電極13の形成は、実装基板用ウエハを切断および分割の後に実行されても良い。
第1の実施形態に記載の製造方法と同様の方法を用いて、直径150mmの実装基板用ウエハを作製した。セラミックス焼成体の平坦化加工は、表面セラミックス層または裏面セラミックス層の被加工面を研磨のための定盤に基板が変形しないように直接載置して行った。被加工面(例えば表面)そのまま研磨基準面とすることで、基板の凸凹や接着部材などの異物、あるいは研磨工程から入るパーティクルが挟まるなどが被加工面に与える影響がなくなるため、被加工面の加工後の平坦性が向上する。得られた多層セラミックス基板を20mm角の評価領域に区分してSFQRを測定した結果を表1に示す。
セラミックス焼成体の平坦化加工において、一方の面(例えば裏面)を平坦な面(例えばラッププレートなど)に荷重をかけて固着し、被加工面(例えば表面)を研磨したこと以外は実施例1と同じ条件で、実装基板用ウエハを作製した。多層セラミックス基板を20mm角の評価領域に区分してSFQRを測定した結果を表1に示す。得られた多層セラミックス基板は、前記複数の評価領域のうちの、78%においてSFQRが2μm以下を達成し、59%においてSFQRが1μm以下を達成していた。
実施例1と同様の方法を用いて、実装基板用ウエハを2枚作製し、チップエリアに従って切断および分割して複数の切断片を得た。得られた切断片のうち、セラミックスチップ基板のSFQRが2μm以下である切断片を抽出し、実施例3の実装基板とした。一方の実装基板用ウエハでは、切り出された60個の切断片うちの60個は、セラミックスチップ基板のSFQRが2μm以下であり、もう一枚の実装基板用ウエハでは、切り出された60個の切断片うちの54個が、セラミックスチップ基板のSFQRが2μm以下であった。形成された配線パターンのライン幅は0.5~1.5μmであり、ライン間隔は0.5~1.5μmであった。
実装基板用ウエハをチップエリアに従って切断および分割して得られた切断片のうち、セラミックスチップ基板のSFQRが2μmを超える切断片を抽出し、これらを比較例1の実装基板とした。比較例1の実装基板における配線パターンを確認した結果を表2に示す。比較例1の実装基板の全てにおいて、最小配線幅が2μmを超えるか、最小配線間隔が0μmを超えていないかの少なくともいずれかであった。すなわち、配線パターン崩れが発生していた。
ステッパー(NIKON製、NSR-2205i12)を用いて、基板の傾きを補正せず露光を行ったこと以外は実施例1と同様にして、実施例4の実装基板を作製した。得られた実装基板用ウエハにおいては、評価領域の少なくとも50%以上においてSBIRが2μm以下であることを確認した。また、実装基板に形成された配線パターンの最小配線間隔は0μmより大きく2μm以下であり、最小配線幅2μm以下を達成していた。
ステッパーの代わりにアライナー(SUSS製、MA-6)を用いて一括露光を行ったこと以外は実施例1と同様にして、実施例5の実装基板を作製した。得られた実装基板用ウエハにおいては、GBIRが2μm以下であることを確認した。また、実装基板に形成された配線パターンの最小配線間隔は0μmより大きく2μm以下であり、最小配線幅2μm以下を達成していた。
2・・・チップエリア
3・・・多層セラミックス基板
4・・・実装基板
5・・・絶縁層
6・・・配線パターン
7・・・表面電極
s1・・・最小配線幅
p1・・・最小配線間隔
8・・・内部電極
9・・・裏面電極
12・・・基準面
t1・・・バンプ電極の高さ
p2・・・バンプ電極のピッチ
13・・・バンプ電極
14・・・非吸着時のグローバルベストフィット基準面
15・・・グリーンシート
16・・・電極ビア
17・・・レーザー
18・・・電極材料
19・・・マスク
20・・・スキージ
21・・・電極付きグリーンシート
22・・・積層グリーンシート体
23・・・セラミックス焼成体
24・・・砥粒
25・・・レーザー
26・・・識別マーク
27・・・スルーホール
28・・・金属下地膜
29・・・フォトレジスト
30・・・フォトレジストパターン
31・・・めっき層
32・・・金属層
300・・・セラミックスチップ基板
Claims (27)
- 表面および裏面を有し、前記表面に位置する表面セラミックス層と、前記裏面に位置する裏面セラミックス層と、前記表面セラミックス層を貫通する複数の表面電極、前記裏面セラミックス層を貫通する複数の裏面電極、および、前記多層セラミックス基板の内部にあって前記複数の表面電極と前記複数の裏面電極との間で電気的接続を行う複数の内部電極を形成した中間セラミックス層とを有する多層セラミックス基板と、
前記多層セラミックス基板の前記表面上に形成され、2μm以下の最小配線幅および2μm以下の最小配線間隔を有する配線パターンと、
を備え、
前記複数の表面電極の電極中心間距離は、前記複数の裏面電極の電極中心間距離よりも小さく、
前記多層セラミックス基板は、20mm角を単位とする複数の評価領域に区分したときに、前記複数の評価領域のうちの少なくとも50%において20mm角の評価領域におけるSFQR(Site Front Least Squares Ranges)が2μm以下になるように表面が平坦化されている、実装基板用ウエハ。 - 前記多層セラミックス基板は、20mm角を単位とする複数の評価領域に区分したときに、前記複数の評価領域のうちの少なくとも50%において20mm角の領域におけるSBIR(Site Back Surface Referenced Ideal Ranges)が2μm以下になるように表面が平坦化されている、請求項1に記載の実装基板用ウエハ。
- 前記多層セラミックス基板は、GBIR(Global Back Ideal Ranges)が2μm以下になるように表面が平坦化されている、請求項1または2に記載の実装基板用ウエハ。
- 前記多層セラミックス基板の前記表面と前記配線パターンとの間に設けられた絶縁層を備え、
前記絶縁層は、前記複数の表面電極の各々を前記配線パターンに電気的に接続する複数の開口部を有しており、
前記複数の表面電極は、それぞれ、前記複数の開口部に対して整合している、請求項1から3のいずれかに記載の実装基板用ウエハ。 - 前記複数の表面電極の各々の中心位置から、前記複数の開口部の対応する1つの中心位置までの距離は、表面電極の半径以下である、請求項4に記載の実装基板用ウエハ。
- 前記複数の開口部の位置は、フォトリソグラフィ工程によって規定されている、請求項4または5に記載の実装基板用ウエハ。
- 前記複数の配線パターンの位置は、フォトリソグラフィ工程によって規定されている、請求項1から6のいずれかに記載の実装基板用ウエハ。
- 請求項1から7のいずれかに記載の実装基板用ウエハのための多層セラミックス基板であって、
表面および裏面を有し、
前記表面に位置する表面セラミックス層と、
前記裏面に位置する裏面セラミックス層と、
前記表面セラミックス層を貫通する複数の表面電極と、
前記裏面セラミックス層を貫通する複数の裏面電極と、
前記複数の表面電極と前記複数の裏面電極との間で電気的接続を行う複数の内部電極を形成した中間セラミックス層と
を備え、
前記複数の表面電極の電極中心間距離は、前記複数の裏面電極の電極中心間距離よりも小さく、
前記多層セラミックス基板は、20mm角を単位とする複数の評価領域に区分したときに、前記複数の評価領域のうちの少なくとも50%において20mm角の領域におけるSFQR(Site Front Least Squares Ranges)が2μm以下になるように表面が平坦化されている、多層セラミックス基板。 - 半導体チップが実装される実装基板であって、
表面に位置する表面セラミックス層と、裏面に位置する裏面セラミックス層と、前記表面セラミックス層を貫通する複数の表面電極、前記裏面セラミックス層を貫通する複数の裏面電極、および、前記多層セラミックス基板の内部にあって前記複数の表面電極と前記複数の裏面電極との間で電気的接続を行う複数の内部電極を形成した中間セラミックス層とを有するセラミックスチップ基板と、
前記セラミックスチップ基板の前記表面上に形成され、2μm以下の最小配線幅および2μm以下の最小配線間隔を有する配線パターンと、
を備え、
前記複数の表面電極の電極中心間距離は、前記複数の裏面電極の電極中心間距離よりも小さく、
前記セラミックスチップ基板は、20mm角の領域におけるSFQR(Site Front Least Squares Ranges)が2μm以下になるように表面が平坦化されている、実装基板。 - 前記セラミックスチップ基板は、20mm角の領域におけるSBIR(Site Back Surface Referenced Ideal Ranges)が2μm以下になるように表面が平坦化されている、請求項9に記載の実装基板。
- 前記配線パターン上に形成された複数のバンプ電極を備える請求項9または10に記載の実装基板。
- 前記複数のバンプ電極の電極中心間距離は、前記裏面電極の電極中心間距離の1/10以下である請求項9から11のいずれかに記載の実装基板。
- 前記セラミックスチップ基板の前記表面と前記配線パターンとの間に設けられた絶縁層を備え、
前記絶縁層は、前記複数の表面電極の各々を前記配線パターンに電気的に接続する複数の開口部を有しており、
前記複数の表面電極は、それぞれ、前記複数の開口部に対して整合している、請求項9から12のいずれかに記載の実装基板。 - 前記複数の表面電極の各々の中心位置から、前記複数の開口部の対応する1つの中心位置までの距離は、表面電極の半径以下である、請求項13に記載の実装基板。
- 前記複数の開口部の位置は、フォトリソグラフィ工程によって規定されている、請求項13または14に記載の実装基板。
- 前記複数の配線パターンの位置は、フォトリソグラフィ工程によって規定されている、請求項9から15のいずれかに記載の実装基板。
- 請求項1から7のいずれかに記載の実装基板用ウエハから個別に切り出された実装基板であって、
前記配線パターン上に形成された複数のバンプ電極を備えている、実装基板。 - 前記複数のバンプ電極の電極中心間距離は、前記裏面電極の電極中心間距離の1/10以下である請求項17に記載の実装基板。
- 請求項9から18のいずれかに記載の実装基板と、
前記実装基板上に実装された複数の半導体チップと、
を備えるチップモジュール。 - 表面に位置する表面セラミックス層と、裏面に位置する裏面セラミックス層と、前記表面セラミックス層を貫通する複数の表面電極、前記裏面セラミックス層を貫通する複数の裏面電極、および、前記多層セラミックス基板の内部にあって前記複数の表面電極と前記複数の裏面電極との間で電気的接続を行う複数の内部電極を形成した中間セラミックス層とを有し、かつ、前記複数の表面電極の電極中心間距離は前記複数の裏面電極の電極中心間距離よりも小さい多層セラミックス基板を用意する工程と、
20mm角を単位とする複数の評価領域に前記多層セラミックス基板を区分したときに、前記複数の評価領域のうちの少なくとも50%において20mm角の評価領域におけるSFQR(Site Front Least Squares Ranges)が2μm以下となるように前記多層セラミックス基板の少なくとも表面を平坦化加工する工程と、
フォトリソグラフィにより、2μm以下の最小配線幅および2μm以下の最小配線間隔を有する配線パターンを前記多層セラミックス基板の前記表面上に形成する工程と、
を含み、
前記多層セラミックス基板を用意する工程は、
前記表面セラミックス層を形成する第1グリーンシートおよび前記裏面セラミックス層を形成する第2グリーンシートを用意する工程と、
前記第1および第2グリーンシートに対するエージングを行う工程と、
前記エージング処理の後に、前記複数の表面電極および前記複数の裏面電極を規定する複数の開口部を前記第1および第2グリーンシートに形成する工程と、
前記表面セラミックス層と前記裏面セラミックス層との間に位置する少なくとも1つのセラミックス層を形成する少なくとも1つの第3グリーンシートを用意する工程と、
前記複数の内部電極を規定する複数の開口部を第3グリーンシートに形成する工程と、
前記第1、第2および第3グリーンシートにおける前記複数の開口部内に導電材料を充填する工程と、
前記第1、第2および第3グリーンシートを積層して圧着することにより積層グリーンシート体を形成する工程と、
前記積層グリーンシート体を焼成して、表面と裏面を接続する内部電極と表面電極と裏面電極とを有するセラミックス焼成体を形成する工程と、
を含む、実装基板用ウエハの製造方法。 - 前記積層グリーンシート体を焼成する工程の前後において、前記多層セラミックス基板は、面内方向に1%以下の距離だけ収縮する、請求項20に記載の実装基板用ウエハの製造方法。
- セラミックスのグリーンシートに複数の電極ビアを形成し、前記グリーンシートの少なくとも一方の面から前記電極ビアに電極ペーストを充填し、電極付きグリーンシートを形成する工程と、
複数枚の前記電極付きグリーンシートの間の各電極を電気的に接続するように積層し、圧着して一体化した積層グリーンシート体を形成する工程と、
前記積層グリーンシート体を焼成して、表面と裏面を接続する内部電極と、表面電極と、裏面電極とを有するセラミックス焼成体を形成する工程と、
前記セラミックス焼成体の少なくとも表面を加工することにより、20mm角を単位とする複数の評価領域に区分したときに前記複数の評価領域のうちの少なくとも50%において20mm角の評価領域におけるSFQRが2μm以下に表面が平坦化された多層セラミックス基板を得る工程と、
前記多層セラミックス基板の少なくとも表面の電極と電気的に接続される配線パターンを、露光装置を用いたフォトリソグラフィによって形成する工程とを含む、実装基板用ウエハの製造方法。 - 前記配線パターンを形成する工程は、
少なくとも前記表面に絶縁層を形成し、前記絶縁層の一部に前記表面の電極を露出させるためのスルーホールを少なくとも1つ以上形成する工程と、
前記絶縁層及び前記スルーホールに金属下地層を形成する工程と、
前記金属下地層の上にフォトレジストを塗布する工程と、
露光装置を用いてフォトレジストを露光する工程と、
露光したフォトレジストを現像してフォトレジストの一部を除去してフォトレジストパターンを得る工程と、
電解めっき法で、フォトレジストパターンのフォトレジストの一部を除去した箇所の前記金属下地層にめっき層を析出させて配線パターンを得る工程と、
前記フォトレジストパターンを除去する工程と、
前記めっき層を析出させた箇所以外の領域に形成された前記金属下地層を除去する工程と、
を含む、請求項22に記載の実装基板用ウエハの製造方法。 - 前記配線パターンを形成する工程は、
少なくとも前記表面に絶縁層を形成し、前記絶縁層の一部に前記表面の電極を露出させるためのスルーホールを少なくとも1つ以上形成する工程と、
前記絶縁層及びスルーホールの上にフォトレジストを塗布する工程と、
露光装置を用いてフォトレジストを露光する工程と、
露光したフォトレジストを現像してフォトレジストの一部を除去してフォトレジストパターンを得る工程と、
前記フォトレジストパターン、絶縁層及びスルーホールの上に真空成膜法によって金属層を形成する工程と、
前記フォトレジストパターンを除去することで、前記フォトレジストパターン上に堆積した金属を除去(リフトオフ)し、前記絶縁層及びスルーホール上に堆積した金属のみを残し、配線パターンを得る工程と、
を含む請求項22に記載の実装基板用ウエハの製造方法。 - 前記多層セラミックス基板を得る工程において、前記セラミックス焼成体の表面セラミックス層及び裏面セラミックス層を片面ずつ平坦化加工する、請求項22から24のいずれかに記載の実装基板用ウエハの製造方法。
- 前記多層セラミックス基板を得る工程において、前記セラミックス焼成体の表面セラミックス層及び裏面セラミックス層を両面同時に平坦化加工する、請求項22から24のいずれかに記載の実装基板用ウエハの製造方法。
- 前記多層セラミックス基板を得る工程において、少なくとも前記表面セラミックス層の表面をCMP(Chemical Mechanical Polishing)を用いて加工する工程を含む、請求項25または26に記載の実装基板用ウエハの製造方法。
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JP6624271B2 (ja) | 2019-12-25 |
US20190318988A1 (en) | 2019-10-17 |
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