WO2014129433A1 - 複合基板、半導体デバイス及び半導体デバイスの製法 - Google Patents

複合基板、半導体デバイス及び半導体デバイスの製法 Download PDF

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WO2014129433A1
WO2014129433A1 PCT/JP2014/053689 JP2014053689W WO2014129433A1 WO 2014129433 A1 WO2014129433 A1 WO 2014129433A1 JP 2014053689 W JP2014053689 W JP 2014053689W WO 2014129433 A1 WO2014129433 A1 WO 2014129433A1
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Prior art keywords
substrate
semiconductor
semiconductor device
composite
bonding
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PCT/JP2014/053689
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English (en)
French (fr)
Inventor
井出　晃啓
達朗 高垣
杉夫 宮澤
裕二 堀
知義 多井
良祐 服部
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日本碍子株式会社
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Priority to KR1020157021923A priority Critical patent/KR102222089B1/ko
Priority to JP2015501445A priority patent/JPWO2014129433A1/ja
Priority to CN201480009140.3A priority patent/CN105074868B/zh
Priority to EP14754763.2A priority patent/EP2960925B1/en
Publication of WO2014129433A1 publication Critical patent/WO2014129433A1/ja
Priority to US14/825,715 priority patent/US9812345B2/en

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Definitions

  • the present invention relates to a composite substrate, a semiconductor device, and a method for manufacturing a semiconductor device.
  • Such a composite substrate includes a support substrate and a functional layer (semiconductor layer).
  • a functional layer semiconductor layer
  • SOI semiconductor-on-Insulator
  • SOS Si-on-Sapphire
  • the present invention has been made to solve such a problem, and a main object thereof is to eliminate a back grinding process in manufacturing a semiconductor device.
  • the present invention adopts the following means in order to achieve the main object described above.
  • the composite substrate of the present invention is A composite substrate in which a semiconductor substrate and an insulating support substrate are bonded together,
  • the support substrate is bonded to a first substrate and a second substrate made of the same insulating material with a strength capable of being peeled off by a blade, and is on the opposite side of the first substrate from the bonding surface with the second substrate. It is bonded to the semiconductor substrate on the surface.
  • the manufacturing method of the semiconductor device of the present invention is as follows: (A) preparing the composite substrate described above; (B) forming a CMOS semiconductor structure on the semiconductor substrate of the composite substrate; (C) peeling and removing the second substrate from the first substrate with a blade; (D) dicing the composite substrate to obtain a semiconductor device; Is included.
  • the semiconductor device of the present invention is obtained by the above-described method for manufacturing a semiconductor device of the present invention.
  • the composite substrate of the present invention is a support substrate in which a first substrate and a second substrate made of the same insulating material are bonded with a strength capable of being peeled off by a blade. Therefore, the support substrate can be made thicker than when only the first substrate is used as the support substrate. As a result, the warpage of the composite substrate that occurs in response to a temperature change can be reduced, and the strength of the composite substrate can be increased. Further, after the CMOS semiconductor structure is formed on the semiconductor substrate, the thickness of the support substrate can be easily reduced by peeling and removing the second substrate from the first substrate with a blade. Therefore, the cost can be reduced compared to the case where the thick support substrate is thinned by the back grinding process. As a result, it is possible to suppress an increase in manufacturing cost when the semiconductor device is formed. Since the removed second substrate can be reused when producing the composite substrate of the present invention, the cost can be suppressed in this respect as well.
  • the above-described composite substrate of the present invention is prepared, a CMOS semiconductor structure is formed on the semiconductor substrate of the composite substrate, and the second substrate is peeled off from the first substrate with a blade and removed. After that, dicing is performed to obtain a semiconductor device.
  • the CMOS semiconductor structure is formed, the thickness of the support substrate can be easily reduced by removing the second substrate from the first substrate with a blade. Therefore, the cost can be reduced compared to the case where the thick support substrate is thinned by the back grinding process. As a result, it is possible to suppress an increase in manufacturing cost when the semiconductor device is formed.
  • FIG. 1 is a cross-sectional view schematically showing a composite substrate 10.
  • 3 is a cross-sectional view schematically showing a manufacturing process of the composite substrate 10.
  • FIG. 4 is a cross-sectional view schematically showing a manufacturing process of the semiconductor device 30.
  • FIG. 1 is a cross-sectional view schematically showing a composite substrate 10 of the present embodiment.
  • the composite substrate 10 includes a semiconductor substrate 12 and a support substrate 14.
  • the semiconductor substrate 12 is a substrate capable of manufacturing a semiconductor structure.
  • Examples of the material of the semiconductor substrate 12 include silicon, and specifically, n-type silicon and p-type silicon. In addition to germanium, compound semiconductors such as GaN and GaAs are also used.
  • the size of the semiconductor substrate 12 is not particularly limited. For example, the diameter is 50 to 150 mm and the thickness is 0.2 to 50 ⁇ m.
  • the support substrate 14 is an insulating substrate, and is bonded to the back surface of the semiconductor substrate 12 by direct bonding or via an organic adhesive layer.
  • the support substrate 14 is formed by directly bonding a first substrate 14a and a second substrate 14b made of the same insulating material with a strength capable of being peeled off by a blade or via an organic adhesive layer.
  • the support substrate 14 is bonded to the semiconductor substrate 12 on the surface of the first substrate 14a opposite to the bonding surface with the second substrate 14b.
  • Examples of the material of the support substrate 14 include silicon, sapphire, alumina, silicon nitride, aluminum nitride, and silicon carbide.
  • the support substrate 14 is, for example, 50 to 300 mm in diameter and 200 to 1200 ⁇ m in thickness.
  • the first and second substrates 14a and 14b are, for example, 50 to 300 mm in diameter and 100 to 600 ⁇ m in thickness.
  • FIG. 2 is a cross-sectional view schematically showing the manufacturing process of the composite substrate 10.
  • first and second substrates 14a and 14b made of the same insulating material in a disk shape are prepared (see FIG. 2A), and the substrates 14a and 14b are joined by direct joining to produce the support substrate 14 (see FIG. 2A). (Refer FIG.2 (b)).
  • the following method is exemplified as a method of directly bonding both the substrates 14a and 14b. That is, first, the bonding surfaces of both the substrates 14a and 14b are washed to remove the dirt adhering to the bonding surfaces.
  • the substrates 14a and 14b are bonded together at room temperature in a vacuum.
  • the bonding strength between the two substrates 14a and 14b is set to a strength that peels when a blade having a thickness of 100 ⁇ m is inserted.
  • the surface roughness of the bonding surface, the irradiation time of the ion beam, the pressure at the time of bonding, and the like are determined by experiments so as to obtain such strength.
  • both the substrates 14a and 14b are silicon substrates
  • the bulk strength of silicon is 2 to 2.5 J / m 2
  • the bond energy of Si and Si of both the substrates 14a and 14b is A smaller value, for example, 0.05 to 0.6 J / m 2 is set. If it is less than 0.05 J / m 2, it may be peeled off during production of the semiconductor device, and if it exceeds 0.6 J / m 2 , the blade may not be smoothly inserted.
  • the bonding strength is 0.05 to 0.6 J which can be peeled off by shortening the ion beam irradiation time when bonding the mirror surfaces. / M 2 .
  • the surface roughness Ra of the bonding surfaces of both the substrates 14a and 14b is about 100 nm, even if the bonding conditions are the same as when the mirror surfaces are bonded to each other, the bonding strength can be made peelable.
  • bonding by plasma activation can also be used.
  • the surfaces are activated by irradiating the surfaces of both substrates with oxygen plasma or nitrogen plasma.
  • oxygen plasma or nitrogen plasma By bonding the two substrates in this state, the spontaneous bonding surface propagates and a bonding surface can be obtained.
  • the heat treatment after bonding is not performed and only activated bonding by plasma is performed.
  • the support substrate 14 and the semiconductor substrate 12 are bonded (see FIG. 2C). Specifically, the front surface of the first substrate 14 a and the back surface of the semiconductor substrate 12 of the support substrate 14 are bonded.
  • the bonding method may be direct bonding or bonding via an organic adhesive layer. Since the direct bonding has already been described, the description thereof is omitted here. However, the surface roughness of the bonding surface, the irradiation time of the ion beam, the pressure at the time of bonding, etc. are determined so that the bonding strength is equal to or higher than the bulk strength of silicon of 2 to 2.5 J / m 2 .
  • the direct bonding method may be a method using plasma or a neutral atom beam, and is not particularly limited.
  • FIG. 3 is a cross-sectional view schematically showing the manufacturing process of the semiconductor device 30.
  • the composite substrate 10 is prepared (see FIG. 3A). Since this has already been described with reference to FIG. 2, the description thereof is omitted here.
  • CMOS semiconductor structure and a rewiring layer are formed on the surface of the semiconductor substrate 12 of the composite substrate 10 (see FIG. 3B).
  • the surface of the semiconductor substrate 12 is partitioned so that a large number of semiconductor devices 30 are formed, and a CMOS semiconductor structure and a redistribution layer are formed at a position corresponding to each semiconductor device using a photolithography technique.
  • the second substrate 14b is peeled off from the first substrate 14a with a blade having a thickness of 100 ⁇ m (see FIG. 3C).
  • the surface (peeling surface) of the first substrate 14a after the second substrate 14b is peeled does not need to be polished because the surface roughness Ra is sufficiently small, but may be polished as necessary.
  • the release surface of the first substrate 14a includes elements derived from the material of the vacuum chamber used for direct bonding. For example, when the material of the vacuum chamber is stainless steel, Fe element and Cr element derived therefrom are included.
  • the second substrate 14b peeled from the first substrate 14a can be reused when the composite substrate 10 is manufactured next time.
  • the support substrate 14 in which the first substrate 14a and the second substrate 14b made of the same insulating material are joined is used, only the first substrate 14a is used as the support substrate 14.
  • the support substrate 14 can be made thicker than the case where it is used. As a result, the warpage of the composite substrate 10 that occurs according to the temperature change can be suppressed, and the strength of the composite substrate 10 can be increased. Further, after the CMOS semiconductor structure and the redistribution layer are formed on the semiconductor substrate 12, the thickness of the support substrate 14 can be easily reduced by removing the second substrate 14b from the first substrate 14a with a blade. That is, the height of the semiconductor device can be reduced.
  • the cost can be reduced compared to the case where a bulk support substrate having the same thickness as the support substrate 14 is thinned by the back grinding process. As a result, an increase in the manufacturing cost of the semiconductor device 30 can be suppressed. Since the removed second substrate 14b can be reused when the composite substrate 10 is manufactured next time, the cost can also be suppressed in this respect.
  • the first and second substrates 14a and 14b are bonded by direct bonding.
  • the first and second substrates 14a and 14b may be bonded via an organic adhesive layer.
  • an organic adhesive is uniformly applied to one or both of the bonding surfaces of the first and second substrates 14a and 14b, and the organic adhesive (for example, urethane-based, epoxy-based, etc.) is solidified in a state where the both are overlapped.
  • the bonding strength is set to be the same as that in the above-described embodiment. Even if it does in this way, the effect of the present invention will be acquired.
  • Example 1 In this embodiment, a support substrate in which a first substrate and a second substrate made of translucent alumina ceramics are bonded is manufactured, a composite substrate is manufactured by bonding the support substrate and a Si substrate, and a CMOS semiconductor structure is formed on the Si substrate. Formed. This point will be described in detail below.
  • a blank substrate made of translucent alumina ceramic was produced by the following procedure.
  • a slurry in which the raw material powder, the dispersion medium, the gelling agent, the dispersant and the catalyst shown in Table 1 were mixed was prepared.
  • ⁇ -alumina powder having a specific surface area of 3.5 to 4.5 m 2 / g and an average primary particle size of 0.35 to 0.45 ⁇ m was used.
  • the slurry was cast in an aluminum alloy mold at room temperature and then left at room temperature for 1 hour. Subsequently, it was left to stand at 40 ° C. for 30 minutes, and after solidification proceeded, it was released from the mold. Furthermore, it was left to stand at room temperature and then at 90 ° C. for 2 hours to obtain a plate-like powder compact.
  • the thickness of each blank substrate was 200 ⁇ m and 450 ⁇ m.
  • a blank substrate having a thickness of 200 ⁇ m is referred to as a first substrate, and a blank substrate having a thickness of 450 ⁇ m is referred to as a second substrate.
  • One surface of the first substrate was finished to Ra ⁇ 1 nm by CMP. Thereafter, the first and second substrates were cleaned to remove surface contamination.
  • substrate was directly joined by the plasma activation method, and it was set as the support substrate.
  • a surface of the first substrate opposite to the surface subjected to the CMP finish processing and one surface of the second substrate were used as a lapping surface made of diamond having a particle diameter of 3 ⁇ m.
  • the surfaces of the first and second substrates were exposed to an oxygen plasma atmosphere for 50 seconds.
  • the spontaneous bonding surface was propagated by pressing the vicinity of the edge portion of the substrate to obtain a support substrate having a total thickness of 650 ⁇ m.
  • the bond energy with the first and second substrates was about 0.1 J / m 2 .
  • the bulk strength of silicon is said to be 2 to 2.5 J / m 2 , and the binding energy with the first and second substrates was weaker than the bulk strength, and it was confirmed that peeling with a blade was possible.
  • the crack opening method is a method in which a blade is inserted into the bonding interface and the surface energy of the bonding interface is measured by the distance of the entering blade.
  • the blade used was a part number 99077 (blade span: about 37 mm, thickness: 0.1 mm, material: stainless steel) manufactured by Feather Safety Razor.
  • the surface of the support substrate subjected to CMP finish and the silicon substrate are bonded together by direct bonding by plasma activation, the silicon substrate is thinned to 1 ⁇ m by polishing, and then annealed at 200 ° C.
  • a composite substrate made of silicon and translucent alumina was obtained.
  • the warpage of the substrate at this time was 50 ⁇ m at a diameter of 150 mm. This was the amount of warp that could be introduced into the semiconductor process.
  • a CMOS semiconductor structure and a rewiring layer were formed on a silicon substrate of the composite substrate.
  • the first and second substrates constituting the support substrate are peeled off with a blade, the second substrate is removed, and the thickness of the support substrate is set to 200 ⁇ m, so that the desired thickness of the support substrate can be achieved without performing a back grinding process. It was confirmed that can be realized.
  • Example 1 a single blank substrate made of a translucent alumina ceramic was used as a support substrate, and this support substrate and a silicon substrate were joined to produce a composite substrate. Specifically, first, as in Example 1, a blank substrate made of translucent alumina ceramic having a diameter of 150 mm and a thickness of 400 ⁇ m was produced, and this was subjected to lapping and CMP to form a blank substrate having a thickness of 200 ⁇ m. This was used as a support substrate.
  • the support substrate and the silicon substrate are bonded together by direct bonding by plasma activation, the silicon substrate is processed to a thickness of 1 ⁇ m by polishing, and further annealed at 200 ° C., and the composite substrate of Comparative Example 1 is obtained. Obtained.
  • the warpage at this time was measured, it was 150 ⁇ m at a diameter of 150 mm, and it was confirmed that the warpage was larger than that in Example 1. In this case, there is a concern that it may cause a pattern shift in a semiconductor lithography process.
  • the composite substrate of the present invention can be used as an SOI substrate or an SOS substrate.

Abstract

　複合基板１０は、半導体基板１２と絶縁性の支持基板１４とを貼り合わせたものである。支持基板１４は、同じ材料で作られた第１基板１４ａと第２基板１４ｂとがブレードで剥離可能な強度で接合され、第１基板１４ａのうち第２基板１４ｂとの接合面とは反対側の面で半導体基板１２と貼り合わされている。

Description

複合基板、半導体デバイス及び半導体デバイスの製法
　本発明は、複合基板、半導体デバイス及び半導体デバイスの製法に関する。
　半導体集積回路の高速動作且つ低消費電力を実現する一つの手段として、ＳＯＩ技術に代表される複合基板を用いた集積回路技術が挙げられる（例えば特許文献１参照）。こうした複合基板は支持基板と機能層（半導体層）からなる。こうした複合基板の半導体層には単結晶基板を用いることで高品質な機能層とすることができる。一方、支持基板には単結晶のみならず、コスト削減の観点から多結晶基板を用いることも提案されている。こうした複合基板の例として、携帯電話用の高周波部品に用いられるＳＯＩ（Si-on-Insulator）ウエハやＳＯＳ（Si-on-Sapphire）ウエハがあげられる。これら高周波デバイスは、近年の小型化要求に伴い、特にデバイスの低背化が重要とされている。しかし、こうした複合基板を用いる場合、異種材料が接合された構造であるため、ウエハの厚みを薄くすると、反りが発生してしまい、デバイス作成に支障が発生することが知られている。そこで近年では、半導体層に全ての機能を作りこんだ後、支持基板を所望の厚さまで削り込むバックグラインド工程が採用されている。
特開平１０－１２５４７号公報
　しかしながら、例えばサファイアの様な硬い材料をグラインディングする場合、砥石の磨耗が激しく、コスト増の要因となる問題があった。
　本発明はこのような問題を解決するためになされたものであり、半導体デバイスを製造する際のバックグラインド工程を不要にすることを主目的とする。
　本発明は、上述の主目的を達成するために以下の手段を採った。
　本発明の複合基板は、
　半導体基板と絶縁性の支持基板とを貼り合わせた複合基板であって、
　前記支持基板は、同じ絶縁材料で作られた第１基板と第２基板とがブレードで剥離可能な強度で接合され、前記第１基板のうち前記第２基板との接合面とは反対側の面で前記半導体基板と貼り合わされたものである。
　本発明の半導体デバイスの製法は、
（ａ）上述した複合基板を準備する工程と、
（ｂ）前記複合基板のうち前記半導体基板にＣＭＯＳ半導体構造を形成する工程と、
（ｃ）ブレードで前記第１基板から前記第２基板を剥離して除去する工程と、
（ｄ）前記複合基板をダイシングして半導体デバイスを得る工程と、
　を含むものである。
　本発明の半導体デバイスは、上述した本発明の半導体デバイスの製法によって得られたものである。
　本発明の複合基板は、支持基板として、同じ絶縁材料で作られた第１基板と第２基板とがブレードで剥離可能な強度で接合されたものである。そのため、第１基板のみを支持基板として使用する場合に比べて、支持基板を厚くすることができる。その結果、温度変化に応じて発生する複合基板の反りを小さく抑えることができるし、複合基板の強度も高くすることができる。また、半導体基板にＣＭＯＳ半導体構造を形成したあとは、ブレードで第１基板から第２基板を剥離して除去すれば、支持基板の厚さを簡単に薄くすることができる。そのため、バックグラインド工程により厚い支持基板を薄くする場合に比べて、低コストで済む。その結果、半導体デバイスにしたときの製造コストが嵩むのを抑えることができる。除去した第２基板は、本発明の複合基板を作製する際に再利用することができるため、その点でもコストを抑えることができる。
　本発明の半導体デバイスの製法では、上述した本発明の複合基板を準備し、その複合基板のうち半導体基板にＣＭＯＳ半導体構造を形成し、ブレードで第１基板から第２基板を剥離して除去したあとダイシングして半導体デバイスを得る。ＣＭＯＳ半導体構造を形成したあとは、ブレードで第１基板から第２基板を剥離して除去すれば、支持基板の厚さを簡単に薄くすることができる。そのため、バックグラインド工程により厚い支持基板を薄くする場合に比べて、低コストで済む。その結果、半導体デバイスにしたときの製造コストが嵩むのを抑えることができる。
複合基板１０を模式的に示す断面図である。 複合基板１０の製造工程を模式的に示す断面図である。 半導体デバイス３０の製造工程を模式的に示す断面図である。
　次に、本発明の実施の形態を図面に基づいて説明する。図１は、本実施形態の複合基板１０を模式的に示す断面図である。この複合基板１０は、半導体基板１２と、支持基板１４とを備えている。
　半導体基板１２は、半導体構造を製造可能な基板である。この半導体基板１２の材質としては、例えば、シリコンが挙げられ、具体的にはｎ型シリコンやｐ型シリコンが挙げられる。また、ゲルマニウムのほか、ＧａＮやＧａＡｓといった化合物半導体も用いられる。半導体基板１２の大きさは、特に限定するものではないが、例えば、直径が５０～１５０ｍｍ、厚さが０．２～５０μｍである。
　支持基板１４は、絶縁性の基板であり、半導体基板１２の裏面に直接接合により接合されているか有機接着層を介して接合されている。この支持基板１４は、同じ絶縁材料で作られた第１基板１４ａと第２基板１４ｂとがブレードで剥離可能な強度で直接接合か有機接着層を介して接合されたものである。また、支持基板１４は、第１基板１４ａのうち第２基板１４ｂとの接合面とは反対側の面で、半導体基板１２と貼り合わされている。支持基板１４の材質としては、シリコン、サファイア、アルミナ、窒化ケイ素、窒化アルミニウム、炭化珪素などが挙げられる。高周波用途の場合、体積抵抗が高いことが必要とされるため、サファイア、アルミナ、窒化アルミニウムが好ましい。更に、低コスト化が要求される場合には、多結晶アルミナが好ましい。特に半導体基板への直接接合とウエハコストの低減とを両立させ、且つウエハ表面の汚染レベルを低く抑えたい（例えば１０×１０10ａｔｍｓ／ｃｍ2以下）場合には、透光性アルミナが好ましい。透光性アルミナは、高純度で且つ緻密にすることができるからである。また、支持基板１４の大きさは、例えば、直径が５０～３００ｍｍ、厚さが２００～１２００μｍである。第１及び第２基板１４ａ，１４ｂの大きさは、例えば、直径が５０～３００ｍｍ、厚さが１００～６００μｍである。
　次に、こうした複合基板１０を製造する方法について、図２を用いて以下に説明する。図２は、複合基板１０の製造工程を模式的に示す断面図である。
　まず、円盤状で同じ絶縁材料からなる第１及び第２基板１４ａ，１４ｂを用意し（図２（ａ）参照）、両基板１４ａ，１４ｂを直接接合により接合して支持基板１４を作製する（図２（ｂ）参照）。両基板１４ａ，１４ｂを直接接合する方法としては、以下の方法が例示される。すなわち、まず、両基板１４ａ，１４ｂの接合面を洗浄し、該接合面に付着している汚れを除去する。次に、両基板１４ａ，１４ｂの接合面にアルゴン等の不活性ガスのイオンビームを照射することで、残留した不純物（酸化膜や吸着物等）を除去すると共に接合面を活性化させる。その後、真空中、常温で両基板１４ａ，１４ｂを貼り合わせる。両基板１４ａ，１４ｂの接合強度は、厚さ１００μｍのブレードを挿入したときに剥離する強度とする。このような強度となるように、接合面の表面粗さ、イオンビームの照射時間、貼り合わせ時の圧力などを実験により決定する。例えば、両基板１４ａ，１４ｂが共にシリコン基板の場合、一般的にシリコンのバルク強度は２～２．５Ｊ／ｍ2と言われているため、両基板１４ａ，１４ｂのＳｉとＳｉの結合エネルギーをそれより小さい値、例えば０．０５～０．６Ｊ／ｍ2となるようにする。０．０５Ｊ／ｍ2を下回ると半導体デバイスの製造中に剥離するおそれがあり、０．６Ｊ／ｍ2を上回るとブレードをスムーズに挿入できないおそれがある。両基板１４ａ，１４ｂの接合面の表面粗さＲａが１ｎｍ程度の場合、鏡面同士を接合する際のイオンビームの照射時間を短くすることにより剥離可能な接合強度である０．０５～０．６Ｊ／ｍ2とすることができる。一方、両基板１４ａ，１４ｂの接合面の表面粗さＲａが１００ｎｍ程度の場合、鏡面同士を接合する際の接合条件と同一とした場合でも、剥離可能な接合強度とすることができる。こうしたイオンビーム照射による接合方法の他に、プラズマ活性化による接合を用いることもできる。例えば両基板の表面に残留する異物を、超音波水洗により除去した後、両基板表面に酸素プラズマ又は窒素プラズマを照射することで、表面を活性化状態とする。この状態にて両基板を貼り合わせることで自発接合面が伝播して接合面を得ることができる。接合エネルギーを容易に剥離できる程度に抑える場合には、接合後の熱処理を実施せず、プラズマによる活性化接合のみを実施した状態にするとよい。
　続いて、支持基板１４と半導体基板１２とを接合する（図２（ｃ）参照）。具体的には、支持基板１４のうち第１基板１４ａの表面と半導体基板１２の裏面とを接合する。接合方法は、直接接合でもよいし、有機接着層を介して接合してもよい。直接接合については、既に述べたので、ここではその説明を省略する。但し、接合強度がシリコンのバルク強度２～２．５Ｊ／ｍ2と同等かそれ以上となるように接合面の表面粗さ、イオンビームの照射時間、貼り合わせ時の圧力などを決定する。有機接着層を介して接合する場合には、まず、支持基板１４の表面及び半導体基板１２の裏面の一方又は両方に有機接着剤を均一に塗布し、両者を重ね合わせた状態で有機接着剤を固化させることにより接合する。以上のようにして、複合基板１０が得られる（図２（ｄ）参照）。直接接合方法はここで示した方法以外に、プラズマを用いたものや、中性原子ビームを用いるなどしてもよく、特に限定されるものではない。
　次に、こうした複合基板１０を用いて半導体デバイス３０を作製する方法について、図３を用いて以下に説明する。図３は、半導体デバイス３０の製造工程を模式的に示す断面図である。
　まず、複合基板１０を準備する（図３（ａ）参照）。これについては、図２を用いて既に説明したため、ここではその説明を省略する。
　次に、複合基板１０のうち半導体基板１２の表面にＣＭＯＳ半導体構造と再配線層を形成する（図３（ｂ）参照）。半導体基板１２の表面は、多数の半導体デバイス３０が形成されるように区画されており、各半導体デバイスに対応する位置にＣＭＯＳ半導体構造と再配線層をフォトリソグラフィ技術を利用して形成する。
　次に、厚さ１００μｍのブレードで第１基板１４ａから第２基板１４ｂを剥離して除去する（図３（ｃ）参照）。第２基板１４ｂを剥離したあとの第１基板１４ａの面（剥離面）は、表面粗さＲａが十分小さいため特に研磨する必要はないが、必要に応じて研磨してもよい。また、第１基板１４ａの剥離面には、第１基板１４ａの材質に由来する元素のほかに、直接接合の際に使用した真空チャンバーの材質に由来する元素が含まれる。例えば、真空チャンバーの材質がステンレス鋼の場合には、それに由来するＦｅ元素やＣｒ元素が含まれる。第１基板１４ａから剥離された第２基板１４ｂは、次回複合基板１０を作製するときに再利用することができる。
　最後に、区画に沿ってダイシングすることにより、多数の半導体デバイス３０を得る（図３（ｄ）参照）。
　以上説明した本実施形態によれば、支持基板１４として、同じ絶縁材料で作られた第１基板１４ａと第２基板１４ｂとが接合されたものを用いたため、第１基板１４ａのみを支持基板１４として使用する場合に比べて、支持基板１４を厚くすることができる。その結果、温度変化に応じて発生する複合基板１０の反りを小さく抑えることができるし、複合基板１０の強度も高くすることができる。また、半導体基板１２にＣＭＯＳ半導体構造と再配線層を形成したあとは、ブレードで第１基板１４ａから第２基板１４ｂを剥離して除去すれば、支持基板１４の厚さを簡単に薄くすること、つまり半導体デバイスの低背化することができる。そのため、支持基板１４と同じ厚さのバルクな支持基板をバックグラインド工程で薄くする場合に比べて、低コストで済む。その結果、半導体デバイス３０の製造コストが嵩むのを抑えることができる。除去した第２基板１４ｂは、次回複合基板１０を作製する際に再利用することができるため、その点でもコストを抑えることができる。
　なお、本発明は上述した実施形態に何ら限定されることはなく、本発明の技術的範囲に属する限り種々の態様で実施し得ることはいうまでもない。
　例えば、上述した実施形態では、第１及び第２基板１４ａ，１４ｂを直接接合により接合する場合を説明したが、第１及び第２基板１４ａ，１４ｂを有機接着層を介して接合してもよい。例えば、第１及び第２基板１４ａ，１４ｂの接合面の一方又は両方に有機接着剤を均一に塗布し、両者を重ね合わせた状態で有機接着剤（例えばウレタン系、エポキシ系等）を固化させることにより接合する。接合強度は上述した実施形態と同様になるようにする。このようにしても、本発明の効果が得られる。
［実施例１］
　本実施例では、透光性アルミナセラミックからなる第１及び第２基板を接合した支持基板を作製し、この支持基板とＳｉ基板とを接合して複合基板を作製し、Ｓｉ基板にＣＭＯＳ半導体構造を形成した。以下、この点を詳説する。
　まず、透光性アルミナセラミック製のブランク基板を以下の手順で作製した。表１に示す原料粉末、分散媒、ゲル化剤、分散剤及び触媒を混合したスラリーを調製した。α－アルミナ粉末は、比表面積３．５～４．５ｍ2／ｇ、平均一次粒子径０．３５～０．４５μｍのものを用いた。このスラリーを、アルミニウム合金製の型に室温で注型の後、室温で１時間放置した。次いで４０℃で３０分放置し、固化を進めてから、離型した。さらに、室温、次いで９０℃の各々にて２時間放置して、板状の粉末成形体を得た。得られた粉末成形体を、大気中１１００℃で仮焼（予備焼成）の後、水素：窒素＝３：１（体積比）の雰囲気中、１７５０℃で焼成を行い、その後、同条件でアニール処理を実施し、直径１５０ｍｍ、厚み１．０ｍｍのブランク基板とした。
Figure JPOXMLDOC01-appb-T000001
　続いて、２枚のブランク基板を高精度研磨加工を以下の手順で実施した。まず、グリーンカーボンによる両面ラップ加工により形状を整えた後、ダイヤモンドスラリーによる両面ラップ加工を実施した。ダイヤモンドの粒径は３μｍとした。それぞれのブランク基板の厚みは、２００μｍと４５０μｍとした。厚みが２００μｍのブランク基板を第１基板、厚みが４５０μｍのブランク基板を第２基板と称する。第１基板の片面に対して、ＣＭＰによりＲａ＜１ｎｍまで仕上げ加工を実施した。その後、表面の汚染を除去するべく、第１及び第２基板に対して洗浄を実施した。
　続いて、第１及び第２基板をプラズマ活性化法により直接接合して支持基板とした。まず、第１基板のうちＣＭＰ仕上げ加工を施した面とは反対側の面と第２基板のうち一方の面を、粒径３μｍのダイヤモンドによるラップ面とした。第１及び第２基板を洗浄して表面の汚れを取った後、第１及び第２基板のそれぞれの表面を酸素プラズマ雰囲気に５０秒間さらした。次いで、第１及び第２基板のそれぞれのビーム照射面を接触させるように重ね合わせた後、基板のエッジ部付近を押さえることで自発接合面を伝播させ、総厚み６５０μｍの支持基板を得た。
　クラックオープニング法を用いて単位面積当たりの結合エネルギーを測定したところ、第１及び第２基板との結合エネルギーは約０．１Ｊ／ｍ2であった。一般的にシリコンのバルク強度が２～２．５Ｊ／ｍ2と言われており、第１及び第２基板との結合エネルギーはバルク強度より弱く、ブレードによる剥離が可能であることを確認した。なお、クラックオープニング法とは、貼り合わせ界面にブレードを挿入し、進入したブレードの距離で接合界面の表面エネルギーを測る方法である。使用したブレードはフェザー安全剃刀社製の品番９９０７７（刃渡り：約３７ｍｍ、厚さ：０．１ｍｍ，材質：ステンレス鋼）とした。
　続いて、支持基板のうちＣＭＰ仕上げを施した表面とシリコン基板とを、プラズマ活性化による直接接合により貼り合せ、研磨加工によりシリコン基板を１μｍまで薄板加工し、その後２００℃にアニール処理を行うことでシリコンと透光性アルミナからなる複合基板を得た。この時点での基板の反りは１５０ｍｍ径にて５０μｍであった。これは半導体プロセスに投入しうる反り量であった。
　この複合基板のうちのシリコン基板にＣＭＯＳ半導体構造と再配線層を形成した。最後に支持基板を構成する第１及び第２基板をブレードにより剥離して第２基板を取り外し、支持基板の厚みを２００μｍとすることで、バックグラインド工程を行うことなく、所望の支持基板の厚みを実現できることを確認した。
[比較例１]
　本比較例では、透光性アルミナセラミックからなる１枚のブランク基板を支持基板とし、この支持基板とシリコン基板とを接合して複合基板を作製した。具体的には、まず、実施例１と同様にして、直径１５０ｍｍ、厚み４００μｍの透光性アルミナセラミック製のブランク基板を作製し、これにラップ加工及びＣＭＰ加工を施して厚み２００μｍのブランク基板とし、これを支持基板とした。続いて、この支持基板とシリコン基板とをプラズマ活性化による直接接合により貼り合わせ、研磨加工によりシリコン基板を１μｍまで薄板加工し、さらに２００℃にてアニール処理を行い、比較例１の複合基板を得た。この時点での反りを測定したところ、１５０ｍｍ径にて１５０μｍであり、実施例１と比べて大きな反りとなることを確認した。この場合、半導体のリソグラフィー工程にてパターンずれを起こす要因となることが懸念される。
　本出願は、２０１３年２月１９日に出願された日本国特許出願第２０１３－３０１６１号を優先権主張の基礎としており、引用によりその内容の全てが本明細書に含まれる。
　本発明の複合基板は、ＳＯＩ基板やＳＯＳ基板として利用可能である。
１０　複合基板、１２　半導体基板、１４　支持基板、３０　半導体デバイス。

Claims (7)

  1. 　半導体基板と絶縁性の支持基板とを貼り合わせた複合基板であって、
    　前記支持基板は、同じ絶縁材料で作られた第１基板と第２基板とがブレードで剥離可能な強度で接合され、前記第１基板のうち前記第２基板との接合面とは反対側の面で前記半導体基板と貼り合わされた、
    　複合基板。
  2. 　前記第１及び第２基板の材料は、シリコン、サファイア、アルミナ、窒化ケイ素、窒化アルミニウム及び炭化珪素からなる群より選ばれた１種である、
    　請求項１に記載の複合基板。
  3. 　前記第１及び第２基板の材料は、透光性アルミナである、
    　請求項１又は２に記載の複合基板。
  4. 　前記ブレードで剥離可能な強度とは、前記第１及び第２基板の単位面積あたりの結合エネルギーが０．０５～０．６Ｊ／ｍ2の範囲である、
    　請求項１～３のいずれか１項に記載の複合基板。
  5. （ａ）請求項１～４のいずれか１項に記載の複合基板を準備する工程と、
    （ｂ）前記複合基板のうち前記半導体基板にＣＭＯＳ半導体構造を形成する工程と、
    （ｃ）ブレードで前記第１基板から前記第２基板を剥離して除去する工程と、
    （ｄ）前記複合基板をダイシングして半導体デバイスを得る工程と、
    　を含む半導体デバイスの製法。
  6. 　前記工程（ａ）では、前記第１基板と前記第２基板とをブレードで剥離可能な強度で接合して前記支持基板を作製し、その後前記支持基板と前記半導体基板とを接合する工程である、
    　請求項５に記載の半導体デバイスの製法。
  7. 　請求項５又は６に記載の半導体デバイスの製法によって得られる、半導体デバイス。
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JP7095785B2 (ja) 2016-03-22 2022-07-05 住友電気工業株式会社 セラミック基板、積層体およびｓａｗデバイス

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US20150328875A1 (en) 2015-11-19
CN105074868A (zh) 2015-11-18
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EP2960925A1 (en) 2015-12-30
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JPWO2014129433A1 (ja) 2017-02-02
EP2960925B1 (en) 2018-04-25
JPWO2014129432A1 (ja) 2017-02-02
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US9911639B2 (en) 2018-03-06
US10629470B2 (en) 2020-04-21
KR20150118143A (ko) 2015-10-21
TW201501378A (zh) 2015-01-01
KR102094026B1 (ko) 2020-03-27
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KR102222089B1 (ko) 2021-03-04
US20150380290A1 (en) 2015-12-31

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