TWI609435B - Composite substrate, semiconductor device and method for manufacturing semiconductor device - Google Patents

Composite substrate, semiconductor device and method for manufacturing semiconductor device Download PDF

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Publication number
TWI609435B
TWI609435B TW103105235A TW103105235A TWI609435B TW I609435 B TWI609435 B TW I609435B TW 103105235 A TW103105235 A TW 103105235A TW 103105235 A TW103105235 A TW 103105235A TW I609435 B TWI609435 B TW I609435B
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Taiwan
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substrate
semiconductor device
substrates
semiconductor
composite
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TW103105235A
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English (en)
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TW201501213A (zh
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Ngk Insulators Ltd
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • B32B27/06—Layered products comprising a layer of synthetic resin as the main or only constituent of a layer, which is next to another layer of the same or of a different material
    • B32B27/08—Layered products comprising a layer of synthetic resin as the main or only constituent of a layer, which is next to another layer of the same or of a different material of synthetic resin
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    • B32B27/18—Layered products comprising a layer of synthetic resin characterised by the use of special additives
    • B32B27/20—Layered products comprising a layer of synthetic resin characterised by the use of special additives using fillers, pigments, thixotroping agents
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    • B32B27/28—Layered products comprising a layer of synthetic resin comprising synthetic resins not wholly covered by any one of the sub-groups B32B27/30 - B32B27/42
    • B32B27/283—Layered products comprising a layer of synthetic resin comprising synthetic resins not wholly covered by any one of the sub-groups B32B27/30 - B32B27/42 comprising polysiloxanes
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    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
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    • H03H9/1007—Mounting in enclosures for bulk acoustic wave [BAW] devices
    • H03H9/1014—Mounting in enclosures for bulk acoustic wave [BAW] devices the enclosure being defined by a frame built on a substrate and a cap, the frame having no mechanical contact with the BAW device
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10N30/01—Manufacture or treatment
    • H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
    • H10N30/072—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
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    • H03H2003/022—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks the resonators or networks being of the cantilever type
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    • H03H2003/023—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks the resonators or networks being of the membrane type
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    • H03H2003/027—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks the resonators or networks being of the microelectro-mechanical [MEMS] type
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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  • Engineering & Computer Science (AREA)
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  • Acoustics & Sound (AREA)
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  • Ceramic Engineering (AREA)
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  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
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  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
  • Recrystallisation Techniques (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Description

複合基板、半導體裝置及半導體裝置的製法
本發明係有關一種複合基板、半導體裝置及半導體裝置的製法。
作為實現半導體積體電路之高速動作且低消耗電力之一種手段，可以舉例以SOI技術為代表之使用複合基板之積體電路技術(例如參照專利文獻1)。這樣的複合基板係由支撐基板與機能層(半導體層)構成。在這樣的複合基板之半導體層中，藉由使用單結晶基板可以成為高品質的機能層。一方面，也提出了在支撐基板中並不只是單結晶，而是從成本減低的觀點使用多結晶基板。作為這樣的複合基板之例示，可以舉例被用於行動電話的高頻零件之SOI(Si-on-Insulator；絕緣體上矽)晶圓或SOS(Si-on-Sapphire；矽-藍寶石基底矽晶)晶圓。此等高頻裝置係伴隨著近年的小型化要求，尤其是使裝置的低背化為重要的。但是，在使用這樣的複合基板之情況下，由於是接合不同材料的構造，因此當將晶圓的厚度變薄時，得知會發生彎翹，而對於裝置作成產生障礙。因此，近年來，採用了在半導體層編造所有的機能後，再將支撐基材刨削成期望的厚度之背磨技術。
先前技術文獻 【專利文獻】
【專利文獻1】日本特開平10-12547號公報
然而，在研磨例如藍寶石之類的硬材料之情況下，磨石的耗損嚴重而有造成成本增加的要因之問題。
本發明係為用以解決這樣的問題而開發出來者，以製造半導體裝置時的不需要磨步驟為主要目的。
本發明係為了達成上述的主要目的而採取以下手段。
本發明之複合基板，其係為貼合半導體基板及絕緣性支撐基板之複合基板，前述支撐基材係以可利用刀片剝離的強度接合利用相同絕緣材料作成的第1基板與第2基板，利用前述第1基板之中與前述第2基板的接合面相反側之面，與半導體基板貼合者。
本發明之半導體裝置的製法，其係為包含以下步驟者：(a)準備上述複合基板之步驟；(b)在前述複合基板之中於前述半導體基板形成CMOS半導體構造之步驟；(c)利用刀片從前述第1基板剝離除去前述第2基板之步驟；及 (d)切割前述複合基板而得到半導體裝置之步驟。
本發明之半導體裝置係利用上述之本發明之半導體裝置的製法所得到者。
本發明之複合基板係為將以可利用刀片剝離的強度接合利用相同絕緣材料作成的第1基板與第2基板作為支撐基板者。為此，與只使用第1基板作為支撐基板的情況相比，可以使支撐基板變厚。其結果為可以將因應溫度變化所發生之複合基板的彎翹抑制為小，也可以提高複合基板的強度。又，若是在半導體基板形成CMOS半導體構造之後，利用刀片從第1基板剝離除去第2基板，就可以簡單地將支撐基板的厚度變薄。為此，與利用背磨步驟將厚的支撐基板變薄的情況相比，能夠以低成本完成。其結果為可以抑制形成半導體裝置時之製造成本增多。由於除去的第2基板係在製作本發明之複合基板時可以再利用，因此在此點也可以抑制成本。
在本發明之半導體裝置的製法中，準備上述之本發明的複合基板，在該複合基板之中於半導體基板形成CMOS半導體構造，並在利用刀片從第1基板剝離除去第2基板之後再切割而得到半導體裝置。若是在形成CMOS半導體構造之後，利用刀片從第1基板剝離除去第2基板，就可以簡單地將支撐基板的厚度變薄。為此，與利用背磨步驟將厚的支撐基板變薄的情況相比，能夠以低成本完成。其結果為可以抑制形成半導體裝置時之製造成本增多。
10‧‧‧複合基板
12‧‧‧半導體基板
14‧‧‧支撐基板
30‧‧‧半導體裝置
圖1為模式顯示複合基板10之剖面圖。
圖2為模式顯示複合基板10的製造步驟之剖面圖。
圖3為模式顯示半導體裝置30的製造步驟之剖面圖。
其次，依據圖面說明本發明之實施形態。圖1為模式顯示本實施形態之複合基板10的剖面圖。該複合基板10係具備：半導體基板12及支撐基板14。
半導體基板12為可製造半導體構造之基板。就該半導體基板12的材質而言，可以舉例如矽，具體而言可以舉例n型矽或p型矽。又，除了鍺之外，也可以使用所謂GaN或GaAs化合物半導體。半導體基板12的尺寸雖然沒有特別限定，但是例如直徑為50~150mm，厚度為0.2~50μm。
支撐基板14為絕緣性基板，藉由直接接合接合在半導體基板12的背面或是透過有機接著層接合。該支撐基板14為以可利用刀片剝離的強度直接接合或是透過有機接著層接合利用相同絕緣材料作成的第1基板14a與第2基板14b者。又，支撐基板14係利用第1基板14a之中與第2基板14b的接合面相反側之面，與半導體基板12貼合。就支撐基板14的材質而言，可以舉例矽、藍寶石、氧化鋁、氮化矽、氮化鋁、碳化矽等。高頻用途的情況下，由於必須使體積阻抗為高，因此藍寶石、氧化鋁、氮化鋁為佳。再者，在要求低成本化的情況下，以多晶氧化鋁為佳。尤其是在兼具對半導體基板的直接 接合與晶圓成本的減低，而且想要將晶圓表面的污染等級抑制為低(例如10×1010atms/cm2以下)的情況下，以透光性氧化鋁為佳。原因是透光性氧化鋁可以達到高純度且細緻。又，支撐基板14的尺寸例如直徑為50~300mm，厚度為200~1200μm。第1及第2基板14a、14b的尺寸例如直徑為50~300mm，厚度為100~600μm。
其次，針對製造這樣的複合基板10的方法，使用圖2在以下進行說明。圖2為模式顯示複合基板10之製造步驟的剖面圖。
首先，準備圓盤狀且利用相同絕緣材料構成之第1及第2基板14a、14b(參照圖2(a))，藉由直接接合接合兩基板14a、14b而製作出支撐基板14(參照圖2(b))。就直接接合兩基板14a、14b的方法而言，例示以下的方法。換言之，首先，洗淨兩基板14a、14b的接合面，除去附著在該接合面之髒污。其次，藉由在兩基板14a、14b的接合面照射氬等鈍性氣體的離子束，除去殘留的不純物(氧化膜或吸附物等)，同時使接合面活性化。之後，在真空中、常溫下貼合兩基板14a、14b。兩基板14a、14b的接合強度係形成為在插入厚度100μm的刀片時可以剝離的強度。以形成為這樣強度的方式，根據實驗決定接合面的表面粗度、離子束的照射時間、貼合時的壓力等。例如在兩基板14a、14b都是矽基板的情況下，由於一般而言矽的總體強度為2~2.5J/m2，因此將兩基板14a、14b之Si與Si的結合能形成為比其更小的值，例如0.05~0.6J/m2。當比0.05J/m2更小時，恐怕在半導體裝置的製造中會剝離，當超過 0.6J/m2時，恐怕無法順利插入刀片。在兩基板14a、14b之接合面的表面粗度Ra為1nm程度的情況下，藉由將接合鏡面時之離子束的照射時間縮短而可以形成可剝離的接合強度之0.05~0.6J/m2。一方面，在兩基板14a、14b之接合面的表面粗度Ra為100nm程度的情況下，即使是與接合鏡面時的接合條件相同的情況，也可以形成可剝離的接合強度。除了根據這樣的離子束照射之接合方法之外，也可以使用根據電漿活性化之接合。例如利用超音波水洗除去殘留在兩基板表面的異物後，藉由在兩基板表面照射氧氣電漿或氮氣電漿，而形成表面活性化的狀態。藉由利用該狀態貼合兩基板，使自發性接合面傳播而可以得到接合面。在將結合能抑制在可容易剝離的程度的情況下，以形成不實施接合後的熱處理，只實施根據電漿的活性化接合之狀態為佳。
接著，接合支撐基板14及半導體基板12(參照圖2(c))。具體而言，接合支撐基板14之中第1基板14a的表面及半導體基板12的背面。接合方法係為直接接合亦可，透過有機接著層進行接合亦可。針對直接接合，因為之前已經闡述，在此省略該說明。但是，以接合強度成為與矽的總體強度2~2.5J/m2相等或是其以上的方式，決定接合面的表面粗度、離子束的照射時間、貼合時的壓力等。在透過有機接著層進行接合的情況下，首先在支撐基板14的表面及半導體基板12的背面之一方或兩方均勻塗布有機接著劑，在將兩者重疊的狀態下藉由使有機接著劑固化而接合。如以上所示，可以得到複合基板10(參照圖2(d))。直接接合的方法除了在此所示的方法以 外，使用電漿者、或是使用中性原子束等亦可，並沒有特別的限定。
其次，針對使用這樣的複合基板10製作半導體裝置30的方法，使用圖3在以下進行說明。圖3為模式顯示半導體裝置30的製造步驟之剖面圖。
首先，準備複合基板10(參照圖3(a))。針對此點，由於之前已經使用圖2進行說明，因此在此省略該說明。
其次，在複合基板10之中於半導體基板12的表面形成CMOS半導體構造及再配線層(參照圖3(b))。半導體基板12的表面被畫分為形成多數個半導體裝置30，並在與各半導體裝置30對應的位置利用光微影技術形成CMOS半導體構造及再配線層。
其次，利用厚度100μm的刀片從第1基板14a剝離除去第2基板14b(參照圖3(c))。剝離第2基板14b後之第1基板14a的面(剝離面)由於表面粗度Ra為非常小而不需要特別研磨，但是因應必要進行研磨亦可。又，在第1基板14a的剝離面中，除了來自第1基板14a材質的元素，也包含有來自直接接合時所使用之真空腔室材質的元素。例如在真空腔室的材質為不鏽鋼的情況下，包含有來自其之Fe元素或Cr元素。從第1基板14a剝離的第2基板14b係可以在下次製作複合基板10時再利用。
最後，藉由沿著畫分進行切割，可以得到多數個半導體裝置30(參照圖3(d))。
根據以上說明的本實施形態，由於使用接合利用相同絕緣材料作成的第1基板14a與第2基板14b者作為支撐基板14，因此與只使用第1基板14a作為支撐基板14的情況相比，可以使支撐基板14變厚。其結果為可以將因應溫度變化所發生之複合基板10的彎翹抑制為小，也可以提高複合基板10的強度。又，若是在半導體基板12形成CMOS半導體構造與再配線層之後，利用刀片從第1基板14a剝離除去第2基板14b，就可以簡單地將支撐基板14的厚度變薄，也就是可以達到半導體裝置的低背化。為此，與利用背磨步驟將與支撐基板14相同厚度的總體的支撐基板變薄的情況相比，能夠以低成本完成。其結果為可以抑制半導體裝置30之製造成本增多。由於除去的第2基板14b係可以在下次製作複合基板10時再利用，因此在此點也可以抑制成本。
又，本發明係不限於上述實施形態，只要是屬於本發明的技術性範圍當然可以利用各種態樣進行實施。
例如，在上述的實施形態中，雖然是以利用直接接合接合第1及第2基板14a、14b的情況進行說明，但是透過有機接著層接合第1及第2基板14a、14b亦可。例如，在第1及第2基板14a、14b的接合面之一方或兩方均勻塗布有機接著劑，並在重疊兩者的狀態下藉由使有機接著劑(例如胺基甲酸乙酯系、環氧系等)固化而接合。接合強度係形成為與上述實施形態相同。如此一來也可以得到本發明的效果。
【實施例】
[實施例1]
在本實施例中，製作接合由透光性氧化鋁陶瓷構成的第1及第2基板之支撐基板，再接合該支撐基板與Si基板而製作出複合基板，並在Si基板形成CMOS半導體構造。以下，詳細說明此點。
首先，利用以下的順序製作出透光性氧化鋁陶瓷製的基底基板。調製混合有表1所示之原料粉末、分散媒、膠化劑、分散劑及觸媒之漿料。α-氧化鋁粉末係使用比表面積3.5~4.5m2/g，平均一次粒子粒徑0.35~0.45μm者。將該漿料在室溫下注入到鋁合金製的模型之後，在室溫下置放1小時。其次在40℃置放30分鐘，進行固化之後脫模。再者，分別在室溫、接著90℃置放2小時，得到板狀的粉末成形體。將得到的粉末成形體在大氣中以1100℃進行煅燒(預備燒成)後，在氫：氮=3：1(體積比)的環境中，以1750℃進行燒成，之後，利用相同條件進行退火處理，構成直徑150mm，厚度1.0mm的基底基板。
接著，對於2塊基底基板利用以下的順序實施高精密度研磨加工。首先，藉由根據綠色低碳之兩面拋光加工調整形狀後，實施根據鑽石漿料之兩面拋光加工。鑽石的粒徑為3μm。各基底基板的厚度為200μm及450μm。將厚度200μm的基底基板稱為第1基板，厚度450μm的基底基板稱為第2基板。對於第1基板的單面，利用CMP實施精緻加工直到Ra<1nm。之後，以要除去表面的污染之方式對於第1及第2基板實施洗淨。
接著，利用電漿活性化法直接接合第1及第2基板而構成支撐基板。首先，將第1基板之中與實施CMP精緻加工的面相反側之面、及第2基板之中的一面，形成為根據粒徑3μm的鑽石之拋光面。在洗淨第1及第2基板洗掉表面的髒污後，將第1及第2基板的各表面曝露在氧氣電漿環境50秒鐘。其次，以第1及第2基板之各光束照射面接觸的方式重疊後，藉由按壓基板的邊緣部附近使自發性接合面傳播，得到總體厚度650μm的支撐基板。
使用裂縫開口法測量每單位面積的結合能時，第1及第2基板之結合能約為0.1J/m2。一般而言矽的總體強度為2~2.5J/m2，可以確認第1及第2基板的結合能比總體強度更弱，可以進行根據刀片的剝離。又，所謂裂縫開口法，其為在貼合界面插入刀片，並利用已進入之刀片的距離測量接合界面的表面能之方法。使用的刀片為羽毛安全剃刀公司製之品號99077(刀片長度：約37mm，厚度：0.1mm，材質：不鏽鋼)。
接著，藉由根據電漿活性化的直接接合，貼合支撐基板之中實施CMP精緻加工的表面與矽基板，並藉由研磨加工將矽基板薄板加工到厚度為1μm，之後藉由在200℃進行退火處理而得到矽與透光性氧化鋁構成之複合基板。此時之基板的彎翹度是150mm直徑50μm。此為可投入半導體製程的彎翹量。
在該複合基板之中的矽基板形成CMOS半導體構造及再配線層。最後，利用刀片剝離構成支撐基板的第1及第2基板並取走第2基板，藉由使支撐基板的厚度成為200μm，可以確認不必進行背磨步驟，就可以實現期望的支撐基板厚度。
[比較例1]
在本比較例中，將由透光性氧化鋁陶瓷構成之1塊基底基板作為支撐基板，並將該支撐基板與矽基板接合而製作出複合基板。具體而言，首先，與實施例1相同，製作直徑150mm、厚度400μm之透光性氧化鋁陶瓷製的基底基板，在其實施拋光加工及CMP加工而形成厚度200μm的基底基板，並將此作為支撐基板。接著，藉由根據電漿活性化的直接接合，貼合該支撐基板與矽基板，並藉由研磨加工將矽基板薄板加工到厚度為1μm，進一步利用200℃進行退火處理，得到比較例1的複合基板。在測量此時之彎翹度時，為150mm直徑150μm，與實施例1相比可以確認造成很大的彎翹。在該情況下，恐怕會造成引7起無法利用半導體的光微影步驟進行圖案的主要原因。
本發明係以於2013年2月19日申請之日本專利 第2013-30161號為優先權主張的基礎，根據引用將其全部內容都包含在本案說明書內。
[產業上的可利用性]
本發明之複合基板係可以用來作為SOI基板或SOS基板。
10‧‧‧複合基板
12‧‧‧半導體基板
14‧‧‧支撐基板
14a‧‧‧第1基板
14b‧‧‧第2基板

Claims (5)

  1. 一種半導體裝置的製法，其特徵在於包含：(a)準備複合基板之步驟，前述複合基板為貼合半導體基板及絕緣性支撐基板後之複合基板，前述支撐基板係以可利用刀片剝離的強度接合利用相同絕緣材料作成的第1基板與第2基板，利用前述第1基板之中與前述第2基板的接合面相反側之面，與前述半導體基板貼合；(b)在前述複合基板之中於前述半導體基板形成CMOS半導體構造之步驟；(c)利用刀片從前述第1基板剝離除去前述第2基板之步驟；及(d)切割前述複合基板而得到半導體裝置之步驟。
  2. 如申請專利範圍第1項之半導體裝置的製法，其中，前述第1及第2基板的材料為選自由矽、藍寶石、氧化鋁、氮化矽、氮化鋁、及碳化矽所組成的群組之1種。
  3. 如申請專利範圍第1或2項之半導體裝置的製法，其中，前述第1及第2基板的材料為透光性氧化鋁。
  4. 如申請專利範圍第1或2項之半導體裝置的製法，其中，前述所謂可利用刀片剝離的強度，係為前述第1及第2基板之每單位面積的結合能為0.05~0.6J/m2的範圍。
  5. 如申請專利範圍第3項之半導體裝置的製法，其中，前述所謂可利用刀片剝離的強度，係為前述第1及第2基板之每單位面積的結合能為0.05~0.6J/m2的範圍。
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