CN105074868B - 复合基板、半导体装置及半导体装置的制法 - Google Patents

复合基板、半导体装置及半导体装置的制法 Download PDF

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CN105074868B
CN105074868B CN201480009140.3A CN201480009140A CN105074868B CN 105074868 B CN105074868 B CN 105074868B CN 201480009140 A CN201480009140 A CN 201480009140A CN 105074868 B CN105074868 B CN 105074868B
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substrate
semiconductor device
semiconductor
supporting
composite
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CN105074868A (zh
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井出晃启
高垣达朗
宫泽杉夫
堀裕二
多井知义
服部良祐
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NGK Insulators Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B18/00—Layered products essentially comprising ceramics, e.g. refractory products
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B27/00—Layered products comprising a layer of synthetic resin
    • B32B27/06—Layered products comprising a layer of synthetic resin as the main or only constituent of a layer, which is next to another layer of the same or of a different material
    • B32B27/08—Layered products comprising a layer of synthetic resin as the main or only constituent of a layer, which is next to another layer of the same or of a different material of synthetic resin
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B27/00—Layered products comprising a layer of synthetic resin
    • B32B27/18—Layered products comprising a layer of synthetic resin characterised by the use of special additives
    • B32B27/20—Layered products comprising a layer of synthetic resin characterised by the use of special additives using fillers, pigments, thixotroping agents
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B27/00—Layered products comprising a layer of synthetic resin
    • B32B27/28—Layered products comprising a layer of synthetic resin comprising synthetic resins not wholly covered by any one of the sub-groups B32B27/30 - B32B27/42
    • B32B27/283—Layered products comprising a layer of synthetic resin comprising synthetic resins not wholly covered by any one of the sub-groups B32B27/30 - B32B27/42 comprising polysiloxanes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B38/00—Ancillary operations in connection with laminating processes
    • B32B38/10—Removing layers, or parts of layers, mechanically or chemically
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B7/00—Layered products characterised by the relation between layers; Layered products characterised by the relative orientation of features between layers, or by the relative values of a measurable parameter between layers, i.e. products comprising layers having different physical, chemical or physicochemical properties; Layered products characterised by the interconnection of layers
    • B32B7/02—Physical, chemical or physicochemical properties
    • B32B7/025—Electric or magnetic properties
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B7/00—Layered products characterised by the relation between layers; Layered products characterised by the relative orientation of features between layers, or by the relative values of a measurable parameter between layers, i.e. products comprising layers having different physical, chemical or physicochemical properties; Layered products characterised by the interconnection of layers
    • B32B7/04—Interconnection of layers
    • B32B7/06—Interconnection of layers permitting easy separation
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B7/00—Layered products characterised by the relation between layers; Layered products characterised by the relative orientation of features between layers, or by the relative values of a measurable parameter between layers, i.e. products comprising layers having different physical, chemical or physicochemical properties; Layered products characterised by the interconnection of layers
    • B32B7/04—Interconnection of layers
    • B32B7/12—Interconnection of layers using interposed adhesives or interposed materials with bonding properties
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B9/00—Layered products comprising a layer of a particular substance not covered by groups B32B11/00 - B32B29/00
    • B32B9/005—Layered products comprising a layer of a particular substance not covered by groups B32B11/00 - B32B29/00 comprising one layer of ceramic material, e.g. porcelain, ceramic tile
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B9/00—Layered products comprising a layer of a particular substance not covered by groups B32B11/00 - B32B29/00
    • B32B9/04—Layered products comprising a layer of a particular substance not covered by groups B32B11/00 - B32B29/00 comprising such particular substance as the main or only constituent of a layer, which is next to another layer of the same or of a different material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/08—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
    • H03H3/10—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves for obtaining desired frequency or temperature coefficient
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/10—Mounting in enclosures
    • H03H9/1007—Mounting in enclosures for bulk acoustic wave [BAW] devices
    • H03H9/1014—Mounting in enclosures for bulk acoustic wave [BAW] devices the enclosure being defined by a frame built on a substrate and a cap, the frame having no mechanical contact with the BAW device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/10—Mounting in enclosures
    • H03H9/1007—Mounting in enclosures for bulk acoustic wave [BAW] devices
    • H03H9/1035—Mounting in enclosures for bulk acoustic wave [BAW] devices the enclosure being defined by two sealing substrates sandwiching the piezoelectric layer of the BAW device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/10—Mounting in enclosures
    • H03H9/1007—Mounting in enclosures for bulk acoustic wave [BAW] devices
    • H03H9/105—Mounting in enclosures for bulk acoustic wave [BAW] devices the enclosure being defined by a cover cap mounted on an element forming part of the BAW device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/25—Constructional features of resonators using surface acoustic waves
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
    • H10N30/072—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2264/00—Composition or properties of particles which form a particulate layer or are present as additives
    • B32B2264/10—Inorganic particles
    • B32B2264/105—Metal
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2307/00—Properties of the layers or laminate
    • B32B2307/20—Properties of the layers or laminate having particular electrical or magnetic properties, e.g. piezoelectric
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2307/00—Properties of the layers or laminate
    • B32B2307/20—Properties of the layers or laminate having particular electrical or magnetic properties, e.g. piezoelectric
    • B32B2307/206—Insulating
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2307/00—Properties of the layers or laminate
    • B32B2307/50—Properties of the layers or laminate having particular mechanical properties
    • B32B2307/538—Roughness
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2309/00—Parameters for the laminating or treatment process; Apparatus details
    • B32B2309/02—Temperature
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2309/00—Parameters for the laminating or treatment process; Apparatus details
    • B32B2309/08—Dimensions, e.g. volume
    • B32B2309/10—Dimensions, e.g. volume linear, e.g. length, distance, width
    • B32B2309/105—Thickness
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2457/00—Electrical equipment
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2457/00—Electrical equipment
    • B32B2457/14—Semiconductor wafers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B37/00—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding
    • B32B37/10—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the pressing technique, e.g. using action of vacuum or fluid pressure
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H03H2003/022—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks the resonators or networks being of the cantilever type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H03H2003/023—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks the resonators or networks being of the membrane type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H03H2003/027—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks the resonators or networks being of the microelectro-mechanical [MEMS] type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/08—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/02535—Details of surface acoustic wave devices
    • H03H9/02543—Characteristics of substrate, e.g. cutting angles
    • H03H9/02574—Characteristics of substrate, e.g. cutting angles of combined substrates, multilayered substrates, piezoelectrical layers on not-piezoelectrical substrate
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    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/80—Constructional details
    • H10N30/85—Piezoelectric or electrostrictive active materials
    • H10N30/853—Ceramic compositions
    • H10N30/8542—Alkali metal based oxides, e.g. lithium, sodium or potassium niobates
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/42—Piezoelectric device making
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49005—Acoustic transducer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
    • Y10T428/12535—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.] with additional, spatially distinct nonmetal component
    • Y10T428/12597—Noncrystalline silica or noncrystalline plural-oxide component [e.g., glass, etc.]

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Abstract

复合基板(10)由半导体基板(12)和绝缘性的支撑基板(14)粘合而成。支撑基板(14)为由相同绝缘材料制作的第1基板(14a)和第2基板(14b)以用刀片可剥离的强度接合而成，半导体基板(12)粘合在第1基板(14a)中与第2基板(14b)的接合面相反一侧的表面上。

Description

复合基板、半导体装置及半导体装置的制法
技术领域
本发明涉及复合基板、半导体装置以及半导体装置的制法。
背景技术
作为用于实现半导体集成电路的高速工作和低耗电的方法之一，可以举出使用以SOI技术为代表的复合基板的集成电路技术(例如参考专利文献1)。这种复合基板由支撑基板和功能层(半导体层)构成。通过在这种复合基板的半导体层上使用单晶基板能够使其成为高品质功能层。另一方面，在支撑基板上不只限于单晶，从降低成本的角度出发，也有人提出使用多晶基板。作为这种复合基板的例子，可以举出手机用高频部件中使用的SOI(绝缘衬底上的硅；Si-on-Insulator)晶片或SOS(蓝宝石硅；Si-on-Sapphire)晶片。这些高频装置，随着最近对小型化的需求，装置的低高度化变得特别重要。但是，我们发现当使用这种复合基板时，由于存在不同材料接合的结构，若削薄晶片的厚度，会产生卷曲，以致妨碍装置的制作。因此近年来，在制成半导体层的全部功能后，采用背面研磨工序将支撑基板磨削至期望的厚度。
现有技术文献
专利文献
专利文献1：日本特开平10-12547号公报
发明内容
发明要解决的问题
然而，当研磨如蓝宝石类硬材料时，磨石的磨损过大，该问题成为成本增加的主要原因。
本发明旨在解决这样的问题，其主要目的在于在半导体装置的制造过程中去除背面研磨工序。
用于解决问题的方法
本发明为了实现上述主要目的采用了以下的方法。
本发明的复合基板为，
由半导体基板和绝缘性支撑基板粘合而成的复合基板，
上述支撑基板为由相同绝缘材料制作的第1基板和第2基板以用刀片可剥离的强度接合而成，上述半导体基板粘合在上述第1基板中的上述第1基板与上述第2基板的接合面的相反一侧的表面上。
本发明的半导体装置的制法包含：
(a)准备上述复合基板的工序；
(b)在所述复合基板中的所述半导体基板上形成CMOS半导体结构的工序；
(c)用刀片从上述第1基板上剥离除去上述第2基板的工序；
(d)将所述符合基板切成方块获得半导体装置的工序。
本发明的半导体装置通过上述本发明的半导体装置的制法获得。
发明的效果
本发明的复合基板为，以由相同绝缘材料制作的第1基板和第2基板以用刀片可剥离的强度接合而成的基板作为支撑基板。为此，与只使用第1基板作为支撑基板的情况相比，能够使支撑基板增厚。因此，能够减小随温度变化而产生的复合基板的卷曲，也能够提高复合基板的强度。另外，在半导体基板上形成CMOS半导体结构之后，用刀片从第1基板上剥离除去第2基板就能够简单地削薄支撑基板的厚度。为此，与利用背面研磨工序削薄厚的支撑基板的情况相比，成本较低。因此，能够抑制半导体装置制造成本的增加。由于除去的第2基板在制作本发明的复合基板时可以被再利用，从这个角度考虑也能够节约成本。
在本发明的半导体装置的制法中，准备上述本发明的复合基板，在该复合基板中的半导体基板上形成CMOS半导体结构，用刀片从第1基板上剥离除去第2基板后通过将所述复合基板切成方块获得半导体装置。在形成CMOS半导体结构后，若用刀片从第1基板上剥离除去第2基板，能够简单地削薄支撑基板的厚度。为此，与利用背面研磨工序削薄厚的支撑基板的情况相比，成本较低。因此，能够抑制半导体装置制造成本的增加。
附图说明
图1：复合基板10的截面示意图。
图2：复合基板10的制造工序的截面示意图。
图3：半导体装置30的制造工序的截面示意图。
符号说明
10 复合基板
12 半导体基板
14 支撑基板
30 半导体装置
具体实施方式
接下来，基于附图对本发明的实施方式进行说明。图1为本实施方式的复合基板10的截面示意图。该复合基板10具备半导体基板12、和支撑基板14。
半导体基板12为能够制造半导体结构的基板。作为该半导体基板12的材料，可以举出例如硅，具体来说可以举出n型硅或p型硅。另外，除锗之外，也可以使用GaN或GaAs等化合物半导体。半导体基板12的大小没有特别地限定，例如，直径可为50～150mm，厚度可为0.2～50μm。
支撑基板14为绝缘性基板，通过直接接合方式或通过引入有机粘合层与半导体基板12的背面接合。该支撑基板14为由相同绝缘材料制作的第1基板14a和第2基板14b以用刀片可剥离的强度直接接合或经由有机粘合层接合而成。另外，支撑基板14通过第1基板14a中与第2基板14b的接合面的相反一侧的表面与半导体基板12粘合。作为支撑基板14的材料可以举出硅、蓝宝石、氧化铝、氮化硅、氮化铝、碳化硅等。在高频用途中，由于需要的体积电阻高，优选蓝宝石、氧化铝、氮化铝。进一步，在要求低成本的情况中，优选多晶氧化铝。尤其当需要同时实现半导体基板直接接合和减低成本两个目的，并且希望将晶片表面的污染抑制在低水平(例如10×1010atms/cm2以下)时，优选透光性的氧化铝。这是由于透光性氧化铝纯度高并且致密。另外，支撑基板14的大小例如，直径可为50～300mm，厚度可为200～1200μm。第1以及第2基板14a、14b的大小例如，直径可为50～300mm，厚度可为100～600μm。
接下来，关于制造这种复合基板10的方法，使用图2进行说明。图2为复合基板10的制造工艺的截面示意图。
首先，准备由相同绝缘材料制成的圆盘状的第1和第2基板14a、14b(参考图2(a))，利用直接接合方式接合两个基板14a、14b制作支撑基板14(参考图2(b))。作为直接接合两个基板14a、14b的方法，列举如下。即，首先，清洗两个基板14a、14b的接合面，除去该接合面上附着的污垢。接下来，利用氩气等惰性气体的离子束照射两个基板14a、14b的接合面，在除去残留的杂质(氧化膜、附着物等)的同时使接合面活化。然后，在常温下在真空中粘合两个基板14a、14b。两个基板14a、14b的接合强度为在插入厚度为100μm的刀片时可剥离的强度。为了达到这种强度，通过试验来确定接合面的粗糙度、离子束的照射时间、粘合时的压力等。例如，当两个基板14a、14b均为硅基板时，由于一般硅材料本身的强度为2～2.5J/m2，使两个基板14a、14b的硅与硅的结合能比上述更小，例如为0.05～0.6J/m2。若低于0.05J/m2，在半导体设备的制造过程中有剥离之虞，若高于0.6J/m2恐怕无法顺利地插入刀片。当两个基板14a、14b的接合面的表面粗糙度Ra为1nm左右时，在接合两个镜面时通过缩短离子束的照射时间，能够剥离的接合强度可以是0.05～0.6J/m2。另一方面，当两个基板14a、14b的接合面的表面粗糙度Ra为100nm左右时，即使使用与接合两个镜面时相同的接合条件，也可以达到能够剥离的接合强度。除这种利用离子束照射的接合方法外，也可以使用等离子体活化的接合方法。例如，通过超声波水洗除去两个基板表面上残留的异物后，用氧等离子体或氮等离子体照射两个基板的表面，使表面达到活化状态。在这种状态中通过粘合两个基板能够得到由自发接合面延展而成的接合面。在将结合能抑制在能够易于剥离的程度的情况中，结合后不进行热处理，使两个基板仅处于利用等离子体活化接合完成后的状态即可。
然后，接合支撑基板14和半导体基板12(参考图2(c))。具体来说，在支撑基板14中将第1基板14a的表面与半导体基板12的背面接合。接合的方法可以是直接接合，也可以是引入有机粘合层接合。由于已经对直接接合进行了描述，此处省略对其的说明。但是，以接合强度为等于或大于硅材料本身的强度2～2.5J/m2的条件来确定接合面的表面粗糙度、离子束的照射时间、粘合时的压力等。在引入有机粘合层进行接合的情况中，首先，在支撑基板14的表面及半导体12的背面中的任一面或两面上均匀地涂布有机粘合剂，使上述两面重合通过有机粘合剂的固化进行接合。完成上述操作，即得到复合基板10(参考图2(d))。直接接合的方法除本文中展示的方法之外，也可以使用等离子体、中性原子束等，没有特别地限定。
接下来，利用图3对使用这种复合基板10制作半导体装置30的方法进行说明。图3为半导体装置30的制造工艺的截面示意图。
首先，准备复合基板10(参考图3(a))。对此，因为已经利用图2进行了说明，此处省略对其的说明。
接下来，在复合基板10中的半导体基板12的表面上形成CMOS半导体结构和再布线层(参考图3(b))。为了在半导体基板12的表面形成多个半导体装置30，将其划分开，在各半导体装置对应的位置上利用光刻技术形成CMOS半导体结构和再布线层。
接下来，利用厚度为100μm的刀片从第1基板14a上剥离除去第2基板14b(参考图3(c))。剥离掉第2基板14b后的第1基板14a的面(剥离面)，由于表面粗糙度Ra很小，不需要特别进行研磨，但是也可以根据需要进行研磨。另外，在第1基板14a的剥离面上，除源自第1基板14a的材料之外的元素，还包含源自直接接合时使用的真空室的材料的元素。例如，当真空室的材料为不锈钢时，包含源自其的Fe元素或Cr元素。从第1基板14a上剥离下来的第2基板14b，在下次制造复合基板10时可以被再利用。
最后，根据划分进行切割，得到多个半导体装置30(参考图3(d))。
根据上述说明的本发明的实施方式，由于支撑基板14由相同绝缘材料制作的第1基板14a和第2基板14b接合而成，与仅使用第1基板14a作为支撑基板14的情况相比，可以增加支撑基板14的厚度。因此，能够降低随着温度变化产生的复合基板10的卷曲，也能够提高复合基板10的强度。另外，在半导体基板12上形成CMOS半导体结构和再布线层后，若用刀片从第1基板14a上剥离除去第2基板14b，能够简单地削薄支撑基板14的厚度，也就是说能够降低半导体装置的高度。为此，与利用背面研磨工序削薄与支撑基板14厚度相同的整块支撑基板的情况相比，成本较低。因此，能够抑制半导体装置30的制造成本的增加。除去的第2基板14b，由于在下次复合基板10的制造时可以被再利用，从这点来看也可以降低成本。
此外，本发明并不限于上述实施方式，不言而喻，在本发明的技术范围内能够得到多种实施方式。
例如，在上述实施方式中，说明了通过直接接合方式接合第1以及第2基板14a、14b，也可以引入有机粘合层接合第1以及第2基板14a、14b。例如，在第1以及第2基板14a、14b的一个或两个接合面上均匀地涂布有机粘合剂(例如聚氨酯类、环氧类)，在上述两基板重合的状态下通过有机粘合剂的固化进行接合。使用与上述实施方式相同的接合强度。如此操作，也可以实现本发明的效果。
实施例
[实施例1]
在本实施例中，制作由透光性氧化铝陶瓷形成的第1以及第2基板14a、14b接合而成的支撑基板，制作由该支撑基板和Si基板接合而成的复合基板，在Si基板上形成CMOS半导体结构。以下，对这一点进行详细说明。
首先，按照以下顺序制造透光性氧化铝陶瓷制空白基板。如表1所示混合原料粉末、分散介质、凝胶化剂、分散剂以及催化剂制备浆料。使用的α-氧化铝粉末的比表面积为3.5～4.5m2/g、平均一次粒径为0.35～0.45μm。在室温下，将该浆料注入到铝合金制的模型中后，在室温下放置1个小时。接下来在40℃下放置30分钟，加速固化，然后从模型中取出。进一步，分别在室温下、90℃下放置2小时，得到板状的粉末成形体。将得到的粉末成形体置于空气中在1100℃下假烧制(预备烧制)后，在氢：氮＝3:1(体积比)的环境中，在1750℃下进行烧制，然后在相同条件下进行退火处理，得到直径为150mm、厚度为1.0mm的空白基板。
[表1]
※MDI是二苯甲烷二异氰酸酯的简称。
接下来，按照以下的顺序对两块空白基板进行高精度研磨加工。首先，利用绿色低碳材料通过两面研磨加工调整基板的形状，然后利用金刚石浆料进行两面研磨加工。金刚石的粒径为3μm。空白基板的厚度分别为200μm和450μm。厚度为200μm的空白基板被称为第1基板，厚度为450μm的空白基板被称为第2基板。对于第1基板的单面，利用CMP进行加工至Ra<1nm。然后，除去表面的污染物，对第1以及第2基板进行清洗。
接下来，通过等离子体活化法直接接合第1以及第2基板以制造支撑基板。利用粒径为3μm的金刚石，以与第1基板中已进行完CMP加工的面相反一侧的表面以及第2基板中的一面为研磨面。洗净第1以及第2基板除去表面污垢后，将第1以及第2基板的表面分别置于氧等离子体环境中50秒。然后，将第1以及第2基板重合使其各自的离子束照射面相接触后，通过挤压基板端面部的周围使自发接合面延展，得到总厚度为650μm的支撑基板。
使用裂缝开口法测定单位面积上的结合能，第1以及第2基板的结合能约为0.1J/m2。一般来说，硅材料本身的强度为2～2.5J/m2，第1以及第2基板的结合能低于硅材料本身的强度，保证了可以利用刀片将其剥离。此外，所谓裂缝开口法是指将刀片插入到粘合界面，通过进入的刀片的距离测定结合界面的表面能的方法。使用的刀片为羽安全剃刀公司制造的商品号为99077(刀刃长度：约37mm、厚度：0.1mm，材质：不锈钢)。
接下来，利用等离子体活化通过直接接合使支撑基板中的进行完CMP的表面与硅基板粘合，通过研磨加工将硅基板加工成1μm厚的薄板，然后在200℃下进行退火处理，得到由硅和透光性氧化铝构成的复合基板。此时在直径150mm的区域上基板的卷曲为50μm。这是可以用于半导体工序中的卷曲量。
在该复合基板中的硅基板上形成CMOS半导体结构和再布线层。最后，利用刀片将构成支撑基板的第1以及第2基板上剥离，并除去第2基板，使支撑基板的厚度为200μm，未进行背面研磨工序，确定能够获得期望的支撑基板的厚度。
[对照例1]
在本对照例中，以由透光性氧化铝陶瓷形成的1块空白基板为支撑基板，通过接合该支撑基板和硅基板来制造复合基板。具体来说，首先按照与实施例1相同的方法，制作直径为150mm、厚度为400μm的透光性氧化铝陶瓷制的空白基板，对其进行研磨加工和CMP加工得到厚度为200μm的空白基板，以此为支撑基板。接下来，利用等离子体活化通过直接接合粘合该支撑基板和硅基板，通过研磨加工将硅基板加工成1μm厚的薄板，进一步在200℃下进行退火处理，得到对照例1的复合基板。测定此时的卷曲，在直径150mm的区域上卷曲为150μm，确定与实施例1相比卷曲变大。这种情况中，在半导体的光刻工序中可能成为导致图形偏差的主要原因。
本申请基于2013年2月19日申请的第2013-30161号日本专利申请主张优先权，通过引用将其全部内容包含在本说明书中。
工业上应用的可能性
本发明的复合基板可以用作SOI基板或SOS基板。

Claims (7)

1.一种半导体装置的制法，其包含：
(a)准备复合基板的工序，
所述复合基板由半导体基板和绝缘性的支撑基板粘合而成，所述支撑基板由第1基板和第2基板以用刀片可剥离的强度直接接合而成，第1基板和第2基板由相同的绝缘材料制作而成，所述半导体基板粘合在所述第1基板中的所述第1基板与所述第2基板的接合面的相反一侧的表面上，
所述支撑基板的厚度为200μm～650μm，
所述第1基板以及第2基板的材料为选自于由硅、蓝宝石、氧化铝、氮化硅、氮化铝以及碳化硅构成的组中的一种；
(b)在所述复合基板中的所述半导体基板上形成CMOS半导体结构的工序；
(c)在所述支撑基板的所述第1基板与所述第2基板之间插入刀片，将所述支撑基板的所述第1基板与所述第2基板剥离，从所述第1基板上除去所述第2基板的工序；
(d)除去所述第2基板后，将从所述第1基板上除去分离所述第2基板后的、所述复合基板切成方块获得半导体装置的工序。
2.一种半导体装置的制法，其包含：
(a)准备复合基板的工序，
所述复合基板由半导体基板和绝缘性的支撑基板粘合而成，所述支撑基板由第1基板和第2基板以用刀片可剥离的强度直接接合而成，第1基板和第2基板由相同的绝缘材料制作而成，所述半导体基板粘合在所述第1基板中的所述第1基板与所述第2基板的接合面的相反一侧的表面上，
所述用刀片可剥离的强度是指，所述第1基板以及第2基板的每单位面积的结合能的范围是0.05～0.6J/m2；
(b)在所述复合基板中的所述半导体基板上形成CMOS半导体结构的工序；
(c)在所述支撑基板的所述第1基板与所述第2基板之间插入刀片，将所述支撑基板的所述第1基板与所述第2基板剥离，从所述第1基板上除去所述第2基板的工序；
(d)除去所述第2基板后，将从所述第1基板上除去分离所述第2基板后的、所述复合基板切成方块获得半导体装置的工序。
3.如权利要求1或2所述的半导体装置的制法，所述工序(a)为，以用刀片可剥离的强度接合所述第1基板与所述第2基板来制作所述支撑基板，然后接合所述支撑基板与所述半导体基板的工序。
4.如权利要求2所述的半导体装置的制法，所述第1基板以及第2基板的材料为选自于由硅、蓝宝石、氧化铝、氮化硅、氮化铝以及碳化硅构成的组中的一种。
5.如权利要求1或4所述的半导体装置的制法，所述第1基板以及第2基板的材料为透光性氧化铝。
6.如权利要求1所述的半导体装置的制法，所述用刀片可剥离的强度是指，所述第1基板以及第2基板的每单位面积的结合能的范围是0.05～0.6J/m2。
7.一种半导体装置，其通过权利要求1～6中任一项所述的半导体装置的制法制得。
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