WO2014103934A1 - パワーモジュール - Google Patents
パワーモジュール Download PDFInfo
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- WO2014103934A1 WO2014103934A1 PCT/JP2013/084257 JP2013084257W WO2014103934A1 WO 2014103934 A1 WO2014103934 A1 WO 2014103934A1 JP 2013084257 W JP2013084257 W JP 2013084257W WO 2014103934 A1 WO2014103934 A1 WO 2014103934A1
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- Prior art keywords
- layer
- copper
- solder
- circuit layer
- power module
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
- B23K35/24—Selection of soldering or welding materials proper
- B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K7/00—Constructional details common to different types of electric apparatus
- H05K7/02—Arrangements of circuit components or wiring on supporting structure
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/02—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
- B23K35/0255—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape for use in welding
- B23K35/0261—Rods, electrodes, wires
- B23K35/0272—Rods, electrodes, wires with more than one layer of coating or sheathing material
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
- B23K35/24—Selection of soldering or welding materials proper
- B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
- B23K35/262—Sn as the principal constituent
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
- B23K35/24—Selection of soldering or welding materials proper
- B23K35/30—Selection of soldering or welding materials proper with the principal constituent melting at less than 1550 degrees C
- B23K35/302—Cu as the principal constituent
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B15/00—Layered products comprising a layer of metal
- B32B15/01—Layered products comprising a layer of metal all layers being exclusively metallic
- B32B15/017—Layered products comprising a layer of metal all layers being exclusively metallic one layer being formed of aluminium or an aluminium alloy, another layer being formed of an alloy based on a non ferrous metal other than aluminium
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- C—CHEMISTRY; METALLURGY
- C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
- C22C—ALLOYS
- C22C13/00—Alloys based on tin
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2101/00—Articles made by soldering, welding or cutting
- B23K2101/36—Electric or electronic devices
- B23K2101/40—Semiconductor devices
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2101/00—Articles made by soldering, welding or cutting
- B23K2101/36—Electric or electronic devices
- B23K2101/42—Printed circuits
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/29111—Tin [Sn] as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83399—Material
- H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/83455—Nickel [Ni] as principal constituent
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- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
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- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
- H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
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- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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Definitions
- the present invention relates to a power module in which a circuit layer provided with a copper layer made of copper or a copper alloy and a semiconductor element are joined using a solder material.
- the power module described above includes a power module substrate in which a metal plate serving as a circuit layer is bonded to one surface of an insulating substrate, and a power mounted on the circuit layer.
- Element semiconductor element
- a heat sink such as a heat sink or a cooler may be disposed on the other surface side of the power module substrate in order to dissipate heat from the power element (semiconductor element).
- a metal plate that becomes a metal layer on the other surface of the insulating substrate Are joined, and the metal layer is joined to a heat sink such as the above-described heat sink or cooler.
- the circuit layer and the power element are joined via a solder material.
- the circuit layer is made of aluminum or an aluminum alloy, for example, as disclosed in Patent Document 3, a Ni plating film is formed on the surface of the circuit layer by electrolytic plating or the like, and this Ni plating is performed. It was necessary to dispose a solder material on the film and join the semiconductor elements. Further, even when the circuit layer is made of copper or a copper alloy, a Ni plating film is formed on the surface of the circuit layer, and a solder material is disposed on the Ni plating film to join the semiconductor element. .
- Patent Document 3 when a power cycle load is applied to a power module in which Ni plating is formed on the surface of a circuit layer made of aluminum or an aluminum alloy and a semiconductor element is soldered, There was a risk that the thermal resistance would increase. In addition, even in a power module in which a Ni plating is formed on the surface of a circuit layer made of copper or a copper alloy and a semiconductor element is soldered, if a load of a power cycle is applied, cracks may occur in the solder and the thermal resistance may increase. was there.
- the present invention has been made in view of the above-described circumstances, and an object of the present invention is to provide a highly reliable power module that can suppress cracks in a solder layer even when a power cycle is applied. .
- a power module according to an aspect of the present invention includes a power module substrate in which a circuit layer is disposed on one surface of an insulating layer;
- a power module comprising: a semiconductor element bonded to one surface of the circuit layer, wherein a copper layer made of copper or a copper alloy is provided on a bonding surface of the circuit layer with the semiconductor element.
- a solder layer formed using a solder material is formed between the circuit layer and the semiconductor element, and a region of the solder layer from the surface of the circuit layer to a thickness of 30 ⁇ m.
- the average crystal grain size measured by EBSD measurement is in the range of 0.1 ⁇ m or more and 10 ⁇ m or less, and the solder layer contains Sn as a main component and Ni is 0.01 mass% or more. 0.0 mass% or less, Cu is contained in a composition of 0.1 mass% or more and 5.0 mass% or less, and in the power cycle test, the power cycle under the condition of energization time of 5 seconds and temperature difference of 80 ° C. was loaded 100,000 times. The rate of increase in thermal resistance is less than 10%.
- the average crystal grain size in the region from the surface of the circuit layer (copper layer) to the thickness of 30 ⁇ m in the solder layer is preferably in the range of 0.5 ⁇ m to 10 ⁇ m.
- the solder layer contains Sn as a main component, has a composition containing Ni in the range of 0.01 mass% to 1.0 mass%, and Cu in the range of 0.1 mass% to 5.0 mass%.
- precipitate particles made of an intermetallic compound containing any one of Cu, Ni, and Sn are dispersed inside the solder layer, and as described above, the crystal grain size of the solder layer can be refined. It becomes.
- the rate of increase in thermal resistance is less than 10% when the power cycle under the condition of energization time of 5 seconds and temperature difference of 80 ° C. is loaded 100,000 times. Even when the power cycle is repeatedly applied, the solder layer is not destroyed at an early stage, and the reliability with respect to the power cycle can be improved.
- the above-mentioned power cycle test is the condition that the load is most applied to the solder layer, if the thermal resistance increase rate when the power cycle is loaded 100,000 times under this condition is less than 10%, In normal use, sufficient reliability can be obtained.
- a power module according to another aspect of the present invention is the power module according to (1), wherein precipitate particles made of (Cu, Ni) 6 Sn 5 are dispersed in the solder layer.
- precipitate particles made of (Cu, Ni) 6 Sn 5 are dispersed in the solder layer.
- the solder layer can be prevented from being destroyed at an early stage, and a highly reliable power module can be provided.
- FIG. 2 is an enlarged explanatory view of a joint portion between a circuit layer and a semiconductor element in FIG. 1. It is a flowchart which shows the manufacturing method of the power module of FIG. It is explanatory drawing of the semiconductor element joining process in the manufacturing method of the power module shown in FIG. It is a schematic explanatory drawing of the power module which is the 2nd Embodiment of this invention.
- FIG. 6 is an enlarged explanatory view of a bonding interface between a copper layer and an aluminum layer in FIG. 5. It is a binary phase diagram of Cu and Al.
- FIG. 6 is an enlarged explanatory view of a joint portion between a circuit layer and a semiconductor element in FIG. 5. It is a flowchart which shows the manufacturing method of the power module of FIG. It is a photograph which shows the EBSD measurement result of the solder layer after the initial stage in the power module of the comparative example 1, and a power cycle load. It is a photograph which shows the EBSD measurement result of the solder layer after the initial stage and power cycle load in the power module of the example 1 of this invention.
- FIG. 1 shows a power module 1 according to a first embodiment of the present invention.
- the power module 1 is mounted on a power module substrate 10 having a circuit layer 12 formed on one surface (first surface) of an insulating substrate (insulating layer) 11 and on the circuit layer 12 (upper surface in FIG. 1).
- the semiconductor element 3 is provided.
- the heat sink 41 is bonded to the other surface side (the second surface side, the lower surface in FIG. 1) of the insulating substrate 11.
- the power module substrate 10 includes an insulating substrate 11 constituting an insulating layer, a circuit layer 12 disposed on one surface (the first surface, the upper surface in FIG. 1) of the insulating substrate 11, and an insulating substrate. 11 and a metal layer 13 disposed on the other surface (the second surface, the lower surface in FIG. 1).
- the insulating substrate 11 prevents electrical connection between the circuit layer 12 and the metal layer 13, and is, for example, AlN (aluminum nitride), Si 3 N 4 (silicon nitride), Al 2 O 3 (alumina). In this embodiment, it is made of highly insulating AlN (aluminum nitride). Further, the thickness of the insulating substrate 11 is set within a range of 0.2 mm or more and 1.5 mm or less, and is set to 0.635 mm in the present embodiment.
- the circuit layer 12 is formed by bonding a conductive metal plate to the first surface of the insulating substrate 11.
- the circuit layer 12 is formed by bonding a copper plate made of an oxygen-free copper rolled plate to the insulating substrate 11.
- the entire circuit layer 12 corresponds to a copper layer made of copper or a copper alloy provided on the bonding surface with the semiconductor element 3.
- the thickness of the circuit layer 12 is preferably set within a range of 0.1 mm to 1.0 mm.
- the metal layer 13 is formed by bonding a metal plate to the second surface of the insulating substrate 11.
- the metal layer 13 is formed by bonding an aluminum plate made of a rolled plate of aluminum (so-called 4N aluminum) having a purity of 99.99 mass% or more to the insulating substrate 11.
- the thickness of the metal layer 13 is set within a range of 0.6 mm or more and 3.0 mm or less.
- the heat sink 41 is for cooling the power module substrate 10 described above, and a top plate portion 42 joined to the power module substrate 10 and a flow path 43 for circulating a cooling medium (for example, cooling water). And.
- the heat sink 41 (top plate portion 42) is preferably made of a material having good thermal conductivity, and in this embodiment, is made of A6063 (aluminum alloy).
- the semiconductor element 3 is made of a semiconductor material such as Si, and a surface treatment film 3a made of Ni, Au, or the like is formed on the bonding surface with the circuit layer 12 as shown in FIG.
- the circuit layer 12 and the semiconductor element 3 are soldered, and the solder layer 20 is formed between the circuit layer 12 and the semiconductor element 3.
- the thickness t1 of the solder layer 20 is in the range of 50 ⁇ m to 200 ⁇ m.
- the solder layer 20 is formed of a Sn—Cu—Ni-based solder material 30. In this embodiment, Sn—0.1 to 4 mass%, Cu—0.01 to 1 mass%. Ni solder material 30 is used.
- an intermetallic compound layer 26 is formed on the surface of the circuit layer 12, and the solder layer 20 is laminated on the intermetallic compound layer 26.
- the intermetallic compound layer 26 is an intermetallic compound of Cu and Sn (Cu 3 Sn).
- the intermetallic compound layer 26 has a thickness t2 of 0.8 ⁇ m or less.
- the solder layer 20 contains Sn as a main component, and has a composition containing Ni in the range of 0.01 mass% to 1.0 mass% and Cu in the range of 0.1 mass% to 5.0 mass%.
- the average crystal grain size measured by EBSD (Electron Backscatter Diffraction) measurement is 10 ⁇ m or less, Preferably, it is in the range of 0.5 ⁇ m or more and 10 ⁇ m or less.
- grains which consist of an intermetallic compound containing Cu, Ni, and Sn are disperse
- the precipitate particles are an intermetallic compound composed of (Cu, Ni) 6 Sn 5 .
- the rate of increase in thermal resistance is less than 10% when a power cycle under conditions of energization time of 5 seconds and temperature difference of 80 ° C. is loaded 100,000 times.
- It is configured as follows. More specifically, an IGBT element as the semiconductor element 3 is soldered to the circuit layer 12 and a connection wiring made of an aluminum alloy is bonded. The power supply to the IGBT element is adjusted by repeating one cycle of an element surface temperature of 140 ° C. when energized (ON) and an element surface temperature of 60 ° C. when not energized (OFF) every 10 seconds. After repeating the above 100,000 times, the rate of increase in thermal resistance is less than 10%.
- the manufacturing method of the power module which is this embodiment is demonstrated using the flowchart of FIG.
- the copper plate used as the circuit layer 12 and the insulating substrate 11 are joined (circuit layer formation process S01).
- the bonding between the insulating substrate 11 and the copper plate to be the circuit layer 12 was performed by a so-called active metal brazing method.
- an active brazing material made of Ag-27.4 mass% Cu-2.0 mass% Ti was used.
- the furnace Laminating a copper plate serving as the circuit layer 12 through the active brazing material on the first surface of the insulating substrate 11, insulating substrate 11, to the stacking direction 1 kgf / cm 2 or more copper plates 35 kgf / cm 2 or less (9.8 ⁇ 10 4 Pa or more and 343 ⁇ 10 4 Pa or less) in a state where the pressure is applied, the furnace is inserted into the heating furnace and heated to join the copper plate to be the circuit layer 12 and the insulating substrate 11.
- the heating temperature is 850 ° C. and the heating time is 10 minutes.
- an aluminum plate to be the metal layer 13 is bonded to the second surface side of the insulating substrate 11 (metal layer forming step S02).
- the insulating substrate 11 and the aluminum plate are laminated via a brazing material, and the insulating substrate 11 and the aluminum plate are joined by brazing.
- the brazing material for example, an Al—Si brazing foil having a thickness of 20 to 110 ⁇ m can be used, and the brazing temperature is preferably 600 to 620 ° C. Thereby, the board
- the heat sink 41 is bonded to the other surface side of the metal layer 13 (heat sink bonding step S03).
- One surface of the metal layer 13 is bonded to the second surface of the insulating substrate 11.
- the metal layer 13 and the top plate portion 42 of the heat sink 41 are laminated via a brazing material, and the metal layer 13 and the heat sink 41 are joined by brazing.
- the brazing material for example, an Al—Si brazing foil having a thickness of 20 to 110 ⁇ m can be used, and the brazing temperature is preferably 590 ° C. to 610 ° C.
- the semiconductor element 3 is bonded onto the circuit layer 12 (semiconductor element bonding step S04).
- a thin Ni plating film 31 having a thickness of 0.2 ⁇ m or less is formed on the surface of the circuit layer 12.
- the semiconductor element 3 is laminated on the Ni plating film 31 via a solder material 30 of Sn-0.1 to 4 mass% Cu-0.01 to 1 mass% Ni.
- the semiconductor element 3 is inserted into a reduction furnace, and the circuit layer 12 and the semiconductor elements 3 are soldered together.
- the reducing furnace has a reducing atmosphere of 1 to 10 vol% of hydrogen, a heating temperature of 280 to 330 ° C., and a holding time of 0.5 to 2 minutes.
- the cooling rate to room temperature is set in the range of 2 to 3 ° C./s on average.
- Ni in the Ni plating film 31 formed on the surface of the circuit layer 12 diffuses toward the solder material 30 and the Ni plating film 31 disappears.
- Cu in the circuit layer 12 diffuses toward the solder material 30, whereby an intermetallic compound containing Cu, Ni, and Sn (in this embodiment, (Cu, Ni) 6 Sn 5 ) in the solder layer 20. ) Is dispersed.
- the solder layer 20 contains Sn as a main component, has a composition containing Ni in a range of 0.01 mass% to 1.0 mass% and Cu in a range of 0.1 mass% to 5.0 mass%.
- the solder layer 20 formed between the circuit layer 12 and the semiconductor element 3 has a thickness of 30 ⁇ m from the surface of the circuit layer 12. Since the average crystal grain size in region A is 10 ⁇ m or less, preferably 0.5 ⁇ m or more and 10 ⁇ m or less, even if cracks occur in the solder layer 20 from the circuit layer 12 side, It is difficult for cracks to propagate, and breakage of the solder layer 20 can be suppressed.
- the solder layer 20 contains Sn as a main component, and Ni is reduced to 0.0. Since the composition contains 01 mass% or more and 1.0 mass% or less and Cu is contained in the range of 0.1 mass% or more and 5.0 mass% or less, an intermetallic compound containing Cu, Ni, and Sn inside the solder layer 20 (this In the embodiment, the precipitate particles made of (Cu, Ni) 6 Sn 5 ) are dispersed, and the crystal grain size of the solder layer 20 can be reduced.
- the rate of increase in thermal resistance is less than 10% when a power cycle with an energization time of 5 seconds and a temperature difference of 80 ° C. is loaded 100,000 times. Since it is configured, the reliability of the solder layer 20 can be improved without breaking the solder layer 20 at an early stage even during a power cycle load.
- the thin Ni plating film 31 having a thickness of 0.2 ⁇ m or less is formed on the surface of the circuit layer 12, the Ni plating film 31 remains when the semiconductor element 3 is soldered. And the Cu of the circuit layer 12 is not suppressed from diffusing to the solder material 30 side, and the precipitate particles made of (Cu, Ni) 6 Sn 5 are reliably dispersed inside the solder layer 20.
- the crystal grain size can be made finer.
- FIG. 5 shows a power module 101 according to the second embodiment of the present invention.
- the power module 101 is mounted on a power module substrate 110 having a circuit layer 112 formed on one surface (first surface) of an insulating substrate (insulating layer) 11 and on the circuit layer 112 (upper surface in FIG. 5).
- the semiconductor element 3 is provided.
- the power module substrate 110 includes an insulating substrate 11 constituting an insulating layer, a circuit layer 112 disposed on one surface (the first surface, the upper surface in FIG. 5) of the insulating substrate 11, and an insulating substrate. 11 and the metal layer 13 disposed on the other surface (the second surface, the lower surface in FIG. 5).
- the circuit layer 112 includes an aluminum layer 112A formed on the first surface of the insulating substrate 11, and a copper layer 112B laminated on one surface side of the aluminum layer 112A. Yes.
- the other surface of the aluminum layer 112 ⁇ / b> A is bonded to the first surface of the insulating substrate 11.
- the aluminum layer 112A is formed by joining aluminum rolled plates having a purity of 99.99 mass% or more.
- the copper layer 112B is formed by solid phase diffusion bonding of a copper plate made of an oxygen-free copper rolled plate to one surface side of the aluminum layer 112A.
- One surface (the upper surface in FIG. 5) of the circuit layer 112 is a bonding surface to which the semiconductor element 3 is bonded.
- the thickness of the circuit layer 112 is preferably set in a range of 0.25 mm to 6.0 mm.
- the thickness of the aluminum layer 112A (aluminum plate) is preferably set in the range of 0.2 mm to 3 mm, and the thickness of the copper layer 112B is preferably set in the range of 50 ⁇ m to 3.0 mm. .
- a diffusion layer 115 is formed at the interface between the aluminum layer 112A and the copper layer 112B.
- the diffusion layer 115 is formed by interdiffusion of Al atoms in the aluminum layer 112A and Cu atoms in the copper layer 112B.
- the diffusion layer 115 has a concentration gradient in which the concentration of aluminum atoms gradually decreases and the concentration of copper atoms increases as it goes from the aluminum layer 112A to the copper layer 112B.
- the diffusion layer 115 is composed of an intermetallic compound composed of Al and Cu.
- the diffusion layer 115 has a structure in which a plurality of intermetallic compounds are stacked along the bonding interface.
- the thickness of the diffusion layer 115 is set in the range of 1 ⁇ m to 80 ⁇ m, preferably in the range of 5 ⁇ m to 80 ⁇ m.
- the ⁇ phase 116 and the ⁇ 2 phase 117 are sequentially formed along the bonding interface between the aluminum layer 112A and the copper layer 112B from the aluminum layer 112A side to the copper layer 112B side.
- the oxide 119 is inside the layer composed of at least one of the ⁇ 2 phase 118 a, the ⁇ phase 118 b , or the ⁇ 2 phase 118 c.
- the oxide 119 is an aluminum oxide such as alumina (Al 2 O 3 ).
- the circuit layer 112 (copper layer 112B) and the semiconductor element 3 are solder-bonded, and the circuit layer 112 (copper layer 112B) and the semiconductor element 3 are interposed.
- a solder layer 20 is formed.
- This solder layer 20 is formed of a Sn—Cu—Ni based solder material as in the first embodiment. In this embodiment, Sn—0.1 to 4 mass% Cu—0.01 to 1 mass is used. % Ni solder material is used.
- an intermetallic compound layer 26 is formed on the surface of the circuit layer 112 (copper layer 112 ⁇ / b> B), and the solder layer 20 is laminated on the intermetallic compound layer 26. ing.
- the intermetallic compound layer 26 is an intermetallic compound of Cu and Sn (Cu 3 Sn).
- the intermetallic compound layer 26 has a thickness t2 of 0.8 ⁇ m or less.
- the solder layer 20 contains Sn as a main component, and has a composition containing Ni in the range of 0.01 mass% to 1.0 mass% and Cu in the range of 0.1 mass% to 5.0 mass%.
- the average crystal grain size measured by EBSD measurement is 10 micrometers or less, Preferably, it is in the range of 0.5 ⁇ m or more and 10 ⁇ m or less.
- grains which consist of intermetallic compounds containing Cu, Ni, and Sn are disperse
- the precipitate particles are an intermetallic compound composed of (Cu, Ni) 6 Sn 5 .
- the rate of increase in thermal resistance is less than 10% when the power cycle under the condition of energization time of 5 seconds and temperature difference of 80 ° C. is loaded 100,000 times. It is configured as follows. More specifically, an IGBT element as the semiconductor element 3 is soldered to the circuit layer 112 (copper layer 112B), and a connection wiring made of an aluminum alloy is bonded. The power supply to the IGBT element is adjusted by repeating one cycle of an element surface temperature of 140 ° C. when energized (ON) and an element surface temperature of 60 ° C. when not energized (OFF) every 10 seconds. After repeating the above 100,000 times, the rate of increase in thermal resistance is less than 10%.
- an aluminum plate is joined to the first surface and the second surface of the insulating substrate 11 to form the aluminum layer 112A and the metal layer 13 (aluminum layer and metal layer forming step S101).
- the insulating substrate 11 and the aluminum plate are laminated via a brazing material, and the insulating substrate 11 and the aluminum plate are joined by brazing.
- the brazing material for example, an Al—Si brazing foil having a thickness of 20 to 110 ⁇ m can be used, and the brazing temperature is preferably 600 to 620 ° C.
- a copper plate is joined to one surface of the aluminum layer 112A to form a copper layer 112B (copper layer forming step S102).
- the other surface of the aluminum layer 112A is a surface joined to the first surface of the insulating substrate 11 in the aluminum layer and metal layer forming step S101.
- the aluminum layer 112A and the copper plate Solid phase diffusion bonding.
- heating temperature is 400 degreeC or more and 548 degrees C or less
- heating time is 15 minutes or more and 270 minutes or less.
- the heating temperature is set to a temperature range from 5 ° C. lower than the eutectic temperature of Al and Cu (548.8 ° C.) to less than the eutectic temperature. It is preferable to do.
- the circuit layer 112 composed of the aluminum layer 112A and the copper layer 112B is formed on the first surface of the insulating substrate 11.
- the semiconductor element 3 is bonded onto the circuit layer 112 (copper layer 112B) (semiconductor element bonding step S103).
- a thin Ni plating film having a thickness of 0.2 ⁇ m or less is formed on the surface of the circuit layer 112 (copper layer 112B).
- the semiconductor element 3 is laminated on the Ni plating film via a solder material of Sn-0.1 to 4 mass% Cu-0.01 to 1 mass% Ni.
- the semiconductor element 3 is inserted into a reduction furnace, and the circuit layer 112 (copper layer 112B) and the semiconductor element 3 are soldered together.
- the reducing furnace has a reducing atmosphere of 1 to 10 vol% of hydrogen, a heating temperature of 280 to 330 ° C., and a holding time of 0.5 to 2 minutes.
- the cooling rate to room temperature is set in the range of 2 to 3 ° C./s on average.
- the solder layer 20 contains Sn as a main component, has a composition containing Ni in a range of 0.01 mass% to 1.0 mass% and Cu in a range of 0.1 mass% to 5.0 mass%.
- the power module 101 it is possible to achieve the same operational effects as those of the first embodiment.
- the circuit layer 112 since the circuit layer 112 has the copper layer 112B, the heat generated from the semiconductor element 3 can be spread in the plane direction by the copper layer 112B, and the power module substrate 110 side can be efficiently processed. Can transfer heat to.
- the aluminum layer 112A having a relatively small deformation resistance is formed on the first surface of the insulating substrate 11, the thermal stress generated during the heat cycle load can be absorbed by the aluminum layer 112A. 11 cracks can be suppressed.
- the copper layer 112B made of copper or copper alloy having a relatively large deformation resistance is formed on one surface side of the circuit layer 112, the deformation of the circuit layer 112 can be suppressed during power cycle loading, High reliability with respect to the power cycle can be obtained.
- the other surface of the circuit layer 112 is a surface bonded to the first surface of the insulating substrate 11.
- the aluminum layer 112A and the copper layer 112B are solid phase diffusion bonded, and the temperature during the solid phase diffusion bonding is 400 ° C. or higher. Diffusion is promoted and solid phase diffusion can be sufficiently achieved in a short time.
- the temperature at the time of solid phase diffusion bonding is 548 ° C. or less, a liquid phase of Al and Cu does not occur, and bumps occur at the bonding interface between the aluminum layer 112A and the copper layer 112B. It can suppress that thickness changes.
- the heating temperature of the above-mentioned solid phase diffusion bonding is set in a range from 5 ° C.
- the compound of Al and Cu is It can be suppressed from being formed more than necessary, and the diffusion rate during solid phase diffusion bonding is ensured, so that solid phase diffusion bonding can be performed in a relatively short time.
- the metal layer has been described as being composed of 4N aluminum having a purity of 99.99 mass% or more.
- the present invention is not limited to this, and the metal layer may be composed of other aluminum or aluminum alloy. It may be made of copper or a copper alloy.
- an oxygen-free copper rolled plate is described as an example of the metal plate serving as the circuit layer.
- the present invention is not limited thereto, and may be composed of other copper or copper alloy. Good.
- the insulating substrate made of AlN is used as the insulating layer.
- the invention is not limited to this, and an insulating substrate made of Al 2 O 3 , Si 3 N 4 or the like may be used.
- the copper substrate used as an insulating substrate and a circuit layer was demonstrated as what joins by the active metal brazing method, it is not limited to this, You may join by the DBC method, the casting method, etc. .
- Transient liquid phase bonding method Transient Liquid Phase Bonding
- metal paste method casting Laws etc.
- composition of the solder material is not limited to the present embodiment, and the composition of the solder layer formed after the solder joining contains Sn as a main component and 0.01 mass% or more and 1.0 mass of Ni. % Or less, Cu may be contained as long as it contains 0.1 mass% or more and 5.0 mass% or less.
- the copper layer is solid-phase diffusion bonded to one surface of the aluminum layer to form the copper layer on the bonding surface of the circuit layer.
- the present invention is not limited to this.
- a copper layer may be formed on one surface of the aluminum layer by a plating method.
- a plating method In the case of forming a copper layer having a thickness of about 5 ⁇ m to 50 ⁇ m, it is preferable to apply a plating method.
- a copper layer having a thickness of about 50 ⁇ m to 3 mm it is preferable to apply solid phase diffusion bonding.
- the power module described in the first embodiment was prepared.
- the insulating substrate is made of AlN and has a size of 27 mm ⁇ 17 mm and a thickness of 0.6 mm.
- the circuit layer was made of oxygen-free copper, and used a layer of 25 mm ⁇ 15 mm and a thickness of 0.3 mm.
- the metal layer was made of 4N aluminum, and used a 25 mm ⁇ 15 mm, 0.6 mm thick layer.
- As the semiconductor element an IGBT element having a size of 13 mm ⁇ 10 mm and a thickness of 0.25 mm was used.
- As the heat sink an aluminum plate (A6063) of 40.0 mm ⁇ 40.0 mm ⁇ 2.5 mm was used.
- the composition of the solder layer after soldering were adjusted to produce various power modules to be Inventive Examples 1 to 8 and Comparative Examples 1 to 5.
- the soldering conditions were as follows: hydrogen 3 vol% reducing atmosphere, heating temperature (heating object temperature) and holding time were as shown in Table 1, and the average cooling rate to room temperature was 2.5 ° C./s.
- the average crystal grain size in the region from the surface of the circuit layer to the thickness of 30 ⁇ m in the solder layer formed between the circuit layer and the IGBT element is determined by EBSD measurement. It was measured.
- the EBSD measurement is performed using an EBSD measurement device (Quanta FEG 450 manufactured by FEI, OIM Data Collection manufactured by EDAX / TSL) and analysis software (OIM Data Analysis ver. 5.3 manufactured by EDAX / TSL) using an electron beam acceleration voltage. : 20 kV, measurement step: 0.6 ⁇ m, measurement range: 300 ⁇ m ⁇ 50 ⁇ m, analysis range: 300 ⁇ m ⁇ 30 ⁇ m.
- composition of solder layer The component analysis of the solder layer was performed by EPMA analysis. Using an EPMA analyzer (JXA-8530F manufactured by JEOL Ltd.), the average composition of the solder layer was analyzed at an acceleration voltage of 15 kV, a spot diameter of 1 ⁇ m or less, and a magnification of 250 times.
- the power supply to the IGBT element is adjusted by repeating one cycle of an element surface temperature of 140 ° C. when energized (ON) and an element surface temperature of 60 ° C. when not energized (OFF) every 10 seconds. Repeated 10,000 times. Then, the rate of increase in thermal resistance from the initial state was evaluated. In all of the inventive examples 1 to 8, the rate of increase in thermal resistance when the power cycle is repeated 100,000 times is less than 10%.
- thermal resistance measurement As the thermal resistance, a transient thermal resistance was measured using a thermal resistance tester (TESEC 4324-KT). Thermal resistance was determined by measuring the voltage difference between the gate and the emitter before and after the application of power, with applied power of 100 W and applied time of 100 ms. The measurement was carried out every 10,000 cycles during the power cycle test described above.
- Comparative Example 1 Comparative Example 3 and Comparative Example 5 in which the crystal grain size of the solder layer was as large as 10 ⁇ m or more, the power cycle life was as short as 70000 to 80000 times. As a result of observing the cross section of the solder layer of Comparative Example 1 after repeating the power cycle 100,000 times, as shown in FIG. 10, the destruction of the solder layer was recognized. Also in Comparative Examples 2 and 4 where the composition of the solder layer was outside the scope of the present invention, the power cycle life was as short as 80000 to 90000 times. This is presumed to be because inclusions were generated in the solder layer due to a large amount of Ni or Cu, and the solder layer was destroyed starting from the inclusions.
- the power cycle life is 110000 times or more, and it is confirmed that the destruction of the solder layer is suppressed.
- the cross section of the solder layer of Example 1 of the present invention after repeating the power cycle 100,000 times as shown in FIG. 11, it is confirmed that the progress of cracks along the crystal grain boundary is suppressed. .
- a power module in which a circuit layer is composed of an aluminum layer and a copper layer was prepared.
- the insulating substrate is made of AlN and has a size of 27 mm ⁇ 17 mm and a thickness of 0.6 mm.
- the metal layer was made of 4N aluminum, and used a 25 mm ⁇ 15 mm, 0.6 mm thick layer.
- As the semiconductor element an IGBT element having a size of 13 mm ⁇ 10 mm and a thickness of 0.25 mm was used.
- As the heat sink an aluminum plate (A6063) of 40.0 mm ⁇ 40.0 mm ⁇ 2.5 mm was used.
- the aluminum layer was made of 4N aluminum, and a layer of 25 mm ⁇ 15 mm and a thickness of 0.6 mm was used.
- the copper layer was formed by plating and solid phase diffusion bonding.
- the surface of the aluminum layer was subjected to zincate treatment, and then a copper layer having a thickness shown in Table 2 was formed by electrolytic plating.
- a copper plate having the thickness shown in Table 2 was prepared, and the copper plate was solid phase diffusion bonded to the surface of the aluminum layer under the conditions exemplified in the second embodiment.
- the power cycle life is 110000 times or more, and it is confirmed that the destruction of the solder layer is suppressed. It was confirmed that even when the circuit layer was formed by forming copper layers of various thicknesses on the aluminum layer, the power cycle characteristics could be improved as in Example 1. Moreover, if the thickness of the copper layer was 5 ⁇ m or more, it was confirmed that the Cu layer remained without any Cu in the copper layer being diffused to the solder side. Furthermore, it was confirmed that if the thickness of the copper layer is 3 mm or less, the power cycle life is 100,000 times or more.
- the solder layer can be prevented from being destroyed at an early stage, and a highly reliable power module can be provided.
- Power Module 3 Semiconductor Element 10 Power Module Substrate 11 Insulating Substrate (Insulating Layer) 12 Circuit layer (copper layer) 13 Metal layer 20 Solder layer 26 Intermetallic compound layer 30 Solder material 31 Ni plating film 101 Power module 112 Circuit layer 112A Aluminum layer 112B Copper layer
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Abstract
Description
本願は、2012年12月25日に日本に出願された特願2012-281345号について優先権を主張し、その内容をここに援用する。
また、パワーモジュール用基板の他方の面側には、パワー素子(半導体素子)からの熱を放散するために、放熱板や冷却器などのヒートシンクが配設されることがある。このとき、絶縁基板と放熱板や冷却器などのヒートシンクとの熱膨張係数に起因する熱応力を緩和するために、パワーモジュール用基板においては、絶縁基板の他方の面に金属層となる金属板が接合され、この金属層と上述の放熱板や冷却器などのヒートシンクが接合される構成とされている。
ここで、回路層がアルミニウムまたはアルミニウム合金で構成されている場合には、例えば特許文献3に開示されているように、回路層の表面に電解めっき等によってNiめっき膜を形成し、このNiめっき膜上にはんだ材を配設して半導体素子を接合する必要があった。
また、回路層が銅又は銅合金で構成されている場合においても、回路層の表面にNiめっき膜を形成し、このNiめっき膜上にはんだ材を配設して半導体素子を接合していた。
また、銅又は銅合金からなる回路層の表面にNiめっきを形成して半導体素子をはんだ接合したパワーモジュールにおいても、パワーサイクルの負荷をかけると、はんだにクラックが生じ、熱抵抗が上昇するおそれがあった。
また、はんだ層が、主成分としてSnを含有するとともに、Niを0.01mass%以上1.0mass%以下、Cuを0.1mass%以上5.0mass%以下、含有する組成とされていることから、はんだ層の内部に、Cu,Ni,Snのいずれかを含む金属間化合物からなる析出物粒子が分散することになり、上述のように、はんだ層の結晶粒径を微細化することが可能となる。
この場合、(Cu,Ni)6Sn5からなる析出物粒子が分散することにより、はんだ層の結晶粒径を確実に微細化することができ、パワーサイクル負荷時のはんだ層の破壊を確実に抑制することが可能となる。
図1に、本発明の第1の実施形態であるパワーモジュール1を示す。このパワーモジュール1は、絶縁基板(絶縁層)11の一方の面(第一の面)に回路層12が形成されたパワーモジュール用基板10と、回路層12上(図1において上面)に搭載された半導体素子3と、を備えている。なお、本実施形態のパワーモジュール1では、絶縁基板11の他方の面側(第二の面側であり、図1において下面)にヒートシンク41が接合されている。
このはんだ層20は、図4に示すように、Sn-Cu-Ni系のはんだ材30によって形成されており、本実施形態では、Sn-0.1~4mass%Cu-0.01~1mass%Niのはんだ材30が用いられている。
はんだ層20は、主成分としてSnを含有するとともに、Niを0.01mass%以上1.0mass%以下、Cuを0.1mass%以上5.0mass%以下、含有する組成とされている。
また、はんだ層20の内部には、Cu,Ni,Snを含む金属間化合物からなる析出物粒子が分散しており、特に、はんだ層20のうち回路層12の表面上から厚さ30μmまでの領域Aに多く分散している。ここで、本実施形態では、析出物粒子は、(Cu,Ni)6Sn5からなる金属間化合物とされている。
詳述すると、半導体素子3としてIGBT素子を回路層12へはんだ付けするとともに、アルミニウム合金からなる接続配線をボンディングする。そして、IGBT素子への通電を、通電(ON)で素子表面温度140℃、非通電(OFF)で素子表面温度60℃となる1サイクルを10秒毎に繰り返すようにして調整し、このパワーサイクルを10万回繰り返した後で、熱抵抗上昇率が10%未満とされている。
まず、回路層12となる銅板と絶縁基板11とを接合する(回路層形成工程S01)。ここで、絶縁基板11と回路層12となる銅板との接合は、いわゆる活性金属ろう付け法によって実施した。本実施形態では、Ag-27.4質量%Cu-2.0質量%Tiからなる活性ろう材を用いた。
これにより、パワーモジュール用基板10が製造される。
次に、このNiめっき膜31の上に、Sn-0.1~4mass%Cu-0.01~1mass%Niのはんだ材30を介して半導体素子3を積層する。
これにより、回路層12と半導体素子3との間に、はんだ層20が形成され、本実施形態であるパワーモジュール1が製出される。
また、回路層12のCuが、はんだ材30側へと拡散することにより、はんだ層20の内部に、Cu,Ni,Snを含む金属間化合物(本実施形態では(Cu,Ni)6Sn5)からなる析出物粒子が分散される。また、はんだ層20が、主成分としてSnを含有するとともに、Niを0.01mass%以上1.0mass%以下、Cuを0.1mass%以上5.0mass%以下、含有する組成となる。
次に、本発明の第2の実施形態であるパワーモジュールについて、添付した図面を参照して説明する。なお、第1の実施形態と同じ部材には同一の符号を付して詳細な説明を省略する。
図5に、本発明の第2の実施形態であるパワーモジュール101を示す。このパワーモジュール101は、絶縁基板(絶縁層)11の一方の面(第一の面)に回路層112が形成されたパワーモジュール用基板110と、回路層112上(図5において上面)に搭載された半導体素子3と、を備えている。
ここで、本実施形態では、アルミニウム層112Aは、純度99.99mass%以上のアルミニウムの圧延板を接合することで形成されている。また、銅層112Bは、無酸素銅の圧延板からなる銅板がアルミニウム層112Aの一方の面側に固相拡散接合されることにより形成されている。
拡散層115は、アルミニウム層112AのAl原子と、銅層112BのCu原子とが相互拡散することによって形成されるものである。この拡散層115においては、アルミニウム層112Aから銅層112Bに向かうにしたがい、漸次アルミニウム原子の濃度が低くなり、かつ銅原子の濃度が高くなる濃度勾配を有している。
本実施形態では、図6に示すように、アルミニウム層112A側から銅層112B側に向けて順に、アルミニウム層112Aと銅層112Bとの接合界面に沿って、θ相116、η2相117が積層し、さらにζ2相118a、δ相118b、及びγ2相118cのうち少なくとも一つの相が積層して構成されている(図7の状態図参照)。
また、本実施形態では、銅層112Bと拡散層115との界面に沿って、酸化物119がζ2相118a、δ相118b、又はγ2相118cのうち少なくとも一つの相からなる層の内部に層状に分散している。なお、この酸化物119は、アルミナ(Al2O3)等のアルミニウム酸化物とされている。
はんだ層20は、主成分としてSnを含有するとともに、Niを0.01mass%以上1.0mass%以下、Cuを0.1mass%以上5.0mass%以下、含有する組成とされている。
また、はんだ層20の内部には、Cu,Ni,Snを含む金属間化合物からなる析出物粒子が分散しており、特に、はんだ層20のうち回路層112(銅層112B)の表面上から厚さ30μmまでの領域Aに多く分散している。ここで、本実施形態では、析出物粒子は、(Cu,Ni)6Sn5からなる金属間化合物とされている。
詳述すると、半導体素子3としてIGBT素子を回路層112(銅層112B)へはんだ付けするとともに、アルミニウム合金からなる接続配線をボンディングする。そして、IGBT素子への通電を、通電(ON)で素子表面温度140℃、非通電(OFF)で素子表面温度60℃となる1サイクルを10秒毎に繰り返すようにして調整し、このパワーサイクルを10万回繰り返した後で、熱抵抗上昇率が10%未満とされている。
まず、絶縁基板11の第一の面及び第二の面にアルミニウム板を接合し、アルミニウム層112A及び金属層13を形成する(アルミニウム層及び金属層形成工程S101)。
絶縁基板11とアルミニウム板とを、ろう材を介して積層し、ろう付けによって絶縁基板11とアルミニウム板を接合する。このとき、ろう材としては、例えば、厚さ20~110μmのAl-Si系ろう材箔を用いることができ、ろう付け温度は600~620℃とすることが好ましい。
アルミニウム層112Aの上に銅板を積層し、これらを積層方向に加圧(圧力3~35kgf/cm2)した状態で真空加熱炉内に装入して加熱することにより、アルミニウム層112Aと銅板とを固相拡散接合する。ここで、銅層形成工程S102において、加熱温度は400℃以上548℃以下、加熱時間は15分以上270分以下とされている。なお、アルミニウム層112Aと銅板との固相拡散接合を行う場合には、加熱温度を、AlとCuの共晶温度(548.8℃)より5℃低い温度から共晶温度未満の温度範囲とすることが好ましい。
この銅層形成工程S102により、絶縁基板11の第一の面にアルミニウム層112Aと銅層112Bとからなる回路層112が形成される。
次に、このNiめっき膜の上に、Sn-0.1~4mass%Cu-0.01~1mass%Niのはんだ材を介して半導体素子3を積層する。
これにより、回路層112(銅層112B)と半導体素子3との間に、はんだ層20が形成され、本実施形態であるパワーモジュール101が製出される。
また、銅層112BのCuが、はんだ材側へと拡散することにより、はんだ層20の内部に、Cu,Ni,Snを含む金属間化合物(本実施形態では(Cu,Ni)6Sn5)からなる析出物粒子が分散される。また、はんだ層20が、主成分としてSnを含有するとともに、Niを0.01mass%以上1.0mass%以下、Cuを0.1mass%以上5.0mass%以下、含有する組成となる。
また、本実施形態では、回路層112が銅層112Bを有しているので、半導体素子3から発生する熱を銅層112Bで面方向に拡げることができ、パワーモジュール用基板110側へ効率的に熱を伝達することができる。
また、回路層112の一方の面側に比較的変形抵抗の大きい銅又は銅合金からなる銅層112Bが形成されているので、パワーサイクル負荷時に、回路層112の変形を抑制することができ、パワーサイクルに対する高い信頼性を得ることが可能となる。尚、回路層112の他方の面は、絶縁基板11の第一の面と接合されている面である。
さらに、上述の固相拡散接合の加熱温度を、AlとCuの共晶温度(548.8℃)より5℃低い温度から共晶温度未満の範囲とした場合には、AlとCuの化合物が必要以上に形成されることを抑制できるとともに、固相拡散接合の際の拡散速度が確保され、比較的短時間で固相拡散接合することができる。
例えば、本実施形態では、金属層を、純度99.99mass%以上の4Nアルミニウムで構成したものとして説明したが、これに限定されることはなく、他のアルミニウム又はアルミニウム合金で構成されていてもよいし、銅又は銅合金で構成されていてもよい。
さらに、絶縁層としてAlNからなる絶縁基板を用いたものとして説明したが、これに限定されることはなく、Al2O3、Si3N4等からなる絶縁基板を用いても良い。
さらに、絶縁基板と金属層となるアルミニウム板を、ろう付けによって接合するものとして説明したが、これに限定されることはなく、過渡液相接合法(Transient Liquid Phase Bonding)、金属ペースト法、鋳造法等を適用してもよい。
例えば、アルミニウム層の一方の面にめっき法により銅層を形成してもよい。なお、厚さ5μmから50μm程度の銅層を形成する場合にはめっき法を適用することが好ましい。厚さが50μmから3mm程度の銅層を形成する場合には固相拡散接合を適用することが好ましい。
前述の第1の実施形態に記載されたパワーモジュールを準備した。絶縁基板は、AlNで構成され、27mm×17mm、厚さ0.6mmのものを使用した。また、回路層は、無酸素銅で構成され、25mm×15mm、厚さ0.3mmのものを使用した。金属層は、4Nアルミニウムで構成され、25mm×15mm、厚さ0.6mmのものを使用した。半導体素子は、IGBT素子とし、13mm×10mm、厚さ0.25mmのものを使用した。ヒートシンクとしては、40.0mm×40.0mm×2.5mmのアルミニウム板(A6063)を使用した。
なお、はんだ接合条件は、水素3vol%還元雰囲気、加熱温度(加熱対象物温度)及び保持時間を表1の条件とし、室温までの平均冷却速度を2.5℃/sとした。
上述のようにして得られたパワーモジュールにおいて、回路層とIGBT素子との間に形成されたはんだ層のうち回路層の表面上から厚さ30μmまでの領域における平均結晶粒径を、EBSD測定によって測定した。
EBSD測定は、EBSD測定装置(FEI社製Quanta FEG 450,EDAX/TSL社製OIM Data Collection)と、解析ソフト(EDAX/TSL社製OIM Data Analysis ver.5.3)によって、電子線の加速電圧:20kV、測定ステップ:0.6μm、測定範囲:300μm×50μm、解析範囲:300μm×30μm、で実施した。
EPMA分析により、はんだ層の成分分析を行った。EPMA分析装置(日本電子株式会社製JXA-8530F)を用いて、加速電圧:15kV、スポット径:1μm以下、倍率:250倍で、はんだ層の平均組成を分析した。
IGBT素子への通電を、通電(ON)で素子表面温度140℃、非通電(OFF)で素子表面温度60℃となる1サイクルを10秒毎に繰り返すようにして調整し、このパワーサイクルを10万回繰り返した。そして、初期状態からの熱抵抗の上昇率を評価した。なお、本発明例1~8においては、すべて、パワーサイクルを10万回繰り返したときの熱抵抗上昇率が10%未満とされている。
IGBT素子への通電を、通電(ON)で素子表面温度140℃、非通電(OFF)で素子表面温度60℃となる1サイクルを10秒毎に繰り返すようにして調整し、このパワーサイクルを繰り返した。そして、初期状態からの熱抵抗の上昇率が10%以上となったサイクル回数(パワーサイクル寿命)を評価した。
熱抵抗として、過渡熱抵抗を熱抵抗テスター(TESEC社製4324-KT)を用いて測定した。印加電力:100W、印加時間:100msとし、電力印加前後のゲート-エミッタ間の電圧差を測定することにより、熱抵抗を求めた。測定は上述したパワーサイクル試験時において、1万サイクル毎に実施した。
また、はんだ層の組成が本発明の範囲から外れた比較例2、4においても、パワーサイクル寿命が80000~90000回と短かった。これは、Ni又はCuが多いため、はんだ層内に介在物が生成し、介在物を起点にはんだ層が破壊されたためと推測される。
絶縁基板は、AlNで構成され、27mm×17mm、厚さ0.6mmのものを使用した。金属層は、4Nアルミニウムで構成され、25mm×15mm、厚さ0.6mmのものを使用した。半導体素子は、IGBT素子とし、13mm×10mm、厚さ0.25mmのものを使用した。ヒートシンクとしては、40.0mm×40.0mm×2.5mmのアルミニウム板(A6063)を使用した。
めっきの場合、アルミニウム層の表面にジンケート処理を施した後、電解めっきにて表2に示す厚さの銅層を形成した。
固相拡散接合の場合、表2に示す厚さの銅板を準備し、第2の実施形態で例示した条件でアルミニウム層の表面に銅板を固相拡散接合した。
なお、はんだ接合条件は、水素3vol%還元雰囲気、加熱温度(加熱対象物温度)及び保持時間を表2の条件とし、室温までの平均冷却速度を2.5℃/sとした。
そして、実施例1と同様の方法により、はんだ層の組成、結晶粒径、パワーサイクル寿命を評価した。評価結果を表2に示す。
また、銅層の厚さが5μm以上であれば、銅層中のCuがすべてはんだ側に拡散してしまうことがなく、銅層が残存することが確認された。さらに、銅層の厚さが3mm以下であれば、パワーサイクル寿命が10万回以上となることが確認された。
3 半導体素子
10 パワーモジュール用基板
11 絶縁基板(絶縁層)
12 回路層(銅層)
13 金属層
20 はんだ層
26 金属間化合物層
30 はんだ材
31 Niめっき膜
101 パワーモジュール
112 回路層
112A アルミニウム層
112B 銅層
Claims (2)
- 絶縁層の一方の面に回路層が配設されたパワーモジュール用基板と、前記回路層の一方の面に接合された半導体素子と、を備えたパワーモジュールであって、
前記回路層のうち前記半導体素子との接合面には、銅又は銅合金からなる銅層が設けられており、
前記回路層と前記半導体素子との間には、はんだ材を用いて形成されたはんだ層が形成されており、
前記はんだ層のうち前記回路層の表面上から厚さ30μmまでの領域においては、EBSD測定によって測定される平均結晶粒径が0.1μm以上10μm以下の範囲内とされており、
前記はんだ層は、主成分としてSnを含有するとともに、Niを0.01mass%以上1.0mass%以下、Cuを0.1mass%以上5.0mass%以下、含有する組成とされており、
パワーサイクル試験において、通電時間5秒、温度差80℃の条件のパワーサイクルを10万回負荷したときの熱抵抗上昇率が10%未満であることを特徴とするパワーモジュール。 - 前記はんだ層には、(Cu,Ni)6Sn5からなる析出物粒子が分散されている請求項1に記載のパワーモジュール。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015230900A (ja) * | 2014-06-03 | 2015-12-21 | 三菱マテリアル株式会社 | パワーモジュール |
US10170442B2 (en) | 2016-12-08 | 2019-01-01 | Panasonic Intellectual Property Management Co., Ltd. | Mount structure including two members that are bonded to each other with a bonding material layer having a first interface layer and a second interface layer |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6048558B2 (ja) * | 2014-10-16 | 2016-12-21 | 三菱マテリアル株式会社 | 冷却器付パワーモジュール用基板及びその製造方法 |
DE112017002999B4 (de) * | 2016-06-16 | 2022-03-24 | Mitsubishi Electric Corporation | Halbleiter-montage-wärmeabführungs-basisplatte und herstellungsverfahren für dieselbe |
JP6379170B2 (ja) * | 2016-12-27 | 2018-08-22 | 有限会社 ナプラ | 半導体装置 |
JP2018153834A (ja) * | 2017-03-17 | 2018-10-04 | 株式会社ニーケプロダクツ | アルミニウム部材同士またはアルミニウム部材と銅部材とをトーチハンダ付けする方法 |
WO2018207856A1 (ja) * | 2017-05-10 | 2018-11-15 | ローム株式会社 | パワー半導体装置およびその製造方法 |
JP6369620B1 (ja) | 2017-12-31 | 2018-08-08 | 千住金属工業株式会社 | はんだ合金 |
TWI820277B (zh) * | 2018-12-27 | 2023-11-01 | 美商阿爾發金屬化工公司 | 無鉛焊料組成物 |
WO2020138283A1 (ja) * | 2018-12-28 | 2020-07-02 | デンカ株式会社 | セラミックス-銅複合体、セラミックス回路基板、パワーモジュール及びセラミックス-銅複合体の製造方法 |
JP2022032542A (ja) * | 2020-08-12 | 2022-02-25 | 富士電機株式会社 | 半導体装置 |
WO2022163695A1 (ja) * | 2021-01-28 | 2022-08-04 | 三菱電機株式会社 | 半導体装置、電力変換装置および半導体装置の製造方法 |
JP2023140056A (ja) * | 2022-03-22 | 2023-10-04 | ネクスファイ・テクノロジー株式会社 | パワー半導体スイッチングモジュール |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3152945B2 (ja) * | 1998-03-26 | 2001-04-03 | 株式会社日本スペリア社 | 無鉛はんだ合金 |
JP2002076551A (ja) | 2000-09-04 | 2002-03-15 | Dowa Mining Co Ltd | 金属セラミックス回路基板及びその製造方法 |
JP2004172378A (ja) | 2002-11-20 | 2004-06-17 | Mitsubishi Materials Corp | パワーモジュール用基板の製造方法並びにパワーモジュール用基板及びパワーモジュール |
JP2005116963A (ja) * | 2003-10-10 | 2005-04-28 | Denso Corp | 半導体装置 |
JP2006289434A (ja) * | 2005-04-11 | 2006-10-26 | Nihon Superior Co Ltd | はんだ合金 |
JP2008098212A (ja) * | 2006-10-06 | 2008-04-24 | Hitachi Ltd | 電子装置およびその製造方法 |
JP2008130697A (ja) * | 2006-11-17 | 2008-06-05 | Sharp Corp | はんだ接合構造、及びはんだ接合構造の製造方法 |
JP2008227336A (ja) | 2007-03-15 | 2008-09-25 | Hitachi Metals Ltd | 半導体モジュール、これに用いられる回路基板 |
JP2011143442A (ja) * | 2010-01-14 | 2011-07-28 | Hitachi Automotive Systems Ltd | 高信頼はんだ接続部をもつパワーモジュール |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07161925A (ja) * | 1993-12-09 | 1995-06-23 | Mitsubishi Electric Corp | パワーモジュール |
JP2002203942A (ja) | 2000-12-28 | 2002-07-19 | Fuji Electric Co Ltd | パワー半導体モジュール |
JP2003133474A (ja) | 2001-10-25 | 2003-05-09 | Kyocera Corp | 電子装置の実装構造 |
US7239016B2 (en) * | 2003-10-09 | 2007-07-03 | Denso Corporation | Semiconductor device having heat radiation plate and bonding member |
WO2005098942A1 (ja) | 2004-04-05 | 2005-10-20 | Mitsubishi Materials Corporation | Ai/ain接合体、パワーモジュール用基板及びパワーモジュール並びにai/ain接合体の製造方法 |
JP2006066716A (ja) | 2004-08-27 | 2006-03-09 | Fuji Electric Holdings Co Ltd | 半導体装置 |
JP4343117B2 (ja) | 2005-01-07 | 2009-10-14 | 株式会社ルネサステクノロジ | 半導体装置およびその製造方法 |
EP1926142A1 (en) | 2005-09-15 | 2008-05-28 | Mitsubishi Materials Corporation | Insulating circuit board and insulating circuit board provided with cooling sink section |
US8198540B2 (en) | 2006-06-06 | 2012-06-12 | Mitsubishi Materials Corporation | Power element mounting substrate, method of manufacturing the same, power element mounting unit, method of manufacturing the same, and power module |
JP4629016B2 (ja) | 2006-10-27 | 2011-02-09 | 三菱マテリアル株式会社 | ヒートシンク付パワーモジュール用基板およびヒートシンク付パワーモジュール用基板の製造方法並びにパワーモジュール |
JP4919863B2 (ja) * | 2007-03-30 | 2012-04-18 | アイシン精機株式会社 | 半田接合部の評価方法 |
JP5331322B2 (ja) * | 2007-09-20 | 2013-10-30 | 株式会社日立製作所 | 半導体装置 |
WO2009051181A1 (ja) | 2007-10-19 | 2009-04-23 | Nihon Superior Sha Co., Ltd. | 無鉛はんだ合金 |
JP2010087072A (ja) | 2008-09-30 | 2010-04-15 | Hitachi Automotive Systems Ltd | パワー半導体モジュールおよびこれを用いたインバータシステム |
JP5658436B2 (ja) * | 2009-04-16 | 2015-01-28 | 株式会社東芝 | 半導体装置 |
JP5428667B2 (ja) * | 2009-09-07 | 2014-02-26 | 日立化成株式会社 | 半導体チップ搭載用基板の製造方法 |
JP5463845B2 (ja) * | 2009-10-15 | 2014-04-09 | 三菱電機株式会社 | 電力半導体装置とその製造方法 |
-
2013
- 2013-12-20 JP JP2013264197A patent/JP5598592B2/ja active Active
- 2013-12-20 WO PCT/JP2013/084257 patent/WO2014103934A1/ja active Application Filing
- 2013-12-20 CN CN201380066872.1A patent/CN104885206B/zh active Active
- 2013-12-20 KR KR1020157015555A patent/KR102154882B1/ko active IP Right Grant
- 2013-12-20 US US14/654,199 patent/US9642275B2/en active Active
- 2013-12-20 TW TW102147513A patent/TWI581342B/zh active
- 2013-12-20 EP EP13868095.4A patent/EP2940719B1/en active Active
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3152945B2 (ja) * | 1998-03-26 | 2001-04-03 | 株式会社日本スペリア社 | 無鉛はんだ合金 |
JP2002076551A (ja) | 2000-09-04 | 2002-03-15 | Dowa Mining Co Ltd | 金属セラミックス回路基板及びその製造方法 |
JP2004172378A (ja) | 2002-11-20 | 2004-06-17 | Mitsubishi Materials Corp | パワーモジュール用基板の製造方法並びにパワーモジュール用基板及びパワーモジュール |
JP2005116963A (ja) * | 2003-10-10 | 2005-04-28 | Denso Corp | 半導体装置 |
JP2006289434A (ja) * | 2005-04-11 | 2006-10-26 | Nihon Superior Co Ltd | はんだ合金 |
JP2008098212A (ja) * | 2006-10-06 | 2008-04-24 | Hitachi Ltd | 電子装置およびその製造方法 |
JP2008130697A (ja) * | 2006-11-17 | 2008-06-05 | Sharp Corp | はんだ接合構造、及びはんだ接合構造の製造方法 |
JP2008227336A (ja) | 2007-03-15 | 2008-09-25 | Hitachi Metals Ltd | 半導体モジュール、これに用いられる回路基板 |
JP2011143442A (ja) * | 2010-01-14 | 2011-07-28 | Hitachi Automotive Systems Ltd | 高信頼はんだ接続部をもつパワーモジュール |
Non-Patent Citations (1)
Title |
---|
See also references of EP2940719A4 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015230900A (ja) * | 2014-06-03 | 2015-12-21 | 三菱マテリアル株式会社 | パワーモジュール |
US10170442B2 (en) | 2016-12-08 | 2019-01-01 | Panasonic Intellectual Property Management Co., Ltd. | Mount structure including two members that are bonded to each other with a bonding material layer having a first interface layer and a second interface layer |
Also Published As
Publication number | Publication date |
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CN104885206B (zh) | 2018-03-30 |
JP5598592B2 (ja) | 2014-10-01 |
EP2940719A1 (en) | 2015-11-04 |
JP2014143406A (ja) | 2014-08-07 |
EP2940719B1 (en) | 2019-01-30 |
EP2940719A4 (en) | 2016-08-24 |
KR102154882B1 (ko) | 2020-09-10 |
KR20150099739A (ko) | 2015-09-01 |
US9642275B2 (en) | 2017-05-02 |
TWI581342B (zh) | 2017-05-01 |
TW201444000A (zh) | 2014-11-16 |
CN104885206A (zh) | 2015-09-02 |
US20150319877A1 (en) | 2015-11-05 |
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