WO2014030670A1 - 半導体発光素子用基板及び半導体発光素子、並びにこれらの製造方法 - Google Patents
半導体発光素子用基板及び半導体発光素子、並びにこれらの製造方法 Download PDFInfo
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- WO2014030670A1 WO2014030670A1 PCT/JP2013/072296 JP2013072296W WO2014030670A1 WO 2014030670 A1 WO2014030670 A1 WO 2014030670A1 JP 2013072296 W JP2013072296 W JP 2013072296W WO 2014030670 A1 WO2014030670 A1 WO 2014030670A1
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Definitions
- the present invention relates to a substrate for a semiconductor light emitting device, a semiconductor light emitting device, and a method for producing them.
- the present invention relates to a semiconductor light emitting device substrate suitable for a III-V nitride semiconductor light emitting device, a semiconductor light emitting device using the substrate obtained by the above-described method, and a method for manufacturing the same.
- the semiconductor light emitting element is used as an ultraviolet, blue or green light emitting diode element or an ultraviolet, blue or green laser diode element.
- a group III-V nitride semiconductor light emitting device having a light emitting layer made of a group III-V nitride semiconductor using nitrogen as a group V element is widely used.
- a semiconductor light emitting device substrate that supports the light emitting structure is formed of sapphire, silicon carbide, silicon, or the like, and usually has a lower refractive index than a semiconductor layer that constitutes the light emitting structure. .
- a group III-V nitride semiconductor light-emitting device basically has an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer sequentially stacked on a substrate such as sapphire, and an n-type electrode is formed on the n-type semiconductor layer.
- a p-type electrode is formed on the p-type semiconductor layer. The light emitted from the light emitting layer is extracted from the p-type electrode side and / or the substrate side. Part of the light generated by the light emitting structure repeats total reflection between the semiconductor light emitting element substrate and the light emitting structure in accordance with the difference in refractive index between the semiconductor light emitting element substrate and the light emitting structure.
- Patent Documents 1 and 2 a mask pattern is formed on a substrate using a photolithography method, and the substrate is dry-etched using the mask pattern to form an uneven structure on the substrate. It has been proposed to form a semiconductor layer on the structure.
- Patent Document 3 proposes that the substrate is dry-etched using inorganic particles arranged on the substrate as an etching mask to form a concavo-convex structure on the substrate, and then a semiconductor layer is formed on the concavo-convex structure. ing.
- Patent Document 3 as a preferred method of disposing inorganic particles on a substrate, the substrate is immersed in the slurry using a slurry in which inorganic particles are dispersed in a medium such as water, or the slurry is added to the substrate. There has been proposed a method of drying after coating or spraying. In addition, in order to form a good semiconductor layer, the inorganic particles should be disposed on the substrate with a coverage of 90% or less. Further, Non-Patent Document 1 discusses the relationship between the pitch of the concavo-convex structure formed on the substrate and the effect of improving the light extraction efficiency.
- the fine uneven structure of the substrate for semiconductor light emitting element is composed of a large number of convex portions arranged on the light emitting structure forming surface.
- the fine uneven structure of the semiconductor light emitting device substrate is formed by dry etching of the light emitting structure forming surface, and a mask used for dry etching is formed by photolithography. Is formed.
- Non-Patent Document 1 it is desired that the pitch of the concavo-convex structure be 1 ⁇ m or less.
- a pitch of several ⁇ m is the limit. For this reason, it has been difficult to obtain sufficient light extraction efficiency with the methods of Patent Documents 1 and 2.
- the semiconductor light emitting element has a color shift or a problem that the radiation intensity varies depending on the viewing angle (high in-plane anisotropy).
- the resist tends to be thick at the concave portions of the substrate, resulting in variations in the time required for disappearance of the mask during etching, resulting in variations in the height and shape of the concavo-convex structure. Therefore, sufficient light extraction efficiency cannot be obtained.
- an etching mask by nanoimprint is applied to a substrate with low flatness, there is a problem that a non-pattern (planned) portion is contaminated by a resist residual film. For this reason, in manufacturing a substrate for a semiconductor light emitting element by conventional photolithography, a substrate having high flatness has to be used.
- a substrate with high flatness particularly a sapphire substrate with high flatness, cannot be obtained without an advanced polishing technique, and thus has a problem that it is very expensive.
- a fine structure having a concavo-convex pitch of 1 ⁇ m or less can be produced by electron beam lithography or interference exposure
- a substrate having a large area of about ⁇ 2 inch to ⁇ 6 inch such as a substrate for a semiconductor light emitting device
- the drawing speed is so slow that it takes about two weeks for one-inch drawing, and processing of a large area substrate is very costly and time consuming.
- a Gaussian beam is used as the light source.
- the appropriate exposure time is different between the central portion and the peripheral portion.
- it is vulnerable to vibrations (ground and building vibrations, air vibrations, etc.), and if any vibration is applied during the exposure time, the image is blurred and the resolution is lowered. Therefore, it is difficult to produce a homogeneous microstructure with a large area.
- the electron beam drawing apparatus and the interference exposure method require a large apparatus and are expensive, which is also a factor that hinders industrial implementation.
- One embodiment of the present invention has been made in view of the above circumstances, and provides a semiconductor light-emitting element in which sufficient light extraction efficiency is obtained and the problem of high color shift and in-plane anisotropy is prevented. This is the issue.
- Another object of the present invention is to provide a semiconductor light emitting device substrate suitable for manufacturing a semiconductor light emitting device that can form a semiconductor layer with few crystal defects and solves the above problems.
- Still another aspect of the present invention is a semiconductor light emitting device that can manufacture a substrate for a semiconductor light emitting device that can solve the above-mentioned problems, and can form a concavo-convex structure with a pitch of 1 ⁇ m or less at a low cost and in a short time by a simple method.
- Still another aspect of the present invention provides a method for manufacturing a semiconductor light-emitting element that can manufacture a semiconductor light-emitting element that solves the above-described problems by using a method for manufacturing a substrate for a semiconductor light-emitting element that solves the above-described problems. Is an issue.
- a particle arranging step in which a plurality of particles are arranged in a single layer so that the deviation D (%) of the arrangement defined by the following formula (1) is 15% or less on the substrate;
- a particle etching process in which the particles are etched and the substrate is not substantially etched, and the plurality of arranged particles are dry-etched to provide a gap between the particles; and
- a method of manufacturing a substrate for a semiconductor light emitting device comprising: a substrate etching step of dry etching the substrate using a plurality of particles after the particle etching step as an etching mask to form an uneven structure on one surface of the substrate .
- the particle arranging step comprises the dropping step of dropping a dispersion liquid in which particles are dispersed in a solvent having a specific gravity smaller than that of water on the surface of water in the water tank, and volatilizing the solvent to form the particles.
- [3] The method for manufacturing a substrate for a semiconductor light-emitting element according to [1] or [2], wherein a mode pitch between the particles is 5 ⁇ m or less.
- [4] The method for manufacturing a substrate for a semiconductor light-emitting element according to [1] or [2], wherein a mode pitch between the particles is 1 ⁇ m or less.
- [5] The method for manufacturing a substrate for a semiconductor light-emitting element according to [1] or [2], wherein the most frequent pitch between the particles is 200 nm to 700 nm.
- the substrate is sapphire, the particles are silica, and the particle etching step uses CF 4 , SF 6 , CHF 3 , C 2 F 6 , C 3 F 8 , CH 2 F 2 as an etching gas.
- the method for manufacturing a substrate for a semiconductor light emitting element according to any one of [1] to [5], wherein the method uses at least one gas selected from the group consisting of Ar and Ar.
- the substrate is sapphire, the particles are silica, and the particle etching step is performed using CF 4 , SF 6 , CHF 3 , C 2 F 6 , C 3 F 8 , CH 2 F 2 , O 2 , as an etching gas.
- the substrate etching step includes Cl 2 , Br 2 , BCl 3 , SiCl 4 , HBr, HI, HCl, and Ar as an etching gas.
- a method for producing a substrate for a semiconductor light-emitting element comprising using at least one gas selected from the group consisting of: [8]
- the particle arraying step includes the dropping step of dropping a dispersion liquid in which particles are dispersed in a solvent having a specific gravity smaller than that of water on the water level in the water tank, and volatilizing the solvent to form the particles.
- the method for producing a substrate for a semiconductor light-emitting element according to [7], comprising a single particle film forming step of forming a single particle film on a liquid surface of water, and a transition step of transferring the single particle film to the substrate.
- TTV The absolute difference between the maximum thickness and the minimum thickness specified by ASTM F657 of the substrate is 5 ⁇ m to 30 ⁇ m
- WARP ASTM F1390
- ) from the reference plane at the center of the substrate defined by ASTM F534.3.1.2 is 10 ⁇ m to 50 ⁇ m [1] to [8]
- a method for manufacturing a semiconductor light emitting device comprising: laminating a semiconductor functional layer including a light emitting layer.
- a substrate for a semiconductor light emitting device having a concavo-convex structure on one surface of the substrate,
- the concavo-convex structure has a large number of convex portions and a flat surface between the convex portions, And a plurality of areas in which the center points of the seven adjacent convex portions are continuously aligned in a positional relationship where the six vertexes of the regular hexagon and the intersection of the diagonal lines are arranged,
- a substrate for a semiconductor light emitting device wherein the area, shape and lattice orientation of the plurality of areas are random.
- a semiconductor light emitting device comprising: [23] The semiconductor light-emitting element according to [22], further comprising a wavelength conversion layer that converts the light emitted from the light-emitting layer to a longer wavelength side than the wavelength of the light emission on the light extraction side of the semiconductor functional layer.
- the wavelength conversion layer contains a blue phosphor emitting fluorescence with a peak wavelength of 410 nm to 483 nm, a green phosphor emitting fluorescence with a peak wavelength of 490 nm to 556 nm, and a red phosphor emitting fluorescence with a peak wavelength of 585 nm to 770 nm
- the semiconductor light emitting device according to [23].
- a semiconductor light emitting device that can obtain sufficient light extraction efficiency and prevent problems of increasing color shift and in-plane anisotropy.
- a semiconductor layer with few crystal defects can be formed, and a semiconductor light emitting element substrate suitable for manufacturing a semiconductor light emitting element that solves the above-described problems can be provided.
- some aspects of the present invention can manufacture a substrate for a semiconductor light emitting device that can solve the above-mentioned problems, and can be used for a semiconductor light emitting device that can form a concavo-convex structure with a pitch of 1 ⁇ m or less at a low cost and in a short time by a simple method
- a method for manufacturing a substrate can be provided.
- some aspects of the present invention can provide a method for manufacturing a semiconductor light-emitting element that can manufacture a semiconductor light-emitting element that solves the above-described problems by using a method for manufacturing a substrate for a semiconductor light-emitting element that solves the above-described problems.
- FIG. 24 is a partial cross-sectional view showing a part of the cross-sectional structure of the semiconductor light emitting device substrate in one embodiment, and is a partial cross-sectional view taken along line 23-23 in FIG. 7;
- FIG. 25 is a partial cross-sectional view showing a part of the cross-sectional structure of the semiconductor light emitting device substrate in one embodiment, and is a partial cross-sectional view taken along line 24-24 in FIG.
- FIG. 8 is a partial perspective view showing, in an enlarged manner, a part of a cross-sectional structure of a semiconductor light emitting device substrate in a semiconductor light emitting device substrate according to a modified example of the technique of the present disclosure, and the left side is described in the embodiment; The right side is a diagram corresponding to FIG. 9 described in the embodiment.
- FIG. 8 is a partial perspective view showing, in an enlarged manner, a part of a cross-sectional structure of a semiconductor light emitting device substrate in a semiconductor light emitting device substrate according to a modified example of the technique of the present disclosure, and the left side is described in the embodiment; The right side is a diagram corresponding to FIG. 9 described in the embodiment.
- FIG. 8 is a partial perspective view showing, in an enlarged manner, a part of a cross-sectional structure of a semiconductor light emitting device substrate in a semiconductor light emitting device substrate according to a modified example of the technique of the present disclosure, and the left side is described in the embodiment; The right side is
- FIG. 8 is a partial perspective view showing, in an enlarged manner, a part of a cross-sectional structure of a semiconductor light emitting device substrate in a semiconductor light emitting device substrate according to a modified example of the technique of the present disclosure, and the left side is described in the embodiment;
- the right side is a diagram corresponding to FIG. 9 described in the embodiment.
- a semiconductor light emitting device substrate 11 according to an embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 1, the semiconductor light emitting device substrate 11 has a concavo-convex structure on one surface of the substrate.
- the concavo-convex structure on the surface of the substrate has a large number of convex portions c11 to c1n. Further, flat surfaces f11 to f1n are formed between the respective convex portions. In FIG. 1, t11 to t1n are the center points of the convex portions c11 to c1n. Based on the measurement result of the AFM (atomic force microscope), a plurality of contour lines are drawn for each convex portion every 20 nm in parallel with the reference plane, and the center of gravity (point determined by the x and y coordinates) of each contour line is obtained. .
- AFM atomic force microscope
- the average position of these barycentric points is the center point of the convex portion.
- m11 to m1n are midpoints of adjacent center points obtained by AFM.
- the flat surfaces f11 to f1n are based on the measurement result of AFM, and the inclination of the straight line connecting the surface height at the middle point in the region and the surface height of any point in the region with respect to the reference surface of the AFM is This is an area that is ⁇ 10 ° or less.
- each flat surface f11 to f1n is preferably at a distance of 2 nm to 300 nm from each midpoint m1 to mn when the most frequent pitch P of the concavo-convex structure is 1 ⁇ m or less, and is at a distance of 5 nm to 100 nm. It is more preferable.
- the periphery of each flat surface f11 to f1n is preferably at a distance of 100 nm to 3000 nm from each of the midpoints m11 to m1n, and is at a distance of 200 nm to 2000 nm. It is more preferable.
- the distance between the periphery of each flat surface and each midpoint is equal to or more than the preferred lower limit value, a sufficient flat surface area is ensured, and the semiconductor layer can be stably epitaxially grown on the substrate. Further, if the distance between the periphery of each flat surface and each midpoint is equal to or less than the preferable upper limit value, it is easy to obtain the effect of improving the light extraction efficiency by forming convex portions with sufficient density. Further, the flat surfaces f11 to f1n are formed with convex portions c11 to c1n so as to be arranged as follows.
- the lengths of the flat surfaces f11 to f1n passing through the apexes of the projections c11 to c1n and perpendicular to the substrate, that is, the section shown in FIG. 1, are the two adjacent projections of the projections c11 to c1n.
- the convex portions c11 to c1n are formed so as to be 5% to 40%, preferably 15% to 25%, with respect to the straight line connecting the apexes of the portions.
- the convex part As the shape of the convex part, a cone, a truncated cone, a bamboo shoot shape or hemisphere with a conical slope bulging outward, a shape with a truncated cone slope bulging outward (a shape obtained by cutting the top of a bamboo shoot or hemisphere) ) And the like.
- the most frequent pitch P of the concavo-convex structure is preferably 100 nm to 5 ⁇ m, more preferably 100 nm to 1 ⁇ m, further preferably 200 nm to 700 nm, and particularly preferably 300 nm to 600 nm. If the most frequent pitch P is within a preferable range, it is easy to prevent total reflection of light.
- the most frequent pitch P is 1 ⁇ m or less, it is possible to more effectively increase the light extraction efficiency of blue to ultraviolet light. Therefore, it is suitable as a concavo-convex structure of a substrate used for a semiconductor light emitting device having a light emission wavelength in a blue to ultraviolet region by forming a film of GaN or InGaN.
- the most frequent pitch P is obtained as follows. First, in a randomly selected region on the uneven surface, a surface parallel to the substrate surface in a square region whose one side is 30 to 40 times the most frequent pitch P is defined as an AFM reference surface. Get an image. For example, when the most frequent pitch is about 300 nm, an image of an area of 9 ⁇ m ⁇ 9 ⁇ m to 12 ⁇ m ⁇ 12 ⁇ m is obtained. Then, this image is waveform-separated by Fourier transform to obtain an FFT image (fast Fourier transform image). Next, the distance from the zero-order peak to the primary peak in the profile of the FFT image is obtained. The reciprocal of the distance thus obtained is the most frequent pitch P in this region.
- FFT image fast Fourier transform image
- Such a process is similarly performed for a total of 25 or more regions of the same area selected at random, and the most frequent pitch in each region is obtained.
- the average value of the most frequent pitch P 1 ⁇ P 25 in 25 locations or more regions thus obtained is the most frequent pitch P.
- the regions are preferably selected at least 1 mm apart, more preferably 5 mm to 1 cm apart.
- the most frequent height H of the convex portion is preferably adjusted between 50 nm and 5 ⁇ m.
- the mode height H of the convex portion is preferably 50 nm or more and 1 ⁇ m or less, and more preferably 100 nm or more and 700 nm or less. If the most frequent height H is within a preferable range, film formation defects of a nitride compound formed thereafter can be reduced, and further, total reflection of light can be prevented and light extraction efficiency can be improved.
- the most frequent height H of the convex portion is obtained as follows. First, a cross-section perpendicular to the substrate, that is, a cross-section as shown in FIG.
- the semiconductor light emitting element substrate 11 has a plurality of areas C 11 to C 1n as shown in FIG.
- Each of the areas C 11 to C 1n is an area in which the center points of the seven adjacent convex portions are continuously aligned in a positional relationship where the six vertexes of the regular hexagon and the intersections of the diagonal lines.
- the position of the center point of each convex portion is indicated by a circle u1 centered on the center point for convenience.
- the circle u ⁇ b> 1 corresponds to a region including not only each convex portion but also a flat surface around it.
- the positional relationship in which the center points of the seven adjacent convex portions are the intersections of the six vertices of the regular hexagon and the diagonal line specifically refers to a relationship that satisfies the following conditions.
- a line segment L1 having a length equal to the most frequent pitch P is drawn from one center point t11 in the direction of the adjacent center point t12.
- line segments L2 to L6 having a length equal to the most frequent pitch P are drawn from the center point t11 in directions of 60 °, 120 °, 180 °, 240 °, and 300 ° with respect to the line segment L1.
- center points adjacent to the center point t11 are within 15% of the most frequent pitch P from the end points of the line segments L1 to L6 on the side opposite to the center point t11, these seven center points are It is in a positional relationship that is the intersection of six vertices of a regular hexagon and a diagonal line.
- the mode Q of each area C 11 to C 1n is preferably in the following range.
- the mode area Q in the 10 mm ⁇ 10 mm AFM image measurement range is preferably 0.026 ⁇ m 2 to 6.5 mm 2 .
- the mode area Q in the 10 mm ⁇ 10 mm AFM image measurement range is preferably 0.65 ⁇ m 2 to 26 mm 2 .
- the mode area Q in the AFM image measurement range of 50 mm ⁇ 50 mm is preferably 2.6 ⁇ m 2 to 650 mm 2 . If the most frequent area Q is within a preferable range, it is easy to prevent problems such as light color shift and in-plane anisotropy.
- Each area C 11 to C 1n has a random area, shape, and lattice orientation, as shown in FIG.
- the lattice orientation of the areas C 11 to C 1n is the basic translation vector (2 in the case of a triangular lattice) obtained by connecting vertices of adjacent convex portions in the same area when viewed from the upper surface of the substrate.
- the standard deviation of ⁇ ab within the 10 mm ⁇ 10 mm AFM image measurement range is preferably 0.08 ⁇ m 2 or more.
- the standard deviation of ⁇ ab within the AFM image measurement range of 10 mm ⁇ 10 mm is preferably 1.95 ⁇ m 2 or more.
- the standard deviation of ⁇ ab in the 50 mm ⁇ 50 mm AFM image measurement range is preferably 8.58 ⁇ m 2 or more. If the standard deviation of ⁇ ab is within a preferable range, the effect of averaging the diffracted light is excellent.
- the degree of randomness of the shapes of the areas C 11 to C 1n is specifically that the ratio of a to b in the formula ( ⁇ ) and the standard deviation of a / b is 0.1 or more. preferable.
- the randomness of the lattice orientation of each area C 11 to C 1n preferably satisfies the following conditions. First, a straight line K0 connecting the center points of any two adjacent convex portions in any area (I) is drawn. Next, one area (II) adjacent to the area (I) is selected, and the six convex points in the area (II) and the center points of the six convex parts adjacent to the convex part are connected. Draw the straight lines K1 to K6.
- the straight lines K1 to K6 are all at an angle different from the straight line K0 by 3 degrees or more, it is defined that the lattice orientations of the area (I) and the area (II) are different.
- the areas adjacent to the area (I) there are preferably two or more areas having a lattice orientation different from the lattice orientation of the area (I), preferably 3 or more, and more preferably 5 or more.
- the concavo-convex structure of the substrate 11 for a semiconductor light emitting device is arranged like a polycrystalline structure in which the lattice orientation is aligned in each of the areas C 11 to C 1n but not macroscopically.
- the randomness of the macroscopic lattice orientation can be evaluated by the ratio between the maximum value and the minimum value of the FFT (Fast Fourier Transform) fundamental wave.
- the ratio between the maximum value and the minimum value of the FFT fundamental wave is obtained by acquiring an AFM image, obtaining a two-dimensional Fourier transform image thereof, and drawing a circle away from the origin by the wave number of the fundamental wave.
- the point having the largest amplitude and the point having the smallest amplitude are extracted and obtained as a ratio of the amplitudes.
- the method for acquiring the AFM image at this time is the same as the method for acquiring the AFM image when obtaining the most frequent pitch P.
- the concavo-convex structure having a large ratio between the maximum value and the minimum value of the FFT fundamental wave has a uniform lattice orientation, and it can be said that the concavo-convex structure has a high single crystallinity when the concavo-convex structure is regarded as a two-dimensional crystal.
- the concavo-convex structure having a small ratio between the maximum value and the minimum value of the FFT fundamental wave does not have the same lattice orientation, and can be said to be arranged like a polycrystalline structure when the concavo-convex structure is regarded as a two-dimensional crystal. .
- the concavo-convex structure of the substrate 11 for a semiconductor light emitting element has a ratio between the maximum value and the minimum value of the FFT fundamental wave in the preferable range, diffracted light is not emitted in a specific in-plane direction, and the diffracted light is evenly distributed. Is emitted. Therefore, the radiation intensity of the semiconductor light emitting element does not vary depending on the viewing angle. In other words, a semiconductor light emitting device having low in-plane radiation anisotropy can be obtained. In addition, color shift can be prevented from occurring in the semiconductor light emitting device. Color shift is a phenomenon in which colors differ depending on the viewing angle.
- the concavo-convex structure of the substrate 11 for the semiconductor light emitting device the reflective electrode is provided on the upper surface and the ultraviolet light is converted into white by the three primary color phosphors
- Bottom emission type white LED which results from the diffracted light overlapping the original spectrum and intensifying certain wavelengths.
- the substrate 11 for semiconductor light-emitting elements has a random structure with an appropriate concavo-convex structure. Therefore, sufficient light extraction efficiency can be obtained, and the problem of high color shift and in-plane anisotropy can be prevented by averaging the diffracted light. Moreover, since the space between the protrusions is a flat surface, the semiconductor layer can be stably grown.
- the method for manufacturing a substrate for a semiconductor light emitting device includes: a particle arranging step of arranging a plurality of particles on the substrate; and the plurality of arranged particles under a condition that the particles are etched and the substrate is not substantially etched.
- each step will be sequentially described with reference to FIGS. 3A to 3D.
- 3A to 3D for convenience of explanation, the unevenness formed on the particles M and the substrate S is extremely enlarged.
- the material of the substrate is made of a material such as sapphire, SiC, Si, MgAl 2 O 4 , LiTaO 3 , LiNbO 3 , ZrB 2 , GaAs, GaP, GaN, AlN, AlGaN, InP, InSn, InAlGaN, or CrB 2.
- a plate material can be used.
- sapphire is preferable in that it has mechanical stability, thermal stability, optical stability, chemical stability, and light transmittance.
- a desired concavo-convex structure can be accurately formed not only on a substrate with high flatness but also on a substrate with low flatness. Since the single particle film used in this embodiment is formed even if the substrate has a certain degree of unevenness, it is possible to form a single particle film mask with a single layer with high accuracy even on a substrate with low flatness. Because it is possible.
- the absolute difference (TTV) between the maximum thickness and the minimum thickness specified by ASTM F657 is 5 ⁇ m to 30 ⁇ m, and the difference between the maximum value and the minimum value from the reference plane specified by ASTM F1390 (WARP).
- H ′ (2.5 ⁇ 0.5) P ⁇ ( ⁇ 0.4 ⁇ 0.1) ⁇ 1.5 (3)
- H ′ is a coefficient of variation in height of the concavo-convex structure
- P is the most frequent pitch ( ⁇ m) of the concavo-convex structure formed on the substrate according to the present embodiment.
- the coefficient of variation H ′ is generally obtained as follows.
- the method for obtaining the most frequent pitch P is as described above. For this embodiment, after obtaining the coefficient of variation for each pitch, the empirical formula (3) was obtained by taking the coefficient of variation on the vertical axis and the pitch on the horizontal axis.
- the coefficient of variation H ′ is preferably 10% or less, more preferably 5% or less, and even more preferably 3% or less. In this embodiment, even when a substrate with low flatness is used within the range of 5 ⁇ m to 30 ⁇ m for TTV, 10 ⁇ m to 50 ⁇ m for WARP, and 10 ⁇ m to 50 ⁇ m for
- the coefficient of variation H is within the range of TTV, WARP, and
- Particle alignment process Particles in the aligning step, as shown in FIG. 3A, causes one of the plurality of particles M 1 on a flat surface X which is a surface of the substrate S 1 are arranged in a single layer. That is, to form a single particle layer of particles M 1.
- Particles M 1 is preferably a inorganic particles, can also be used such as organic polymer materials depending on the conditions. If it is an inorganic particle, it can etch easily on the conditions in which the board
- the inorganic particles for example, particles composed of oxides, nitrides, carbides, borides, sulfides, selenides, metals and the like, metal particles, and the like can be used.
- the organic particles thermoplastic resins such as polystyrene and PMMA, thermosetting resins such as phenol resins and epoxy resins, and the like can be used.
- oxides examples include silica, alumina, zirconia, titania, ceria, zinc oxide, tin oxide, and yttrium aluminum garnet (YAG). Further, these constituent elements are partially substituted with other elements. Can also be used.
- nitride examples include silicon nitride, aluminum nitride, boron nitride, and the like, and those obtained by partially replacing these constituent elements with other elements can also be used.
- a compound such as sialon composed of silicon, aluminum, oxygen, and nitrogen can also be used.
- carbide examples include SiC, boron carbide, diamond, graphite, fullerenes, and those in which these constituent elements are partially substituted with other elements can also be used.
- Examples of borides that can be used include ZrB 2 , CrB 2, and the like, and those obtained by partially substituting these constituent elements with other elements can also be used.
- Examples of the sulfide that can be used include zinc sulfide, calcium sulfide, cadmium sulfide, strontium sulfide, and the like, and those obtained by partially replacing these constituent elements with other elements can also be used.
- Examples of the selenide that can be used include zinc selenide, cadmium selenide, and the like, and those obtained by partially substituting these constituent elements with other elements can also be used.
- As the metal that can be used particles made of one or more kinds of metals selected from the group consisting of Si, Ni, W, Ta, Cr, Ti, Mg, Ca, Al, Au, Ag, and Zn are used. Can do.
- each of the above inorganic particles can be used alone as the particle M 1 , or a mixture of these inorganic particles can be used as the particle M. Further, it is possible to use coated particles such as inorganic particles coated with oxide of nitride as particles M 1. Furthermore, it is possible to use phosphor particles obtained by introducing an activator such as cerium or europium in the inorganic particles as the particles M 1.
- the particle M 1 may be a mixture of two or more types of particles consisting of different materials.
- the particle M 1 may be a laminate of different materials, for example, inorganic particles made of an inorganic nitride may be coated particles with inorganic oxides. Among the compounds constituting the inorganic particles, oxides are preferable in terms of shape stability, and silica is more preferable among them.
- a plurality of particles M 1 are arranged in a single layer on the substrate S 1 so that the deviation D (%) of the arrangement defined by the following formula (1) is 15% or less.
- D [%]
- represents the absolute value of the difference between A and B.
- the deviation D is preferably 0.5% or more and 15% or less, more preferably 1.0% or more and 10% or less, and still more preferably 1.0% to 3.0%.
- the average particle diameter A of particles M 1 the method comprising: an average primary particle diameter of the particles M 1 constituting the single particle layer, a particle size distribution determined by a particle dynamic light scattering method in Gaussian curve It can obtain
- the pitch between the particles M the distance between two vertices and the vertices of the particles M 1 adjacent in the sheet surface direction, it is these the mode and modal pitch B between the particles M 1.
- the distance between the apex and the apex of the neighboring particles M 1 is equal to the center of the adjacent particles M 1 and the center distance.
- the pitch of the concavo-convex structure of the semiconductor light-emitting device substrate of this embodiment results in reflecting the pitch between the particles M 1, the modal pitch B between the preferred particle M 1 is a substrate for a semiconductor light emitting device of this embodiment This is the same as the preferable most frequent pitch P in the concavo-convex structure. That is, the modal pitch B between the particles M 1 is preferably 100 nm ⁇ 5 [mu] m, more preferably 100 nm ⁇ 1 [mu] m, more preferably in the range of 200 nm ⁇ 700 nm, particularly preferably in the range of 300 nm ⁇ 600 nm.
- Modal pitch B between the particles M 1 is specifically obtained as follows. First, in selected regions randomly in the single particle film, for 30 times to 40 times the sheet surface and parallel to the square region of the modal pitch B between one side particles M 1, obtain AFM images. For example, in the case of a single particle film using particles M 1 having a particle size of 300 nm, an image of a region of 9 ⁇ m ⁇ 9 ⁇ m to 12 ⁇ m ⁇ 12 ⁇ m is obtained. Then, this image is waveform-separated by Fourier transform to obtain an FFT image (fast Fourier transform image). Next, the distance from the zero-order peak to the primary peak in the profile of the FFT image is obtained. The reciprocal of the distance thus obtained is the most frequent pitch B 1 in this region.
- AFM images For example, in the case of a single particle film using particles M 1 having a particle size of 300 nm, an image of a region of 9 ⁇ m ⁇ 9 ⁇ m to 12 ⁇ m ⁇ 12 ⁇ m is obtained.
- Such processing is similarly performed for a total of 25 or more regions having the same area selected at random, and the most frequent pitches B 1 to B 25 in each region are obtained.
- the average value of the most frequent pitches B 1 to B 25 in the 25 or more regions thus obtained is the most frequent pitch B in the equation (1).
- the regions are preferably selected at least 1 mm apart, more preferably 5 mm to 1 cm apart.
- Deviation D of this arrangement is an index indicating the degree of close packing of the particles M 1. That is, a small deviation D of the arrangement of particles means that the degree of close-packing is high, the interval between the particles is controlled, and the accuracy of the arrangement is high. To 15% or less the deviation D (%) of sequence, variation coefficient of the particle diameter of particles M 1 (the value obtained by dividing the standard deviation mean) is preferably 20% or less, 10% or less More preferably, it is 5% or less. As described below, the pitch of the concavo-convex structure provided on the substrate S 1 according to the present embodiment (the pitch of the center point of the convex portion) is equal to the modal pitch B between the particles M 1.
- the aspect ratio of the projections c11 to c1n is 0.5 to 1.0.
- the bottom surfaces of the convex portions c11 to c1n are surfaces surrounded by the boundary between the flat surface f1n and the convex portion c1n.
- the bottom surface dimensions R11 to R1n of the convex portions c11 to c1n are distances between two points intersecting the boundary between the flat surface f1n and the convex portion c1n on a straight line passing through the center point t1n.
- the mode R can be calculated as follows.
- an arbitrary portion where 30 or more convex portions c1n are included is extracted, the size of the bottom surface of the convex portion is obtained by the above method for each c1n included therein, and the obtained value is used as the effective number of digits. Rounded by two digits, the bottom surface diameters R11 to R1n of each projection c1n are set, and the mode value is set as the mode dimension R.
- the aspect ratio of the convex portions c11 to c1n By setting the aspect ratio of the convex portions c11 to c1n to 0.5 to 1.0, it becomes difficult to confine light between the convex portions c11 to c1n, and the light extraction efficiency is improved.
- the particle arranging step is preferably performed by a method utilizing the concept of the so-called LB method (Langmuir-Blodgett method). Specifically, a dropping step of dropping a dispersion in which particles are dispersed in a solvent having a specific gravity smaller than that of water is dropped on the surface of water in the water tank, and a single particle film made of particles is formed by volatilizing the solvent. It is preferable to perform the particle arranging step by a method having a single particle film forming step and a transfer step of transferring the single particle film to the substrate. This method combines the accuracy of monolayering, the ease of operation, the response to large areas, and reproducibility.
- the volatile and hydrophobic solvent includes one or more volatile organic solvents such as chloroform, methanol, ethanol, isopropanol, acetone, methyl ethyl ketone, ethyl ethyl ketone, toluene, hexane, cyclohexane, ethyl acetate, and butyl acetate. Is mentioned.
- the particles M 1 is an inorganic particle, usually the surface because of the hydrophilic, it is preferable to use a hydrophobic with a hydrophobic agent.
- a hydrophobizing agent for example, a surfactant, a metal alkoxysilane, or the like can be used.
- Hydrophobized particles M 1 is hydrophobizing agent similar surfactants described in 2009-162831 JP-and a metal alkoxysilanes can be carried out in a similar manner.
- the dispersion before dropping onto the liquid surface is microfiltered with a membrane filter or the like, and aggregated particles (from a plurality of primary particles) present in the dispersion are used. Secondary particles) are preferably removed. If the microfiltration is performed in advance as described above, it is difficult to generate a portion where two or more layers are formed or a defective portion where particles are not present, and it is easy to obtain a single particle film with high accuracy.
- the formed single particle It is possible to detect a defect portion of the film to some extent based on the difference in surface pressure.
- a defect portion having a size of about several ⁇ m to several tens of ⁇ m is difficult to detect as a difference in surface pressure. If microfiltration is performed in advance, defects having a size of several ⁇ m to several tens of ⁇ m are less likely to occur, and a highly accurate single particle film can be easily obtained.
- the dispersion liquid demonstrated above is dripped at the liquid level of lower layer water (drip process). Then, the solvent as the dispersion medium is volatilized, and the particles M 1 are developed as a single layer on the liquid surface of the lower layer water, so that a single particle film that is two-dimensionally closely packed can be formed (single particle film). Forming step).
- the particle concentration of the dispersion dropped into the lower layer water is preferably 1% by mass to 10% by mass.
- the dropping rate is preferably 0.001 ml / second to 0.01 ml / second.
- the concentration or dropping of the particles M 1 in the dispersion is in this range, the particles are partially clustered to aggregate into two or more layers, it occurs defective portion does not exist particles, between particles The tendency for the pitch to expand is suppressed. Therefore, it is easier to obtain a single particle film in which each particle is two-dimensionally closely packed with high accuracy.
- the single-particle film forming step single-particle film is formed by self-organization of particles M 1.
- the principle is that when the particles are aggregated, surface tension acts due to the dispersion medium existing between the particles, and as a result, the particles M 1 do not exist at random, but a two-dimensional close-packed structure. Is automatically formed. In other words, the close-packing by surface tension can be said to be arrangement by lateral capillary force.
- colloidal silica uniformity high particle M 1 particle size a spherical, when three collection contact floated on the water surface, so as to minimize the total length of the particles waterline Surface tension acts on the surface.
- the three particles M 1 are stabilized in an arrangement based on an equilateral triangle indicated by T 1 in the figure.
- the single particle film forming step is preferably performed under ultrasonic irradiation conditions.
- the solvent of the dispersion is volatilized while irradiating ultrasonic waves from the lower layer water to the water surface, the closest packing of the particles M is promoted, and each particle M 1 is more closely packed in two dimensions with higher accuracy. A membrane is obtained.
- the output of the ultrasonic wave is preferably 1 W to 1200 W, and more preferably 50 W to 600 W.
- the frequency of the ultrasonic wave is not particularly limited, but is preferably, for example, 28 kHz to 5 MHz, and more preferably 700 kHz to 2 MHz.
- the frequency is too high, energy absorption of water molecules begins, and a phenomenon in which water vapor or water droplets rise from the water surface is not preferable.
- the frequency is too low, the cavitation radius in the lower layer water becomes large, bubbles are generated in the water, and rise toward the water surface. If such bubbles accumulate under the single particle film, the flatness of the water surface is lost, which is inconvenient.
- a standing wave is generated on the water surface by ultrasonic irradiation. If the output is too high at any frequency, or if the wave height of the water surface becomes too high due to the tuning conditions of the ultrasonic transducer and the transmitter, the single particle film will be destroyed by the water surface wave, so care must be taken.
- the ultrasonic frequency and output are appropriately set in consideration of the above, close-packing of particles can be effectively promoted without destroying the single particle film being formed.
- the natural frequency calculated from the particle size of the particles should be used as a guide.
- the particle diameter is small, for example, 100 nm or less, the natural frequency becomes very high, and it is difficult to apply ultrasonic vibration as calculated.
- the necessary frequency can be reduced to a practical range.
- the ultrasonic irradiation time may be sufficient to complete the rearrangement of particles, and the required time varies depending on the particle size, ultrasonic frequency, water temperature, and the like.
- the normal production conditions are preferably 10 seconds to 60 minutes, more preferably 3 minutes to 30 minutes.
- the advantage obtained by ultrasonic irradiation is the effect of destroying the soft agglomerates of particles that are likely to occur when preparing a dispersion of nanoparticles, in addition to the closest packing of particles (to make the random array 6-way closest) The generated point defects, line defects, crystal transitions and the like are also repaired to some extent.
- the single particle film formed on the liquid surface by a single particle film forming process then, take transferred leave the substrate S 1 of a single layer state (transition step).
- a specific method for transferring the single particle film to the substrate S 1 is not particularly limited.
- the hydrophobic substrate S 1 is lowered from above while being kept in a substantially parallel state with respect to the single particle film.
- the single particle layer was transferred to the substrate S 1, transferred taking method; the lower water beforehand aquarium prior to forming a single particle film
- a single-particle film without using special equipment can take transferred to the substrate S 1, be a single-particle film of larger area, the secondary closest packing state in that easy to take transferred remains on the substrate S 1 was maintained in the process after it is preferred to employ a so-called LB trough method (Journal of Materials and Chemistry, Vol.11 , 3333 (2001), Journal ofMaterials and Chemistry, (See Vol.12, 3268 (2002) etc.)
- 5A and 5B schematically show an outline of the LB trough method.
- the particle M is extremely enlarged for convenience of explanation.
- the substrate S 1 is preliminarily immersed in the lower layer water W 1 in the water tank V 1 in the substantially vertical direction, and the dropping step and the single particle film forming step are performed in that state, and the single particle film F 1 is thus obtained.
- the single particle film F can be transferred to the substrate S 1 by pulling the substrate S 1 upward while maintaining a substantially vertical direction (FIG. 5B).
- the concavo-convex structure may be formed only on one surface of the substrate S 1 , and thus the single particle film F 1 may be taken and transferred only to the flat surfaces X 1 of the substrate S 1.
- the flat surface X 1 the opposite surface (back surface) substrate S 1 is shielded by thick, flat surfaces X 1 only in a state that prevents the diffraction of particles M 1 on the back side from the flat surface X 1 side Taking transferred monoparticulate film F 1, preferred because take transferred monoparticulate film F 1 more precisely. However, it can be transferred to both sides.
- the temperature condition (temperature of the lower layer water) of the transition step and the pulling speed of the substrate S 1 are increased. even if slightly varies such, there is no risk of such a single-particle film F 1 is multilayered by disintegration in the transition process.
- the temperature of the lower layer water is usually about 10 ° C. to 30 ° C. depending on the environmental temperature which varies depending on the season and weather.
- the water tank V 1 the not shown in Wilhelmy plate or the like for measuring the surface pressure of the single particle film F 1 and the surface pressure sensor and the principle, in the direction along the single-particle film F 1 on the liquid surface
- an LB trough device having a movable barrier (not shown) to be compressed.
- the single particle film F 1 can be compressed to a preferable diffusion pressure (density) while measuring the surface pressure of the single particle film F 1 , and constant toward the substrate S 1 . Can move at speed.
- a preferable diffusion pressure is 5 mNm ⁇ 1 to 80 mNm ⁇ 1 , more preferably 10 mNm ⁇ 1 to 40 mNm ⁇ 1 . With such a diffusion pressure, it is easy to obtain a single particle film F 1 in which each particle is two-dimensionally closely packed with higher accuracy.
- the speed at which the substrate S 1 is pulled up is preferably 0.5 mNm ⁇ 1 to 20 mm / min.
- the temperature of the lower layer water is usually 10 ° C. to 30 ° C. as described above. Note that the LB trough device can be obtained as a commercial product.
- each particle is transferred to the substrate S 1 in the state of the single particle film F 1 that is two-dimensionally closely packed with the highest possible accuracy. does not become full closest packing, transferred taken particles on the substrate S 1 is a polycrystalline state.
- a plurality of areas that are continuously aligned in a positional relationship in which the center points of the seven adjacent convex portions are the intersections of the six vertices of the regular hexagon and the diagonal line. an uneven structure provided can be formed on the substrate S 1.
- a method using a binder and a sintering method there are a method using a binder and a sintering method.
- a binder solution is supplied to the flat surface X side of the substrate S 1 on which the single particle film is formed, and is allowed to penetrate between the particles M 1 constituting the single particle film and the substrate S 1 .
- the amount of the binder used is preferably 0.001 to 0.02 times the mass of the single particle film. With such a range, the binder is too multi causes clogged binder between particles M 1, without causing the problem of adversely affecting the accuracy of the single-particle film, it is possible to secure the sufficient particles.
- the binder solution may be removed excess binder solution.
- the binder metal alkoxysilanes, general organic binders, inorganic binders and the like exemplified above as the hydrophobizing agent can be used. After the binder solution has permeated, heat treatment may be appropriately performed depending on the type of the binder. . When metal alkoxysilane is used as a binder, it is preferably heat-treated at 40 ° C. to 80 ° C. for 3 minutes to 60 minutes.
- each particle M 1 constituting the single particle layer it is sufficient to fuse to the substrate S 1.
- the heating temperature may be determined according to the material of the particle M 1 and the material of the substrate S 1 , but the particle M 1 having a particle size of 1 ⁇ m ⁇ or less starts an interfacial reaction at a temperature lower than the original melting point of the substance. Sintering is completed on the relatively low temperature side. If the heating temperature is too high, the fusion area of the particles increases, and as a result, the shape of the single particle film may change, which may affect the accuracy. In addition, if heating is performed in air, the substrate S 1 and each particle M 1 may be oxidized.
- the conditions are determined in consideration of the possibility of such oxidation. It is necessary to set. For example, if a silicon substrate is used as the substrate S 1 and sintered at 1100 ° C., a thermal oxide layer having a thickness of about 200 nm is formed on the surface of the substrate S 1 . When heated in N 2 gas or argon gas, it is easy to avoid oxidation.
- the particle arrangement step is not particularly limited as long as the deviation D (%) of the arrangement can be 1.0% or more and 15% or less, and the following method can be adopted in addition to the LB method.
- particle adsorption method a method of providing an etching mask made of a single particle film on a substrate (see Japanese Patent Application Laid-Open No. 58-120255).
- a binder layer is formed on a substrate, a particle dispersion is applied thereon, and then the binder layer is softened by heating, so that only the first particle layer is embedded in the binder layer, A method of washing off excess particles (see JP-A-2005-279807).
- the particle etching step the plurality of particles M 1 arranged under the condition that the substrate S 1 is not substantially etched is dry-etched. As a result, as shown in FIG. 3B, only the particles M 1 are substantially etched to become particles M 11 having a small particle diameter, and a gap is provided between the particles M 11 .
- the substrate S 11 after the particles etching process substantially the same as the substrate S 1, substantial irregularities are not formed on the flat surface X 11 is one surface of the substrate S 11, a flat surface X 11 flat surface X 1 are equivalent.
- an etching gas may be appropriately selected.
- the particle M 1 is silica, selected from CF 4 , SF 6 , CHF 3 , C 2 F 6 , C 3 F 8 , CH 2 F 2 , O 2 , and NF 3 if dry etching using one or more gasses, with little effect on the substrate S 1, can be etched particles M 1.
- the substrate S is sapphire and the particle M 1 is titania (TiO 2 ), CF 4 , SF 6 , CHF 3 , C 2 F 6 , C 3 F 8 , CH 2 F 2 , O 2 , and If dry etching is performed using one or more gases selected from NF 3, the same effect as described above can be obtained.
- the substrate S is sapphire and the particle M 1 is polystyrene, selected from CF 4 , SF 6 , CHF 3 , C 2 F 6 , C 3 F 8 , CH 2 F 2 , O 2 , and NF 3
- the same effect as described above can be obtained by dry etching using one or more gases.
- the substrate S is silicon, when the particle M 1 is polystyrene, obtained the same effect as if dry etching using O 2 gas.
- the diameter of the thickness direction of the substrate S 1 (vertical direction) (hereinafter referred to as "height".) Previously sufficiently leave There is a need. Also, since the etching mask is between the adjacent particles M 11 are spaced apart sufficiently, size of the substrate S 1 in the planar direction of particle M 11 (horizontal direction) (hereinafter referred to as "area”.) It is sufficiently small It needs to be. Therefore, the particle etching process is preferably performed under the condition that the area is reduced while suppressing a decrease in height. In order to satisfy the above condition, the bias power may be set low or the pressure may be reduced.
- Substrate etching process The substrate etching step, the substrate S 11 after the particles etching step the particles M 11 after the particles etching process as an etching mask to dry etching.
- Substrate S 11 first, since exposed to the etching gas in the voids between the particles M 11, portions thereof prior, is etched while maintaining the flatness. Then, since the smaller is gradually etched even particles M 11, toward the lower portion from the lower portion of the peripheral center of each particle M 11, gradually, etching of the substrate S 11 proceeds. As a result, as shown in FIG. 3C, the particles M 11 small particles M 12 further grain size.
- a truncated cone-shaped convex portion Y 12 to the lower and the top surface of each particle M 12 is formed with a plurality.
- Protrusions Y 12 each other voids (bottom surface of the recess) corresponds substantially with the gap between the particles M 11, the portion becomes a flat surface X 12.
- a plurality of conical convex portions Y 13 having apexes at the lower side of the central portion of each particle M 12 are formed on the substrate S 13 after the substrate etching process is completed.
- Protrusions Y 13 each other voids (bottom surface of the recess) is a flat surface X 13.
- the flat surface X 13 substantially corresponds to the gap between the particles M 11 and the flat surface X 12, and is a bottom surface of a deeper recess than the flat surface X 12 .
- the dry etching rate of the substrate S 12 (substrate S 1 ) needs to exceed the etching rate of the particles M 12 (particles M 1 ), and the dry etching selectivity of the formula (2) is greater than 100%. Cost.
- the dry etching selectivity of the formula (2) in the substrate etching process is preferably 200% or more, and more preferably 300% or more.
- an etching gas may be appropriately selected. For example, when the substrate S 1 is sapphire and the particle M 1 is silica, using one or more gases selected from Cl 2 , Br 2 , BCl 3 , SiCl 4 , HBr, HI, HCl, and Ar. What is necessary is just to dry-etch.
- a reactive ion etching apparatus As an etching apparatus that can be used, a reactive ion etching apparatus, an ion beam etching apparatus, or the like that can perform anisotropic etching and can generate a bias electric field of about 20 W at the minimum can generate plasma.
- the temperature in the chamber is preferably maintained at 60 ° C. to 200 ° C., more preferably 80 ° C. to 150 ° C.
- the etching rate of the substrate is increased and handling is easy, so that the manufacturing efficiency can be increased.
- the substrate is a sapphire substrate, it is particularly preferable to perform the substrate etching process at the above temperature.
- the shape of the convex portion Y 13 can be adjusted bias power, pressure in the vacuum chamber, the type of the etching gas. For example, if the pressure is lowered, the shape has a gentle inclination angle. In addition, it is good also as a truncated cone-shaped convex part by finishing a board
- the pitch of the concavo-convex structure provided on the substrate S 1 is equal to the most frequent pitch B between the particles M 1 described above. Since the arrangement of the particles M 1 in FIG. 3A has a high degree of fine packing, an uneven structure with a desired pitch can be accurately formed by appropriately selecting the average particle diameter A of the particles M 1 . In addition, since the particle etching process is performed before the substrate etching process, the bottom surface of the concave portion between the convex portions can be made flat. Therefore, the semiconductor layer can be stably grown on the flat surface. Therefore, it can be set as the board
- the cost for producing a relatively small uneven structure with a pitch of 1 ⁇ m or less (submicron pitch). And less time.
- the manufacturing cost of particles serving as an etching mask decreases as the particle size decreases, and the process time required for the dry etching process decreases as the particle size decreases.
- the cost of the apparatus is equivalent when a relatively small uneven structure with a pitch of 1 ⁇ m or less and a relatively large uneven structure with a pitch of several ⁇ m are manufactured.
- the concavo-convex structure is arranged like a polycrystalline structure in which the macroscopic lattice orientation is random (that is, the ratio between the maximum value and the minimum value of the FFT fundamental wave is small). It may be provided on the substrate S 1.
- the semiconductor light emitting device of the present embodiment includes the semiconductor light emitting device substrate of the present embodiment, a semiconductor functional layer laminated on the surface on which the concavo-convex structure is formed, a p-type electrode, and an n-type electrode.
- the semiconductor functional layer includes at least a light emitting layer.
- the semiconductor functional layer is preferably composed of a group III-V nitride semiconductor in which the group V element is nitrogen.
- GaN, InGaN, AlGaN, InAlGaN, GaAs, AlGaAs, InGaAsP, InAlGaAsP, InP, InGaAs, InAlAs, ZnO, ZnSe, ZnS and the like can be mentioned.
- III-V nitride semiconductor needs to be formed on a substrate such as sapphire.
- Typical group III-V nitride semiconductors are gallium nitride and indium nitride. Strictly speaking, aluminum nitride is an insulator, but in the present embodiment, it is treated as equivalent to a group III-V nitride semiconductor in accordance with the practice of the semiconductor light emitting device field.
- the layer structure of the semiconductor functional layer includes at least an n-type conductivity layer, a p-type conductivity layer, and a III-V group nitride semiconductor layer having a light emitting layer sandwiched between them.
- a light emitting layer is preferred.
- the III-V nitride semiconductor functional layer includes high-quality layers.
- a single layer or multiple layers (including a case of a thick film layer and a superlattice thin film layer) necessary for forming a crystal are included.
- a buffer layer may be included.
- Each of the above layers may also be composed of a plurality of layers.
- Specific semiconductor functional layers include a buffer layer made of GaN, AlN, etc., an n-type conductive layer (clad layer) made of n-GaN, n-AlGaN, etc., a light emitting layer made of InGaN, GaN, etc.
- Examples include a multilayer film in which a p-type conductive layer (clad layer) made of undoped GaN, p-GaN, etc., and a cap layer made of Mg-doped AlGaN and Mg-doped GaN are sequentially stacked (for example, Japanese Patent Laid-Open No. Hei 6).
- electrodes made of a metal such as Ni, Au, Pt, Pd, Rh, Ti, and Al can be used as an n-type electrode and a p-type electrode for supplying current to the light emitting layer.
- electrodes made of a metal such as Ni, Au, Pt, Pd, Rh, Ti, and Al can be used as an n-type electrode and a p-type electrode for supplying current to the light emitting layer.
- the function of the semiconductor functional layer preferably includes n-type conductivity, p-type conductivity, and activity to recombine carriers.
- the stacked structure in the semiconductor functional layer may be a double hetero structure in which an active layer is sandwiched between an n-type semiconductor layer and a p-type semiconductor layer, or a multiple quantum well structure in which a plurality of quantum well structures are stacked. It may be.
- the semiconductor light emitting device of this embodiment is a wavelength conversion layer that converts the light emitted from the light emitting layer on the light extraction side of the semiconductor functional layer to a wavelength longer than the light emission wavelength in order to adjust the light emission wavelength.
- a wavelength conversion layer can be disposed between the light emitting layer and the p-type electrode.
- a wavelength conversion layer may be disposed outside the p-type electrode (outside the element) (in this case, a phosphor is contained in the resin embedding the LED element).
- a wavelength conversion layer can be disposed between the light emitting layer and the substrate.
- the wavelength conversion layer can be disposed on the surface opposite to the surface on which the semiconductor light emitting element is provided. In this case, you may arrange
- the emission wavelength of the light-emitting layer contains a large amount of emission energy in the ultraviolet region
- a blue phosphor that emits fluorescence with a peak wavelength of 410 nm to 483 nm
- white extraction light suitable for illumination can be obtained.
- a white phosphor suitable for illumination can be obtained by including a yellow phosphor that emits fluorescence having a peak wavelength of 570 nm to 578 nm in the wavelength conversion layer. Light can be obtained.
- the manufacturing method of the semiconductor light emitting device of this embodiment includes a step of obtaining a light emitting device substrate by the method of manufacturing a light emitting device substrate of this embodiment, and a surface on which the uneven structure of the obtained light emitting device substrate is formed.
- a method of laminating a semiconductor functional layer on a substrate for a semiconductor light emitting device is a known epitaxial growth method such as MOVPE (metal organic vapor phase epitaxy), MBE (molecular beam epitaxy), HVPE (hydride vapor phase epitaxy), or the like. Can be used.
- the epitaxial growth method include a vapor phase epitaxial growth method, a liquid phase epitaxial growth method, and a molecular beam epitaxial growth method.
- a target made of a constituent element of a compound semiconductor layer is sputtered, and a material for forming a semiconductor layer is generated by a reaction between particles sputtered from the target and an impurity element in a gas phase.
- the n-type semiconductor layer may be formed by any epitaxial growth method or reactive sputtering method to which an n-type impurity is added.
- the method for forming the p-type semiconductor layer may be an epitaxial growth method or a reactive sputtering method to which a p-type impurity is added.
- the supersaturated solution containing the compound semiconductor layer forming material maintains the equilibrium state between the solid phase and the liquid phase, while the compound semiconductor layer forming material is placed on the light emitting structure forming surface of the substrate for the semiconductor light emitting device.
- the compound semiconductor layer forming material is grown as a crystal on a light emitting structure forming surface.
- a molecule or atom beam composed of a constituent element of a compound semiconductor layer irradiates the light emitting structure forming surface, and the compound semiconductor layer forming material is grown as a crystal on the light emitting structure forming surface.
- the halide vapor phase growth method using a hydride such as AsH 3 or PH 3 as the group V raw material is preferable in that the thickness of the growing compound semiconductor layer is large.
- Group III materials include general formulas such as trimethylgallium [(CH 3 ) 3 Ga, hereinafter referred to as TMG], triethylgallium [(C 2 H 5 ) 3 Ga, hereinafter referred to as TEG], and the like.
- Trialkylgallium represented by R 1 R 2 R 3 Ga (where R 1 , R 2 and R 3 represent lower alkyl groups), trimethylaluminum [(CH 3 ) 3 Al, hereinafter referred to as TMA
- R 1 R 2 R 3 such as triethylaluminum [(C 2 H 5 ) 3 Al, hereinafter sometimes referred to as TEA], triisobutylaluminum [(i-C 4 H 9 ) 3 Al]
- Trialkylaluminum represented by Al (wherein R 1 , R 2 and R 3 represent lower alkyl groups), trimethylamine alane [(CH 3 ) 3 N: AlH 3 ], trimethylindium [(CH 3 ) 3 In, hereinafter sometimes referred to as TMI], and general formulas R 1 R 2 R 3 In such as triethylindium [(C 2 H 5 ) 3 In] (where R 1 , R 2 and R 3 are lower A trialkylindium represented by (indicating an alkyl group), a
- Group V raw material examples include ammonia, hydrazine, methyl hydrazine, 1,1-dimethylhydrazine, 1,2-dimethylhydrazine, t-butylamine, and ethylenediamine. These can be used alone or in any combination. Among these raw materials, ammonia and hydrazine are preferable because they do not contain carbon atoms in their molecules and thus cause less carbon contamination in the semiconductor.
- gases such as nitrogen, hydrogen, argon, and helium can be used singly or as a mixture, and hydrogen and helium are preferred as the growth atmosphere gas and the carrier gas of the organometallic raw material.
- the uneven structure of the substrate has an appropriate randomness. Therefore, it is possible to obtain a semiconductor light emitting device that can obtain a sufficient light extraction efficiency and prevents the problem of increasing color shift and in-plane anisotropy.
- the semiconductor since the semiconductor is stacked on the substrate having a flat surface between the convex portions, the semiconductor layer can be stably grown on the flat surface. Therefore, it is difficult to generate crystal defects in the semiconductor layer.
- the semiconductor light emitting element substrate (hereinafter, referred to as element substrate 211 ⁇ / b> B) has a light emitting structure forming surface 211 ⁇ / b> S that is one side surface.
- the light emitting structure is formed on the light emitting structure forming surface 211S.
- the substrate material described in the first embodiment can be used as the material for forming the element substrate 211B.
- the light emitting structure forming surface 211S has crystallinity suitable for imparting crystallinity to the light emitting structure.
- the light emitting structure forming surface 211S has a concavo-convex structure composed of a large number of fine concavo-convex structures. Fine irregularities are repeated along the direction in which the light emitting structure forming surface 211S extends.
- the concavo-convex structure of the light emitting structure forming surface 211 ⁇ / b> S includes a large number of convex portions 212, a large number of bridge portions 213, and a large number of flat portions 214.
- Each of the many flat portions 214 is a plane extending along one crystal plane, and is arranged on one plane.
- the flat portion 214 is a plane in which one surface selected from the group consisting of the c-plane, m-plane, a-plane, and r-plane is continuous.
- the flat portion 214 is, for example, a plane in which one plane selected from the group consisting of the (001) plane, the (111 plane), and the (110) plane is continuous. is there.
- the crystal plane of the flat portion 214 may be a higher index plane than the index plane, and may be one crystal plane suitable for imparting crystallinity to the light emitting structure.
- the crystal plane included in each of the plurality of flat portions 214 urges the semiconductor layer to have crystallinity on the light emitting structure formation surface 211S.
- Each of the large number of convex portions 212 protrudes from the flat portion 214 connected to the convex portion 212 and has a shape that narrows from the base end connected to the flat portion 214 toward the distal end.
- Each of the plurality of convex portions 212 has a hemispherical shape.
- the shape which the convex part 212 has is not limited to a hemispherical shape, and may be a conical shape or a pyramid shape.
- the generatrix that appears in the cross section may be a curved line.
- the shape of the convex portion 212 may be a multi-stage shape that narrows from the proximal end toward the distal end, or may be a shape that once thickens in the middle from the distal end toward the proximal end.
- Each of the multiple convex portions 212 may have a different shape.
- the interval between the convex portions 212 adjacent to each other is the pitch of the convex portions 212.
- the pitch of the convex part 212 you may be the same as that of 1st Embodiment.
- the mode value of the pitch is preferably 100 nm or more and 5 ⁇ m or less. If the pitch of the convex portions 212 is 100 nm or more and 5 ⁇ m or less, the light emitting structure forming surface 211S has convex portions with the necessary arrangement and density to such an extent that total reflection of light on the light emitting structure forming surface 211S is suppressed. 212 is formed. At this time, the balance between the convex portion 212 and the flat portion 214 is appropriately designed.
- the mode value of the pitch of the convex portions 212 is 5 ⁇ m or less, the large number of convex portions 212 are sufficiently prevented from being visually recognized, and the thickness of the element substrate 211B is unnecessarily large. It can be suppressed.
- the mode value of such a pitch can be obtained by the method for obtaining the mode pitch P described in the first embodiment. For example, as shown below, it is obtained by image processing based on the AFM image. First, an AFM image is obtained for a rectangular region arbitrarily selected on the light emitting structure forming surface 211S. At this time, in the rectangular area where the AFM image is obtained, the length of one side of the rectangular area is 30 to 40 times the mode value of the pitch. Next, a fast Fourier transform image based on the AFM image is obtained by waveform separation of the AFM image using Fourier transform.
- the distance between the zero-order peak and the first-order peak in the fast Fourier transform image is obtained, and the reciprocal of the distance is treated as the pitch of the convex portions 212 in one rectangular area.
- the pitch is measured for 25 or more different rectangular areas, and the average value of the measured values thus obtained is the mode value of the pitch of the convex portion 212.
- the rectangular regions are preferably at least 1 mm apart, and more preferably 5 mm to 1 cm apart.
- the height from the flat portion 214 in each of the multiple convex portions 212 may be the same as that in the first embodiment.
- the height from the flat portion 214 in each of the many convex portions 212 is preferably 50 nm or more and 300 nm or less. If the height of the plurality of convex portions 212 is 50 nm or more and 300 nm or less, total reflection of light on the light emitting structure forming surface 211S is easily suppressed.
- the height of the convex portion 212 is 50 nm or more and 300 nm or less, in the semiconductor layer formed on the light emitting structure forming surface 211S, the occurrence of film formation defects due to the formation of the convex portion 212 can be suppressed.
- the mode value of the height of the convex portion 212 is obtained by image processing based on the AFM image, for example, as shown below.
- an AFM image is obtained for a rectangular region arbitrarily selected on the light emitting structure forming surface 211S, and a sectional shape of the concavo-convex structure is obtained from the AFM image.
- the difference between the height of the apex at the convex portion 212 and the height of the flat portion 214 connected to the convex portion 212 is measured.
- the heights of the convex portions 212 are similarly measured for five or more different rectangular regions, and the heights of the convex portions 212 of 25 or more in total are measured.
- the rectangular regions are preferably at least 1 mm apart, and more preferably 5 mm to 1 cm apart.
- an equatorial direction profile using a two-dimensional Fourier transform image is created, and the mode value of the height at the convex portion 212 is obtained from the reciprocal of the primary peak.
- the bridge portion can be configured so as to connect between the convex portions 212 adjacent to each other.
- the bridge portion By providing the bridge portion, it is possible to obtain the optical effect and mechanical strength effect described later. Epitaxial growth in the LED film forming process can be effectively performed.
- Each of the large number of bridge portions 213 protrudes from the flat portion 214 connected to the bridge portion 213 and connects between the convex portions 212 adjacent to each other.
- the height of each of the multiple bridge portions 213 is lower than the height of the convex portion 212 and has a ridge shape that connects the centers of the convex portions 212 having a hemispherical shape.
- bridge portion 213 is not limited to a linear shape, and may be a curved shape or a broken line shape. Each of the multiple bridge portions 213 may have a different shape.
- Bridge portion 213 includes a top surface 213T.
- the top surface 213T includes a flat surface.
- the length along the longitudinal direction of the bridge portion 213 is preferably 50 nm or more and 300 nm or less. If the length along the longitudinal direction of the bridge portion 213 is not less than 50 nm and not more than 300 nm, total reflection of light on the light emitting structure forming surface 211S can be easily suppressed.
- the length of the bridge portion 213 along the short direction is preferably 10 nm or more and 100 nm or less. When the length along the short direction of the bridge portion 213 is 10 nm or more and 100 nm or less, total reflection of light on the light emitting structure forming surface 211S is easily suppressed. Further, the mechanical strength of the bridge portion 213 is ensured to such an extent that the light emitting structure can sufficiently withstand the film stress.
- the plurality of convex portions 212 has a plurality of convex portion pairs TP ⁇ b> 2 in a plan view of the light emitting structure forming surface 211 ⁇ / b> S.
- One convex portion pair TP2 is composed of two convex portions 212 adjacent to each other, and two convex portions 212 included in one convex portion pair TP2 are connected by one bridge portion 213.
- one flat portion 214 is surrounded by three convex pairs TP2.
- the plurality of convex portions 212 includes a plurality of convex portion groups TG2.
- One convex part group TG2 is composed of six convex part pairs TP2.
- one convex portion 212 in the six convex portion pairs TP2 is common to each other.
- the seven convex portions 212 constituting one convex portion group TG2 have a hexagonal filling structure.
- six convex portions 212 are disposed at six vertices of the hexagon, and one convex portion 212 is disposed at a portion surrounded by the six convex portions 212.
- each of the plurality of convex portion groups TG2 six convex portions 212 are equally arranged around one central convex portion 212. Then, six bridge portions 213 extend radially from one convex portion 212 as the center toward the other convex portion 212. In one convex part group TG2, the height of each of the six bridge parts 213 tends to be lower as the distance between the convex parts 212 connected by the bridge part 213 is larger.
- the light emitting structure forming surface 211S has a plurality of convex portion groups TG2, the effect of suppressing total reflection by the convex portions 212 is enhanced. Further, it is possible to suppress the film stress of the light emitting structure formed on the light emitting structure forming surface 211 ⁇ / b> S from being concentrated on one convex portion 212. And the mechanical strength required for the convex part 212 is also suppressed.
- the plurality of convex portions 212 has a plurality of convex portion groups TL2.
- Each of the plurality of convex portion groups TL2 includes two or more convex portion groups TG2.
- two different convex portion groups TG2 share two or more convex portions 212 with each other.
- any one of the direction in which the convex portion group TG2 is arranged, the area occupied by one convex portion TL2, and the shape of one convex portion TL2, preferably any two, Preferably all are different from each other.
- each of the plurality of convex portions TL2 is randomly arranged including its size and shape.
- the height of each of the plurality of bridge portions 213 is preferably lower as the distance between the convex portions 212 connected by the bridge portion 213 is larger.
- the light emitting structure forming surface 211S has a plurality of convex portions TL2, the refraction of light entering the light emitting structure forming surface 211S is averaged within the light emitting structure forming surface 211S.
- the fine concavo-convex structure has moderate randomness. Therefore, the effect of suppressing total reflection is averaged at the light emitting structure forming surface 211S.
- one bridge portion 213 is formed for each convex portion pair TP2, the effect of suppressing total reflection is further enhanced. A large number of such bridge portions 213 are formed, and one flat portion 214 is surrounded by the three bridge portions 213.
- the light emitting structure forming surface 211S may have an isolated convex portion group TG2 or an isolated convex portion 212 in addition to the plurality of convex portions TL2.
- each of the plurality of convex portions TL2 may have the same size as each other, or may have the same shape.
- each of the plurality of convex portion groups TL2 may be configured such that the direction in which the convex portion groups TG2 are arranged may be equal to each other as long as they are separated from each other.
- the height of the apex of the convex portion 212 with respect to the flat portion 214 is a protrusion height HT 2.
- the bridge height HB 2 is lower than the convex height HT 2, preferably lower than half of the convex height HT 2.
- HB 2 / HT 2 0.01 to 0.40 is preferable, and 0.05 to 0.20 is more preferable.
- the bridge height HB 2 is preferably constant over substantially the entire bridge portion 213 along the direction in which the bridge portion 213 extends.
- the bridge height HB 2 is also constant along the direction intersecting the direction in which the bridge portion 213 extends.
- the top surface 213T of the bridge portion 213 includes a plane. The plane extends along the direction in which the bridge portion 213 extends and is continuous along the direction intersecting with the direction in which the bridge portion 213 extends. Similar to the flat portion 214, the top surface 213T of the bridge portion 213 includes a plane extending along one crystal plane.
- the top surface 213T of the bridge portion 213 is selected from the group consisting of, for example, the c-plane, m-plane, a-plane, and r-plane, as with the flat section 214.
- One plane is a continuous plane.
- the top surface 213T of the bridge portion 213 is also selected from the group consisting of, for example, the 001, 111, and 110 surfaces, as with the flat portion 214. This is a plane in which one surface is continuous.
- the semiconductor layer is promoted to have crystallinity on the top surface 213T of the bridge portion 213 in addition to the flat portion 214. Therefore, even if a part of the flat portion 214 is used as the bridge portion 213, it is possible to suppress the crystallinity of the semiconductor layer from being lowered due to this.
- a method for manufacturing a substrate for a semiconductor light emitting device includes: a particle arranging step of arranging a plurality of particles on a substrate; and dry etching the plurality of arranged particles under a condition that the particles are etched and the substrate is not substantially etched.
- a substrate etching step for forming the structure an etching step for the light emitting structure forming surface 11S).
- Etching process of the single-particle film F 1 may be carried out in essentially the same manner as in the first embodiment.
- a single particle film F 1 composed of a single layer of particles M 1 is formed on the light emitting structure forming surface 211S.
- the single particle film F 1 has a hexagonal packed structure of particles M 1 having a diameter R21.
- One hexagonal packing structure is composed of seven particle M 1.
- the hexagonal packed structure, six particles M 1 is arranged into six vertexes having a hexagonal, and the portion surrounded by six particles M 1, 1 single particles M 1 is filled. That is, in one hexagonal packing structure, the one around the particles M 1 as the center, six particles M 1 are arranged like.
- Hexagonal packing structure includes three particles M 1 arranged in three vertices with the triangles. Region surrounded by three particles M 1 when viewed from the normal direction of the substrate is the minimum clearance by a single-particle film F 1. When viewed from the normal direction of the substrate, the light emitting structure forming surface 211S has a first exposed portion S21 exposed to the outside through such a minimum gap.
- the particles M 1 constituting the single particle film F 1 are etched under the etching conditions in which the element substrate 211B is not substantially etched.
- the particle diameter of particles M 1 constituting the single particle film F 1 is reduced to the diameter R22 by selective etching.
- the light emitting structure forming surface 211S has a second exposed portion S22 that is exposed to the outside through such a new gap. That is, the second exposed surface S22 is newly formed around the first exposed surface S21, so that the first exposed surface S21 becomes one continuous exposed surface.
- the light-emitting structure forming surface 211S is substantially maintained etched, the same state as reduced diameter front of particles M 1.
- the etching conditions luminous structure forming surface 211S is not substantially etched, the ratio of the etching rate of the light emitting structure formed surface 211S to the etching rate of the particles M 1 is preferably 25% or less. Ratio of the etching rate of the light emitting structure formed surface 211S to the etching rate of the particles M 1 is preferably more preferably 15% or less, in particular 10% or less. In addition, what is necessary is just to select the etching gas used for reactive etching appropriately for such etching conditions.
- the element substrate 211B is sapphire, when the particle M 1 is silica, CF 4, SF 6, CHF 3, C 2 F 6, C 3 F 8, CH 2 F 2, O 2, NF
- One or more gases selected from the group consisting of 3 may be used as the etching gas.
- the light-emitting structure forming surface 211S are etched reduced diameter particles M 1 as a mask.
- the first exposed portion S21 through a gap surrounded by the three particles M 1 that are adjacent to each other, exposed to the plasma of the etching gas.
- the second exposed portion S22 through the gap between the two particles M 1 that are adjacent to each other, exposed to the plasma of the etching gas. Then, the particles M 1 constituting the single particle layer is also exposed to the plasma of the etching gas.
- a first exposure unit S21 the gap between the first first region 214 of the combined second exposed portion S22 located around the exposed section S21 has two mutually adjacent particles M 1
- the area is larger than the second region 213 in which the second exposed portions S22 are added. Therefore, the etching rate of the first region 214 is higher than the etching rate of the second region 213. Therefore, the etching of the first region 214 proceeds faster than the etching of the second region 213 on the light emitting structure forming surface 211S. Further, in the light-emitting structure forming surface 211S, the etching of the second region 213, progresses faster than the etching of the portion covered by the particles M 1.
- the etching rate in the second region 213 increases as the size of the second region 213 increases.
- a flat portion 214 is formed in the first region 214 as a deeply depressed portion on the light emitting structure forming surface 211S.
- a bridge portion 213 is formed in the second region 213 as a portion that is recessed shallower than the flat portion 214.
- a convex portion 212 having a hemispherical shape is formed as a portion other than the flat portion 214 and the bridge portion 213.
- the height of the bridge portion 213 decreases as the distance between the convex portions 212 connected by the bridge portion 213 increases.
- the interval between the convex portions 212 is 300 nm to 700 nm, in which case the height of the bridge Is 10 to 300 nm, and when the most frequent pitch is 400 nm, the interval between the convex portions 212 is 10 nm to 100 nm. In this case, the height of the bridge is 5 nm to 100 nm.
- the distance between the convex portions 212 and the height of the bridge change depending on the dry etching conditions including the combination of the material of the particle mask and the base material and the selection of gas, the above numerical values vary depending on the conditions.
- the magnitude of the second exposed portion S22 is changed, the light emitting structure forming face 211S of the etching step subsequent bridge is finally formed 213
- the height of will change.
- the etching rate of the single particle film F 1 is increased for etching process of the light emitting structure forming surface 211S.
- the etching rate of the particles M 1 is made slower to the light emitting structure forming surface 211S, the rate of extension of the second exposed portion S22 also becomes slower.
- the height of the bridge portion 213 increases.
- etching rate of the single particle film F 1 is used as an etching gas of the light-emitting structure forming surface 211S.
- the etching rate of the particles M 1 is closer to the light emitting structure forming surface 211S, the rate of extension of the second exposed portion S22, is even faster.
- the gas used in this case may be comprised from 1 type of gas, and may be comprised from 2 or more types of gas.
- the change in the height of the bridge portion 213, the height of the changing of the bridge section 213 by changing the above-mentioned etching gas may be combined. Even if the bridge portion is not actively produced (even when the height of the bridge portion is substantially zero), the effect of increasing the distance between the convex portions 212 by reducing the mask particle size as described above, LED As a result, it is possible to secure a larger area of the flat portion necessary for the film forming process, and to enable more efficient epitaxial crystal growth with less crystal defects. As a result, a semiconductor layer is formed on such a substrate. Thus, the benefit of improving the light emission efficiency of the semiconductor light emitting device manufactured in this manner can be obtained.
- Pitch of the convex portion 212 is equivalent to the spacing between the particles M 1 adjacent to each other, the arrangement of the protrusions 212 are also similar to the arrangement of the particles M 1.
- the arrangement of the bridge portion 213 is a line connecting the center of the particle M 1 adjacent to each other, the shape of the bridge portion 213 is a linear connecting the centers of the particles M 1 adjacent to each other.
- the membrane elements are stacked portion of the single particle film, Totsubudan TL2 is formed, portions hexagonal packed structure of particles M 1 are stacked, the projection Group TG2 is formed.
- the etching rate of the light emitting structure forming surface 211S is preferably higher than the etching rate of the particles M 1.
- Ratio of the etching rate of the light emitting structure formed surface 211S to the etching rate of the particles M 1 is preferably 200% or more, and more preferably 300% or less.
- the etching gas used for reactive etching appropriately for such etching conditions.
- a device substrate 211B sapphire when the particle M 1 are silica, Cl 2, BCl 3, SiCl 4, HBr, HI, one or more gases selected from the group consisting of HCl as an etching gas Use it.
- the semiconductor light emitting element 200 has an element substrate 211 ⁇ / b> B as a base material.
- the semiconductor light emitting device 200 has a light emitting structure 221 that covers the uneven structure of the light emitting structure forming surface 211S on the light emitting structure forming surface 211S of the device substrate 211B.
- the light-emitting structure 221 includes a stacked body including a plurality of semiconductor layers, and emits light by recombining carriers by supplying current. Each of the plurality of semiconductor layers is sequentially stacked from the light emitting structure forming surface 211S.
- the semiconductor light emitting device 200 can employ the same configuration as the semiconductor light emitting device described in the first embodiment.
- the semiconductor light emitting device 200 can be formed by the method described in the first embodiment. According to this embodiment, the following effects can be obtained.
- the convex portion group TG2 has a hexagonal filling structure and the bridge portion 213 is connected to each of the convex portions 212 constituting the hexagonal filling structure, the effect according to the above (1) is further enhanced.
- the arrangement of the convex portions 212 has randomness, the uniformity of the effect according to the above (1) is enhanced in the plane of the light emitting structure forming surface 211S.
- the top surface 213T of the bridge portion 213 is a crystal plane, the growth of the semiconductor layer due to the formation of the convex portion 212 is suppressed.
- one single particle film F 1 functions as a mask for forming the convex portion 212 and the flat portion 214 and a mask for forming the bridge portion 213.
- the number of steps required for manufacturing the element substrate 211B is smaller than a method in which a mask for forming the convex portion 212 and a mask for forming the bridge portion 213 are separately required. Less.
- this embodiment can also be changed and implemented as follows.
- the step of selectively etching the single particle film F 1 is omitted.
- the top surface 213 ⁇ / b> T of the bridge portion 213 may be a concave curved surface that is recessed toward the flat portion 214 when viewed from the direction intersecting the direction in which the bridge portion 213 is connected.
- the bridge part 213 should just be a part which has height lower than the height of the convex part 212, and connects some adjacent convex parts 212 to each other.
- the top surface 213 ⁇ / b> T of the bridge portion 213 is a concave curved surface that is recessed toward the flat portion 214 when viewed from the direction intersecting with the connecting direction of the bridge portion 213, and As shown on the right side of FIG. 15, it may be a convex curved surface protruding from the flat portion 214 when viewed from the continuous direction of the bridge portion 213.
- the top surface 213T of the bridge portion 213 may not be a crystal plane.
- the flat part 214 may be surrounded by four or more convex part pairs TP2. Further, the flat portion 214 may not be surrounded by the convex portion pair TP2.
- a structure in which two flat portions 214 sandwich one bridge portion 213 in a direction intersecting with a direction in which the bridge portions 213 are connected may be employed.
- the heights of the bridge portions 213 may be equal to each other.
- the substrate for a semiconductor light emitting device of this embodiment has a light emitting structure forming surface on which a light emitting structure including a semiconductor layer is formed, and the light emitting structure forming surface is a flat surface extending along one crystal plane.
- the two protrusions protruding from the flat part, and one bridge part protruding from the flat part the amount protruding from the flat part is more in the bridge part than the protrusion
- the two convex portions are connected by the one bridge portion, the most frequent pitch of the convex portions is 100 nm or more and 5 ⁇ m or less, and the aspect ratio of the plurality of convex portions is 0.5 to 1.. 0 may be sufficient.
- the substrate for a semiconductor light emitting device of this embodiment has a light emitting structure forming surface on which a light emitting structure including a semiconductor layer is formed, and the light emitting structure forming surface is a flat surface extending along one crystal plane.
- the two protrusions protruding from the flat part, and one bridge part protruding from the flat part, the amount protruding from the flat part is more in the bridge part than the protrusion
- the two convex portions are connected by the one bridge portion, the mode pitch of the convex portions is 100 nm or more and 1 ⁇ m or less, and the aspect ratio of the plurality of convex portions is 0.5 to 1.. There may be zero.
- the substrate for a semiconductor light emitting device of this embodiment has a light emitting structure forming surface on which a light emitting structure including a semiconductor layer is formed, and the light emitting structure forming surface is a flat surface extending along one crystal plane.
- the two protrusions protruding from the flat part, and one bridge part protruding from the flat part, the amount protruding from the flat part is more in the bridge part than the protrusion
- the two convex portions are connected by the one bridge portion, the mode pitch of the convex portions is 200 nm to 700 nm, and the aspect ratio of the multiple convex portions is 0.5 to 1.0. There may be.
- the substrate for a semiconductor light emitting device of this embodiment has a light emitting structure forming surface on which a light emitting structure including a semiconductor layer is formed, and the light emitting structure forming surface is a flat surface extending along one crystal plane.
- the two protrusions protruding from the flat part, and one bridge part protruding from the flat part the amount protruding from the flat part is more in the bridge part than the protrusion
- the two convex portions are connected by the one bridge portion, the most frequent pitch of the convex portions is 100 nm or more and 5 ⁇ m or less, and the aspect ratio of the plurality of convex portions is 0.5 to 1..
- the length along the longitudinal direction of the bridge portion may be 50 nm or more and 300 nm or less.
- the substrate for a semiconductor light emitting device of this embodiment has a light emitting structure forming surface on which a light emitting structure including a semiconductor layer is formed, and the light emitting structure forming surface is a flat surface extending along one crystal plane.
- the two convex portions are connected by the one bridge portion, the most frequent pitch of the convex portions is 100 nm or more and 5 ⁇ m or less, and the aspect ratio of the plurality of convex portions is 0.5 to 1.. 0 and the length along the short direction of the bridge portion may be 10 nm or more and 100 nm or less.
- the substrate for a semiconductor light emitting device of this embodiment has a light emitting structure forming surface on which a light emitting structure including a semiconductor layer is formed, and the light emitting structure forming surface is a flat surface extending along one crystal plane.
- the two convex portions are connected by the one bridge portion, the most frequent pitch of the convex portions is 100 nm or more and 5 ⁇ m or less, and the aspect ratio of the plurality of convex portions is 0.5 to 1.. 0, and the bridge portion height may be lower than half the height of the convex portion.
- the height of the bridge portion may be substantially zero.
- the exposed portion of the sapphire crystal c plane that can be the starting point of epitaxial growth is adjusted by increasing the distance between the two convex portions by reducing the particle size. By increasing the number, it is possible to perform high-quality film formation with a low crystal dislocation density in the LED film formation process, and to contribute to obtaining a highly efficient LED light-emitting element.
- the substrate for a semiconductor light emitting device of this embodiment is a substrate for a semiconductor light emitting device having a concavo-convex structure on one surface of the substrate, and the concavo-convex structure has a plurality of convex portions and a flat surface between the convex portions.
- the lattice orientation is random
- the aspect ratio of the large number of convex portions is 0.5 to 1.0
- the substrate for a semiconductor light emitting device of this embodiment is a substrate for a semiconductor light emitting device having a concavo-convex structure on one surface of the substrate, and the concavo-convex structure has a plurality of convex portions and a flat surface between the convex portions.
- the lattice orientation is random
- the aspect ratio of the large number of convex portions is 0.5 to 1.0
- bromine hexadecyltrimethylammonium bromide (surfactant) having a concentration of 50% by mass was added to this dispersion so as to have a concentration of 2.5 mmol / L and stirred for 30 minutes. Trimethylammonium was adsorbed. At this time, the dispersion and the brominated hexadecyltrimethylammonium were mixed so that the mass of brominated hexadecyltrimethylammonium was 0.04 times the mass of the colloidal silica particles.
- chloroform having the same volume as the volume of the dispersion was added to the dispersion and stirred sufficiently to extract the hydrophobized colloidal silica from the oil phase.
- hydrophobized colloidal silica dispersion having a concentration of 1.5% by mass is provided with a surface pressure sensor for measuring the surface pressure of the single particle film, and a movable barrier for compressing the single particle film in the direction along the liquid surface.
- a surface pressure sensor for measuring the surface pressure of the single particle film
- a movable barrier for compressing the single particle film in the direction along the liquid surface.
- ultrasonic waves (output 120W, frequency 1.5MHz) are radiated from the lower layer water to the water surface to promote the two-dimensional close-packing of particles and volatilize chloroform, which is the solvent of the dispersion.
- this single particle film is compressed by a movable barrier until the diffusion pressure becomes 18 mNm ⁇ 1 , the sapphire wafer is pulled up at a rate of 5 mm / min, the single particle film is transferred onto one side of the substrate, and a single particle made of colloidal silica is used.
- a sapphire wafer with a particle film etching mask was obtained.
- Dry etching for reducing the particle size of the single particle film etching mask made of colloidal silica on the sapphire wafer thus obtained was performed. Specifically, SiO 2 particles having an initial average particle size of 3.02 ⁇ m and a processed average particle size of 2.80 ⁇ m are obtained with CF 4 gas under the conditions of an antenna power of 1500 W, a bias of 80 W, and a pressure of 5 Pa. So reduced. Then, the dry etching which processes the sapphire wafer which is a base material was performed.
- the SiO 2 mask / sapphire substrate was dry-etched with Cl 2 gas under the conditions of an antenna power of 1500 W, a bias of 300 W, a pressure of 1 Pa, and an etching chamber temperature of 80 to 110 ° C.
- the sapphire substrate for a semiconductor light-emitting element having a concavo-convex structure composed of a flat bridge portion is obtained.
- Each GaN-based semiconductor layer was formed by a generally used MOCVD (Metal Organic Chemical Vapor Deposition) method.
- MOCVD Metal Organic Chemical Vapor Deposition
- an ammonia gas and an alkyl compound gas such as group III elements such as trimethyl gallium, trimethyl ammonium, and trimethyl indium are supplied to a sapphire substrate in a temperature environment of 700 ° C. to 1000 ° C. to cause a thermal decomposition reaction.
- a target crystal is formed by epitaxial growth.
- the structure of the n-type semiconductor layer is as follows: Al 0.9 Ga 0.1 N as a low-temperature growth buffer layer is 15 nm, undoped GaN is 4.5 ⁇ m, Si-doped GaN is 3 ⁇ m as an n-clad layer, and 250 nm of undoped GaN are sequentially stacked. did.
- multiple quantum wells that improve the internal quantum efficiency are formed by sandwiching several layers with a narrow band gap.
- undoped In 0.15 Ga 0.85 N Quantum well layer
- Si-doped GaN barrier layer
- the layers were stacked so that N was 9 layers and Si-doped GaN was 10 layers.
- As the p-type semiconductor layer 15 nm of Mg-doped AlGaN, 200 nm of undoped GaN, and 15 nm of Mg-doped GaN were stacked.
- the Mg-doped GaN of the p-type semiconductor layer which is the outermost layer, to the undoped GaN of the n-type semiconductor layer were etched away to expose the Si-doped GaN layer.
- An n electrode made of Al and W was formed on the exposed surface, and an n pad electrode made of Pt and Au was formed on the n electrode.
- a p electrode made of Ni and Au was formed on the entire surface of the p-type semiconductor layer, and a p pad electrode made of Au was formed on the p electrode.
- a bare chip semiconductor element (the size of one element is 300 ⁇ m ⁇ 350 ⁇ m) was formed.
- a photoresist is spin-coated on a sapphire substrate having a diameter of 2 inches and a thickness of 0.42 mm at a thickness of 750 nm. After a mask having a pitch of 3 ⁇ m is drawn by a laser lithography method, fine processing by dry etching is performed. A sapphire substrate for a semiconductor light-emitting element having an uneven structure constituted by a mode pitch of 3 ⁇ m, a structure height of 1.5 ⁇ m, and a flat portion distance of 0.4 ⁇ m was obtained.
- n-type semiconductor layer, an active layer, and a p-type semiconductor layer having the same structure as in Example 1 were sequentially stacked on the concavo-convex structure surface of the sapphire substrate for a semiconductor light-emitting device thus obtained, and then a p-electrode and an n-electrode were formed.
- a semiconductor light emitting device (the size of one device is 300 ⁇ m ⁇ 350 ⁇ m) was completed.
- n-type semiconductor layer, an active layer, and a p-type semiconductor layer having the same structure as in Example 1 were sequentially stacked on the concavo-convex structure surface of the sapphire substrate for a semiconductor light-emitting device thus obtained, and then a p-electrode and an n-electrode were formed.
- a semiconductor light emitting device (the size of one device is 300 ⁇ m ⁇ 350 ⁇ m) was completed.
- a photoresist is spin-coated at a thickness of 100 nm on a sapphire substrate having a diameter of 2 inches and a thickness of 0.42 mm.
- a sapphire substrate for a semiconductor light emitting device having a concavo-convex structure composed of a mode pitch of 300 nm, a structure height of 150 nm, and a flat portion distance of 40 nm was obtained.
- n-type semiconductor layer, an active layer, and a p-type semiconductor layer having the same structure as in Example 1 were sequentially stacked on the concavo-convex structure surface of the sapphire substrate for a semiconductor light-emitting device thus obtained, and then a p-electrode and an n-electrode were formed.
- a semiconductor light emitting device (the size of one device is 300 ⁇ m ⁇ 350 ⁇ m) was completed.
- In-plane radial anisotropy (total area surrounded by curve and straight line) / (average value x 360 degrees)
- a semiconductor light emitting device having a large numerical value of in-plane radiation anisotropy exhibits radiation characteristics with high anisotropy and low uniformity with respect to radiation in the in-plane direction.
- a semiconductor light emitting device having a small numerical value of in-plane radiation anisotropy exhibits radiation characteristics with low anisotropy and high uniformity with respect to radiation in the in-plane direction.
- the flat portion distance indicates an average value of the widths of the flat surfaces existing between the center points of the adjacent convex portions.
- Example 1 and Example 2 low in-plane radiation anisotropy was confirmed.
- Comparative Example 1 produced by the photolithography method
- Comparative Example 2 produced by the interference exposure method. From this, according to the present invention, it was found that sufficient light extraction efficiency and low in-plane radiation anisotropy can be obtained by a simpler method than the conventional method.
- a sapphire substrate for a semiconductor light emitting device having an uneven structure composed of 3 ⁇ m, a structure height of 1.5 ⁇ m, and a flat portion distance of 0.4 ⁇ m was obtained. Further, when 20 sampling positions were extracted from the central portion and the outer peripheral portion of the substrate, and the shape of the convex portion was measured to obtain the variation coefficient H ′, values of 1.77 and 2.12 were obtained, respectively.
- n-type semiconductor layer, an active layer, and a p-type semiconductor layer having the same structure as in Example 1 were sequentially stacked on the concavo-convex structure surface of the sapphire substrate for a semiconductor light-emitting device thus obtained, and then a p-electrode and an n-electrode were formed.
- a semiconductor light emitting device (the size of one device is 300 ⁇ m ⁇ 350 ⁇ m) was completed.
- n-type semiconductor layer, an active layer, and a p-type semiconductor layer having the same structure as in Example 1 were sequentially stacked on the concavo-convex structure surface of the sapphire substrate for a semiconductor light-emitting device thus obtained, and then a p-electrode and an n-electrode were formed.
- a semiconductor light emitting device (the size of one device is 300 ⁇ m ⁇ 350 ⁇ m) was completed.
- Example 4 Fine processing by the particle mask method is performed in the same manner as in Example 2 except that a sialic substrate having a TTV of 5.89 ⁇ m, a WARP of 18.78 ⁇ m, and a
- the coefficient of variation H ′ of the convex part at the central part and the outer peripheral part of the substrate was 2.51 and 2.68, respectively.
- n-type semiconductor layer, an active layer, and a p-type semiconductor layer having the same structure as in Example 1 were sequentially stacked on the concavo-convex structure surface of the sapphire substrate for a semiconductor light-emitting device thus obtained, and then a p-electrode and an n-electrode were formed.
- a semiconductor light emitting device (the size of one device is 300 ⁇ m ⁇ 350 ⁇ m) was completed.
- a circular mask having a pitch of 300 nm is drawn by an electron beam lithography method in the same manner as in Comparative Example 2 except that a sire substrate having a TTV of 5.56 ⁇ m, a WARP of 18.57 ⁇ m, and a
- the coefficient of variation H ′ of the convex portion at the central portion of the substrate and the outer peripheral portion was 5.09 and 10.13, respectively.
- An n-type semiconductor layer, an active layer, and a p-type semiconductor layer having the same structure as in Example 1 were sequentially stacked on the concavo-convex structure surface of the sapphire substrate for a semiconductor light-emitting device thus obtained, and then a p-electrode and an n-electrode were formed.
- a semiconductor light emitting device (the size of one device is 300 ⁇ m ⁇ 350 ⁇ m) was completed.
- Comparative Example 3 produced by the photolithography method and Comparative Example 4 produced by the interference exposure method, it was confirmed that there was a large difference in the above numerical values between the in-plane center portion and the outer peripheral portion. Therefore, according to Examples 3 and 4, the concavo-convex structure with high accuracy even when a relatively flat substrate having TTV of 5 ⁇ m to 30 ⁇ m, WARP of 10 ⁇ m to 50 ⁇ m, and
- n-type semiconductor layer, an active layer, and a p-type semiconductor layer having the same structure as in Example 1 were sequentially stacked on the concavo-convex structure surface of the sapphire substrate for a semiconductor light-emitting device thus obtained, and then a p-electrode and an n-electrode were formed.
- a semiconductor light emitting device (the size of one device is 300 ⁇ m ⁇ 350 ⁇ m) was completed.
- a photoresist is spin-coated on a sapphire substrate having a diameter of 2 inches and a thickness of 0.42 mm at a thickness of 300 nm, a mask having a pitch of 1 ⁇ m is drawn by laser lithography, and fine processing by dry etching is performed.
- n-type semiconductor layer, an active layer, and a p-type semiconductor layer having the same structure as in Example 1 were sequentially stacked on the concavo-convex structure surface of the sapphire substrate for a semiconductor light-emitting device thus obtained, and then a p-electrode and an n-electrode were formed.
- a semiconductor light emitting device (the size of one device is 300 ⁇ m ⁇ 350 ⁇ m) was completed.
- Example 5 since the bridge portion is provided in the fine structure, the external quantum efficiency is about 10% higher than that in Comparative Example 5 without the bridge portion. In Example 5, it is interpreted that the light confined in the waveguide mode inside the LED element is scattered and extracted from the light extraction surface because of the bridge portion. On the other hand, in Comparative Example 5 without a bridge portion, the external quantum efficiency is inferior because there is no light extraction effect described above.
- a substrate for a semiconductor light-emitting element which is less likely to cause crystal defects in a semiconductor layer by a simple technique, provides sufficient light extraction efficiency, and prevents color shift.
- 11 semiconductor light-emitting device substrate, C 1 ... area, c11 ... protrusion, f11 ... flat surface, t11 ... center point, S 1 ... substrate, M 1 ... particles, F 1 ... single particle film, W 1 ... lower water , V 1, water tank, S 21, first exposed portion, S 22, second exposed portion, TP 2, convex portion pair, TG 2, convex portion group, TL 2, convex portion group, 211 B, element substrate, 211 S, light emitting structure.
Abstract
Description
本願は、2012年8月21日に、日本に出願された特願2012-182302号及び2013年6月14日に、日本に出願された特願2013-126025号に基づき優先権を主張し、その内容をここに援用する。
この発光構造体を支持する半導体発光素子用基板は、サファイア、炭化珪素、あるいは、シリコンなどから形成されて、発光構造体を構成する半導体層などよりも、通常、低い屈折率を有している。
発光構造体の生成する光の一部は、半導体発光素子用基板と発光構造体との間の屈折率の差異に従い、半導体発光素子用基板と発光構造体との間で全反射を繰り返す。結果として、発光構造体の生成する光は、発光構造体の内部で減衰してしまう。
この問題を解決するため、基板に予め凹凸構造を形成してから半導体層を積層することにより、前記凹凸状基板の凹凸構造を利用して光の角度を変えて全反射を抑制し、光取り出し効率を向上させる方法が種々提案されている(特許文献1~3、非特許文献1)。
また、特許文献3では、基板上に配置した無機粒子をエッチングマスクとして前記基板をドライエッチングすることで基板上に凹凸構造を形成し、その後この凹凸構造上に半導体層を形成することが提案されている。特許文献3において、基板上に無機粒子を配置する好ましい方法として、無機粒子を水等の媒体に分散させたスラリーを用いて、前記スラリー中へ前記基板を浸漬させるかまたは、前記スラリーを前記基板上に塗布あるいは噴霧した後に乾燥させる方法が提案されている。また、良好な半導体層を形成するために、無機粒子は90%以下の被覆率で基板に配置されるべきであるとされている。
また、非特許文献1では、基板上に形成する凹凸構造のピッチと、光取り出し効率の向上効果との関係について検討がなされている。そして、1000nmピッチの凹凸構造では、殆ど光取り出し効率の向上効果が得られなかったのに対して、500nmピッチの凹凸構造によって、平坦な基板の場合と比べて170%の光取り出し効率が得られたことが記載されている。
なお、ピッチが1μm以下の凹凸構造を有する微細構造体の作製方法としては、従来電子線描画法や干渉露光法などが知られている。
一方で、それゆえに、発光構造体の生成した光の取り出される効率を高める点では、上述された微細な凹凸構造でも、依然として改善の余地が残されている。
また、回折光の影響により、半導体発光素子にカラーシフトや、見る角度によって放射強度が異なる(面内異方性が高い)問題が発生することがあった。
そのため、従来のフォトリソグラフィーによる半導体発光素子用基板の作製においては、平坦性の高い基板を用いなければならなかった。しかし、平坦性の高い基板、特に平坦性の高いサファイア基板は、高度な研磨技術がなければ得られないため、非常に高価であるという問題があった。
すなわち、電子線描画法は1インチの描画に約2週間を要するほど描画速度が遅く、大面積の基板の加工には、非常にコストと時間がかかる。また、大面積を長時間掛けて描画する間の環境(電圧、振動、気温等)を一定に保つことが難しく、均質な微細構造体の作製が難しい。
また、干渉露光法では、光源にガウシアンビームを使用しており、露光対象の面積が大きくなると中央部と周辺部での適正露光時間が異なることとなる。また、振動(地面や建物の振動、空気の振動など)に弱く、露光時間中に少しでも振動が加わると像がぶれて解像度が低下する。そのため、均質な微細構造体を大面積で作製することは難しい。
電子線描画装置や干渉露光法は、必要な装置が大がかりであり、高価であることも、工業的実施を妨げる要因となっている。
さらに、本発明者が検討した結果、仮に部分的な重なりを避けたとしても、無機粒子同士が接触した箇所が多数生じ、その部分の基板は、断面が略逆三角形状にエッチングされることが分かった。基板上での半導体層のエピタキシャル成長には、凹部に平坦な底面が存在することが必要である。そのため、特許文献3の方法では、半導体層に結晶欠陥が発生する懸念があった。
また、本発明の他の態様は、結晶欠陥が少ない半導体層を形成することができ、上記課題を解決する半導体発光素子の製造に好適な半導体発光素子用基板を提供することを課題とする。
また、本発明のさらに他の態様は、上記課題を解決する半導体発光素子用基板を製造でき、簡便な手法で、低コストかつ短時間でピッチが1μm以下の凹凸構造も形成できる半導体発光素子用基板の製造方法を提供することを課題とする。
また、本発明のさらに他の態様は、上記課題を解決する半導体発光素子用基板の製造方法を用いることにより、上記課題を解決する半導体発光素子を製造できる半導体発光素子の製造方法を提供することを課題とする。
[1] 基板に下記式(1)で定義される配列のずれD(%)が15%以下となるように、複数の粒子を単一層で配列させる粒子配列工程と、
前記粒子がエッチングされ、前記基板が実質的にエッチングされない条件で、前記配列した複数の粒子をドライエッチングして粒子間に間隙を設ける粒子エッチング工程と、
前記粒子エッチング工程後の複数の粒子をエッチングマスクとして前記基板をドライエッチングし、前記基板の一方の面に凹凸構造を形成する基板エッチング工程を備えることを特徴とする半導体発光素子用基板の製造方法。
D[%]=|B-A|×100/A・・・(1)
但し、式(1)中、Aは粒子の平均粒径、Bは粒子間の最頻ピッチである。また、|B-A|はAとBとの差の絶対値を示す。
[2] 前記粒子配列工程が、水槽内の水の液面に水よりも比重が小さい溶剤中に粒子が分散した分散液を滴下する滴下工程と、前記溶剤を揮発させることにより前記粒子からなる単粒子膜を水の液面上に形成する単粒子膜形成工程と、前記単粒子膜を基板に移し取る移行工程とを有する[1]に記載の半導体発光素子用基板の製造方法。
[3] 前記粒子間の最頻ピッチが5μm以下である[1]または[2]に記載の半導体発光素子用基板の製造方法。
[4] 前記粒子間の最頻ピッチが1μm以下である[1]または[2]に記載の半導体発光素子用基板の製造方法。
[5] 前記粒子間の最頻ピッチが200nm~700nmである[1]または[2]に記載の半導体発光素子用基板の製造方法。
[6] 前記基板がサファイアであり、前記粒子がシリカであり、前記粒子エッチング工程が、エッチングガスとしてCF4、SF6、CHF3、C2F6、C3F8、CH2F2、O2、およびNF3からなる群から選択される少なくとも1種のガスを用いる工程であり、前記基板エッチング工程が、エッチングガスとしてCl2、Br2、BCl3、SiCl4、HBr、HI、HCl、およびArからなる群から選択される少なくとも1種のガスを用いる工程である[1]~[5]のいずれか一項に記載の半導体発光素子用基板の製造方法。
[7] 基板に複数の粒子を単一層で配列させる粒子配列工程と、
前記粒子がエッチングされ、前記基板が実質的にエッチングされない条件で、前記配列した複数の粒子をドライエッチングして粒子間に間隙を設ける粒子エッチング工程と、
前記粒子エッチング工程後の複数の粒子をエッチングマスクとして前記基板をドライエッチングし、前記基板の一方の面に凹凸構造を形成する基板エッチング工程を備え、
前記基板がサファイアであり、前記粒子がシリカであり、前記粒子エッチング工程が、エッチングガスとしてCF4、SF6、CHF3、C2F6、C3F8、CH2F2、O2、およびNF3からなる群から選択される少なくとも1種のガスを用いる工程であり、前記基板エッチング工程が、エッチングガスとしてCl2、Br2、BCl3、SiCl4、HBr、HI、HCl、およびArからなる群から選択される少なくとも1種のガスを用いる工程であることを特徴とする半導体発光素子用基板の製造方法。
[8] 前記粒子配列工程が、水槽内の水の液面に水よりも比重が小さい溶剤中に粒子が分散した分散液を滴下する滴下工程と、前記溶剤を揮発させることにより前記粒子からなる単粒子膜を水の液面上に形成する単粒子膜形成工程と、前記単粒子膜を基板に移し取る移行工程とを有する[7]に記載の半導体発光素子用基板の製造方法。
[9] 前記基板のASTM F657で規定される最大厚み及び最小厚みの間の絶対差(TTV)が5μm~30μm、ASTM F1390規定される基準面からのズレの最大値と最小値の差(WARP)が10μm~50μm、ASTM F534.3.1.2で規定される基板の中心部での基準面からの隔たりの絶対値(|BOW|)が10μm~50μmである[1]~[8]のいずれか一項に記載の半導体発光素子用基板の製造方法。
[10] 基板の上面に複数の粒子を単一層で配列させて単粒子膜を形成する粒子配列工程と、
前記粒子がエッチングされ、前記基板が実質的にエッチングされない条件で、前記配列した複数の粒子をドライエッチングして粒子間に間隙を設ける粒子エッチング工程と、
前記単粒子膜をマスクにして前記上面をエッチングする基板エッチング工程と、を含み、
前記基板エッチング工程では、
前記粒子エッチング工程後に前記基板の上面において露出している領域に段差を形成する半導体発光素子用基板の製造方法。
[11] 前記粒子エッチング工程では、前記複数の粒子の各々を縮小する[10]に記載の半導体発光素子用基板の製造方法。
[12] 前記基板エッチング工程において、
複数の粒子のうち、2つの粒子の間の隙間が大きいほど、前記段差が小さくなる[10]または[11]に記載の半導体発光素子用基板の製造方法。
[13] 前記粒子配列工程では、前記複数の粒子をLB法によって配列する[12]に記載の半導体発光素子用基板の製造方法。
[14] [10]から[13]のいずれか1つに記載の半導体発光素子用基板の製造方法によって半導体発光素子用基板を形成する工程と、
前記半導体発光素子用基板にて前記段差が形成された前記上面に、半導体層を含む発光構造体を形成する工程と、を含む半導体発光素子の製造方法。
[15][1]~[14]のいずれか一項に記載の製造方法により半導体発光素子用基板を得る工程と、得られた半導体発光素子用基板の凹凸構造が形成された面に、少なくとも発光層を含む半導体機能層を積層する工程を備える半導体発光素子の製造方法。
[16] 基板の一方の面に凹凸構造を有する半導体発光素子用基板であって、
前記凹凸構造は、多数の凸部と各凸部の間の平坦面とを有し、
かつ、隣接する7つの凸部の中心点が正六角形の6つの頂点と対角線の交点となる位置関係で連続して整列しているエリアを複数備え、
前記複数のエリアの面積、形状及び格子方位がランダムである半導体発光素子用基板。
[17] 前記凹凸構造の最頻ピッチが5μm以下であり、前記多数の凸部のアスペクト比が0.5~1.0である[16]に記載の半導体発光素子用基板。
[18] 前記凹凸構造の最頻ピッチが1μm以下であり、前記多数の凸部のアスペクト比が0.5~1.0である[16]に記載の半導体発光素子用基板。
[19] 前記凹凸構造の最頻ピッチが200nm~700nmであり、前記多数の凸部のアスペクト比が0.5~1.0である[16]に記載の半導体発光素子用基板。
[20] 前記凸部間を連結するブリッジ部を更に備える[16]から[19]のいずれか1つに記載の半導体発光素子用基板。
[21]前記基板がサファイアである[16]~[20]のいずれか一項に記載の半導体発光素子用基板。
[22][16]~[20]のいずれか一項に記載の半導体発光素子用基板と、前記半導体発光素子用基板上に積層された半導体機能層を備え、前記半導体機能層は少なくとも発光層を含む半導体発光素子。
[23]前記半導体機能層の光取出し側に、前記発光層から出射される発光を、前記発光の波長より長波長側に波長変換する波長変換層を備える[22]に記載の半導体発光素子。
[24]前記波長変換層が、ピーク波長410nm~483nmの蛍光を発する青色蛍光体、ピーク波長490nm~556nmの蛍光を発する緑色蛍光体、およびピーク波長585nm~770nmの蛍光を発する赤色蛍光体を含有する[23]に記載の半導体発光素子。
[25]前記波長変換層がピーク波長570nm~578nmの蛍光を発する黄色蛍光体を含有する[24]に記載の半導体発光素子。
また、本発明のいくつかの態様によれば、結晶欠陥が少ない半導体層を形成することができ、上記課題を解決する半導体発光素子の製造に好適な半導体発光素子用基板を提供できる。
また、本発明のいくつかの態様は、上記課題を解決する半導体発光素子用基板を製造でき、簡便な手法で、低コストかつ短時間でピッチが1μm以下の凹凸構造も形成できる半導体発光素子用基板の製造方法を提供できる。
また、本発明のいくつかの態様は、上記課題を解決する半導体発光素子用基板の製造方法を用いることにより、上記課題を解決する半導体発光素子を製造できる半導体発光素子の製造方法を提供できる。
<半導体発光素子用基板>
図1、2を用いて、本発明の一実施形態に係る半導体発光素子用基板11について説明する。図1に示すように、半導体発光素子用基板11は基板の一方の面に凹凸構造を有している。
図1におけるt11~t1nは各凸部c11~c1nの中心点である。AFM(原子間力顕微鏡)の測定結果に基づき、基準面と平行に各凸部について20nm毎に複数の等高線を引き、各等高線の重心点(x座標とy座標で決定される点)を求める。これらの各重心点の平均位置(各x座標の平均とy座標の平均で決定される位点)が、前記凸部の中心点である。
図1におけるm11~m1nは、AFMで求めた隣接する中心点の中点である。また、平坦面f11~f1nは、AFMの測定結果に基づき、その領域内の中点における表面高さと、その領域内における任意の点の表面高さとを結ぶ直線の、AFMの基準面に対する傾きが±10゜以下である領域である。
各平坦面の周辺と各中点との距離が好ましい下限値以上であれば、充分な平坦面の面積が確保され、基板上でに半導体層を安定してエピタキシャル成長させやすい。また、各平坦面の周辺と各中点との距離が好ましい上限値以下であれば、充分な密度で凸部を形成して、光取り出し効率向上の効果を得やすい。
また、各平坦面f11~f1nは、以下のような配置となるように凸部c11~c1nを形成する。凸部c11~c1nの頂点を通り、基板に垂直な断面、即ち図1に示す断面で見たときの平坦面f11~f1nの長さが、凸部c11~c1nのうちの隣り合う二つの凸部の頂点同士を結ぶ直線に対し、5%~40%、好ましくは15%~25%となるよう凸部c11~c1nが形成される。
凹凸構造の最頻ピッチPは、100nm~5μmが好ましく、100nm~1μmがより好ましく、200nm~700nmの範囲がさらに好ましく、300nm~600nmの範囲が特に好ましい。最頻ピッチPが好ましい範囲内であれば、光の全反射を防止しやすい。特に、最頻ピッチPが1μm以下であると、青~紫外の光取り出し効率をより効果的に高めることが可能である。そのため、GaNやInGaNなどの成膜を行って発光波長が青~紫外の領域の半導体発光素子に使用する基板の凹凸構造として好適である。
まず、凹凸面における無作為に選択された領域で、一辺が最頻ピッチPの30~40倍の正方形の領域における基板面と平行な面をAFM基準面とし、当前記正方形の領域について、AFMイメージを得る。例えば、最頻ピッチが300nm程度の場合、9μm×9μm~12μm×12μmの領域のイメージを得る。そして、このイメージをフーリエ変換により波形分離し、FFT像(高速フーリエ変換像)を得る。ついで、FFT像のプロファイルにおける0次ピークから1次ピークまでの距離を求める。こうして求められた距離の逆数がこの領域における最頻ピッチPである。このような処理を無作為に選択された合計25カ所以上の同面積の領域について同様に行い、各領域における最頻ピッチを求める。こうして得られた25カ所以上の領域における最頻ピッチP1~P25の平均値が最頻ピッチPである。なお、この際、各領域同士は、少なくとも1mm離れて選択されることが好ましく、より好ましくは5mm~1cm離れて選択される。
最頻高さHが好ましい範囲内であれば、その後成膜される窒化化合物の成膜欠陥が低減され、更には光の全反射を防止し、光取り出し効率を改善することができる。
凸部の最頻高さHは、具体的には次のようにして求められる。
まず、AFMイメージから、任意の方向と位置における長さ1mmの線に沿った凸部c11~c1nの頂点を通り、基板に垂直な断面、即ち図1のような断面を得る。この断面の凸部が30個以上含まれる任意の部分を抽出し、その中に含まれる各凸部について、その頂点の高さと、当前記凸部に隣接する凸部との間の平坦部における最も低い位置の高さとの差を求める。得られた値を有効桁数2桁で丸め各凸部の高さとし、その最頻値を最頻高さHとする。
各エリアC11~C1nは、隣接する7つの凸部の中心点が正六角形の6つの頂点と対角線の交点となる位置関係で連続して整列している領域である。なお、図2では、各凸部の中心点の位置を、便宜上、その中心点を中心とする円u1で示している。円u1は、図1に示すように、各凸部だけでなく、その周辺の平坦面を含む領域に相当する。
本実施形態において、隣接する7つの凸部の中心点が正六角形の6つの頂点と対角線の交点となる位置関係とは、具体的には、以下の条件を満たす関係をいう。
まず、1つの中心点t11から、隣接する中心点t12の方向に長さが最頻ピッチPと等しい長さの線分L1を引く。次いで中心点t11から、線分L1に対して、60゜、120゜、180゜、240゜、300゜の各方向に、最頻ピッチPと等しい長さの線分L2~L6を引く。中心点t11に隣接する6つの中心点が、中心点t11と反対側における各線分L1~L6の終点から、各々最頻ピッチPの15%以内の範囲にあれば、これら7つの中心点は、正六角形の6つの頂点と対角線の交点となる位置関係にある。
最頻ピッチPが500nm未満の時、10mm×10mmのAFMイメージ測定範囲内における最頻面積Qは、0.026μm2~6.5mm2であることが好ましい。
最頻ピッチPが500nm以上1μm未満の時、10mm×10mmのAFMイメージ測定範囲内における最頻面積Qは、0.65μm2~26mm2であることが好ましい。
最頻ピッチPが1μm以上の時、50mm×50mmのAFMイメージ測定範囲内における最頻面積Qは、2.6μm2~650mm2であることが好ましい。
最頻面積Qが好ましい範囲内であれば、光のカラーシフトや面内異方性が高くなる問題を防止しやすい。
面積のランダム性の度合いは、具体的には、以下の条件を満たすことが好ましい。
まず、ひとつのエリアの境界線が外接する最大面積の楕円を描き、その楕円を下記式(α)で表す。
X2/a2+Y2/b2=1・・・・・・(α)
最頻ピッチPが500nm未満の時、10mm×10mmのAFMイメージ測定範囲内におけるπabの標準偏差は、0.08μm2以上であることが好ましい。
最頻ピッチPが500nm以上1μm未満の時、10mm×10mmのAFMイメージ測定範囲内におけるπabの標準偏差は、1.95μm2以上であることが好ましい。
最頻ピッチPが1μm以上の時、50mm×50mmのAFMイメージ測定範囲内におけるπabの標準偏差は、8.58μm2以上であることが好ましい。
πabの標準偏差が好ましい範囲内であれば、回折光の平均化の効果が優れる。
また各エリアC11~C1nの格子方位のランダム性は、具体的には、以下の条件を満たすことが好ましい。
まず、任意のエリア(I)における任意の隣接する2つの凸部の中心点を結ぶ直線K0を画く。次に、前記エリア(I)に隣接する1つのエリア(II)を選択し、そのエリア(II)における任意の凸部と、その凸部に隣接する6つの凸部の中心点を結ぶ6本の直線K1~K6を画く。直線K1~K6が、直線K0に対して、いずれも3度以上異なる角度である場合、エリア(I)とエリア(II)との格子方位が異なる、と定義する。
エリア(I)に隣接するエリアの内、格子方位がエリア(I)の格子方位と異なるエリアが2以上存在することが好ましく、3以上存在することが好ましく、5以上存在することがさらに好ましい。
FFT基本波の最大値と最小値の比が大きい凹凸構造は、格子方位が揃っており、凹凸構造を2次元結晶とみなした場合単結晶性が高い構造配置と言える。反対に、FFT基本波の最大値と最小値の比が小さい凹凸構造は、格子方位が揃っておらず、凹凸構造を2次元結晶とみなした場合は多結晶構造のような配置であると言える。
また、半導体発光素子においてカラーシフトが発生することも防止できる。カラーシフトは見る角度によっては色が異なる現象である。たとえば、光が蛍光体により波長変換されたのち素子内で光が再び半導体発光素子用基板11の凹凸構造による回折を行う場合(上面に反射電極を設け3原色蛍光体により紫外光を白色に変換するボトムエミッション型の白色LEDなど)、回折光が元のスペクトルに重なり、特定の波長が強められる結果生じる。
上記好ましい範囲のFFT基本波の最大値と最小値の比を有する凹凸構造であれば、回折光の出射する角度が偏らないようにできるため、カラーシフトを抑制できる。
本実施形態の半導体発光素子用基板の製造方法は、基板に複数の粒子を配列させる粒子配列工程と、前記粒子がエッチングされ、前記基板が実質的にエッチングされない条件で、前記配列した複数の粒子をドライエッチングして粒子間に間隙を設ける粒子エッチング工程と、前記粒子エッチング工程後の複数の粒子をエッチングマスクとして前記基板をドライエッチングし、前記基板の一方の面に凹凸構造を形成する基板エッチング工程とを備える。
以下、本実施形態の半導体発光素子用基板の製造方法に用いる基板(加工前基板)について説明した後、各工程を図3A~図3Dに添って順次説明する。なお、図3A~図3Dでは、説明の便宜上、粒子Mと基板Sに形成される凹凸を極端に拡大している。
基板の材質としては、サファイア、SiC、Si、MgAl2 O4 、LiTaO3 、LiNbO3 、ZrB2 、GaAs、GaP、GaN、AlN 、AlGaN、InP、InSn、InAlGaN、又はCrB2 等の材料から成る板材を用いることができる。中でも、機械的安定性、熱安定性、光学安定性、化学的安定性、また光透過性を有する点で、サファイアが好ましい。
具体的には、ASTM F657で規定される最大厚み及び最小厚みの間の絶対差(TTV)が5μm~30μm、ASTM F1390規定される基準面からのズレの最大値と最小値の差(WARP)が10μm~50μm、ASTM F534.3.1.2で規定される基板の中心部での基準面からの隔たりの絶対値(|BOW|)が10μm~50μmである基板を使用しても、下式(3)を満たす半導体発光素子用基板を得ることができる。
ここで、H’は凹凸構造の高さの変動係数、Pは本実施形態により基板に形成される凹凸構造の最頻ピッチ(μm)である。
変動係数H’は一般的に次のようにして求められる。まず、最頻高さHを前述のように求め、次に平均値μ=ΣH/n(ΣH:データ数の総和、n=データ数)、ならびに標準偏差σ=((Σ(H-μ)^2)/n)^(1/2)を求めた後に、変動係数H’=σ/μ×100が求められる。また、最頻ピッチPの求め方は、前述の通りである。本実施形態については、各ピッチにつき変動係数を求めた後に、縦軸に変動係数、横軸にピッチをとることで、経験式(3)を得た。
半導体発光素子用基板の凹凸構造が式(3)を満たせば、その後成膜される窒化化合物の成膜欠陥が低減され、さらには光の全反射を防止し、光取り出し効率を改善することが可能となる。成膜欠陥が低減される条件としては、変動係数H’が10%以下の条件であることが好ましく、5%以下であることがより好ましく、3%以下であることがさらに好ましい。本実施形態では、TTVが5μm~30μm、WARPが10μm~50μm、|BOW|が10μm~50μmの範囲内における平坦性の低い基板を使用しても、式(3)が基板全面について、常に成り立つことを見出している。一方、従来法であるフォトリソグラフィー法による半導体発光素子基板によれば、マスクとして用いるフォトレジストの厚さにもよるが、基板全面において、上記TTV、WARP、|BOW|の範囲において、変動係数H’を10%以下にすることは困難である。
粒子配列工程では、図3Aに示すように、基板S1の一方の面である平坦面Xに複数の粒子M1を単一層で配列させる。すなわち、粒子M1の単粒子膜を形成する。
粒子M1は無機粒子であることが好ましいが、条件によっては有機高分子材料なども使用できる。無機粒子であれば、粒子エッチング工程において基板Mが実質的にエッチングされない条件で容易にエッチングできる。
無機粒子としては、例えば、酸化物、窒化物、炭化物、硼化物、硫化物、セレン化物及び金属等の化合物からなる粒子および金属粒子等を使用することができる。有機粒子としては、ポリスチレン、PMMA等の熱可塑性樹脂、フェノール樹脂、エポキシ樹脂等の熱硬化性樹脂等が使用可能である。
窒化物として用いることができるものとしては、窒化珪素、窒化アルミニウム、窒化硼素等が挙げられ、さらに、これらの構成元素を他元素で部分置換したものも使用できる。
例えば、シリコンとアルミニウムと酸素と窒素からなるサイアロン等の化合物も用いることができる。
炭化物として用いることができるものとしては、SiC、炭化硼素、ダイヤモンド、グラファイト、フラーレン類等が挙げられ、さらに、これらの構成元素を他元素で部分置換したものも用いることができる。
硫化物として用いることができるものとしては、硫化亜鉛、硫化カルシウム、硫化カドミウム、硫化ストロンチウム等が挙げられ、さらに、これらの構成元素を他元素で部分置換したものも用いることができる。
セレン化物として用いることができるのもとしては、セレン化亜鉛、セレン化カドミウム、等が挙げられ、さらに、これらの構成元素を他元素で部分置換したものも用いることができる。
金属として用いることができるものとしては、Si、Ni、W、Ta、Cr、Ti、Mg、Ca、Al、Au、AgおよびZnからなる群より選ばれる1種類以上の金属からなる粒子を用いることができる。
また、粒子M1は、互いに異なる材料からなる2種類以上の粒子の混合物であってもよい。また、粒子M1は、互いに異なる材料からなる積層体であってもよく、例えば、無機窒化物からなる無機粒子が、無機酸化物によって被覆された粒子であってもよい。
上記無機粒子を構成する化合物の中でも、形状安定性の点で酸化物が好ましく、その中でもシリカがより好ましい。
D[%]=|B-A|×100/A・・・(1)
但し、式(1)中、Aは粒子M1の平均粒径、Bは粒子M1間の最頻ピッチである。また、|B-A|はAとBとの差の絶対値を示す。
ずれDは、0.5%以上15%以下であることが好ましく、1.0%以上10%以下であることがより好ましく、1.0%~3.0%であることが更に好ましい。
一方、粒子M間のピッチとは、シート面方向における隣り合う2つの粒子M1の頂点と頂点の距離であり、粒子M1間の最頻ピッチBとはこれらの最頻値である。なお、粒子M1が球形で隙間なく接していれば、隣り合う粒子M1の頂点と頂点との距離は、隣り合う粒子M1の中心と中心の距離と等しい。
本実施形態の半導体発光素子用基板の凹凸構造のピッチは粒子M1間のピッチを反映したものとなるので、好ましい粒子M1間の最頻ピッチBは、本実施形態の半導体発光素子用基板の凹凸構造における好ましい最頻ピッチPと同じである。すなわち、粒子M1間の最頻ピッチBは、100nm~5μmが好ましく、100nm~1μmがより好ましく、200nm~700nmの範囲がさらに好ましく、300nm~600nmの範囲が特に好ましい。
まず、単粒子膜における無作為に選択された領域で、一辺が粒子M1間の最頻ピッチBの30倍~40倍のシート面と平行な正方形の領域について、AFMイメージを得る。例えば粒径300nmの粒子M1を用いた単粒子膜の場合、9μm×9μm~12μm×12μmの領域のイメージを得る。そして、このイメージをフーリエ変換により波形分離し、FFT像(高速フーリエ変換像)を得る。ついで、FFT像のプロファイルにおける0次ピークから1次ピークまでの距離を求める。こうして求められた距離の逆数がこの領域における最頻ピッチB1である。このような処理を無作為に選択された合計25カ所以上の同面積の領域について同様に行い、各領域における最頻ピッチB1~B25を求める。こうして得られた25カ所以上の領域における最頻ピッチB1~B25の平均値が式(1)における最頻ピッチBである。なお、この際、各領域同士は、少なくとも1mm離れて選択されることが好ましく、より好ましくは5mm~1cm離れて選択される。
また、この際、FFT像のプロファイルにおける1次ピークの面積から、各イメージについて、その中の粒子M間のピッチのばらつきを評価することもできる。
配列のずれD(%)を15%以下とするため、粒子M1の粒径の変動係数(標準偏差を平均値で除した値)は、20%以下であることが好ましく、10%以下であることがより好ましく、5%以下であることがさらに好ましい。
後述のように、本実施形態によって基板S1に設けられる凹凸構造のピッチ(凸部の中心点のピッチ)は、粒子M1間の最頻ピッチBと同等となる。配列のずれD(%)が小さければ、凹凸構造のピッチは、粒子M1の平均粒径Aとほぼ同等となるので、粒子M1の平均粒径Aを適切に選択することにより、所望のピッチの凹凸構造を精度良く形成することができる。
まず、AFMイメージから、凸部c1nが30個以上含められる任意の部分を抽出し、その中に含まれる各c1nについて上記方法で凸部の底面の寸法を求め、得られた値を有効桁数2桁で丸め、各凸部c1nの底面直径R11~R1nとし、その最頻値を最頻寸法Rとする。
粒子配列工程は、いわゆるLB法(ラングミュア-ブロジェット法)の考え方を利用した方法により行うことが好ましい。
具体的には、水槽内の水の液面に水よりも比重が小さい溶剤中に粒子が分散した分散液を滴下する滴下工程と、溶剤を揮発させることにより粒子からなる単粒子膜を形成する単粒子膜形成工程と、単粒子膜を基板に移し取る移行工程とを有する方法により粒子配列工程を行うことが好ましい。
この方法は、単層化の精度、操作の簡便性、大面積化への対応、再現性などを兼ね備える。例えばNature, Vol.361, 7 January, 26(1993)などに記載されている液体薄膜法や特開昭58-120255号公報などに記載されているいわゆる粒子吸着法に比べて非常に優れ、工業生産レベルにも対応できる。
LB法による粒子配列工程について、以下に具体的に説明する。
まず、水よりも比重が小さい溶剤中に、粒子M1を加えて分散液を調製する。一方、水槽(トラフ)を用意し、これに、その液面上で粒子M1を展開させるための水(以下、下層水という場合もある。)を入れる。
粒子M1は、表面が疎水性であることが好ましい。また、溶剤としても疎水性のものを選択することが好ましい。疎水性の粒子M1及び溶剤と下層水とを組み合わせることによって、後述するように、粒子M1の自己組織化が進行し、2次元的に最密充填した単粒子膜が形成される。
溶剤は、また、高い揮発性を有することも重要である。揮発性が高く疎水性である溶剤としては、クロロホルム、メタノール、エタノール、イソプロパノール、アセトン、メチルエチルケトン、エチルエチルケトン、トルエン、ヘキサン、シクロヘキサン、酢酸エチル、酢酸ブチルなどの1種以上からなる揮発性有機溶剤が挙げられる。
粒子M1の疎水化は、特開2009-162831号公報に記載された疎水化剤と同様の界面活性剤、金属アルコキシシランなどを用い、同様の方法で行うことができる。
詳しくは後述する移行工程において、単粒子膜の表面圧を計測する表面圧力センサーと、単粒子膜を液面方向に圧縮する可動バリアとを備えたLBトラフ装置を使用すると、形成された単粒子膜の欠陥箇所を表面圧の差に基づきある程度検知することが可能である。
しかし、数μm~数十μm程度の大きさの欠陥箇所は、表面圧の差として検知されにくい。あらかじめ精密ろ過を行っておくと、数μm~数十μm程度の大きさの欠陥が発生にくくなり、高精度な単粒子膜を得やすくなる。
下層水に滴下する分散液の粒子濃度は1質量%~10質量%とすることが好ましい。また、滴下速度を0.001ml/秒~0.01ml/秒とすることが好ましい。分散液中の粒子M1の濃度や滴下量がこのような範囲であると、粒子が部分的にクラスター状に凝集して2層以上となる、粒子が存在しない欠陥箇所が生じる、粒子間のピッチが広がるなどの傾向が抑制される。そのため、各粒子が高精度で2次元に最密充填した単粒子膜がより得られやすい。
特に、例えばコロイダルシリカのように、球形であって粒径の均一性も高い粒子M1が、水面上に浮いた状態で3つ集まり接触すると、粒子群の喫水線の合計長を最小にするように表面張力が作用する。その結果、図4に示すように、3つの粒子M1は図中T1で示す正三角形を基本とする配置で安定化する。
また、超音波の周波数には特に制限はないが、例えば28kHz~5MHzが好ましく、より好ましくは700kHz~2MHzである。振動数が高すぎると、水分子のエネルギー吸収が始まり、水面から水蒸気または水滴が立ち上る現象が起きるため好ましくない。一方、振動数が低すぎると、下層水中のキャビテーション半径が大きくなり、水中に泡が発生して水面に向かって浮上してくる。このような泡が単粒子膜の下に集積すると、水面の平坦性が失われるため不都合である。
超音波照射によって水面に定常波が発生する。いずれの周波数でも出力が高すぎたり、超音波振動子と発信機のチューニング条件によって水面の波高が高くなりすぎたりすると、単粒子膜が水面波で破壊されるため注意が必要である。
超音波照射によって得られる利点は粒子の最密充填化(ランダム配列を6方最密化する)の他に、ナノ粒子の分散液調製時に発生しやすい粒子の軟凝集体を破壊する効果、一度発生した点欠陥、線欠陥、または結晶転移などもある程度修復する効果がある。
単粒子膜形成工程により液面上に形成された単粒子膜を、ついで、単層状態のまま基板S1に移し取る(移行工程)。
単粒子膜を基板S1に移し取る具体的な方法には特に制限はなく、例えば、疎水性の基板S1を単粒子膜に対して略平行な状態に保ちつつ、上方から降下させて単粒子膜に接触させ、ともに疎水性である単粒子膜と基板との親和力により、単粒子膜を基板S1に移行させ、移し取る方法;単粒子膜を形成する前にあらかじめ水槽の下層水内に基板S1を略水平方向に配置しておき、単粒子膜を液面上に形成した後に液面を徐々に降下させることにより、基板S1に単粒子膜を移し取る方法などがある。
上記各方法によっても、特別な装置を使用せずに単粒子膜を基板S1に移し取ることができるが、より大面積の単粒子膜であっても、その2次的な最密充填状態を維持したまま基板S1に移し取りやすい点で、以降工程においては、いわゆるLBトラフ法を採用することが好ましい(Journal of Materials and Chemistry, Vol.11, 3333 (2001)、Journal ofMaterials and Chemistry, Vol.12, 3268 (2002)など参照。)
この方法では、水槽V1内の下層水W1に基板S1をあらかじめ略鉛直方向に浸漬しておき、その状態で上述の滴下工程と単粒子膜形成工程とを行い、単粒子膜F1を形成する(図5A)。そして、単粒子膜形成工程後に、基板S1を略鉛直方向を保ったまま上方に引き上げることによって、単粒子膜Fを基板S1に移し取ることができる(図5B)。
なお、この図では、基板S1の両面に単粒子膜F1を移し取る状態を示しているが、凹凸構造は、基板S1の一方の面のみに形成すればよいので、単粒子膜F1は基板S1の平坦面X1のみに移し取ればよい。基板S1の平坦面X1と反対側の面(裏面)を厚板で遮蔽することによって、平坦面X1側から裏面への粒子M1の回り込みを防止した状態で平坦面X1のみに単粒子膜F1を移し取れば、より精密に単粒子膜F1を移し取れるので好ましい。しかし、両面に移し取っても何ら差し支えない。
すなわちこのような装置によれば、単粒子膜F1の表面圧を計測しながら、単粒子膜F1を好ましい拡散圧(密度)に圧縮でき、また、基板S1の方に向けて一定の速度で移動させることができる。そのため、単粒子膜F1の液面から基板S1への移行が円滑に進行し、小面積の単粒子膜F1しか基板S1に移行できないなどのトラブルが生じにくい。好ましい拡散圧は、5mNm-1~80mNm-1であり、より好ましくは10mNm-1~40mNm-1である。このような拡散圧であると、各粒子がより高精度で2次元に最密充填した単粒子膜F1が得られやすい。また、基板S1を引き上げる速度は、0.5mNm-1~20mm/分が好ましい。下層水の温度は、先述したように、通常10℃~30℃である。なお、LBトラフ装置は、市販品として入手することができる。
移行工程により、基板S1に粒子M1の単粒子膜F1を移行させることができるが、移行工程の後には、移行した単粒子膜F1を基板S1に固定するための固定工程を行ってもよい。移行工程だけでは、後述の粒子エッチング工程及び基板エッチング工程中に粒子M1が基板S1上を移動してしまう可能性がある。特に、各粒子M1の直径が徐々に小さくなる基板エッチング工程の最終段階になると、このような可能性が大きくなる。
単粒子膜を基板S1に固定する固定工程を行うことによって、粒子M1が基板S1上を移動してしまう可能性が抑えられ、より安定かつ高精度にエッチングすることができる。
バインダーを使用する方法では、単粒子膜が形成された基板S1の平坦面X側にバインダー溶液を供給して単粒子膜を構成する粒子M1と基板S1との間にこれを浸透させる。
バインダーの使用量は、単粒子膜の質量の0.001倍~0.02倍が好ましい。このような範囲であれば、バインダーが多すぎて粒子M1間にバインダーが詰まってしまい、単粒子膜の精度に悪影響を与えるという問題を生じることなく、十分に粒子を固定することができる。バインダー溶液を多く供給してしまった場合には、バインダー溶液が浸透した後に、スピンコーターを使用したり、基板S1を傾けたりして、バインダー溶液の余剰分を除去すればよい。
バインダーとしては、先に疎水化剤として例示した金属アルコキシシランや一般の有機バインダー、無機バインダーなどを使用でき、バインダー溶液が浸透した後には、バインダーの種類に応じて、適宜加熱処理を行えばよい。金属アルコキシシランをバインダーとして使用する場合には、40℃~80℃で3分間~60分間の条件で加熱処理することが好ましい。
また、加熱を空気中で行うと、基板S1や各粒子M1が酸化する可能性があるため、焼結法を採用する場合には、このような酸化の可能性を考慮して、条件を設定することが必要となる。例えば、基板S1としてシリコン基板を用い、これを1100℃で焼結すると、この基板S1の表面には約200nmの厚さで熱酸化層が形成されてしまう。N2ガスやアルゴンガス中で加熱すると、酸化を避けやすい。
粒子配列工程は、配列のずれD(%)を1.0%以上15%以下にできれば特に限定はなく、LB法による他、以下の方法を採用することができる。
1)基板をコロイド粒子の懸濁液中に浸漬し、その後、基板と静電気的に結合した第1層目の粒子層のみを残し第2層目以上の粒子層を除去する(粒子吸着法)ことで、単粒子膜からなるエッチングマスクを基板上に設ける方法(特開昭58-120255号公報参照)。
2)基板上にバインダー層を形成し、その上に粒子の分散液を塗布し、その後バインダー層を加熱により軟化させることで、第1層目の粒子層のみをバインダー層中に包埋させ、余分な粒子を洗い落とす方法(特開2005-279807号公報参照)。
粒子エッチング工程では、基板S1が実質的にエッチングされない条件で配列された複数の粒子M1をドライエッチングする。これにより、図3Bに示すように、実質的に粒子M1のみがエッチングされて粒径の小さい粒子M11となり、粒子M11間に間隙が設けられる。一方、粒子エッチング工程後の基板S11は、実質的に基板S1と同じで、基板S11の一方の表面である平坦面X11に実質的な凹凸は形成されず、平坦面X11と平坦面X1は同等である。
ドライエッチング選択比[%]=基板S1のドライエッチング速度/粒子M1のドライエッチング速度×100・・・(2)
上記条件とするためには、バイアスパワーを低めに設定したり、圧力を低圧にしたりすればよい。
基板エッチング工程では、粒子エッチング工程後の粒子M11をエッチングマスクとして粒子エッチング工程後の基板S11をドライエッチングする。基板S11は、まず、粒子M11同士の空隙においてエッチングガスに晒されるので、その部分が先行して、平坦性を保ったままエッチングされる。そして、粒子M11も徐々にエッチングされて小さくなるため、各粒子M11の周辺の下側部分から中心の下側部分に向かい、徐々に、基板S11のエッチングが進行する。その結果、図3Cに示すように、粒子M11はさらに粒径の小さい粒子M12となる。また、この時点での基板S12には、各粒子M12の下側を頂面とする円錐台状の凸部Y12が複数形成される。凸部Y12同士の空隙(凹部の底面)は粒子M11同士の空隙とほぼ対応し、その部分は平坦面X12となる。
このようなドライエッチング条件とするためには、エッチングガスを適切に選択すればよい。例えば、基板S1がサファイアであり、粒子M1がシリカである場合、Cl2、Br2、BCl3、SiCl4、HBr、HI、HCl、およびArから選択される1以上のガスを用いてドライエッチングすればよい。
基板エッチング工程では、チャンバー内の温度を60℃~200℃に保持して行うことが好ましく、80℃~150℃に保持して行うことがより好ましい。
チャンバー内の温度を上記温度に保つことによって、基板のエッチング速度を高め且つ、ハンドリングがしやすいため、製造効率を高めることができる。
前記基板がサファイア基板である場合、特に上記温度で基板エッチング工程を行うことが好ましい。
なお、図3Cの段階で基板エッチング工程を終了させ、円錐台状の凸部としてもよい。その場合、残留する粒子M12は、粒子M12に対してエッチング性があり、基板S12に対して耐エッチング性があるエッチングガスを用いる化学的除去方法や、ブラシロール洗浄機などによる物理的除去方法により除去できる。
また、基板エッチング工程の前に粒子エッング工程を行うため、凸部と凸部の間、すなわち凹部の底面を平坦面とすることができる。そのため、半導体層を平坦面上に安定して成長させることができる。したがって、半導体層の結晶欠陥を発生させにくい半導体発光素子用の基板とすることができる。
また、本実施形態の製造方法によれば、巨視的な格子方位がランダムである(即ち、FFT基本波の最大値と最小値の比が小さい)多結晶構造のような配置であるの凹凸構造を基板S1に設けることができる。
本実施形態の半導体発光素子は、本実施形態の半導体発光素子用基板と、その凹凸構造が形成された面に積層された半導体機能層と、p型電極と、n型電極を備える。半導体機能層は少なくとも発光層を含む。
半導体機能層は、V族元素が窒素であるIII-V族窒化物半導体で構成されていることが好ましい。例えば、GaN、InGaN、AlGaN、InAlGaN、GaAs、AlGaAs、InGaAsP、InAlGaAsP、InP、InGaAs、InAlAs、ZnO、ZnSe、ZnS等が挙げられる。III-V族窒化物半導体は、サファイア等の基板上に形成する必要があるからである。
代表的なIII-V族窒化物半導体は、窒化ガリウム、窒化インジウムである。窒化アルミニウムは厳密には絶縁体であるが、本実施形態においては、半導体発光素子分野の慣習に従い、III-V族窒化物半導体に前記当するものとして扱う。
たとえば、バッファ層を含む場合もある。
また、上記各層も、それぞれ、複数の層から構成されることがある。
具体的な半導体機能層としては、GaN、AlN等からなるバッファ層、n-GaN、n-AlGaN等からなるn型の導電性を有する層(クラッド層)、InGaN、GaN等からなる発光層、アンドープGaN、p-GaN等からなるp型の導電性を有する層(クラッド層)、MgドープAlGaN、MgドープGaNからなるキャップ層が順次積層されてなる多層膜が挙げられる(例えば、特開平6-260682号公報、特開平7-15041号公報、特開平9-64419号公報、特開平9-36430号公報を参照)。
なお、発光層に電流を供給するためのn型電極及びp型電極としては、Ni、Au、Pt、Pd、Rh、Ti、Al等の金属からなる電極を用いることができる。
例えば、発光層の発光波長が紫外線領域の発光エネルギーを多く含む場合は、前記波長変換層にピーク波長410nm~483nmの蛍光を発する青色蛍光体、ピーク波長490nm~556nmの蛍光を発する緑色蛍光体、およびピーク波長585nm~770nmの蛍光を発する赤色蛍光体を含有させることによって、照明用に適した白色の取出し光を得ることができる。また、発光層の発光波長が青色領域の発光エネルギーを多く含む場合は、前記波長変換層にピーク波長570nm~578nmの蛍光を発する黄色蛍光体を含有させることによって、照明用に適した白色の取出し光を得ることができる。
本実施形態の半導体発光素子の製造方法は、本実施形態の発光素子用基板の製造方法により発光素子用基板を得る工程と、得られた発光素子用基板の凹凸構造が形成された面に、少なくとも発光層を含む半導体機能層を積層する工程を備える。
半導体発光素子用基板に半導体機能層を積層する方法は、MOVPE法(有機金属気相成長法)、MBE法(分子線エピタキシ法)、HVPE法(ハイドライド気相成長法)などの公知のエピタキシャル成長方法を用いることができる。エピタキシャル成長法は、気相エピタキシャル成長法、液相エピタキシャル成長法、分子線エピタキシャル成長法などである。反応性スパッタ法は、化合物半導体層の構成元素からなるターゲットをスパッタし、ターゲットからスパッタされた粒子と気相中の不純物元素との反応によって半導体層の形成材料を生成する。n型半導体層を形成する方法は、n型不純物の添加されるエピタキシャル成長法や反応性スパッタ法であればよい。p型半導体層を形成する方法は、p型不純物の添加されるエピタキシャル成長法や反応性スパッタ法であればよい。
図6から図13を参照して、本実施形態における半導体発光素子用基板、半導体発光素子、半導体発光素子用基板の製造方法、および、半導体発光素子の製造方法の一実施の形態を説明する。
図6に示されるように、半導体発光素子用基板(以下、素子用基板211Bと示す)は、1つの側面である発光構造体形成面211Sを有している。半導体発光素子の製造工程にて、発光構造体形成面211Sには、発光構造体が形成される。
多数の凸部212の各々は、その凸部212に接続する平坦部214から突き出しており、かつ、平坦部214に接続する基端から先端に向かって細くなっている形状を有している。複数の凸部212の各々は、半球形状を有している。
本実施形態においては、ブリッジ部を互いに隣り合う凸部212間を連結する形で構成できる。ブリッジ部を設けることにより後述する光学的効果や機械強度の効果を得ることができるが、ブリッジ部を設けない場合でも、マスク粒子の粒径縮小によって平坦部214の範囲が広がることで、後のLED成膜工程におけるエピタキシャル成長を効果的に行うことが可能となる。
多数のブリッジ部213の各々は、ブリッジ部213に接続する平坦部214から突き出しており、かつ、互いに隣り合う凸部212の間を連結している。多数のブリッジ部213の各々の高さは、凸部212の高さよりも低く、かつ、半球形状を有する凸部212の中心同士を結ぶ突条形状を有している。なお、ブリッジ部213の有する形状は、直線形状に限らず、曲線形状であってもよいし、折線形状であってもよい。多数のブリッジ部213の各々の有する形状は、互いに異なっていてもよい。ブリッジ部213は、頂面213Tを含む。頂面213Tは平面を含んでいる。
半導体発光素子用基板の製造方法は、基板に複数の粒子を配列させる粒子配列工程と、前記粒子がエッチングされ、前記基板が実質的にエッチングされない条件で、前記配列した複数の粒子をドライエッチングして粒子間に間隙を設ける粒子エッチング工程(単粒子膜F1のエッチング工程)と、前記粒子エッチング工程後の複数の粒子をエッチングマスクとして前記基板をドライエッチングし、前記基板の一方の面に凹凸構造を形成する基板エッチング工程(発光構造体形成面11Sのエッチング工程)とを備える。以下、半導体発光素子用基板の製造方法に含まれる各工程を、処理の順に説明するが、粒子配列工程については、第1実施形態と同様の方法で行うことができるため、説明を省略する。
単粒子膜F1のエッチング工程は、基本的に第1実施形態と同様の方法で行うことができる。
一側面として、図10に示されるように、単層の粒子M1から構成される単粒子膜F1は、発光構造体形成面211Sに形成される。単粒子膜F1は、直径R21を有する粒子M1の六方充填構造を有している。1つの六方充填構造は、7つの粒子M1から構成されている。六方充填構造では、6つの粒子M1が、六角形の有する6つの頂点に配置され、かつ、6つの粒子M1によって囲まれる部分に、1つの粒子M1が充填されている。すなわち、1つの六方充填構造では、中心となる1つの粒子M1の周囲に、6つの粒子M1が等配されている。
図12に示されるように、エッチング工程では、縮径された粒子M1をマスクとして発光構造体形成面211Sがエッチングされる。この際に、発光構造体形成面211Sにて、第1の露出部S21は、互いに隣り合う3つの粒子M1に囲まれた隙間を通じて、エッチングガスのプラズマに曝される。発光構造体形成面211Sにて、第2の露出部S22は、互いに隣り合う2つの粒子M1の間の隙間を通じて、エッチングガスのプラズマに曝される。そして、単粒子膜を構成する粒子M1もまた、エッチングガスのプラズマに曝される。
結果として、発光構造体形成面211Sには、深く窪んだ部分として、第1の領域214に平坦部214が形成される。また、平坦部214よりも浅く窪んだ部分として、第2の領域213にブリッジ部213が形成される。そして、平坦部214、および、ブリッジ部213以外の部分として、半球形状を有する凸部212が形成される。複数のブリッジ部213のなかでは、ブリッジ部213によって連結される凸部212の間の間隔が大きいほど、ブリッジ部213の高さが低くなる。ブリッジ部を積極的に作製する場合、例えばシリカ粒子マスクとサファイア基板の組み合わせの場合、最頻ピッチが3.0μmのとき、凸部212間の間隔が300nm~700nmとなり、その場合ブリッジの高さは10~300nmであり、また、最頻ピッチが400nmのとき、凸部212間の間隔が10nm~100nmとなり、その場合ブリッジの高さは5nm~100nmである。その他、粒子マスクの材質と基材の材質の組み合わせ、およびガスの選択を含むドライエッチング条件によって凸部212間の間隔およびブリッジの高さは変わるため、上記数値は条件によって変動する。
なお、上述した単粒子膜F1のエッチング工程にて、第2の露出部S22の大きさが変わると、それに続く発光構造体形成面211Sのエッチング工程では、最終的に形成されるブリッジ部213の高さが変わる。こうしたブリッジ部213の高さの変更方法には、単粒子膜F1のエッチング工程以外にも、発光構造体形成面211Sのエッチングで使用されるエッチングガスの変更が挙げられる。
例えば、単粒子膜F1のエッチング速度を上げ、かつ、素子用基板211Bのエッチング速度を下げるガスが、発光構造体形成面211Sのエッチング工程に用いられる。このとき、粒子M1のエッチング速度は、発光構造体形成面211Sに対してさらに遅くなり、第2の露出部S22の広がる速度も、さらに遅くなる。結局は、第1の露出部S221におけるエッチングの進行度合いと、第2の露出部S22におけるエッチングの進行度合いとの間に大きな差が生じ、結果として、ブリッジ部213の高さは高くなる。
これに対して、単粒子膜F1のエッチング速度を下げ、かつ、素子用基板211Bのエッチング速度を上げるガスが、発光構造体形成面211Sのエッチングガスに用いられる。このとき、粒子M1のエッチング速度は、発光構造体形成面211Sに対して近くなり、第2の露出部S22の広がる速度は、さらに速くなる。結局は、第1の露出部S221におけるエッチングの進行度合いと、第2の露出部S22におけるエッチングの進行度合いとの間の差は小さくなり、結果として、ブリッジ部213の高さは低くなる。なお、この際に用いるガスは1種類のガスから構成されてもよいし、2種類以上のガスから構成されてもよい。
さらに、上述した単粒子膜F1のエッチング工程にて、ブリッジ部213の高さの変更と、上述したエッチングガスの変更によるブリッジ部213の高さの変更とが組み合わされてもよい。
なお、ブリッジ部を積極的に作製しなくても(ブリッジ部の高さが実質ゼロに相当する場合でも)、前述のようにマスク粒径縮小によって凸部212間の間隔が広がる効果で、LED成膜工程に必要な平坦部の面積をより多く確保することができ、より効率的で結晶欠陥の少ないエピタキシャル結晶成長が可能となるため、結果としてこのような基板上に半導体層を成膜して作製した半導体発光素子の発光効率が向上するという恩恵が得られる。
図13に示されるように、半導体発光素子200は、素子用基板211Bを基材として有している。半導体発光素子200は、素子用基板211Bの発光構造体形成面211Sに、発光構造体形成面211Sの凹凸構造を覆う発光構造体221を有している。発光構造体221は、複数の半導体層から構成される積層体を有し、電流の供給によってキャリアを再結合させて発光する。複数の半導体層の各々は、発光構造体形成面211Sから順に積み重ねられる。
半導体発光素子200は、第1実施形態に記載の半導体発光素子と同様の構成を採用することが出来る。また、半導体発光素子200は、第1実施形態に記載の方法で形成することができる。
本実施形態によれば、以下の効果が得られる。
(2)1つの凸部212に複数のブリッジ部213が連結しているため、1つの凸部212に1つのブリッジ部213が連結している構成と比べて、上記(1)に準じた効果がさらに高められる。
(4)凸部212の配置がランダム性を有するため、発光構造体形成面211Sの面内において、上記(1)に準じた効果の均一性が高められる。
(5)ブリッジ部213の頂面213Tが結晶面であるため、凸部212の形成に起因して半導体層の成長が不足することが抑えられる。
なお、本実施形態は、以下のように変更して実施することもできる。
図14の左側に示されるように、ブリッジ部213の頂面213Tは、ブリッジ部213の連結する方向と交差する方向から見て、平坦部214に向けて窪んだ凹曲面であってもよい。要は、ブリッジ部213は、凸部212の高さよりも低い高さを有して、互いに隣り合う凸部212の一部同士を連結する部分であればよい。
平坦部214は、4つ以上の凸部対TP2によって囲まれてもよい。さらに、平坦部214は、凸部対TP2によって囲まれていなくともよい。例えば、ブリッジ部213の連結する方向と交差する方向にて、2つの平坦部214が、1つのブリッジ部213を挟む構造であってもよい。
互いに隣り合う凸部212の間の間隔が、互いに異なる凸部対TP2において、ブリッジ部213の高さは、互いに等しくてもよい。
本実施形態の半導体発光素子用基板は、半導体層を含む発光構造体が形成される発光構造体形成面を有し、前記発光構造体形成面は、1つの結晶面に沿って広がっている平坦部と、前記平坦部から突き出した2つの凸部と、前記平坦部から突き出した1つのブリッジ部と、を備え、前記平坦部から突き出している量は、前記凸部よりも前記ブリッジ部にて小さく、前記2つの凸部は、前記1つのブリッジ部によって連結されており、前記凸部の最頻ピッチが100nm以上1μm以下であり、前記多数の凸部のアスペクト比が0.5~1.0あってもよい。
本実施形態の半導体発光素子用基板は、半導体層を含む発光構造体が形成される発光構造体形成面を有し、前記発光構造体形成面は、1つの結晶面に沿って広がっている平坦部と、前記平坦部から突き出した2つの凸部と、前記平坦部から突き出した1つのブリッジ部と、を備え、前記平坦部から突き出している量は、前記凸部よりも前記ブリッジ部にて小さく、前記2つの凸部は、前記1つのブリッジ部によって連結されており、前記凸部の最頻ピッチが200nm~700nmであり、前記多数の凸部のアスペクト比が0.5~1.0あってもよい。
本実施形態の半導体発光素子用基板は、半導体層を含む発光構造体が形成される発光構造体形成面を有し、前記発光構造体形成面は、1つの結晶面に沿って広がっている平坦部と、前記平坦部から突き出した2つの凸部と、前記平坦部から突き出した1つのブリッジ部と、を備え、前記平坦部から突き出している量は、前記凸部よりも前記ブリッジ部にて小さく、前記2つの凸部は、前記1つのブリッジ部によって連結されており、前記凸部の最頻ピッチが100nm以上5μm以下であり、前記多数の凸部のアスペクト比が0.5~1.0であり、ブリッジ部の短手方向に沿った長さが10nm以上100nm以下であってもよい。
本実施形態の半導体発光素子用基板は、基板の一方の面に凹凸構造を有する半導体発光素子用基板であって、前記凹凸構造は、多数の凸部と各凸部の間の平坦面とを有し、かつ、隣接する7つの凸部の中心点が正六角形の6つの頂点と対角線の交点となる位置関係で連続して整列しているエリアを複数備え、前記複数のエリアの面積、形状及び格子方位がランダムであり、前記多数の凸部のアスペクト比が0.5~1.0であり、凸部の頂点を通り、前記基板に垂直な断面で見たときの平坦面f11~f1nの長さが、凸部c11~c1nのうちの隣り合う二つの凸部の頂点同士を結ぶ直線に対し、15%~25%となってもよい。
<半導体発光素子の作成>
直径2インチ、厚さ0.42mmのサファイア基板上に、φ3μmのSiO2コロイダルシリカ粒子を特願2008-522506に開示される単層コーティング法によって単層コートした。
具体的には、平均粒径が3.02μmのSiO2コロイダルシリカ粒子(粒径の変動係数=0.85%)の球形コロイダルシリカの3.0質量%水分散体(分散液)を用意した。
ついで、この分散液に濃度50質量%の臭素化ヘキサデシルトリメチルアンモニウム(界面活性剤)を2.5mmol/Lとなるように加え、30分攪拌して、コロイダルシリカ粒子の表面に臭素化ヘキサデシルトリメチルアンモニウムを吸着させた。この際、臭素化ヘキサデシルトリメチルアンモニウムの質量がコロイダルシリカ粒子の質量の0.04倍となるように分散液と臭素化ヘキサデシルトリメチルアンモニウムとを混合した。
ついで、この分散液に、この分散液の体積と同体積のクロロホルムを加え十分に攪拌して、疎水化されたコロイダルシリカを油相抽出した。
滴下中より、超音波(出力120W、周波数1.5MHz)を下層水中から水面に向けて照射して粒子が2次元的に最密充填するのを促しつつ、分散液の溶剤であるクロロホルムを揮発させ、単粒子膜を形成させた。
ついで、この単粒子膜を可動バリアにより拡散圧が18mNm-1になるまで圧縮し、サファイアウェハを5mm/分の速度で引き上げ、単粒子膜を基板の片面上に移し取り、コロイダルシリカからなる単粒子膜エッチングマスク付きのサファイアウェハを得た。
続いて基材であるサファイアウェハを加工するドライエッチングを行った。具体的には、アンテナパワー1500W、バイアス300W、圧力1Pa、エッチングチャンバー内の温度80~110℃の条件で、Cl2ガスにてSiO2マスク/サファイア基板をドライエッチング加工し、表1に示す最頻ピッチ3μm、構造高さ1.5μm、平坦部距離0.4μm、ブリッジ部に相当する部分の長さ0.4μm、ブリッジ部に相当する部分の高さ3nm以下(実質ブリッジ部は高さを持たないため、ブリッジ部は平坦である)で構成される凹凸構造を備える半導体発光素子用サファイア基板を得た。
こうして得た得られた半導体発光素子用サファイア基板の凹凸構造面に、n型半導体層、活性層、p型半導体層を順次積層し、続いてp電極およびn電極を形成して、半導体発光素子を完成した。各GaN系の半導体層は、一般に広く利用されるMOCVD(Metal Organic Chemical Vapor Deposition)法によって形成した。MOCVD法において、アンモニアガスとIII族元素のトリメチルガリウム、トリメチルアンモニウム、トリメチルインジウムなどのアルキル化合物ガスを、700℃~1000℃の温度環境でサファイア基板上に供給して熱分解反応させ、基板上で目的の結晶をエピタキシャル成長により成膜する。
活性層は再結合の確率を高くするためバンドギャップの狭い層を数層挟んで内部量子効率の向上を行う多重量子井戸を形成した。その構成としては、アンドープIn0.15Ga0.85N(量子井戸層)を4nm、SiドープGaN(バリア層)10nmの膜厚で交互に成膜し、アンドープIn0.15Ga0.85Nが9層、SiドープGaNが10層となるように積層した。
p型半導体層としては、MgドープAlGaNを15nm、アンドープGaNを200nm、MgドープGaNを15nm積層した。
n電極を形成する領域において、最表層であるp型半導体層のMgドープGaNからn型半導体層のアンドープGaNまでをエッチング除去し、SiドープのGaN層を露出させた。この露出面にAlとWからなるn電極を形成し、n電極上にPtとAuからなるnパッド電極を形成した。
p型半導体層の表面全面にNiとAuからなるp電極を形成し、p電極上にAuからなるpパッド電極を形成した。
以上の操作でベアチップの状態の半導体素子(一つの素子のサイズが300μm×350μm)を形成した。
直径2インチ、厚さ0.42mmのサファイア基板上にフォトレジストを厚さ750nmでスピンコートし、レーザーリソグラフィー法によりピッチ3μmのマスクを描画したのち、ドライエッチングによる微細加工を行って、表1に示す最頻ピッチ3μm、構造高さ1.5μm、平坦部距離0.4μmで構成される凹凸構造を備える半導体発光素子用サファイア基板を得た。
こうして得た得られた半導体発光素子用サファイア基板の凹凸構造面に、実施例1と同じ構成のn型半導体層、活性層、p型半導体層を順次積層し、続いてp電極およびn電極を形成して、半導体発光素子(一つの素子のサイズが300μm×350μm)を完成した。
平均粒径が305nmのSiO2コロイダルシリカ粒子(粒径の変動係数=3.4%)を用い、n型半導体層のアンドープGaNを2.5μmとする以外は、実施例1と同じ方法で粒子マスク法による微細加工を行い、表1に示す最頻ピッチ300nm、構造高さ150nm、平坦部距離40nm、ブリッジ部に相当する部分の長さ30nm、ブリッジ部に相当する部分の高さ3nm以下(実質ブリッジ部は高さを持たないため、ブリッジ部は平坦である)で構成される凹凸構造を備える半導体発光素子用サファイア基板を得た。
こうして得られた半導体発光素子用サファイア基板の凹凸構造面に、実施例1と同じ構成のn型半導体層、活性層、p型半導体層を順次積層し、続いてp電極およびn電極を形成して、半導体発光素子(一つの素子のサイズが300μm×350μm)を完成した。
直径2インチ、厚さ0.42mmのサファイア基板上にフォトレジストを厚さ100nmでスピンコートし、電子線リソグラフィー法によりピッチ300nmのマスクを描画したのち、ドライエッチングによる微細加工を行って、表1に示す最頻ピッチ300nm、構造高さ150nm、平坦部距離40nmで構成される凹凸構造を備える半導体発光素子用サファイア基板を得た。
こうして得た得られた半導体発光素子用サファイア基板の凹凸構造面に、実施例1と同じ構成のn型半導体層、活性層、p型半導体層を順次積層し、続いてp電極およびn電極を形成して、半導体発光素子(一つの素子のサイズが300μm×350μm)を完成した。
各実施例、比較例で得られた半導体発光素子(樹脂包埋前のベアチップ)をベアチップのまま小型プローバー(ESSテック社製sp-0-2Ls)にマウントし、オープンプローブにて駆動電流20-40mAで点灯させ、以下の評価を行った。結果を表1に示す。
Newport製PR50CCの回転ステージ上に半導体発光素子を取り付け点灯させた。回転ステージをZ軸を中心として0.5°/secで360度回転させつつ、半導体発光素子の発光面から仰角30度、距離150mmの位置からCCDカメラ(トプコン社製輝度計BM7A)にて輝度を連続測定した。
縦軸を輝度、横軸を回転角度としたグラフに、測定結果をプロットして得た曲線と、0度~360度の輝度平均値の直線を重ねて書き、以下の式より面内放射異方性を求めた。
面内放射異方性=(曲線と直線で囲まれた面積の総和)/(平均値×360度)
面内放射異方性の数値が大きな半導体発光素子は、面内方向の放射に関して異方性が高く均等性が低い放射特性を示す。反対に、面内放射異方性の数値が小さな半導体発光素子は、面内方向の放射に関して異方性が低く均等性が高い放射特性を示す。
光取り出し効率向上効果を確認するため、外部量子効率を、labsphere社製スペクトラフレクト積分球とCDS-600型分光器にて測定した。
表1に示すように、実施例1、実施例2では、低い面内放射異方性が確認された。一方、フォトリソグラフィー法で作製した比較例1、干渉露光法で作製した比較例2では、高い面内放射異方性が確認された。このことから、本発明によれば、従来法よりより簡便な方法で、充分な光取り出し効率と低い面内放射異方性が得られることが分かった。
[実施例3]
こうして得られた半導体発光素子用サファイア基板の凹凸構造面に、実施例1と同じ構成のn型半導体層、活性層、p型半導体層を順次積層し、続いてp電極およびn電極を形成して、半導体発光素子(一つの素子のサイズが300μm×350μm)を完成した。
TTVが5.24μm、WARPが17.31μm、|BOW|が11.07μmのサファイア基板を使用する以外は比較例1と同じ方法で、レーザーリソグラフィー法を使用しピッチ3μmの円形マスク作製後、ドライエッチングによる微細加工を行い、表2に示す最頻ピッチ3μm、構造高さ1.5μm、平坦部距離0.4μmで構成される凹凸構造を備える半導体発光素子用サファイア基板を得た。また基板中央部、外周部の凸部の変動係数H’は、各々4.82、10.45の値が得られた。
こうして得られた半導体発光素子用サファイア基板の凹凸構造面に、実施例1と同じ構成のn型半導体層、活性層、p型半導体層を順次積層し、続いてp電極およびn電極を形成して、半導体発光素子(一つの素子のサイズが300μm×350μm)を完成した。
TTVが5.89μm、WARPが18.78μm、|BOW|が11.02μmのサァイア基板を使用する以外は実施例2と同じ方法で粒子マスク法による微細加工を行い、表1に示す最頻ピッチ300nm、構造高さ150nm、平坦部距離40nmで構成される凹凸構造を備える半導体発光素子用サファイア基板を得た。また基板中央部、外周部の凸部の変動係数H’は、各々2.51、2.68の値が得られた。
こうして得られた半導体発光素子用サファイア基板の凹凸構造面に、実施例1と同じ構成のn型半導体層、活性層、p型半導体層を順次積層し、続いてp電極およびn電極を形成して、半導体発光素子(一つの素子のサイズが300μm×350μm)を完成した。
TTVが5.56μm、WARPが18.57μm、|BOW|が10.85μmのサァイア基板を使用する以外は比較例2と同じ方法で電子線リソグラフィー法によりピッチ300nmの円形マスクを描画したのち、ドライエッチングによる微細加工を行って、表1に示す最頻ピッチ300nm、構造高さ150nm、平坦部距離40nmで構成される凹凸構造を備える半導体発光素子用サファイア基板を得た。また基板中央部、外周部の凸部の変動係数H’は、各々5.09、10.13の値が得られた。
こうして得られた半導体発光素子用サファイア基板の凹凸構造面に、実施例1と同じ構成のn型半導体層、活性層、p型半導体層を順次積層し、続いてp電極およびn電極を形成して、半導体発光素子(一つの素子のサイズが300μm×350μm)を完成した。
各実施例、比較例で得られた半導体発光素子(樹脂包埋前のベアチップ)を基板中央部、外周部から各20点抽出し、ベアチップのまま小型プローバー(ESSテック社製sp-0-2Ls)にマウントし、オープンプローブにて駆動電流20-40mAで点灯させ、以下の評価を行った。結果を表2に示す。
光取り出し効率向上効果を確認するため、外部量子効率を、labsphere社製スペクトラフレクト積分球とCDS-600型分光器にて測定した。
表2に示すように、実施例3、実施例4では面内中央部、外周部ともに、変動係数H’、光取り出し効率向上率および光取り出し効率向上率の標準偏差がほぼ同一な値を示すため、サファイア基板上の凹凸構造の面内均一性が高いことが確認された。一方、フォトリソグラフィー法で作製した比較例3、干渉露光法で作製した比較例4では、面内中央部と外周部で上記の数値に大きな差があることが確認された。このことから、実施例3及び4によれば、TTVが5μm~30μm、WARPが10μm~50μm、|BOW|が10μm~50μmである平坦性の比較的低い基板を使用しても精度良く凹凸構造の面内均一性が保たれ、充分な光取り出し効率が得られることが分かった。
平均粒径が1.06μmのSiO2コロイダルシリカ粒子(粒径の変動係数=3.1%)を用い、n型半導体層のアンドープGaNを4.0μmとする以外は、実施例1と同じ方法で粒子マスク法による微細加工を行い、表1に示す最頻ピッチ1.0μm、構造高さ510nm、ブリッジ部の長さ280nm、ブリッジ部の高さ106nmで構成される凹凸構造を備える半導体発光素子用サファイア基板を得た。
こうして得られた半導体発光素子用サファイア基板の凹凸構造面に、実施例1と同じ構成のn型半導体層、活性層、p型半導体層を順次積層し、続いてp電極およびn電極を形成して、半導体発光素子(一つの素子のサイズが300μm×350μm)を完成した。
直径2インチ、厚さ0.42mmのサファイア基板上にフォトレジストを厚さ300nmでスピンコートし、レーザーリソグラフィー法によりピッチ1μmのマスクを描画したのち、ドライエッチングによる微細加工を行って、表3に示す最頻ピッチ1μm、構造高さ500μm、平坦部距離290nmで構成される凹凸構造を備える半導体発光素子用サファイア基板を得た。
こうして得た得られた半導体発光素子用サファイア基板の凹凸構造面に、実施例1と同じ構成のn型半導体層、活性層、p型半導体層を順次積層し、続いてp電極およびn電極を形成して、半導体発光素子(一つの素子のサイズが300μm×350μm)を完成した。
各実施例、比較例で得られた半導体発光素子(樹脂包埋前のベアチップ)をベアチップのまま小型プローバー(ESSテック社製sp-0-2Ls)にマウントし、オープンプローブにて駆動電流20-40mAで点灯させ、以下の評価を行った。結果を表3に示す。
光取り出し効率向上効果を確認するため、外部量子効率を、labsphere社製スペクトラフレクト積分球とCDS-600型分光器にて測定した。
Claims (25)
- 基板に下記式(1)で定義される配列のずれD(%)が15%以下となるように、複数の粒子を単一層で配列させる粒子配列工程と、
前記粒子がエッチングされ、前記基板が実質的にエッチングされない条件で、前記配列した複数の粒子をドライエッチングして粒子間に間隙を設ける粒子エッチング工程と、
前記粒子エッチング工程後の複数の粒子をエッチングマスクとして前記基板をドライエッチングし、前記基板の一方の面に凹凸構造を形成する基板エッチング工程を備えることを特徴とする半導体発光素子用基板の製造方法。
D[%]=|B-A|×100/A・・・(1)
但し、式(1)中、Aは粒子の平均粒径、Bは粒子間の最頻ピッチである。また、|B-A|はAとBとの差の絶対値を示す。 - 前記粒子配列工程が、水槽内の水の液面に水よりも比重が小さい溶剤中に粒子が分散した分散液を滴下する滴下工程と、前記溶剤を揮発させることにより前記粒子からなる単粒子膜を水の液面上に形成する単粒子膜形成工程と、前記単粒子膜を基板に移し取る移行工程とを有する請求項1に記載の半導体発光素子用基板の製造方法。
- 前記粒子間の最頻ピッチが5μm以下である請求項1または2に記載の半導体発光素子用基板の製造方法。
- 前記粒子間の最頻ピッチが1μm以下である請求項1または2に記載の半導体発光素子用基板の製造方法。
- 前記粒子間の最頻ピッチが200nm~700nmである請求項1または2に記載の半導体発光素子用基板の製造方法。
- 前記基板がサファイアであり、前記粒子がシリカであり、前記粒子エッチング工程が、エッチングガスとしてCF4、SF6、CHF3、C2F6、C3F8、CH2F2、O2、およびNF3からなる群から選択される少なくとも1種のガスを用いる工程であり、前記基板エッチング工程が、エッチングガスとしてCl2、Br2、BCl3、SiCl4、HBr、HI、HCl、およびArからなる群から選択される少なくとも1種のガスを用いる工程である請求項1~5のいずれか一項に記載の半導体発光素子用基板の製造方法。
- 基板に複数の粒子を単一層で配列させる粒子配列工程と、
前記粒子がエッチングされ、前記基板が実質的にエッチングされない条件で、前記配列した複数の粒子をドライエッチングして粒子間に間隙を設ける粒子エッチング工程と、
前記粒子エッチング工程後の複数の粒子をエッチングマスクとして前記基板をドライエッチングし、前記基板の一方の面に凹凸構造を形成する基板エッチング工程を備え、
前記基板がサファイアであり、前記粒子がシリカであり、前記粒子エッチング工程が、エッチングガスとしてCF4、SF6、CHF3、C2F6、C3F8、CH2F2、O2、およびNF3からなる群から選択される少なくとも1種のガスを用いる工程であり、前記基板エッチング工程が、エッチングガスとしてCl2、Br2、BCl3、SiCl4、HBr、HI、HCl、およびArからなる群から選択される少なくとも1種のガスを用いる工程であることを特徴とする半導体発光素子用基板の製造方法。 - 前記粒子配列工程が、水槽内の水の液面に水よりも比重が小さい溶剤中に粒子が分散した分散液を滴下する滴下工程と、前記溶剤を揮発させることにより前記粒子からなる単粒子膜を水の液面上に形成する単粒子膜形成工程と、前記単粒子膜を基板に移し取る移行工程とを有する請求項7に記載の半導体発光素子用基板の製造方法。
- 前記基板のASTM F657で規定される最大厚み及び最小厚みの間の絶対差(TTV)が5μm~30μm、ASTM F1390規定される基準面からのズレの最大値と最小値の差(WARP)が10μm~50μm、ASTM F534.3.1.2で規定される基板の中心部での基準面からの隔たりの絶対値(|BOW|)が10μm~50μmである請求項1~8のいずれか一項に記載の半導体発光素子用基板の製造方法。
- 基板の上面に複数の粒子を単一層で配列させて単粒子膜を形成する粒子配列工程と、
前記粒子がエッチングされ、前記基板が実質的にエッチングされない条件で、前記配列した複数の粒子をドライエッチングして粒子間に間隙を設ける粒子エッチング工程と、
前記単粒子膜をマスクにして前記上面をエッチングする基板エッチング工程と、を含み、
前記基板エッチング工程では、
前記粒子エッチング工程後に前記基板の上面において露出している領域に段差を形成する
半導体発光素子用基板の製造方法。 - 前記粒子エッチング工程では、前記複数の粒子の各々を縮小する
請求項10に記載の半導体発光素子用基板の製造方法。 - 前記基板エッチング工程において、
複数の粒子のうち、2つの粒子の間の隙間が大きいほど、前記段差が小さくなる
請求項10または11に記載の半導体発光素子用基板の製造方法。 - 前記粒子配列工程では、前記複数の粒子をLB法によって配列する
請求項12に記載の半導体発光素子用基板の製造方法。 - 請求項10から13のいずれか1つに記載の半導体発光素子用基板の製造方法によって半導体発光素子用基板を形成する工程と、
前記半導体発光素子用基板にて前記段差が形成された前記上面に、半導体層を含む発光構造体を形成する工程と、を含む
半導体発光素子の製造方法。 - 請求項1~14のいずれか一項に記載の製造方法により発光素子用基板を得る工程と、得られた発光素子用基板の凹凸構造が形成された面に、少なくとも発光層を含む半導体機能層を積層する工程を備える半導体発光素子の製造方法。
- 基板の一方の面に凹凸構造を有する半導体発光素子用基板であって、
前記凹凸構造は、多数の凸部と各凸部の間の平坦面とを有し、
かつ、隣接する7つの凸部の中心点が正六角形の6つの頂点と対角線の交点となる位置関係で連続して整列しているエリアを複数備え、
前記複数のエリアの面積、形状及び格子方位がランダムである半導体発光素子用基板。 - 前記凹凸構造の最頻ピッチが100nm以上5μm以下であり、前記多数の凸部のアスペクト比が0.5~1.0である請求項16に記載の半導体発光素子用基板。
- 前記凹凸構造の最頻ピッチが100nm以上1μm以下であり、前記多数の凸部のアスペクト比が0.5~1.0である請求項16に記載の半導体発光素子用基板。
- 前記凹凸構造の最頻ピッチが200nm~700nmであり、前記多数の凸部のアスペクト比が0.5~1.0である請求項16に記載の半導体発光素子用基板。
- 前記凸部間を連結するブリッジ部を更に備える請求項16から請求項19のいずれか1項に記載の半導体発光素子用基板。
- 前記基板がサファイアである請求項16~20のいずれか一項に記載の半導体発光素子用基板。
- 請求項16~20のいずれか一項に記載の半導体発光素子用基板と、前記半導体発光素子用基板上に積層された半導体機能層を備え、前記半導体機能層は少なくとも発光層を含む半導体発光素子。
- 前記半導体機能層の光取出し側に、前記発光層から出射される発光を、前記発光の波長より長波長側に波長変換する波長変換層を備える請求項22に記載の半導体発光素子。
- 前記波長変換層が、ピーク波長410nm~483nmの蛍光を発する青色蛍光体、ピーク波長490nm~556nmの蛍光を発する緑色蛍光体、およびピーク波長585nm~770nmの蛍光を発する赤色蛍光体を含有する請求項23に記載の半導体発光素子。
- 前記波長変換層がピーク波長570nm~578nmの蛍光を発する黄色蛍光体を含有する請求項24に記載の半導体発光素子。
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Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102013108876B4 (de) * | 2013-08-16 | 2022-08-18 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Fotolithografisches Verfahren zur Herstellung einer Struktur in einem Strahlung emittierenden Halbleiterbauelement |
US20170137328A1 (en) * | 2014-06-18 | 2017-05-18 | Osram Sylvania Inc. | Method of making a ceramic wavelength converter assembly |
US10073193B2 (en) * | 2014-07-15 | 2018-09-11 | Oji Holdings Corporation | Optical element |
JP6482120B2 (ja) * | 2015-03-31 | 2019-03-13 | デクセリアルズ株式会社 | 原盤の製造方法、光学体の製造方法、光学部材の製造方法、および表示装置の製造方法 |
US9558943B1 (en) * | 2015-07-13 | 2017-01-31 | Globalfoundries Inc. | Stress relaxed buffer layer on textured silicon surface |
CN108886075B (zh) * | 2015-07-29 | 2021-07-13 | 日机装株式会社 | 发光元件的制造方法 |
US10276455B2 (en) * | 2016-07-29 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | System and method for measurement of semiconductor device fabrication tool implement |
JP6558326B2 (ja) * | 2016-08-23 | 2019-08-14 | 信越化学工業株式会社 | ハーフトーン位相シフトマスクブランクの製造方法、ハーフトーン位相シフトマスクブランク、ハーフトーン位相シフトマスク及びフォトマスクブランク用薄膜形成装置 |
JP6772820B2 (ja) * | 2016-12-22 | 2020-10-21 | 日亜化学工業株式会社 | 再生基板の製造方法及び発光素子の製造方法 |
US10395936B2 (en) | 2017-04-24 | 2019-08-27 | International Business Machines Corporation | Wafer element with an adjusted print resolution assist feature |
CN106941074B (zh) * | 2017-04-27 | 2023-03-03 | 林文华 | 一种方形晶片加工装置及其工作方法 |
JP2019082594A (ja) * | 2017-10-31 | 2019-05-30 | ソニー株式会社 | 表示装置 |
WO2021193183A1 (ja) * | 2020-03-24 | 2021-09-30 | デンカ株式会社 | 蛍光体粒子、複合体、発光装置および自発光型ディスプレイ |
CN112750928A (zh) * | 2020-12-30 | 2021-05-04 | 广东中图半导体科技股份有限公司 | 桥链型图形化蓝宝石衬底、制备方法及led外延片 |
Citations (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58120255A (ja) | 1981-12-31 | 1983-07-18 | エクソン・リサ−チ・アンド・エンジニアリング・カンパニ− | 平版印刷マスクの製造方法 |
JPH06260682A (ja) | 1993-01-08 | 1994-09-16 | Nichia Chem Ind Ltd | 青色発光素子 |
JPH0715041A (ja) | 1993-06-28 | 1995-01-17 | Nichia Chem Ind Ltd | 窒化ガリウム系化合物半導体発光素子 |
JPH0936430A (ja) | 1995-02-23 | 1997-02-07 | Nichia Chem Ind Ltd | 窒化物半導体発光素子 |
JPH0964419A (ja) | 1995-08-28 | 1997-03-07 | Sumitomo Chem Co Ltd | 3−5族化合物半導体及び発光素子 |
JP2002280611A (ja) | 2001-03-21 | 2002-09-27 | Mitsubishi Cable Ind Ltd | 半導体発光素子 |
JP2003318441A (ja) | 2001-07-24 | 2003-11-07 | Nichia Chem Ind Ltd | 半導体発光素子 |
JP2005279807A (ja) | 2004-03-29 | 2005-10-13 | Toshiba Corp | 凸凹パターンの形成方法および凸凹パターン形成用部材 |
JP2007019318A (ja) | 2005-07-08 | 2007-01-25 | Sumitomo Chemical Co Ltd | 半導体発光素子、半導体発光素子用基板の製造方法及び半導体発光素子の製造方法 |
JP2007223864A (ja) * | 2006-02-24 | 2007-09-06 | Matsushita Electric Ind Co Ltd | 酸窒化物、酸窒化物蛍光体及びその酸窒化物蛍光体を用いた発光装置 |
WO2008001670A1 (fr) * | 2006-06-30 | 2008-01-03 | Oji Paper Co., Ltd. | Masque de gravure de film monoparticulaire et son procédé de production, procédé de production d'une structure fine avec un masque de gravure de film monoparticulaire et structure fine obtenue à l'aide du procédé de production |
JP2008522506A (ja) | 2004-11-29 | 2008-06-26 | 株式会社エヌ・ティ・ティ・ドコモ | ビデオ符号化における時間予測 |
JP2009162831A (ja) | 2007-12-28 | 2009-07-23 | Oji Paper Co Ltd | 凹凸パターンシート及びその製造方法、光学シートの製造方法、並びに光学装置 |
JP2009223154A (ja) * | 2008-03-18 | 2009-10-01 | Hoya Corp | 基板上に規則的に二次元配置した構造体、及びその形成方法 |
JP2011146522A (ja) * | 2010-01-14 | 2011-07-28 | Panasonic Corp | 基板の加工方法 |
JP2011187787A (ja) * | 2010-03-10 | 2011-09-22 | Toshiba Corp | 半導体発光素子、およびそれを用いた照明装置、ならびに半導体発光素子の製造方法 |
Family Cites Families (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4407695A (en) * | 1981-12-31 | 1983-10-04 | Exxon Research And Engineering Co. | Natural lithographic fabrication of microstructures over large areas |
EP0731490A3 (en) * | 1995-03-02 | 1998-03-11 | Ebara Corporation | Ultra-fine microfabrication method using an energy beam |
US6051149A (en) * | 1998-03-12 | 2000-04-18 | Micron Technology, Inc. | Coated beads and process utilizing such beads for forming an etch mask having a discontinuous regular pattern |
US6228538B1 (en) * | 1998-08-28 | 2001-05-08 | Micron Technology, Inc. | Mask forming methods and field emission display emitter mask forming methods |
US6143580A (en) * | 1999-02-17 | 2000-11-07 | Micron Technology, Inc. | Methods of forming a mask pattern and methods of forming a field emitter tip mask |
US6521541B2 (en) * | 2000-08-23 | 2003-02-18 | California Institute Of Technology | Surface preparation of substances for continuous convective assembly of fine particles |
US7005079B2 (en) * | 2003-04-07 | 2006-02-28 | Chungwha Picture Tubes, Ltd. | Manufacturing method of light-guiding apparatus for using in backlight of liquid crystal display |
EP1667241B1 (en) * | 2003-08-19 | 2016-12-07 | Nichia Corporation | Semiconductor light emitting diode and method of manufacturing the same |
KR20060127743A (ko) * | 2005-06-06 | 2006-12-13 | 스미토모덴키고교가부시키가이샤 | 질화물 반도체 기판과 그 제조 방법 |
JP2007273746A (ja) * | 2006-03-31 | 2007-10-18 | Sumitomo Chemical Co Ltd | 固体表面の微細加工方法および発光素子 |
SG140481A1 (en) * | 2006-08-22 | 2008-03-28 | Agency Science Tech & Res | A method for fabricating micro and nano structures |
KR100966367B1 (ko) * | 2007-06-15 | 2010-06-28 | 삼성엘이디 주식회사 | 반도체 발광소자 및 그의 제조방법 |
CN101420003B (zh) * | 2007-10-24 | 2011-11-30 | 泰谷光电科技股份有限公司 | 发光二极管的制造方法 |
EP2211374A4 (en) | 2007-11-16 | 2012-10-10 | Ulvac Inc | PROCESS FOR TREATING SUBSTRATE AND SUBSTRATE PROCESSED THEREBY |
US8946772B2 (en) * | 2008-02-15 | 2015-02-03 | Mitsubishi Chemical Corporation | Substrate for epitaxial growth, process for manufacturing GaN-based semiconductor film, GaN-based semiconductor film, process for manufacturing GaN-based semiconductor light emitting element and GaN-based semiconductor light emitting element |
KR101533296B1 (ko) * | 2008-07-08 | 2015-07-02 | 삼성전자주식회사 | 패턴 형성 기판을 구비한 질화물 반도체 발광소자 및 그제조방법 |
JP5311408B2 (ja) * | 2008-12-26 | 2013-10-09 | シャープ株式会社 | 窒化物半導体発光素子 |
JP5196403B2 (ja) * | 2009-03-23 | 2013-05-15 | 国立大学法人山口大学 | サファイア基板の製造方法、および半導体装置 |
TWI425643B (zh) * | 2009-03-31 | 2014-02-01 | Sony Corp | 固態攝像裝置及其製造方法、攝像裝置和抗反射結構之製造方法 |
WO2010120778A2 (en) | 2009-04-13 | 2010-10-21 | Sinmat, Inc. | Chemical mechanical fabrication (cmf) for forming tilted surface features |
TWI394873B (zh) * | 2009-04-27 | 2013-05-01 | Aurotek Corp | 具有週期結構之藍寶石基板之製造方法 |
WO2011027679A1 (ja) * | 2009-09-07 | 2011-03-10 | エルシード株式会社 | 半導体発光素子 |
JP5723377B2 (ja) * | 2009-11-09 | 2015-05-27 | スリーエム イノベイティブ プロパティズ カンパニー | 半導体のためのエッチングプロセス |
CN102754217B (zh) * | 2009-11-17 | 2016-07-06 | 3M创新有限公司 | 吸光基材的织构化表面 |
US8318604B2 (en) * | 2009-11-23 | 2012-11-27 | The Board Of Trustees Of The Leland Stanford Junior University | Substrate comprising a nanometer-scale projection array |
EP2387081B1 (en) * | 2010-05-11 | 2015-09-30 | Samsung Electronics Co., Ltd. | Semiconductor light emitting device and method for fabricating the same |
CN102259832A (zh) * | 2010-05-27 | 2011-11-30 | 清华大学 | 三维纳米结构阵列的制备方法 |
TWI540756B (zh) * | 2010-08-06 | 2016-07-01 | Nichia Corp | 藍寶石基板及半導體發光元件 |
KR20120029767A (ko) * | 2010-09-17 | 2012-03-27 | 엘지디스플레이 주식회사 | 반도체 발광소자 제조 방법 |
CN102064257A (zh) * | 2010-09-29 | 2011-05-18 | 苏州纳晶光电有限公司 | 一种蓝宝石图形衬底及其制备方法 |
CN102468392A (zh) * | 2010-11-17 | 2012-05-23 | 晶发光电股份有限公司 | 具有网状结构的发光二极管 |
KR101340845B1 (ko) * | 2011-01-13 | 2013-12-13 | 한국기계연구원 | 기능성 표면의 제조방법 |
WO2012176728A1 (ja) * | 2011-06-23 | 2012-12-27 | 旭化成株式会社 | 微細パタン形成用積層体及び微細パタン形成用積層体の製造方法 |
EP2942821A1 (en) * | 2012-04-02 | 2015-11-11 | Asahi Kasei E-materials Corporation | Optical substrate, semiconductor light-emitting element and method of manufacturing semiconductor light-emitting element |
-
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- 2013-08-22 TW TW102130111A patent/TWI599072B/zh active
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Patent Citations (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58120255A (ja) | 1981-12-31 | 1983-07-18 | エクソン・リサ−チ・アンド・エンジニアリング・カンパニ− | 平版印刷マスクの製造方法 |
JPH06260682A (ja) | 1993-01-08 | 1994-09-16 | Nichia Chem Ind Ltd | 青色発光素子 |
JPH0715041A (ja) | 1993-06-28 | 1995-01-17 | Nichia Chem Ind Ltd | 窒化ガリウム系化合物半導体発光素子 |
JPH0936430A (ja) | 1995-02-23 | 1997-02-07 | Nichia Chem Ind Ltd | 窒化物半導体発光素子 |
JPH0964419A (ja) | 1995-08-28 | 1997-03-07 | Sumitomo Chem Co Ltd | 3−5族化合物半導体及び発光素子 |
JP2002280611A (ja) | 2001-03-21 | 2002-09-27 | Mitsubishi Cable Ind Ltd | 半導体発光素子 |
JP2003318441A (ja) | 2001-07-24 | 2003-11-07 | Nichia Chem Ind Ltd | 半導体発光素子 |
JP2005279807A (ja) | 2004-03-29 | 2005-10-13 | Toshiba Corp | 凸凹パターンの形成方法および凸凹パターン形成用部材 |
JP2008522506A (ja) | 2004-11-29 | 2008-06-26 | 株式会社エヌ・ティ・ティ・ドコモ | ビデオ符号化における時間予測 |
JP2007019318A (ja) | 2005-07-08 | 2007-01-25 | Sumitomo Chemical Co Ltd | 半導体発光素子、半導体発光素子用基板の製造方法及び半導体発光素子の製造方法 |
JP2007223864A (ja) * | 2006-02-24 | 2007-09-06 | Matsushita Electric Ind Co Ltd | 酸窒化物、酸窒化物蛍光体及びその酸窒化物蛍光体を用いた発光装置 |
WO2008001670A1 (fr) * | 2006-06-30 | 2008-01-03 | Oji Paper Co., Ltd. | Masque de gravure de film monoparticulaire et son procédé de production, procédé de production d'une structure fine avec un masque de gravure de film monoparticulaire et structure fine obtenue à l'aide du procédé de production |
JP2009162831A (ja) | 2007-12-28 | 2009-07-23 | Oji Paper Co Ltd | 凹凸パターンシート及びその製造方法、光学シートの製造方法、並びに光学装置 |
JP2009223154A (ja) * | 2008-03-18 | 2009-10-01 | Hoya Corp | 基板上に規則的に二次元配置した構造体、及びその形成方法 |
JP2011146522A (ja) * | 2010-01-14 | 2011-07-28 | Panasonic Corp | 基板の加工方法 |
JP2011187787A (ja) * | 2010-03-10 | 2011-09-22 | Toshiba Corp | 半導体発光素子、およびそれを用いた照明装置、ならびに半導体発光素子の製造方法 |
Non-Patent Citations (4)
Title |
---|
JOURNAL OF MATERIALS AND CHEMISTRY, vol. 11, 2001, pages 3333 |
JOURNAL OF MATERIALS AND CHEMISTRY, vol. 12, 2002, pages 3268 |
NATURE, vol. 361, 26 January 1993 (1993-01-26), pages 7 |
TAKU SHINAGAWA; YUKI ABE; HIROYUKI MATSUMOTO; BOCHENG LI; KAZUMA MURAKAMI; NARIHITO OKADA; KAZUYUKI TADATOMO; MASATO KANNAKA; HIDE: "Light-emitting diodes fabricated on nanopatterned sapphire substrates by thermal lithography", 2010, WILEY-VCH VERLAG GMBH & CO. KGAA, article "Light-emitting diodes fabricated on nanopatterned sapphire substrates by thermal lithography" |
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Publication number | Publication date |
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TWI650879B (zh) | 2019-02-11 |
US20150221824A1 (en) | 2015-08-06 |
KR20150046032A (ko) | 2015-04-29 |
EP2889922A4 (en) | 2016-05-04 |
US20160197236A1 (en) | 2016-07-07 |
TWI599072B (zh) | 2017-09-11 |
CN104584243B (zh) | 2018-12-25 |
EP2889922B1 (en) | 2018-03-07 |
TW201735396A (zh) | 2017-10-01 |
US9515223B2 (en) | 2016-12-06 |
US9748441B2 (en) | 2017-08-29 |
TW201414009A (zh) | 2014-04-01 |
CN104584243A (zh) | 2015-04-29 |
CN108389944A (zh) | 2018-08-10 |
US20170309784A1 (en) | 2017-10-26 |
CN108389944B (zh) | 2021-04-02 |
EP2922103A1 (en) | 2015-09-23 |
EP2922103B1 (en) | 2017-04-05 |
JPWO2014030670A1 (ja) | 2016-07-28 |
EP2889922A1 (en) | 2015-07-01 |
JP6036830B2 (ja) | 2016-11-30 |
KR102019058B1 (ko) | 2019-09-06 |
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