WO2013105350A1 - 半導体装置とその製造方法 - Google Patents
半導体装置とその製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 211
- 238000004519 manufacturing process Methods 0.000 title claims description 29
- 239000000758 substrate Substances 0.000 claims abstract description 67
- 230000002093 peripheral effect Effects 0.000 claims description 53
- 229910052751 metal Inorganic materials 0.000 claims description 49
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- 239000003990 capacitor Substances 0.000 description 18
- 239000012535 impurity Substances 0.000 description 14
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- 238000009792 diffusion process Methods 0.000 description 9
- 210000000746 body region Anatomy 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
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- 238000000059 patterning Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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Abstract
Description
図14に示すように、変形例1のトレンチ電極42(42a~42c)は、X方向の幅がそれぞれ同一でない点で実施例2のトレンチ電極41と異なる。なお、トレンチ電極42は、隣接するトレンチ電極42の対向する面同士の間隔が略均等となるように配置される。この構成によっても、変形例1の半導体装置は、実施例2の半導体装置10aと同様の作用効果を有する。
図15に示すように、変形例2の半導体装置は、絶縁層58の上面に複数の電極74が形成されている点で実施例2の半導体装置10aと異なる。電極74は、絶縁層58の上面に形成され、絶縁層58の上面から突出しているトレンチ電極41に接触しないように配置されている。これにより、隣接する電極74同士でもコンデンサが形成される。この構成によれば、外来電荷が絶縁層58の上面に付着することを物理的に抑制するとともに、電極74により形成されるコンデンサにより、外来電荷が絶縁層58内に進入することを電気的に抑制することができる。従って、外来電荷に起因して耐圧が低下することをより抑制することができる。なお、電極74は、例えば、電極54,64を形成する金属と同一の金属(例えば、アルミニウム)により形成されるが、電極74を形成する物質はこれに限られない。例えば、電極74は、ポリシリコンにより形成してもよい。
図16に示すように、変形例3の半導体装置は、絶縁層58の上面に半導電性のシリコン窒化膜(いわゆるSInSiN膜)78が形成されている点で実施例2の半導体装置10aと異なる。半導電性シリコン窒化膜78は、電極54と電極64の間に位置しており、絶縁層58の上面に接触するとともに、電極54の一方の側面の少なくとも一部、及び電極64の一方の側面の少なくとも一部と接触するように形成されている。即ち、半導電性シリコン窒化膜78は、トレンチ電極41bを覆うように形成され、電極54,64に接続されている。この構成によれば、外来電荷が絶縁層58の上面に付着することを抑制することができ、外来電荷に起因して耐圧が低下することを抑制することができる。
図17に示すように、変形例4の半導体装置は、トレンチ電極41の下部に複数のp型拡散層80が形成されている点で実施例2の半導体装置10aと異なる。p型拡散層80は、リサーフ領域56及び周辺ドリフト領域30aに露出しているトレンチ電極41a、41bの下部に形成されている。即ち、p型拡散層80は、端部n型領域62に露出しているトレンチ電極41cの下部には形成されていない。p型拡散層80の不純物濃度は、リサーフ領域56のp型不純物濃度よりも高い。この構成によれば、電気力線が複数のp型拡散層80を回避して表面側へ抜ける。このため、トレンチ電極41a、41bの下端のコーナ部は曲線状でなくてもよく、例えば略直角であってもよい。
図19に示すように、変形例1のトレンチ電極44(44a1~44c1、44b2)は、X方向の幅がそれぞれ等しくない点で実施例3のトレンチ電極43と異なる。この場合でも、トレンチ電極44は、隣接するトレンチ電極44の対向する面同士の間隔が略均等となるように配置される。この構成によっても、実施例3の半導体装置10bと同様の作用効果を奏することができる。
図20に示すように、変形例2のトレンチ電極45(45a1~45c1、45b2)は、Z方向の幅がそれぞれ等しくない点で実施例3のトレンチ電極43と異なる。なお、各トレンチ電極43は、その上端又は下端の少なくとも一方が、絶縁層58の上面又は下面にそれぞれ露出している。この構成によっても、実施例3の半導体装置10bと同様の作用効果を奏することができる。
図21に示すように、変形例3の半導体装置は、絶縁層58の上面に複数の電極82が形成されている点で実施例3の半導体装置10bと異なる。電極82は、絶縁層58の上面から突出している上側トレンチ電極43に接触しないように形成されている。これにより、隣接する電極82同士がコンデンサを形成する。この構成によれば、外来電荷が絶縁層58の上面に付着することを物理的に抑制するとともに、電極82により形成されるコンデンサにより、外来電荷が絶縁層58内に進入することを電気的に抑制することができる。従って、外来電荷に起因して耐圧が低下することをより抑制することができる。なお電極82は、例えばアルミニウムやポリシリコン等により形成されるが、電極82を形成する物質はこれに限られない。
図22に示すように、変形例4の半導体装置は、絶縁層58の上面に半導電性のシリコン窒化膜(いわゆるSInSiN膜)86が形成されている点で実施例3の半導体装置10bと異なる。半導電性シリコン窒化膜86は、図16に示す変形例と同様、電極54と電極64の間に位置し、上側トレンチ電極43b1を覆うように形成されている。この構成によれば、外来電荷が絶縁層58の上面に付着することを抑制することができ、外来電荷に起因して耐圧が低下することを抑制することができる。
図23に示すように、変形例5の半導体装置は、下側トレンチ電極43b2の下部に複数のp型拡散層88が形成されている点で実施例3の半導体装置10bと異なる。p型拡散層88は、リサーフ領域56及び周辺ドリフト領域30aに露出している下側トレンチ電極43b2の下部に形成されている。p型拡散層88の不純物濃度は、リサーフ領域56のp型不純物濃度よりも高い。この構成によれば、電気力線が複数のp型拡散層80を回避して表面側へ抜ける。このため、トレンチ電極43b2の下端のコーナ部は曲線状でなくてもよい。
Claims (10)
- 半導体基板12を有する半導体装置10であって、
半導体基板12が、
半導体素子が形成されているアクティブ領域20と、
アクティブ領域20と半導体基板12の端面12aとの間の外周領域50、
を有しており、
外周領域50の少なくとも一部の上面に、絶縁層58が形成されており、
絶縁層58内に、半導体基板12の厚み方向における幅がアクティブ領域20から半導体基板12の端面12aに向かう方向における幅よりも大きい複数のフローティング電極40が、アクティブ領域20から半導体基板12の端面12aに向かう方向に沿って間隔を隔てて配置されている、
半導体装置。 - 絶縁層58内に配置されるフローティング電極41~45は、前記絶縁層58の上面または下面の少なくとも一方の面に露出していることを特徴とする請求項1に記載の半導体装置。
- 前記絶縁層58を前記厚み方向に直交する平面で切断した任意の断面において、アクティブ領域20から半導体基板12の端面12aに向かう任意の直線上に、少なくとも1つのフローティング電極41~45が存在することを特徴とする請求項1に記載の半導体装置。
- フローティング電極40は、前記絶縁層58の上面に露出しており、前記絶縁層58の下面には露出していないことを特徴とする、請求項1又は2に記載の半導体装置。
- フローティング電極41~42は、前記絶縁層58の上面及び下面に露出していることを特徴とする、請求項1から3のいずれか一項に記載の半導体装置。
- 絶縁層58内に配置される複数のフローティング電極43~45は、前記絶縁層58の上面に露出している第1フローティング電極43a1~43c1、44a1~44c1、45a1~45c1と、前記絶縁層58の下面に露出している第2フローティング電極43b2、44b2、45b2とを有しており、第1フローティング電極43a1~43c1、44a1~44c1、45a1~45c1と第2フローティング電極43b2、44b2、45b2が交互に配置されていることを特徴とする、請求項1又は2に記載の半導体装置。
- フローティング電極41~45をその長手方向と直交する平面で切断した断面において、フローティング電極41~45の下面と側面のコーナ部が曲線状となっていることを特徴とする、請求項1から6のいずれか一項に記載の半導体装置。
- 半導体装置の製造方法であって、
半導体基板のうちの半導体素子が形成されるアクティブ領域と半導体装置の端面となる箇所との間の外周領域上に絶縁層を形成する工程と、
絶縁層に、半導体基板の厚み方向における幅がアクティブ領域から半導体基板の端面となる箇所に向かう方向における幅よりも大きい複数のトレンチを、アクティブ領域から半導体装置の端面となる箇所に向かう方向に沿って間隔を隔てて形成する工程と、
絶縁層上に金属層を形成する工程と、
トレンチの上部の金属層をマスクしていない状態で、各トレンチ内に金属層が残存し、かつ、各トレンチ内の金属層が互いに分離されるように金属層をエッチングする工程、
を有する製造方法。 - 絶縁層を形成する工程では、アクティブ領域上にも絶縁層を形成し、
金属層を形成する工程の前に、アクティブ領域上の絶縁層にコンタクトホールを形成する工程をさらに有し、
金属層を形成する工程では、コンタクトホール内にも金属層を形成し、
金属層をエッチングする工程は、コンタクトホールの上部の金属層をマスクした状態で行う、
請求項8の製造方法。 - トレンチを形成する工程と、コンタクトホールを形成する工程を、共通のエッチングにより行う請求項9に記載の製造方法。
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015032664A (ja) * | 2013-08-01 | 2015-02-16 | 住友電気工業株式会社 | ワイドバンドギャップ半導体装置 |
WO2015040675A1 (ja) * | 2013-09-17 | 2015-03-26 | 株式会社日立製作所 | 半導体装置、電力変換装置、鉄道車両、および半導体装置の製造方法 |
US9412809B2 (en) | 2013-02-15 | 2016-08-09 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
JP2016171272A (ja) * | 2015-03-16 | 2016-09-23 | 株式会社東芝 | 半導体装置 |
JP2018078169A (ja) * | 2016-11-08 | 2018-05-17 | ローム株式会社 | 電子部品 |
DE102014005879B4 (de) | 2014-04-16 | 2021-12-16 | Infineon Technologies Ag | Vertikale Halbleitervorrichtung |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104205334B (zh) * | 2012-03-05 | 2017-09-01 | 三菱电机株式会社 | 半导体装置 |
JP2014204038A (ja) * | 2013-04-08 | 2014-10-27 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
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US11777027B2 (en) * | 2021-06-29 | 2023-10-03 | Sanken Electric Co., Ltd. | Semiconductor device |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001111034A (ja) * | 1999-10-07 | 2001-04-20 | Fuji Electric Co Ltd | プレーナ型半導体装置 |
JP2003188381A (ja) * | 2001-12-21 | 2003-07-04 | Denso Corp | 半導体装置 |
JP2005209983A (ja) | 2004-01-26 | 2005-08-04 | Mitsubishi Electric Corp | 半導体装置 |
JP2007123570A (ja) * | 2005-10-28 | 2007-05-17 | Toyota Industries Corp | 半導体装置 |
JP2008187125A (ja) * | 2007-01-31 | 2008-08-14 | Toshiba Corp | 半導体装置 |
JP2011040773A (ja) * | 2010-10-04 | 2011-02-24 | Mitsubishi Electric Corp | 半導体装置 |
JP2011077202A (ja) * | 2009-09-29 | 2011-04-14 | Fuji Electric Holdings Co Ltd | 半導体装置 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5607718A (en) * | 1993-03-26 | 1997-03-04 | Kabushiki Kaisha Toshiba | Polishing method and polishing apparatus |
JPH09283754A (ja) * | 1996-04-16 | 1997-10-31 | Toshiba Corp | 高耐圧半導体装置 |
JP3958404B2 (ja) * | 1997-06-06 | 2007-08-15 | 三菱電機株式会社 | 横型高耐圧素子を有する半導体装置 |
JP3850146B2 (ja) * | 1998-07-07 | 2006-11-29 | 三菱電機株式会社 | 分離構造とその分離構造を備える半導体装置 |
US7368785B2 (en) * | 2005-05-25 | 2008-05-06 | United Microelectronics Corp. | MOS transistor device structure combining Si-trench and field plate structures for high voltage device |
JP5050329B2 (ja) | 2005-08-26 | 2012-10-17 | サンケン電気株式会社 | トレンチ構造半導体装置及びその製造方法 |
JP2008227474A (ja) * | 2007-02-13 | 2008-09-25 | Toshiba Corp | 半導体装置 |
JP5315638B2 (ja) * | 2007-07-24 | 2013-10-16 | サンケン電気株式会社 | 半導体装置 |
JP5358963B2 (ja) * | 2008-02-04 | 2013-12-04 | 富士電機株式会社 | 半導体装置およびその製造方法 |
CN101414635B (zh) * | 2008-12-01 | 2010-08-11 | 西安电子科技大学 | 凹槽绝缘栅型栅-漏复合场板功率器件及其制作方法 |
CN102177587B (zh) * | 2008-12-10 | 2013-08-14 | 丰田自动车株式会社 | 半导体装置 |
JP5391447B2 (ja) | 2009-04-06 | 2014-01-15 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
JP5376365B2 (ja) * | 2009-04-16 | 2013-12-25 | 三菱電機株式会社 | 半導体装置 |
JP5543758B2 (ja) * | 2009-11-19 | 2014-07-09 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2011159903A (ja) * | 2010-02-03 | 2011-08-18 | Rohm Co Ltd | 半導体装置 |
CN102214689B (zh) | 2010-04-06 | 2012-11-07 | 上海华虹Nec电子有限公司 | 超级结器件的终端保护结构及其制造方法 |
-
2012
- 2012-11-27 CN CN201280066749.5A patent/CN104040720B/zh not_active Expired - Fee Related
- 2012-11-27 US US14/372,103 patent/US9385188B2/en active Active
- 2012-11-27 JP JP2013553204A patent/JP5772987B2/ja not_active Expired - Fee Related
- 2012-11-27 EP EP12865395.3A patent/EP2804214B1/en active Active
- 2012-11-27 WO PCT/JP2012/080624 patent/WO2013105350A1/ja active Application Filing
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001111034A (ja) * | 1999-10-07 | 2001-04-20 | Fuji Electric Co Ltd | プレーナ型半導体装置 |
JP2003188381A (ja) * | 2001-12-21 | 2003-07-04 | Denso Corp | 半導体装置 |
JP2005209983A (ja) | 2004-01-26 | 2005-08-04 | Mitsubishi Electric Corp | 半導体装置 |
JP2007123570A (ja) * | 2005-10-28 | 2007-05-17 | Toyota Industries Corp | 半導体装置 |
JP2008187125A (ja) * | 2007-01-31 | 2008-08-14 | Toshiba Corp | 半導体装置 |
JP2011077202A (ja) * | 2009-09-29 | 2011-04-14 | Fuji Electric Holdings Co Ltd | 半導体装置 |
JP2011040773A (ja) * | 2010-10-04 | 2011-02-24 | Mitsubishi Electric Corp | 半導体装置 |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9412809B2 (en) | 2013-02-15 | 2016-08-09 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
JP2015032664A (ja) * | 2013-08-01 | 2015-02-16 | 住友電気工業株式会社 | ワイドバンドギャップ半導体装置 |
WO2015040675A1 (ja) * | 2013-09-17 | 2015-03-26 | 株式会社日立製作所 | 半導体装置、電力変換装置、鉄道車両、および半導体装置の製造方法 |
DE102014005879B4 (de) | 2014-04-16 | 2021-12-16 | Infineon Technologies Ag | Vertikale Halbleitervorrichtung |
JP2016171272A (ja) * | 2015-03-16 | 2016-09-23 | 株式会社東芝 | 半導体装置 |
JP2018078169A (ja) * | 2016-11-08 | 2018-05-17 | ローム株式会社 | 電子部品 |
US11094443B2 (en) | 2016-11-08 | 2021-08-17 | Rohm Co., Ltd. | Electronic component |
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