WO2013047323A1 - 半導体装置の製造方法、半導体装置 - Google Patents

半導体装置の製造方法、半導体装置 Download PDF

Info

Publication number
WO2013047323A1
WO2013047323A1 PCT/JP2012/074075 JP2012074075W WO2013047323A1 WO 2013047323 A1 WO2013047323 A1 WO 2013047323A1 JP 2012074075 W JP2012074075 W JP 2012074075W WO 2013047323 A1 WO2013047323 A1 WO 2013047323A1
Authority
WO
WIPO (PCT)
Prior art keywords
seed layer
substrate
groove
semiconductor device
barrier layer
Prior art date
Application number
PCT/JP2012/074075
Other languages
English (en)
French (fr)
Inventor
純一 濱口
周司 小平
勇太 坂本
昭文 佐野
恒吉 鎌田
好之 門倉
廣石　城司
幸展 沼田
鈴木　康司
Original Assignee
株式会社アルバック
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社アルバック filed Critical 株式会社アルバック
Priority to KR1020137032923A priority Critical patent/KR20140070503A/ko
Priority to CN201280028713.8A priority patent/CN103620746A/zh
Priority to US14/347,779 priority patent/US9337092B2/en
Publication of WO2013047323A1 publication Critical patent/WO2013047323A1/ja

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/02—Pretreatment of the material to be coated
    • C23C14/024—Deposition of sublayers, e.g. to promote adhesion of the coating
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04—Coating on selected surface areas, e.g. using masks
    • C23C14/046—Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/14—Metallic material, boron or silicon
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/14—Metallic material, boron or silicon
    • C23C14/16—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/58—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a semiconductor device manufacturing method and a semiconductor device, and more particularly to a technique for forming fine wiring with high accuracy.
  • aluminum or an aluminum alloy has been used as a fine wiring material such as a semiconductor element formed on a substrate.
  • aluminum has a low melting point and poor migration resistance, it has been difficult to cope with high integration and high speed of semiconductor elements.
  • Patent Document 1 has a problem that it is difficult to embed copper without a gap in the groove. That is, when copper is laminated inside the groove by sputtering, copper is not deposited up to the inside of the fine groove, and copper is deposited only in the vicinity of the opening end of the groove while the inside of the groove is hollow.
  • the barrier metal layer formed in advance on the inner wall surface of the groove is poor in wettability with the molten copper, resulting in a cavity inside the groove.
  • copper solidified in the state Thus, when a cavity arises in the copper wiring formed in the inside of a groove
  • An aspect according to the present invention has been made to solve the above-described problem, and a method for manufacturing a semiconductor device capable of obtaining a wiring having excellent conductivity by embedding a conductive material in a minute groove without gaps, and An object is to provide a semiconductor device.
  • a method of manufacturing a semiconductor device includes a groove forming step of forming a groove in a base, a barrier layer forming step of forming a barrier layer covering at least an inner wall surface of the groove, and the barrier layer And a seed layer melting step for melting the seed layer by a reflow method, wherein the seed layer is made of Cu.
  • the seed layer forming step includes a step of forming a Cu thin film covering the barrier layer and a step of heat treating the Cu thin film, and the heat treatment is performed at 100 ° C. As described above, it may be performed in a temperature range of 400 ° C. or lower.
  • the seed layer forming step and the seed layer melting step are not only embedded in the groove by the seed layer forming step and the seed layer melting step once. You may repeat twice or more.
  • the barrier layer employs a configuration made of a material containing at least one of Ta, Ti, W, Ru, V, Co, and Nb. May be.
  • the base may include a semiconductor substrate and an insulating layer formed on one surface of the semiconductor substrate.
  • a semiconductor device includes a groove formed in a base, a barrier layer that covers an inner wall surface of the groove, and a conductor embedded in an inner region of the barrier layer, The conductor was formed by melting a seed layer made of Cu covering the barrier layer by a reflow method.
  • the seed layer made of Cu covering the barrier layer is melted by the reflow method, so that the Cu of the conductive material has cavities inside the groove portions. It is possible to obtain a highly accurate conductor that is uniformly distributed without occurrence and has no local disconnection.
  • FIG. 1 is an enlarged cross-sectional view showing a main part of a semiconductor device according to an embodiment of the present invention.
  • the semiconductor device 10 includes a base body 11.
  • the base 11 is composed of an insulating substrate such as a glass substrate or a resin substrate.
  • a semiconductor element or the like may be formed on a part of the base body 11.
  • a groove portion (trench) 12 is formed on one surface 11 a of the base 11.
  • the groove portion 12 is formed of, for example, a fine groove having a narrow width and a deep depth dug in the thickness direction of the base body 11 from the one surface 11a of the base body 11.
  • the width W of the bottom of the groove 12 is formed to be about 20 nm to 50 nm, for example.
  • the depth D of the groove 12 is formed to be about 80 nm to 200 nm, for example.
  • a conductor constituting the circuit wiring of the semiconductor element is formed in the inner region of the groove 12.
  • a barrier layer (barrier metal) 13 is formed so as to cover the inner wall surface 12a.
  • the barrier layer 13 includes, for example, Ta (tantalum) nitride, Ta silicide, Ta carbide, Ti (titanium) nitride, Ti silicide, Ti carbide, W (tungsten) nitride, W silicide, W carbide, Ru (Ruthenium), Ru oxide, V (vanadium) oxide, Co (cobalt) oxide, Nb (niobium) oxide, and the like.
  • the barrier layer (barrier metal) 13 is formed so that the thickness t1 is about 1 nm to 3 nm, for example.
  • a conductor 14 made of a conductive material is formed in an inner region of the barrier layer (barrier metal) 13 in the groove 12.
  • the conductor 14 is made of Cu (copper).
  • the conductor 14 is formed by embedding the groove 12 by forming a seed layer in an inner region of the barrier layer (barrier metal) 13 and melting (reflowing) the seed layer.
  • the conductor 14 is, for example, a circuit wiring of a semiconductor element formed on the base 11.
  • the seed layer made of Cu is formed in the inner region of the barrier layer (barrier metal) 13, and the conductor 14 is formed by melting (reflowing) the seed layer.
  • the conductor 14 is formed, the conductive material is embedded inside the groove 12 without a gap. Therefore, it is possible to realize the semiconductor device 10 including the conductor (circuit wiring) 14 made of Cu having uniform electric resistance and no fear of disconnection.
  • FIG. 2 and FIG. 3 are enlarged cross-sectional views showing the main part of the method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • the base 11 is prepared (see FIG. 2A).
  • an insulating substrate or a semiconductor substrate is used as the base 11.
  • the insulating substrate include a glass substrate and a resin substrate.
  • a semiconductor substrate a silicon wafer, a SiC wafer, etc. are mentioned, for example.
  • a semiconductor element (not shown) is formed on the base 11 in advance.
  • a groove portion 12 having a predetermined depth is formed on one surface 11a of the base 11 (see FIG. 2B: groove portion forming step).
  • the groove portion 12 is formed, for example, so as to have a pattern that represents a circuit wiring of a semiconductor element.
  • etching by photolithography or processing by laser light can be used as a method for forming the groove 12 on the one surface 11a of the base 11.
  • a barrier layer (barrier metal) 13 having a predetermined thickness is formed on one surface 11a of the base 11 including the inner wall surface 12a of the groove 12 (see FIG. 2C: barrier layer forming step).
  • the barrier layer (barrier metal) 13 is formed using a material containing at least one of Ta, Ti, W, Ru, V, Co, and Nb, for example.
  • a sputtering method or a CVD method is preferably used.
  • the barrier layer (barrier metal) 13 is formed so that the thickness t1 is about 1 nm to 3 nm, for example.
  • FIG. 4 shows an example of a sputtering apparatus (film forming apparatus) used for forming the barrier layer.
  • a sputtering apparatus (film forming apparatus) 1 includes a vacuum chamber 2, and a substrate holder 7 and a target 5 that are respectively disposed inside the vacuum chamber 2.
  • a vacuum evacuation system 9 and a gas supply system 4 are connected to the vacuum chamber 2, and the inside of the vacuum chamber 2 is evacuated and sputtered from the gas supply system 4 while evacuating, and nitrogen or oxygen in the chemical structure.
  • the reaction gas is oxygen
  • the flow rate is 0.1 sccm or more and 5 sccm or less
  • a film forming atmosphere lower than atmospheric pressure for example, the total pressure is 10 ⁇ 4 Pa or more and 10 to 10 sc ⁇ 1 Pa or less.
  • the substrate 11 is held by the substrate 11 in a state where the one surface 11 a side where the groove 12 is formed in the base 11 is directed to the target 5.
  • a sputtering power source 8 and a bias power source 6 are arranged outside the vacuum chamber 2, and the target 5 is connected to the sputtering power source 8 and the substrate holder 7 is connected to the bias power source 6.
  • the magnetic field forming means 3 is disposed outside the vacuum chamber 2, and when the negative voltage is applied to the target 5 while the vacuum chamber 2 is placed at the ground potential and the film forming atmosphere inside the vacuum chamber 2 is maintained, the target 5 is magnetron. Sputtered.
  • the target 5 is mainly composed of the material for forming the barrier layer (barrier metal) 13 described above. When the target 5 is magnetron sputtered, the material for forming the barrier layer 13 is released as sputtered particles.
  • the released sputtered particles and the reactive gas are incident on one surface 11 a where the groove portion 12 is formed on the base 11, and the barrier layer 13 is formed so as to cover the one surface 11 a including the inner wall surface 12 a of the groove 12.
  • a seed layer 15 is formed so as to cover the barrier layer 13 (see FIG. 3A: seed layer forming step).
  • the seed layer 15 is reflowed in the next step and becomes a conductive material embedded in the groove 12.
  • the seed layer 15 is made of Cu.
  • the seed layer 15 is formed using a sputtering method in the same manner as the barrier layer 13 described above.
  • the seed layer 15 is formed to have a thickness of about 15 nm to 55 nm, for example.
  • a method for forming the seed layer 15 using the sputtering apparatus (film forming apparatus) 1 will be described.
  • the inside of the vacuum chamber 2 is evacuated by the evacuation system 9, and sputter gas and nitrogen or oxygen are introduced into the chemical structure from the gas supply system 4 while evacuating.
  • a reaction gas containing oxygen is introduced (for example, when the reaction gas is oxygen, the flow rate is 0.1 sccm or more and 5 sccm or less), and a film-forming atmosphere lower than atmospheric pressure (for example, the total pressure is 10 ⁇ 4 Pa or more and 10 ⁇ 1 Pa or less).
  • the sputtering power source 8 is started to apply a negative voltage to the cathode electrode (not shown).
  • a predetermined pressure for example, 4.0 ⁇ 10 ⁇ 2 Pa pressure
  • the sputtering power source 8 is started to apply a negative voltage to the cathode electrode (not shown).
  • discharge is started, and the target 5 is made Cu, and plasma is generated near the surface of the target 5.
  • film formation by sputtering is performed for a predetermined time, a copper thin film is formed so as to cover the barrier layer 13, and then the substrate 11 is unloaded from the vacuum chamber 2.
  • a temperature adjusting means (not shown) is provided in the substrate holder 7 of the sputtering apparatus 1 described above, and the temperature of the base 11 is adjusted to a predetermined temperature when forming a copper thin film (for example, ⁇ 20 ° C.).
  • the magnetic field forming unit 3 is configured to move and rotate in parallel with the surface of the target 5, and a sputtered region (erosion region) on the surface of the target 5 is formed at an arbitrary position on the target. Can do.
  • the substrate 11 on which the seed layer 15 is formed is heated to a temperature equal to or higher than the melting temperature of the seed layer 15 to perform reflow (see FIG. 3B: seed layer melting step).
  • the seed layer 15 is melted and the inside of the groove 12, that is, the inner region of the barrier layer 13 is filled with the conductive material M made of Cu.
  • the melting temperature of the seed layer 15 is, for example, 100 ° C. or more and 400 ° C. or less.
  • the inner region of the barrier layer 13 is not sufficiently filled with the conductive material M made of Cu, it is preferable to repeat the seed layer forming step and the seed layer melting step twice or more. Thereby, it is possible to more reliably fill the inner region of the barrier layer 13 with the conductive material M made of Cu.
  • the barrier layer 13 and the conductive material M stacked on the one surface 11a of the substrate 11 excluding the groove 12 are removed (see FIG. 3C).
  • a conductor 14 that embeds the groove 12, that is, a circuit wiring, is formed for each groove 12.
  • Example 1 A silicon substrate with a silicon oxide film having a thickness of 0.775 mm was prepared as a substrate. Next, a groove having a depth of 100 nm was formed on one surface of the substrate by etching using photolithography. Next, a barrier layer made of Ta having a thickness of 3 nm was formed on one surface of the substrate including the inner wall surface of the groove by sputtering. Next, a seed layer copper thin film having a thickness of 25 nm was formed by a sputtering method so as to cover the barrier layer. When forming the copper thin film, the temperature of the substrate was adjusted to ⁇ 20 ° C.
  • the substrate on which the seed layer was formed was heated to 400 ° C., and the seed layer was melted to embed a conductive material made of Cu in the groove portion, that is, the inner region of the barrier layer.
  • the filling ratio of the groove portion (ratio in which the groove portion is filled with Cu, volume%) is measured using a scanning electron microscope (SEM). Examined. The case where the filling rate was 90% or more was evaluated as ⁇ , the case where the filling rate was 80% or more and less than 90% was evaluated as ⁇ , and the case where the filling rate was less than 80% was evaluated as ⁇ .
  • SEM scanning electron microscope
  • Example 2 Cu was filled in the groove portion of the substrate in the same manner as in Experimental Example 1 except that a seed layer made of Cu having a thickness of 35 nm was formed. Further, in the same manner as in Experimental Example 1, the filling rate of the grooves was examined. The results are shown in Table 1.
  • Example 3 Cu was filled in the groove portion of the substrate in the same manner as in Experimental Example 1 except that a seed layer made of Cu having a thickness of 45 nm was formed. Further, in the same manner as in Experimental Example 1, the filling rate of the grooves was examined. The results are shown in Table 1.
  • Example 4 A substrate was filled with a conductor in the same manner as in Experimental Example 1 except that the substrate on which the seed layer was formed was heated to 300 ° C., the seed layer was melted, and Cu was embedded inside the groove. Further, in the same manner as in Experimental Example 1, the filling rate of the grooves was examined. The results are shown in Table 1.
  • Example 5 A seed layer made of Cu having a thickness of 35 nm was formed, and the substrate on which the seed layer was formed was heated to 300 ° C., and the seed layer was melted to embed Cu inside the groove portion. The conductor was filled in the groove portion of the substrate. Further, in the same manner as in Experimental Example 1, the filling rate of the grooves was examined. The results are shown in Table 1.
  • Example 6 A seed layer made of Cu having a thickness of 45 nm was formed, and the substrate on which the seed layer was formed was heated to 300 ° C., and the seed layer was melted to embed Cu inside the groove portion. The conductor was filled in the groove portion of the substrate. Further, in the same manner as in Experimental Example 1, the filling rate of the grooves was examined. The results are shown in Table 1.
  • Example 7 A seed layer made of Cu having a thickness of 55 nm was formed, and the substrate on which the seed layer was formed was heated to 300 ° C., and the seed layer was melted to embed Cu inside the groove portion. The conductor was filled in the groove portion of the substrate. Further, in the same manner as in Experimental Example 1, the filling rate of the grooves was examined. The results are shown in Table 1.
  • Example 8 A substrate was filled with a conductor in the same manner as in Experimental Example 1 except that the substrate on which the seed layer was formed was heated to 200 ° C., the seed layer was melted, and Cu was embedded inside the groove. Further, in the same manner as in Experimental Example 1, the filling rate of the grooves was examined. The results are shown in Table 1.
  • Example 9 A seed layer made of Cu having a thickness of 35 nm was formed, and the substrate on which the seed layer was formed was heated to 200 ° C., and the seed layer was melted to embed Cu inside the groove portion. The conductor was filled in the groove portion of the substrate. Further, in the same manner as in Experimental Example 1, the filling rate of the grooves was examined. The results are shown in Table 1.
  • Example 10 A seed layer made of Cu having a thickness of 45 nm was formed, and the substrate on which the seed layer was formed was heated to 200 ° C., and the seed layer was melted to embed Cu inside the groove portion. The conductor was filled in the groove portion of the substrate. Further, in the same manner as in Experimental Example 1, the filling rate of the grooves was examined. The results are shown in Table 1.
  • Example 11 A silicon substrate with a silicon oxide film having a thickness of 0.775 mm was prepared as a substrate. Next, a groove having a depth of 100 nm was formed on one surface of the substrate by etching using photolithography. Next, a barrier layer made of Ta having a thickness of 3 nm was formed on one surface of the substrate including the inner wall surface of the groove by sputtering. Next, a copper thin film having a thickness of 25 nm was formed by sputtering so as to cover the barrier layer. When forming the copper thin film, the temperature of the substrate was adjusted to ⁇ 20 ° C.
  • the substrate on which the seed layer was formed was heated to 400 ° C., and the seed layer was melted to embed a conductive material made of Cu in the groove portion, that is, the inner region of the barrier layer.
  • a copper thin film was formed in the inner region of the barrier layer by sputtering.
  • the temperature of the substrate was adjusted to ⁇ 20 ° C.
  • the substrate on which the seed layer was formed was heated to 400 ° C., and the seed layer was melted to embed a conductive material made of Cu inside the groove. Thereafter, in the same manner as in Experimental Example 1, the filling rate of the grooves was examined. The results are shown in Table 2.
  • Example 12 A substrate was filled with a conductor in the same manner as in Experimental Example 11 except that the substrate on which the seed layer was formed was heated to 350 ° C., the seed layer was melted, and Cu was embedded inside the groove. Further, in the same manner as in Experimental Example 1, the filling rate of the grooves was examined. The results are shown in Table 2.
  • Example 13 A seed layer made of Cu having a thickness of 35 nm was formed, and the substrate on which the seed layer was formed was heated to 350 ° C., and the seed layer was melted to embed Cu inside the groove portion. The conductor was filled in the groove portion of the substrate. Further, in the same manner as in Experimental Example 1, the filling rate of the grooves was examined. The results are shown in Table 2.
  • Example 14 A seed layer made of Cu having a thickness of 40 nm was formed, and the substrate on which the seed layer was formed was heated to 350 ° C., and the seed layer was melted to embed Cu inside the groove portion. The conductor was filled in the groove portion of the substrate. Further, in the same manner as in Experimental Example 1, the filling rate of the grooves was examined. The results are shown in Table 2.
  • Example 15 A seed layer made of Cu having a thickness of 15 nm was formed, and the substrate on which the seed layer was formed was heated to 300 ° C., and the seed layer was melted to embed Cu inside the groove portion. The conductor was filled in the groove portion of the substrate. Further, in the same manner as in Experimental Example 1, the filling rate of the grooves was examined. The results are shown in Table 2.
  • Example 16 The substrate in which the seed layer was formed was heated to 300 ° C., and the conductor was filled in the groove portion of the substrate in the same manner as in Experimental Example 11 except that the seed layer was melted and Cu was embedded inside the groove portion. Further, in the same manner as in Experimental Example 1, the filling rate of the grooves was examined. The results are shown in Table 2.
  • Example 17 A seed layer made of Cu having a thickness of 35 nm was formed, and the substrate on which the seed layer was formed was heated to 300 ° C., and the seed layer was melted to embed Cu inside the groove portion. The conductor was filled in the groove portion of the substrate. Further, in the same manner as in Experimental Example 1, the filling rate of the grooves was examined. The results are shown in Table 2.
  • Example 18 A seed layer made of Cu having a thickness of 40 nm was formed, and the substrate on which the seed layer was formed was heated to 300 ° C., and the seed layer was melted to embed Cu inside the groove portion. The conductor was filled in the groove portion of the substrate. Further, in the same manner as in Experimental Example 1, the filling rate of the grooves was examined. The results are shown in Table 2.
  • Example 19 A seed layer made of Cu having a thickness of 45 nm was formed, and the substrate on which the seed layer was formed was heated to 300 ° C., and the seed layer was melted to embed Cu inside the groove portion. The conductor was filled in the groove portion of the substrate. Further, in the same manner as in Experimental Example 1, the filling rate of the grooves was examined. The results are shown in Table 2.
  • Example 20 A substrate was filled with a conductor in the same manner as in Experimental Example 11 except that the substrate on which the seed layer was formed was heated to 250 ° C., the seed layer was melted, and Cu was embedded inside the groove. Further, in the same manner as in Experimental Example 1, the filling rate of the grooves was examined. The results are shown in Table 2.
  • Example 21 A seed layer made of Cu having a thickness of 35 nm was formed, and the substrate on which the seed layer was formed was heated to 250 ° C., and the seed layer was melted to embed Cu inside the groove portion. The conductor was filled in the groove portion of the substrate. Further, in the same manner as in Experimental Example 1, the filling rate of the grooves was examined. The results are shown in Table 2.
  • Example 22 A seed layer made of Cu having a thickness of 40 nm was formed, and the substrate on which the seed layer was formed was heated to 250 ° C., and the seed layer was melted to embed Cu inside the groove portion. The conductor was filled in the groove portion of the substrate. Further, in the same manner as in Experimental Example 1, the filling rate of the grooves was examined. The results are shown in Table 2.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Organic Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Mechanical Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

　半導体装置の製造方法は、基体に溝部を形成する溝部形成工程と、少なくとも前記溝部の内壁面を覆うバリア層を形成するバリア層形成工程と、前記バリア層を覆うシード層を形成するシード層形成工程と、前記シード層をリフロー法によって溶融させるシード層溶融工程と、を備え、前記シード層はＣｕからなる。

Description

半導体装置の製造方法、半導体装置
　本発明は、半導体装置の製造方法、半導体装置に関し、詳しくは微細な配線を高精度に形成する技術に関する。
　本願は、２０１１年９月３０日に、日本に出願された日本国特願２０１１－２１５８４７号に基づき優先権を主張し、その内容をここに援用する。
　従来、基板に形成した半導体素子等の微細な配線材料として、アルミニウムやアルミニウム合金が用いられていた。しかし、アルミニウムは融点が低く、かつ耐マイグレーション性に劣るため、半導体素子の高集積化、高速化への対応が困難であった。
　このため、近年は配線材料として、銅が用いられるようになっている。銅はアルミニウムより融点が高く、かつ電気抵抗率も低いため、ＬＳＩ配線材料として有力である。しかし、配線材料として銅を用いる際には微細加工が困難であるという課題があった。例えば、特許文献１には、絶縁層に溝を形成し、この溝の内部に銅を埋め込み、その後、溝からはみ出した余分な銅を除去することにより、微細な溝内に銅配線を形成する方法が提案されている。
日本国特公平６－１０３６８１号公報
　しかしながら、特許文献１に記載された発明では、溝の内部に隙間無く銅を埋め込むことが困難であるという課題があった。
　即ち、溝の内部にスパッタリングによって銅を積層する場合、微細な溝の内部まで銅が堆積せず、溝の内部は空洞のまま溝の開口端付近だけ銅が堆積してしまう。
　また、リフロー法によって溝の内部を溶融した銅によって埋め込む場合、溝の内壁面に予め形成されるバリアメタル層に対して、溶融した銅との濡れ性が悪く、溝の内部に空洞が生じた状態で銅が固化するという課題があった。
　このように溝の内部に形成した銅配線に空洞が生じると、銅配線の抵抗値が高くなり、断線の虞もある。
　本発明に係る態様は上記課題を解決するためになされたものであり、微細な溝部の内部に隙間無く導電材料を埋め込み、導電性に優れた配線を得ることが可能な半導体装置の製造方法および半導体装置を提供することを目的とする。
　上記課題を解決するために、本発明は次のような半導体装置の製造方法、半導体装置を採用した。
（１）本発明に係る一態様の半導体装置の製造方法は、基体に溝部を形成する溝部形成工程と、少なくとも前記溝部の内壁面を覆うバリア層を形成するバリア層形成工程と、前記バリア層を覆うシード層を形成するシード層形成工程と、前記シード層をリフロー法によって溶融させるシード層溶融工程と、を備え、前記シード層はＣｕからなる。
（２）上記（１）の態様において、前記シード層形成工程は、前記バリア層を覆うＣｕ薄膜を形成する工程と、前記Ｃｕ薄膜を熱処理する工程と、を有し、前記熱処理が、１００℃以上、４００℃以下の温度範囲で行われてもよい。
（３）上記（１）または（２）の態様において、１回の前記シード層形成工程および前記シード層溶融工程で溝内部を埋め込むだけでなく、前記シード層形成工程および前記シード層溶融工程を２回以上繰り返してもよい。
（４）上記（１）から（３）いずれかに記載の態様において、前記バリア層は、Ｔａ，Ｔｉ，Ｗ，Ｒｕ，Ｖ，Ｃｏ，Ｎｂのうち、少なくとも一種を含む材料からなる構成を採用してもよい。
（５）上記（１）から（４）いずれかに記載の態様において、前記基体は、半導体基板と、前記半導体基板の一面に形成された絶縁層とからなる構成を採用してもよい。
（６）本発明に係る一態様の半導体装置は、基体に形成された溝部と、前記溝部の内壁面を覆うバリア層と、前記バリア層の内側領域に埋め込まれた導電体と、を備え、前記導電体は、前記バリア層を覆うＣｕからなるシード層をリフロー法によって溶融させて形成された。
　本発明に係る上記態様の半導体装置の製造方法および半導体装置によれば、バリア層を覆うＣｕからなるシード層をリフロー法によって溶融させるので、導電材料のＣｕが溝部の隅々まで内部に空洞を生じることなく均一に行き渡り、局所的な断線部分のない高精度な導電体を得ることができる。
本発明に係る一実施形態の半導体装置を示す要部拡大断面図である。 本発明に係る一実施形態の半導体装置の製造方法を段階的に示した要部拡大断面図である。 本発明に係る一実施形態の半導体装置の製造方法を段階的に示した要部拡大断面図である。 本発明に係る実施形態で用いられるスパッタリング装置（成膜装置）の一例を示す模式図である。
　以下、本発明に係る実施形態の半導体装置の製造方法および半導体装置について、図面に基づき説明する。なお、本実施形態は発明の趣旨をより良く理解させるために、一例を挙げて説明するものであり、特に指定のない限り、本発明を限定するものではない。また、以下の説明で用いる図面は、本発明の特徴をわかりやすくするために、便宜上、要部となる部分を拡大して示している場合があり、各構成要素の寸法比率などが実際と同じであるとは限らない。
（半導体装置）
　図１は、本発明に係る一実施形態の半導体装置を示す要部拡大断面図である。
　半導体装置１０は、基体１１を備えている。基体１１は、絶縁性基板、例えばガラス基板、樹脂基板などから構成される。なお、この基体１１の一部に、例えば半導体素子等が形成されていてもよい。
　基体１１の一面１１ａには、溝部（トレンチ）１２が形成されている。溝部１２は、例えば、基体１１の一面１１ａから基体１１の厚み方向に掘り下げられた幅が細く、かつ深い微細な溝からなる。溝部１２の底部の幅Ｗは、例えば２０ｎｍ～５０ｎｍ程度になるように形成される。また、溝部１２の深さＤは、例えば８０ｎｍ～２００ｎｍ程度になるように形成される。このような溝部１２の内側領域に、例えば半導体素子の回路配線を構成する導電体が形成される。
　溝部１２には、内壁面１２ａを覆うように、バリア層（バリアメタル）１３が形成されている。バリア層１３は、例えば、Ｔａ（タンタル）窒化物、Ｔａ珪化物、Ｔａ炭化物、Ｔｉ（チタン）窒化物、Ｔｉ珪化物、Ｔｉ炭化物、Ｗ（タングステン）窒化物、Ｗ珪化物、Ｗ炭化物、Ｒｕ（ルテニウム）、およびＲｕ酸化物、Ｖ（バナジウム）酸化物、Ｃｏ（コバルト）酸化物，Ｎｂ（ニオブ）酸化物などから構成される。
　バリア層（バリアメタル）１３は、厚みｔ１が例えば１ｎｍ～３ｎｍ程度になるように形成される。
　更に、溝部１２におけるバリア層（バリアメタル）１３の内側領域には、導電材料からなる導電体１４が形成されている。導電体１４は、Ｃｕ（銅）から構成されている。この導電体１４は、バリア層（バリアメタル）１３の内側領域にシード層を形成し、このシード層を溶融（リフロー）することによって、溝部１２を埋め込むことにより形成する。
　導電体１４は、例えば、基体１１に形成された半導体素子の回路配線となる。
　このような構成の半導体装置１０によれば、バリア層（バリアメタル）１３の内側領域に、Ｃｕからなるシード層を形成し、このシード層を溶融（リフロー）して導電体１４を形成することによって、導電体１４の形成時に、導電材料が溝部１２の内側を隙間無く埋め込まれる。よって、電気抵抗が均一で、かつ断線などの懸念の無いＣｕからなる導電体（回路配線）１４を備えた半導体装置１０が実現できる。
（半導体装置の製造方法）
　図２、図３は、本発明に係る一実施形態の半導体装置の製造方法を段階的に示した要部拡大断面図である。
　本発明に係る実施形態の半導体装置を製造する際には、まず、基体１１を用意する（図２（ａ）参照）。基体１１としては、絶縁性基板、半導体基板が用いられる。絶縁性基板としては、例えば、ガラス基板、樹脂基板が挙げられる。また、半導体基板としては、例えば、シリコンウェーハ、ＳｉＣウェーハなどが挙げられる。基体１１には、例えば、予め半導体素子（図示略）が形成されている。
　次に、この基体１１の一面１１ａに、所定の深さの溝部１２を形成する（図２（ｂ）参照：溝部形成工程）。溝部１２は、例えば、半導体素子の回路配線を象ったパターンとなるように形成される。基体１１の一面１１ａに溝部１２を形成する方法としては、例えば、フォトリソグラフィーによるエッチング加工や、レーザー光による加工を用いることができる。
　次に、溝部１２の内壁面１２ａを含む基体１１の一面１１ａに、所定の厚みのバリア層（バリアメタル）１３を形成する（図２（ｃ）参照：バリア層形成工程）。バリア層（バリアメタル）１３は、例えば、Ｔａ、Ｔｉ、Ｗ、Ｒｕ、Ｖ、Ｃｏ、Ｎｂのうちの少なくとも１種を含む材料を用いて形成する。バリア層１３の形成は、例えば、スパッタリング法やＣＶＤ法を用いることが好ましい。また、バリア層（バリアメタル）１３は、厚みｔ１が例えば１ｎｍ～３ｎｍ程度になるように形成される。
　図４は、バリア層の形成に用いるスパッタリング装置（成膜装置）の一例を示している。
　スパッタリング装置（成膜装置）１は、真空槽２と、真空槽２内部にそれぞれ配置された基板ホルダ７およびターゲット５とを有している。
　真空槽２には真空排気系９とガス供給系４とが接続されており、真空槽２内部を真空排気し、真空排気しながらガス供給系４からスパッタガスと、化学構造中に窒素又は酸素を含む反応ガスを導入し（例えば反応ガスが酸素の場合、流量が０．１ｓｃｃｍ以上５ｓｃｃｍ以下）、真空槽２内部に大気圧よりも低い成膜雰囲気（例えば全圧が１０－４Ｐａ以上１０－１Ｐａ以下）を形成する。
　そして、基体１１に溝部１２が形成された一面１１ａ側をターゲット５に向けた状態で基板ホルダ７に保持させておく。真空槽２の外部にはスパッタ電源８とバイアス電源６がそれぞれ配置され、ターゲット５はスパッタ電源８に、基板ホルダ７はバイアス電源６にそれぞれ接続されている。
　真空槽２の外部に磁界形成手段３が配置されており、真空槽２を接地電位に置き、真空槽２内部の成膜雰囲気を維持しながら、ターゲット５に負電圧を印加するとターゲット５はマグネトロンスパッタされる。ターゲット５は、上述したバリア層（バリアメタル）１３の形成材料が主成分とされる。
　そして、ターゲット５がマグネトロンスパッタされると、バリア層１３の形成材料がスパッタ粒子として放出される。
　放出されたスパッタ粒子と、反応ガスは基体１１に溝部１２が形成された一面１１ａに入射し、溝部１２の内壁面１２ａを含む基体１１の一面１１ａを覆うようにバリア層１３が形成される。
　次に、バリア層１３を覆うようにシード層１５を形成する（図３（ａ）参照：シード層形成工程）。このシード層１５は、次工程においてリフローされ、溝部１２に埋め込まれる導電材料となる。シード層１５は、Ｃｕから構成される。シード層１５は、上述したバリア層１３と同様に、スパッタリング法を用いて形成される。シード層１５は、例えば厚みが１５ｎｍ～５５ｎｍ程度になるように形成される。
　スパッタリング装置（成膜装置）１を用いたシード層１５の形成方法について説明する。
　まず、基板ホルダ７上に基体１１を配置した状態で、真空排気系９により真空槽２内部を真空排気し、真空排気しながらガス供給系４からスパッタガスと、化学構造中に窒素又は酸素を含む反応ガスを導入し（例えば反応ガスが酸素の場合、流量が０．１ｓｃｃｍ以上５ｓｃｃｍ以下）、真空槽２内部に大気圧よりも低い成膜雰囲気（例えば全圧が１０－４Ｐａ以上１０－１Ｐａ以下）を形成する。
　スパッタガスを導入し、真空槽２内が所定の圧力（例えば４．０×１０－２Ｐａの圧力）に安定した後、スパッタ電源８を起動して、カソード電極（図示略）に負電圧を印加することにより、放電が開始され、ターゲット５をＣｕとして、ターゲット５の表面近傍にプラズマを発生させる。
　そして、スパッタリングによる成膜を所定時間行い、バリア層１３を覆うように銅薄膜を形成した後、真空槽２から基体１１を搬出する。
　なお、上述のスパッタリング装置１の基板ホルダ７内には温度調節手段（図示略）が設けられており、銅薄膜を形成する際、基体１１の温度を所定の温度に調節しておく（例えば－２０℃）。
　スパッタリング装置１では、磁界形成手段３がターゲット５表面と平行に移動・回転できるように構成されており、ターゲット５表面のスパッタされる領域（エロージョン領域）をターゲット上の任意の位置に形成させることができる。
　次に、シード層１５を形成した基体１１を、シード層１５の溶融温度以上に加熱してリフローを行う（図３（ｂ）参照：シード層溶融工程）。これにより、シード層１５は溶融して溝部１２の内側、即ちバリア層１３の内側領域がＣｕからなる導電材料Ｍによって埋め込まれる。
　シード層１５の溶融温度を、例えば、１００℃以上、４００℃以下とする。
　なお、バリア層１３の内側領域へのＣｕからなる導電材料Ｍの充填が十分でない場合には、シード層形成工程およびシード層溶融工程を２回以上繰り返すことが好ましい。これにより、より確実に、バリア層１３の内側領域へＣｕからなる導電材料Ｍを充填することができる。
　この後、溝部１２を除いた基体１１の一面１１ａに積層されているバリア層１３、導電材料Ｍを除去する（図３（ｃ）参照）。これによって、それぞれの溝部１２ごとに、溝部１２を埋め込む導電体１４、即ち回路配線が形成される。
　以下、実験例により本発明に係る実施形態をさらに具体的に説明するが、本発明は以下の実験例に限定されるものではない。
「実験例１」
　基体として厚み０．７７５ｍｍのシリコン酸化膜付シリコン基板を用意した。
　次に、この基体の一面に、フォトリソグラフィーによるエッチング加工により、深さ１００ｎｍの溝部を形成した。
　次に、溝部の内壁面含む基体の一面に、スパッタリング法により、厚みの３ｎｍのＴａからなるバリア層を形成した。
　次に、バリア層を覆うように、スパッタリング法により、厚み２５ｎｍのシード層銅薄膜を形成した。銅薄膜を形成する際、基体の温度を－２０℃に調節した。
　次に、シード層を形成した基体を４００℃に加熱して、シード層を溶融して溝部の内側、即ちバリア層の内側領域にＣｕからなる導電材料を埋め込んだ。
　バリア層の内側領域にＣｕからなる導電材料を埋め込んだ後、その基体について、走査型電子顕微鏡（ＳＥＭ）を用いて、溝部の充填率（溝部がＣｕによって充填されている割合、体積％）を調べた。
　なお、充填率が９０％以上の場合を○、充填率が８０％以上９０％未満の場合を△、充填率が８０％未満の場合を×と評価した。
　結果を表１に示す。
「実験例２」
　厚み３５ｎｍのＣｕからなるシード層を形成したこと以外は実験例１と同様にして、基体の溝部内にＣｕを充填した。
　また、実験例１と同様にして、溝部の充填率を調べた。
　結果を表１に示す。
「実験例３」
　厚み４５ｎｍのＣｕからなるシード層を形成したこと以外は実験例１と同様にして、基体の溝部内にＣｕを充填した。
　また、実験例１と同様にして、溝部の充填率を調べた。
　結果を表１に示す。
「実験例４」
　シード層を形成した基体を３００℃に加熱して、シード層を溶融して溝部の内側にＣｕを埋め込んだこと以外は実験例１と同様にして、基体の溝部内に導電体を充填した。
　また、実験例１と同様にして、溝部の充填率を調べた。
　結果を表１に示す。
「実験例５」
　厚み３５ｎｍのＣｕからなるシード層を形成し、シード層を形成した基体を３００℃に加熱して、シード層を溶融して溝部の内側にＣｕを埋め込んだこと以外は実験例１と同様にして、基体の溝部内に導電体を充填した。
　また、実験例１と同様にして、溝部の充填率を調べた。
　結果を表１に示す。
「実験例６」
　厚み４５ｎｍのＣｕからなるシード層を形成し、シード層を形成した基体を３００℃に加熱して、シード層を溶融して溝部の内側にＣｕを埋め込んだこと以外は実験例１と同様にして、基体の溝部内に導電体を充填した。
　また、実験例１と同様にして、溝部の充填率を調べた。
　結果を表１に示す。
「実験例７」
　厚み５５ｎｍのＣｕからなるシード層を形成し、シード層を形成した基体を３００℃に加熱して、シード層を溶融して溝部の内側にＣｕを埋め込んだこと以外は実験例１と同様にして、基体の溝部内に導電体を充填した。
　また、実験例１と同様にして、溝部の充填率を調べた。
　結果を表１に示す。
「実験例８」
　シード層を形成した基体を２００℃に加熱して、シード層を溶融して溝部の内側にＣｕを埋め込んだこと以外は実験例１と同様にして、基体の溝部内に導電体を充填した。
　また、実験例１と同様にして、溝部の充填率を調べた。
　結果を表１に示す。
「実験例９」
　厚み３５ｎｍのＣｕからなるシード層を形成し、シード層を形成した基体を２００℃に加熱して、シード層を溶融して溝部の内側にＣｕを埋め込んだこと以外は実験例１と同様にして、基体の溝部内に導電体を充填した。
　また、実験例１と同様にして、溝部の充填率を調べた。
　結果を表１に示す。
「実験例１０」
　厚み４５ｎｍのＣｕからなるシード層を形成し、シード層を形成した基体を２００℃に加熱して、シード層を溶融して溝部の内側にＣｕを埋め込んだこと以外は実験例１と同様にして、基体の溝部内に導電体を充填した。
　また、実験例１と同様にして、溝部の充填率を調べた。
　結果を表１に示す。
「実験例１１」
　基体として厚み０．７７５ｍｍのシリコン酸化膜付シリコン基板を用意した。
　次に、この基体の一面に、フォトリソグラフィーによるエッチング加工により、深さ１００ｎｍの溝部を形成した。
　次に、溝部の内壁面含む基体の一面に、スパッタリング法により、厚みの３ｎｍのＴａからなるバリア層を形成した。
　次に、バリア層を覆うように、スパッタリング法により、厚み２５ｎｍの銅薄膜を形成した。銅薄膜を形成する際、基体の温度を－２０℃に調節した。
　次に、シード層を形成した基体を４００℃に加熱して、シード層を溶融して溝部の内側、即ちバリア層の内側領域にＣｕからなる導電材料を埋め込んだ。
　再び、バリア層の内側領域に、スパッタリング法により、銅薄膜を形成した。銅薄膜を形成する際、基体の温度を－２０℃に調節した。
　次に、シード層を形成した基体を４００℃に加熱して、シード層を溶融して溝部の内側にＣｕからなる導電材料を埋め込んだ。
　その後、実験例１と同様にして、溝部の充填率を調べた。
　結果を表２に示す。
「実験例１２」
　シード層を形成した基体を３５０℃に加熱して、シード層を溶融して溝部の内側にＣｕを埋め込んだこと以外は実験例１１と同様にして、基体の溝部内に導電体を充填した。
　また、実験例１と同様にして、溝部の充填率を調べた。
　結果を表２に示す。
「実験例１３」
　厚み３５ｎｍのＣｕからなるシード層を形成し、シード層を形成した基体を３５０℃に加熱して、シード層を溶融して溝部の内側にＣｕを埋め込んだこと以外は実験例１１と同様にして、基体の溝部内に導電体を充填した。
　また、実験例１と同様にして、溝部の充填率を調べた。
　結果を表２に示す。
「実験例１４」
　厚み４０ｎｍのＣｕからなるシード層を形成し、シード層を形成した基体を３５０℃に加熱して、シード層を溶融して溝部の内側にＣｕを埋め込んだこと以外は実験例１１と同様にして、基体の溝部内に導電体を充填した。
　また、実験例１と同様にして、溝部の充填率を調べた。
　結果を表２に示す。
「実験例１５」
　厚み１５ｎｍのＣｕからなるシード層を形成し、シード層を形成した基体を３００℃に加熱して、シード層を溶融して溝部の内側にＣｕを埋め込んだこと以外は実験例１１と同様にして、基体の溝部内に導電体を充填した。
　また、実験例１と同様にして、溝部の充填率を調べた。
　結果を表２に示す。
「実験例１６」
　シード層を形成した基体を３００℃に加熱して、シード層を溶融して溝部の内側にＣｕを埋め込んだこと以外は実験例１１と同様にして、基体の溝部内に導電体を充填した。
　また、実験例１と同様にして、溝部の充填率を調べた。
　結果を表２に示す。
「実験例１７」
　厚み３５ｎｍのＣｕからなるシード層を形成し、シード層を形成した基体を３００℃に加熱して、シード層を溶融して溝部の内側にＣｕを埋め込んだこと以外は実験例１１と同様にして、基体の溝部内に導電体を充填した。
　また、実験例１と同様にして、溝部の充填率を調べた。
　結果を表２に示す。
「実験例１８」
　厚み４０ｎｍのＣｕからなるシード層を形成し、シード層を形成した基体を３００℃に加熱して、シード層を溶融して溝部の内側にＣｕを埋め込んだこと以外は実験例１１と同様にして、基体の溝部内に導電体を充填した。
　また、実験例１と同様にして、溝部の充填率を調べた。
　結果を表２に示す。
「実験例１９」
　厚み４５ｎｍのＣｕからなるシード層を形成し、シード層を形成した基体を３００℃に加熱して、シード層を溶融して溝部の内側にＣｕを埋め込んだこと以外は実験例１１と同様にして、基体の溝部内に導電体を充填した。
　また、実験例１と同様にして、溝部の充填率を調べた。
　結果を表２に示す。
「実験例２０」
　シード層を形成した基体を２５０℃に加熱して、シード層を溶融して溝部の内側にＣｕを埋め込んだこと以外は実験例１１と同様にして、基体の溝部内に導電体を充填した。
　また、実験例１と同様にして、溝部の充填率を調べた。
　結果を表２に示す。
「実験例２１」
　厚み３５ｎｍのＣｕからなるシード層を形成し、シード層を形成した基体を２５０℃に加熱して、シード層を溶融して溝部の内側にＣｕを埋め込んだこと以外は実験例１１と同様にして、基体の溝部内に導電体を充填した。
　また、実験例１と同様にして、溝部の充填率を調べた。
　結果を表２に示す。
「実験例２２」
　厚み４０ｎｍのＣｕからなるシード層を形成し、シード層を形成した基体を２５０℃に加熱して、シード層を溶融して溝部の内側にＣｕを埋め込んだこと以外は実験例１１と同様にして、基体の溝部内に導電体を充填した。
　また、実験例１と同様にして、溝部の充填率を調べた。
　結果を表２に示す。
Figure JPOXMLDOC01-appb-T000001
 　　　　　　　　　　　　　　　　　　
 
Figure JPOXMLDOC01-appb-T000002
 　　　　　　　　　　　　　　　　　　
 
　表１の結果から、シード層の厚みを３５ｎｍ以上、シード層の溶融温度を３００℃以上とすれば、溝部に対する導電材料（Ｃｕ）の充填性が向上することが分かった。
　表２の結果から、シード層形成工程およびシード層溶融工程を２回繰り返した場合、シード層の厚みを３５ｎｍ以上、シード層の溶融温度を２５０℃以上とすれば、溝部に対して、導電材料（Ｃｕ）を十分に充填できることが分かった。
　１０　半導体装置
　１１　基体
　１２　溝部（トレンチ）
　１３　バリア層（バリアメタル）
　１４　導電体（回路配線）
　１５　シード層

Claims (6)

  1. 　基体に溝部を形成する溝部形成工程と、
    　少なくとも前記溝部の内壁面を覆うバリア層を形成するバリア層形成工程と、
    　前記バリア層を覆うシード層を形成するシード層形成工程と、
    　前記シード層をリフロー法によって溶融させるシード層溶融工程と、を備え、
    　前記シード層はＣｕからなることを特徴とする半導体装置の製造方法。
  2. 　前記シード層形成工程は、前記バリア層を覆うＣｕ薄膜を形成する工程と、前記Ｃｕ薄膜を熱処理する工程と、を有し、
    　前記熱処理が、１００℃以上、４００℃以下の温度範囲で行われることを特徴とする請求項１記載の半導体装置の製造方法。
  3. 　前記シード層形成工程および前記シード層溶融工程を２回以上繰り返すことを特徴とする請求項１記載の半導体装置の製造方法。
  4. 　前記バリア層は、Ｔａ，Ｔｉ，Ｗ，Ｒｕ，Ｖ，Ｃｏ，Ｎｂのうち、少なくとも一種を含む材料からなることを特徴とする請求項１記載の半導体装置の製造方法。
  5. 　前記基体は、半導体基板と、前記半導体基板の一面に形成された絶縁層とからなることを特徴とする請求項１記載の半導体装置の製造方法。
  6. 　基体に形成された溝部と、前記溝部の内壁面を覆うバリア層と、前記バリア層の内側領域に埋め込まれた導電体と、を備え、
    　前記導電体は、前記バリア層を覆うＣｕからなるシード層をリフロー法によって溶融させて形成されたことを特徴とする半導体装置。
PCT/JP2012/074075 2011-09-30 2012-09-20 半導体装置の製造方法、半導体装置 WO2013047323A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020137032923A KR20140070503A (ko) 2011-09-30 2012-09-20 반도체 장치의 제조방법, 반도체 장치
CN201280028713.8A CN103620746A (zh) 2011-09-30 2012-09-20 半导体装置的制造方法及半导体装置
US14/347,779 US9337092B2 (en) 2011-09-30 2012-09-20 Method of manufacturing semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2011215847 2011-09-30
JP2011-215847 2011-09-30

Publications (1)

Publication Number Publication Date
WO2013047323A1 true WO2013047323A1 (ja) 2013-04-04

Family

ID=47995355

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2012/074075 WO2013047323A1 (ja) 2011-09-30 2012-09-20 半導体装置の製造方法、半導体装置

Country Status (6)

Country Link
US (1) US9337092B2 (ja)
JP (1) JPWO2013047323A1 (ja)
KR (1) KR20140070503A (ja)
CN (1) CN103620746A (ja)
TW (1) TWI479599B (ja)
WO (1) WO2013047323A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021504924A (ja) * 2017-11-21 2021-02-15 ワトロー エレクトリック マニュファクチュアリング カンパニー 集積ヒーターおよび製造方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11527437B2 (en) 2020-09-15 2022-12-13 Applied Materials, Inc. Methods and apparatus for intermixing layer for enhanced metal reflow

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08264535A (ja) * 1995-03-27 1996-10-11 Fujitsu Ltd 半導体装置の製造方法
JPH08316233A (ja) * 1994-06-21 1996-11-29 Toshiba Corp 半導体装置の製造方法
JPH1074760A (ja) * 1996-08-30 1998-03-17 Sony Corp 配線形成方法
JP2002075994A (ja) * 2000-08-24 2002-03-15 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2008071850A (ja) * 2006-09-13 2008-03-27 Sony Corp 半導体装置の製造方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06103681A (ja) 1992-09-18 1994-04-15 Nec Home Electron Ltd 磁気ディスク装置
US6475903B1 (en) 1993-12-28 2002-11-05 Intel Corporation Copper reflow process
US5654232A (en) * 1994-08-24 1997-08-05 Intel Corporation Wetting layer sidewalls to promote copper reflow into grooves
US5891803A (en) * 1996-06-26 1999-04-06 Intel Corporation Rapid reflow of conductive layers by directional sputtering for interconnections in integrated circuits
US6077780A (en) * 1997-12-03 2000-06-20 Advanced Micro Devices, Inc. Method for filling high aspect ratio openings of an integrated circuit to minimize electromigration failure
KR100259357B1 (ko) * 1998-02-07 2000-06-15 김영환 반도체 소자의 배선형성방법
US6184137B1 (en) * 1998-11-25 2001-02-06 Applied Materials, Inc. Structure and method for improving low temperature copper reflow in semiconductor features
KR100465063B1 (ko) * 2002-04-01 2005-01-06 주식회사 하이닉스반도체 반도체 소자의 금속배선 형성방법
US7030016B2 (en) 2004-03-30 2006-04-18 Taiwan Semiconductor Manufacturing Co., Ltd. Post ECP multi-step anneal/H2 treatment to reduce film impurity
JP4760236B2 (ja) * 2005-05-27 2011-08-31 日立化成工業株式会社 単結晶の熱処理方法
CN101399220A (zh) * 2007-09-27 2009-04-01 力晶半导体股份有限公司 金属互连的制造方法
KR100975652B1 (ko) * 2007-10-05 2010-08-17 한국과학기술원 아연 및 아연합금을 이용한 비아 및 그의 형성 방법, 그를3차원 다중 칩 스택 패키지 제조 방법
US20090194875A1 (en) * 2008-01-31 2009-08-06 International Business Machines Corporation HIGH PURITY Cu STRUCTURE FOR INTERCONNECT APPLICATIONS
KR20130053338A (ko) * 2011-11-15 2013-05-23 삼성전자주식회사 Ｔｓｖ 구조를 구비한 집적회로 소자
US8637957B1 (en) * 2012-07-18 2014-01-28 International Business Machines Corporation Low cost anti-fuse structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08316233A (ja) * 1994-06-21 1996-11-29 Toshiba Corp 半導体装置の製造方法
JPH08264535A (ja) * 1995-03-27 1996-10-11 Fujitsu Ltd 半導体装置の製造方法
JPH1074760A (ja) * 1996-08-30 1998-03-17 Sony Corp 配線形成方法
JP2002075994A (ja) * 2000-08-24 2002-03-15 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2008071850A (ja) * 2006-09-13 2008-03-27 Sony Corp 半導体装置の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021504924A (ja) * 2017-11-21 2021-02-15 ワトロー エレクトリック マニュファクチュアリング カンパニー 集積ヒーターおよび製造方法

Also Published As

Publication number Publication date
JPWO2013047323A1 (ja) 2015-03-26
TW201324683A (zh) 2013-06-16
CN103620746A (zh) 2014-03-05
TWI479599B (zh) 2015-04-01
US9337092B2 (en) 2016-05-10
US20150221552A1 (en) 2015-08-06
KR20140070503A (ko) 2014-06-10

Similar Documents

Publication Publication Date Title
US11881432B2 (en) Interconnect wires including relatively low resistivity cores
KR102574313B1 (ko) 배리어 막 증착 및 처리
JP2011091242A (ja) 半導体装置の製造方法
TW200952080A (en) A process for selective growth of films during ECP plating
TWI651807B (zh) Ｃｕ配線之製造方法
WO2013047323A1 (ja) 半導体装置の製造方法、半導体装置
JP2012248613A (ja) 半導体装置の製造方法
JP2013171940A (ja) 半導体装置の製造方法
JP2013077631A (ja) 半導体装置の製造方法、半導体装置
JP2006245240A (ja) 半導体装置及びその製造方法
JP5607243B2 (ja) 半導体装置の製造方法
TWI435386B (zh) 被膜表面處理方法
JP5965628B2 (ja) Ｃｕ層形成方法及び半導体装置の製造方法
JP5794905B2 (ja) リフロー法及び半導体装置の製造方法
JP4066820B2 (ja) 半導体上に銅（Ｃｕ）を主成分とする配線層を形成するための製造方法
JP2013074173A (ja) 半導体装置の製造方法、半導体装置
WO2011034092A1 (ja) バリアメタル膜の形成方法
JP2013080779A (ja) 半導体装置の製造方法、半導体装置
JP2004031497A (ja) 半導体装置およびその製造方法
JP2014086537A (ja) Ｃｕ層形成方法及び半導体装置の製造方法
JP2013143442A (ja) デバイスの製造方法および製造装置
JP2010135432A (ja) 半導体装置および半導体装置の製造方法
WO2011034089A1 (ja) 成膜方法
JP2005311087A (ja) アルミニウム配線の形成方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12835980

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2013536211

Country of ref document: JP

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 20137032923

Country of ref document: KR

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 14347779

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12835980

Country of ref document: EP

Kind code of ref document: A1