TWI479599B - 半導體裝置之製造方法、半導體裝置 - Google Patents

半導體裝置之製造方法、半導體裝置 Download PDF

Info

Publication number
TWI479599B
TWI479599B TW101135371A TW101135371A TWI479599B TW I479599 B TWI479599 B TW I479599B TW 101135371 A TW101135371 A TW 101135371A TW 101135371 A TW101135371 A TW 101135371A TW I479599 B TWI479599 B TW I479599B
Authority
TW
Taiwan
Prior art keywords
seed layer
groove portion
substrate
semiconductor device
experimental example
Prior art date
Application number
TW101135371A
Other languages
English (en)
Other versions
TW201324683A (zh
Inventor
Junichi Hamaguchi
Shuji Kodaira
Yuta Sakamoto
Akifumi Sano
Koukichi Kamada
Yoshiyuki Kadokura
Joji Hiroishi
Yukinobu Numata
Koji Suzuki
Original Assignee
Ulvac Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ulvac Inc filed Critical Ulvac Inc
Publication of TW201324683A publication Critical patent/TW201324683A/zh
Application granted granted Critical
Publication of TWI479599B publication Critical patent/TWI479599B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/02—Pretreatment of the material to be coated
    • C23C14/024—Deposition of sublayers, e.g. to promote adhesion of the coating
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04—Coating on selected surface areas, e.g. using masks
    • C23C14/046—Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/14—Metallic material, boron or silicon
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/14—Metallic material, boron or silicon
    • C23C14/16—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/58—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Description

半導體裝置之製造方法、半導體裝置
本發明係關於一種半導體裝置之製造方法、半導體裝置，詳細而言，本發明係關於一種高精度地形成微細之配線之技術。
本申請案係基於2011年9月30日於日本申請之日本專利特願2011-215847號而主張優先權，並將其內容引用至本文。
先前，作為形成於基板上之半導體元件等微細之配線材料，使用有鋁或鋁合金。然而，鋁之熔點較低，且耐滲移性較差，故而難以應對半導體元件之高積體化、高速化。
因此，近年來使用銅作為配線材料。銅之熔點高於鋁，且電阻率亦較低，故而作為LSI(Large Scale Integration，大型積體電路)配線材料較為有力。然而，於使用銅作為配線材料時，存在微細加工較為困難之問題。例如，於專利文獻1中提出有如下方法：於絕緣層上形成槽，並將銅埋入至該槽之內部，其後，去除自槽露出之多餘之銅，藉此於微細之槽內形成銅配線。
[先前技術文獻] [專利文獻]
專利文獻1：日本專利特公平6-103681號公報
然而，專利文獻1中所記載之發明存在難以將銅無間隙地埋入至槽之內部的問題。
即，於藉由濺鍍而將銅積層於槽之內部之情形時，銅未堆積至微細之槽之內部，而於槽之內部為空腔之狀態下僅堆積於槽之開口端附近。
又，於藉由回焊法而利用熔融之銅填埋槽之內部之情形時，存在如下問題：對於預先形成於槽之內壁面之障壁金屬層而言，其與熔融之銅之潤濕性較差，從而導致於在槽之內部產生有空腔之狀態下銅固化。
若如此於形成於槽之內部之銅配線中產生空腔，則銅配線之電阻值變高，且亦有斷線之虞。
本發明之態樣係為了解決上述課題而成者，其目的在於提供一種可將導電材料無間隙地埋入至微細之槽部之內部，而獲得導電性優異之配線的半導體裝置之製造方法及半導體裝置。
為了解決上述課題，本發明採用如下半導體裝置之製造方法、半導體裝置。
(1)本發明之一態樣之半導體裝置之製造方法包括：槽部形成步驟，其於基體上形成槽部；障壁層形成步驟，其形成至少覆蓋上述槽部之內壁面之障壁層；籽晶層形成步驟，其形成覆蓋上述障壁層之籽晶層；籽晶層熔融步驟，其藉由回焊法而使上述籽晶層熔融；且上述籽晶層包含Cu。
(2)如上述(1)之態樣，其中上述籽晶層形成步驟包括形成覆蓋上述障壁層之Cu薄膜之步驟及熱處理上述Cu薄膜之步驟，且上述熱處理亦可於100℃以上、400℃以下之溫度範圍內進行。
(3)如上述(1)或(2)之態樣，其中不僅於1次之上述籽晶層形成步驟及上述籽晶層熔融步驟中填埋槽內部，亦可將上述籽晶層形成步驟及上述籽晶層熔融步驟重複2次以上。
(4)如上述(1)至(3)中任一項之態樣，其中上述障壁層亦可採用如下構成，其包括包含Ta、Ti、W、Ru、V、Co及Nb中之至少一種之材料。
(5)如上述(1)至(4)中任一項之態樣，其中上述基體亦可採用如下構成，其包括：半導體基板；及絕緣層，其形成於上述半導體基板之一面上。
(6)本發明之一態樣之半導體裝置包括：槽部，其形成於基體上；障壁層，其覆蓋上述槽部之內壁面；及導電體，其埋入於上述障壁層之內側區域；且上述導電體係藉由回焊法使覆蓋上述障壁層之包含Cu之籽晶層熔融而形成。
根據本發明之上述態樣之半導體裝置之製造方法及半導體裝置，由於藉由回焊法使覆蓋障壁層之包含Cu之籽晶層熔融，故導電材料Cu可於內部不產生空腔地均勻地遍佈於槽部之每個角落，從而獲得無局部性斷線部分之高精度導電體。
以下，根據圖式，對本發明之實施形態之半導體裝置之製造方法及半導體裝置進行說明。再者，本實施形態中，為了更佳地理解發明之宗旨，係列舉一例而進行說明，只要無特別指定，則不限定本發明。又，以下說明中所使用之圖式中，為了易於理解本發明之特徵，為方便起見，存在將作為要部之部分放大表示之情形，且各構成要素之尺寸比率等並不一定與實際相同。
(半導體裝置)
圖1係表示本發明之一實施形態之半導體裝置的要部放大剖面圖。
半導體裝置10包括基體11。基體11包括絕緣性基板，例如玻璃基板、樹脂基板等。再者，亦可於該基體11之一部分例如形成有半導體元件等。
於基體11之一面11a上形成有槽部(溝槽)12。槽部12例如包括自基體11之一面11a沿基體11之厚度方向向下挖掘而成的寬度較窄且較深之微細之槽。槽部12之底部之寬度W例如係以變為20 nm~50 nm左右之方式形成。又，槽部12之深度D例如係以變為80 nm~200 nm左右之方式形成。於此種槽部12之內側區域例如形成構成半導體元件之電路配線之導電體。
於槽部12中，以覆蓋內壁面12a之方式而形成有障壁層(障壁金屬)13。障壁層13例如包括氮化Ta(鉭)、矽化Ta、碳化Ta、氮化Ti(鈦)、矽化Ti、碳化Ti、氮化W(鎢)、矽化 W、碳化W、Ru(釕)、及氧化Ru、氧化V(釩)、氧化Co(鈷)、氧化Nb(鈮)等。
障壁層(障壁金屬)13係以厚度t1例如變為1 nm~3 nm左右之方式形成。
進而，於槽部12中之障壁層(障壁金屬)13之內側區域形成有包含導電材料之導電體14。導電體14包括Cu(銅)。該導電體14係藉由於障壁層(障壁金屬)13之內側區域形成籽晶層，並藉由熔融(回焊)該籽晶層而填埋槽部12而形成。
導電體14例如成為基體11上所形成之半導體元件之電路配線。
根據此種構成之半導體裝置10，於障壁層(障壁金屬)13之內側區域形成包含Cu之籽晶層，並藉由熔融(回焊)該籽晶層而形成導電體14，藉此，於導電體14之形成時，導電材料無間隙地填埋槽部12之內側。因此，可實現包括電阻均勻且無斷線等憂慮之包含Cu之導電體(電路配線)14的半導體裝置10。
(半導體裝置之製造方法)
圖2、圖3係階段性地表示本發明之一實施形態之半導體裝置之製造方法的要部放大剖面圖。
於製造本發明之實施形態之半導體裝置時，首先，準備基體11(參照圖2(a))。作為基體11，可使用絕緣性基板、半導體基板。作為絕緣性基板，例如可列舉玻璃基板、樹脂基板。又，作為半導體基板，例如可列舉矽晶圓、SiC晶圓等。於基體11上例如預先形成有半導體元件(圖示省 略)。
繼而，於該基體11之一面11a上形成特定深度之槽部12(參照圖2(b)：槽部形成步驟)。槽部12例如係以成為仿照半導體元件之電路配線之圖案之方式形成。作為於基體11之一面11a上形成槽部12之方法，例如可使用利用光微影法之蝕刻加工或利用雷射光之加工。
繼而，於包含槽部12之內壁面12a之基體11之一面11a上形成特定厚度之障壁層(障壁金屬)13(參照圖2(c)：障壁層形成步驟)。障壁層(障壁金屬)13例如係使用包含Ta、Ti、W、Ru、V、Co及Nb中之至少1種之材料而形成。障壁層13之形成例如較佳為使用濺鍍法或CVD(Chemical Vapor Deposition，化學氣相沈積)法。又，障壁層(障壁金屬)13係以厚度t1例如變為1 nm~3 nm左右之方式形成。
圖4表示用於障壁層之形成之濺鍍裝置(成膜裝置)之一例。
濺鍍裝置(成膜裝置)1包括：真空槽2；以及基板固持器7及靶5，其分別配置於真空槽2內部。
真空槽2上連接有真空排氣系統9及氣體供給系統4，將真空槽2內部真空排氣，且一面真空排氣一面自氣體供給系統4導入濺鍍氣體及化學結構中包含氮或氧之反應氣體(例如反應氣體為氧氣之情形時，流量為0.1 sccm以上5 sccm以下)，於真空槽2內部形成低於大氣壓之成膜環境(例如全壓為10-4 Pa以上10-1 Pa以下)。
而且，預先將於基體11上形成有槽部12之一面11a側於 朝向靶5之狀態下保持於基板固持器7上。於真空槽2之外部分別配置濺鍍電源8及偏壓電源6，且靶5連接於濺鍍電源8，基板固持器7連接於偏壓電源6。
於真空槽2之外部配置有磁場形成機構3，當將真空槽2置於接地電位，一面維持真空槽2內部之成膜環境，一面對靶5施加負電壓時，靶5被磁控濺鍍。靶5係以上述之障壁層(障壁金屬)13之形成材料為主成分。
繼而，當靶5被磁控濺鍍時，障壁層13之形成材料作為濺鍍粒子而釋出。
所釋出之濺鍍粒子與反應氣體入射至於基體11上形成有槽部12之一面11a，以覆蓋包含槽部12之內壁面12a之基體11之一面11a之方式形成障壁層13。
繼而，以覆蓋障壁層13之方式形成籽晶層15(參照圖3(a)：籽晶層形成步驟)。該籽晶層15於下一步驟中被回焊，成為埋入於槽部12之導電材料。籽晶層15包括Cu。籽晶層15與上述之障壁層13同樣，使用濺鍍法而形成。籽晶層15例如係以厚度變為15 nm~55 nm左右之方式形成。
對使用濺鍍裝置(成膜裝置)1之籽晶層15之形成方法進行說明。
首先，於在基板固持器7上配置有基體11之狀態下，藉由真空排氣系統9將真空槽2內部真空排氣，且一面真空排氣一面自氣體供給系統4導入濺鍍氣體及化學結構中包含氮或氧之反應氣體(例如反應氣體為氧氣之情形時，流量為0.1 sccm以上5 sccm以下)，於真空槽2內部形成低於大 氣壓之成膜環境(例如全壓為10-4 Pa以上10-1 Pa以下)。
導入濺鍍氣體，並於真空槽2內穩定於特定之壓力(例如4.0×10-2 Pa之壓力)後，啟動濺鍍電源8，而對陰極(圖示省略)施加負電壓，藉此開始放電，從而使靶5成為Cu，而於靶5之表面附近產生電漿。
繼而，將利用濺鍍之成膜進行特定時間而以覆蓋障壁層13之方式形成銅薄膜之後，自真空槽2搬出基體11。
再者，於上述之濺鍍裝置1之基板固持器7內設置有溫度調節機構(圖示省略)，於形成銅薄膜時預先將基體11之溫度調節為特定之溫度(例如-20℃)。
於濺鍍裝置1中，磁場形成機構3係以可平行於靶5表面地移動、轉動之方式而構成，從而可將靶5表面之被濺鍍區域(侵蝕區域)形成於靶上之任意位置。
繼而，將形成有籽晶層15之基體11加熱至籽晶層15之熔融溫度以上而進行回焊(參照圖3(b)：籽晶層熔融步驟)。藉此，籽晶層15熔融，槽部12之內側即障壁層13之內側區域由包含Cu之導電材料M填埋。
將籽晶層15之熔融溫度例如設為100℃以上、400℃以下。
再者，於包含Cu之導電材料M對障壁層13之內側區域之填充不充分之情形時，較佳為將籽晶層形成步驟及籽晶層熔融步驟重複2次以上。藉此，可更確實地將包含Cu之導電材料M填充至障壁層13之內側區域。
之後，將積層於除槽部12以外之基體11之一面11a上之 障壁層13、導電材料M去除(參照圖3(c))。藉此，於各槽部12之每一者中形成填埋槽部12之導電體14即電路配線。
[實施例]
以下，藉由實驗例而進一步具體地說明本發明之實施形態，但本發明並不限定於以下之實驗例。
「實驗例1」
準備厚度0.775 mm之帶矽氧化膜之矽基板作為基體。
繼而，藉由利用光微影法之蝕刻加工而於該基體之一面上形成深度100 nm之槽部。
繼而，藉由濺鍍法而於包含槽部之內壁面之基體之一面上形成厚度3 nm之包含Ta之障壁層。
繼而，藉由濺鍍法，以覆蓋障壁層之方式而形成厚度25 nm之籽晶層銅薄膜。於形成銅薄膜時，將基體之溫度調節為-20℃。
繼而，將形成有籽晶層之基體加熱至400℃而將籽晶層熔融，從而將包含Cu之導電材料埋入至槽部之內側即障壁層之內側區域。
將包含Cu之導電材料埋入至障壁層之內側區域後，針對該基體，使用掃描型電子顯微鏡(SEM，Scanning Electron Microscope)來調查槽部之填充率(槽部由Cu填充之比例、體積%)。
再者，將填充率為90%以上之情形評價為○，將填充率為80%以上且未達90%之情形評價為△，將填充率未達80%之情形評價為×。
結果示於表1。
「實驗例2」
形成厚度35 nm之包含Cu之籽晶層，除此以外，以與實驗例1相同之方式將Cu填充至基體之槽部內。
又，以與實驗例1相同之方式調查槽部之填充率。
結果示於表1。
「實驗例3」
形成厚度45 nm之包含Cu之籽晶層，除此以外，以與實驗例1相同之方式將Cu填充至基體之槽部內。
又，以與實驗例1相同之方式調查槽部之填充率。
結果示於表1。
「實驗例4」
將形成有籽晶層之基體加熱至300℃而將籽晶層熔融，從而將Cu埋入至槽部之內側，除此以外，以與實驗例1相同之方式將導電體填充至基體之槽部內。
又，以與實驗例1相同之方式調查槽部之填充率。
結果示於表1。
「實驗例5」
形成厚度35 nm之包含Cu之籽晶層，並將形成有籽晶層之基體加熱至300℃而將籽晶層熔融，從而將Cu埋入至槽部之內側，除此以外，以與實驗例1相同之方式將導電體填充至基體之槽部內。
又，以與實驗例1相同之方式調查槽部之填充率。
結果示於表1。
「實驗例6」
形成厚度45 nm之包含Cu之籽晶層，並將形成有籽晶層之基體加熱至300℃而將籽晶層熔融，從而將Cu埋入至槽部之內側，除此以外，以與實驗例1相同之方式將導電體填充至基體之槽部內。
又，以與實驗例1相同之方式調查槽部之填充率。
結果示於表1。
「實驗例7」
形成厚度55 nm之包含Cu之籽晶層，並將形成有籽晶層之基體加熱至300℃而將籽晶層熔融，從而將Cu埋入至槽部之內側，除此以外，以與實驗例1相同之方式將導電體填充至基體之槽部內。
又，以與實驗例1相同之方式調查槽部之填充率。
結果示於表1。
「實驗例8」
將形成有籽晶層之基體加熱至200℃而將籽晶層熔融，從而將Cu埋入至槽部之內側，除此以外，以與實驗例1相同之方式將導電體填充至基體之槽部內。
又，以與實驗例1相同之方式調查槽部之填充率。
結果示於表1。
「實驗例9」
形成厚度35 nm之包含Cu之籽晶層，並將形成有籽晶層之基體加熱至200℃而將籽晶層熔融，從而將Cu埋入至槽部之內側，除此以外，以與實驗例1相同之方式將導電體 填充至基體之槽部內。
又，以與實驗例1相同之方式調查槽部之填充率。
結果示於表1。
「實驗例10」
形成厚度45 nm之包含Cu之籽晶層，並將形成有籽晶層之基體加熱至200℃而將籽晶層熔融，從而將Cu埋入至槽部之內側，除此以外，以與實驗例1相同之方式將導電體填充至基體之槽部內。
又，以與實驗例1相同之方式調查槽部之填充率。
結果示於表1。
「實驗例11」
準備厚度0.775 mm之帶矽氧化膜之矽基板作為基體。
繼而，藉由利用光微影法之蝕刻加工而於該基體之一面上形成深度100 nm之槽部。
繼而，藉由濺鍍法而於包含槽部之內壁面之基體之一面上形成厚度3 nm之包含Ta之障壁層。
繼而，藉由濺鍍法，以覆蓋障壁層之方式而形成厚度25 nm之銅薄膜。於形成銅薄膜時，將基體之溫度調節為-20℃。
繼而，將形成有籽晶層之基體加熱至400℃而將籽晶層熔融，從而將包含Cu之導電材料埋入至槽部之內側即障壁層之內側區域。
再次藉由濺鍍法而於障壁層之內側區域形成銅薄膜。於形成銅薄膜時，將基體之溫度調節為-20℃。
繼而，將形成有籽晶層之基體加熱至400℃而將籽晶層熔融，從而將包含Cu之導電材料埋入至槽部之內側。
其後，以與實驗例1相同之方式調查槽部之填充率。
結果示於表2。
「實驗例12」
將形成有籽晶層之基體加熱至350℃而將籽晶層熔融，從而將Cu埋入至槽部之內側，除此以外，以與實驗例11相同之方式將導電體填充至基體之槽部內。
又，以與實驗例1相同之方式調查槽部之填充率。
結果示於表2。
「實驗例13」
形成厚度35 nm之包含Cu之籽晶層，並將形成有籽晶層之基體加熱至350℃而將籽晶層熔融，從而將Cu埋入至槽部之內側，除此以外，以與實驗例11相同之方式將導電體填充至基體之槽部內。
又，以與實驗例1相同之方式調查槽部之填充率。
結果示於表2。
「實驗例14」
形成厚度40 nm之包含Cu之籽晶層，並將形成有籽晶層之基體加熱至350℃而將籽晶層熔融，從而將Cu埋入至槽部之內側，除此以外，以與實驗例11相同之方式將導電體填充至基體之槽部內。
又，以與實驗例1相同之方式調查槽部之填充率。
結果示於表2。
「實驗例15」
形成厚度15 nm之包含Cu之籽晶層，並將形成有籽晶層之基體加熱至300℃而將籽晶層熔融，從而將Cu埋入至槽部之內側，除此以外，以與實驗例11相同之方式將導電體填充至基體之槽部內。
又，以與實驗例1相同之方式調查槽部之填充率。
結果示於表2。
「實驗例16」
將形成有籽晶層之基體加熱至300℃而將籽晶層熔融，從而將Cu埋入至槽部之內側，除此以外，以與實驗例11相同之方式將導電體填充至基體之槽部內。
又，以與實驗例1相同之方式調查槽部之填充率。
結果示於表2。
「實驗例17」
形成厚度35 nm之包含Cu之籽晶層，並將形成有籽晶層之基體加熱至300℃而將籽晶層熔融，從而將Cu埋入至槽部之內側，除此以外，以與實驗例11相同之方式將導電體填充至基體之槽部內。
又，以與實驗例1相同之方式調查槽部之填充率。
結果示於表2。
「實驗例18」
形成厚度40 nm之包含Cu之籽晶層，並將形成有籽晶層之基體加熱至300℃而將籽晶層熔融，從而將Cu埋入至槽部之內側，除此以外，以與實驗例11相同之方式將導電體 填充至基體之槽部內。
又，以與實驗例1相同之方式調查槽部之填充率。
結果示於表2。
「實驗例19」
形成厚度45 nm之包含Cu之籽晶層，並將形成有籽晶層之基體加熱至300℃而將籽晶層熔融，從而將Cu埋入至槽部之內側，除此以外，以與實驗例11相同之方式將導電體填充至基體之槽部內。
又，以與實驗例1相同之方式調查槽部之填充率。
結果示於表2。
「實驗例20」
將形成有籽晶層之基體加熱至250℃而將籽晶層熔融，從而將Cu埋入至槽部之內側，除此以外，以與實驗例11相同之方式將導電體填充至基體之槽部內。
又，以與實驗例1相同之方式調查槽部之填充率。
結果示於表2。
「實驗例21」
形成厚度35 nm之包含Cu之籽晶層，並將形成有籽晶層之基體加熱至250℃而將籽晶層熔融，從而將Cu埋入至槽部之內側，除此以外，以與實驗例11相同之方式將導電體填充至基體之槽部內。
又，以與實驗例1相同之方式調查槽部之填充率。
結果示於表2。
「實驗例22」
形成厚度40 nm之包含Cu之籽晶層，並將形成有籽晶層之基體加熱至250℃而將籽晶層熔融，從而將Cu埋入至槽部之內側，除此以外，以與實驗例11相同之方式將導電體填充至基體之槽部內。
又，以與實驗例1相同之方式調查槽部之填充率。
結果示於表2。
根據表1之結果可知，若將籽晶層之厚度設為35 nm以上、將籽晶層之熔融溫度設為300℃以上，則導電材料(Cu)對於槽部之填充性提高。
根據表2之結果可知，於將籽晶層形成步驟及籽晶層熔 融步驟重複2次之情形時，若將籽晶層之厚度設為35 nm以上、將籽晶層之熔融溫度設為250℃以上，則可對槽部充分地填充導電材料(Cu)。
10‧‧‧半導體裝置
11‧‧‧基體
11a‧‧‧基體之一面
12‧‧‧槽部(溝槽)
12a‧‧‧槽部之內壁面
13‧‧‧障壁層(障壁金屬)
14‧‧‧導電體(電路配線)
15‧‧‧籽晶層
D‧‧‧深度
t1‧‧‧厚度
W‧‧‧寬度
圖1係表示本發明之一實施形態之半導體裝置的要部放大剖面圖。
圖2(a)~(c)係階段性地表示本發明之一實施形態之半導體裝置之製造方法的要部放大剖面圖。
圖3(a)~(c)係階段性地表示本發明之一實施形態之半導體裝置之製造方法的要部放大剖面圖。
圖4係表示本發明之實施形態中所使用之濺鍍裝置(成膜裝置)之一例的示意圖。
10‧‧‧半導體裝置
11‧‧‧基體
11a‧‧‧基體之一面
12‧‧‧槽部(溝槽)
12a‧‧‧槽部之內壁面
13‧‧‧障壁層(障壁金屬)
14‧‧‧導電體(電路配線)
D‧‧‧深度
t1‧‧‧厚度
W‧‧‧寬度

Claims (3)

  1. 一種半導體裝置之製造方法，其特徵在於包括：槽部形成步驟，其於基體上形成槽部；障壁層形成步驟，其形成至少覆蓋上述槽部之內壁面之障壁層；籽晶層形成步驟，其形成覆蓋上述障壁層之籽晶層；及籽晶層熔融步驟，其藉由回焊法而使上述籽晶層熔融；上述籽晶層包含35nm以上之Cu，使上述籽晶層熔融步驟之熔融溫度為250℃以上；且將上述籽晶層形成步驟及上述籽晶層熔融步驟重複2次以上而填充上述槽部。
  2. 如請求項1之半導體裝置之製造方法，其中上述障壁層包括包含Ta、Ti、W、Ru、V、Co及Nb中之至少一種之材料。
  3. 如請求項1之半導體裝置之製造方法，其中上述基體包括：半導體基板；及絕緣層，其形成於上述半導體基板之一面上。
TW101135371A 2011-09-30 2012-09-26 半導體裝置之製造方法、半導體裝置 TWI479599B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011215847 2011-09-30

Publications (2)

Publication Number Publication Date
TW201324683A TW201324683A (zh) 2013-06-16
TWI479599B true TWI479599B (zh) 2015-04-01

Family

ID=47995355

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101135371A TWI479599B (zh) 2011-09-30 2012-09-26 半導體裝置之製造方法、半導體裝置

Country Status (6)

Country Link
US (1) US9337092B2 (zh)
JP (1) JPWO2013047323A1 (zh)
KR (1) KR20140070503A (zh)
CN (1) CN103620746A (zh)
TW (1) TWI479599B (zh)
WO (1) WO2013047323A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10681778B2 (en) * 2017-11-21 2020-06-09 Watlow Electric Manufacturing Company Integrated heater and method of manufacture
US11527437B2 (en) 2020-09-15 2022-12-13 Applied Materials, Inc. Methods and apparatus for intermixing layer for enhanced metal reflow

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002075994A (ja) * 2000-08-24 2002-03-15 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
US20060216930A1 (en) * 2004-03-30 2006-09-28 Hsien-Ping Feng Post ECP multi-step anneal/H2 treatment to reduce film impurity

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06103681A (ja) 1992-09-18 1994-04-15 Nec Home Electron Ltd 磁気ディスク装置
US6475903B1 (en) 1993-12-28 2002-11-05 Intel Corporation Copper reflow process
JP3337876B2 (ja) * 1994-06-21 2002-10-28 株式会社東芝 半導体装置の製造方法
US5654232A (en) * 1994-08-24 1997-08-05 Intel Corporation Wetting layer sidewalls to promote copper reflow into grooves
JPH08264535A (ja) * 1995-03-27 1996-10-11 Fujitsu Ltd 半導体装置の製造方法
US5891803A (en) * 1996-06-26 1999-04-06 Intel Corporation Rapid reflow of conductive layers by directional sputtering for interconnections in integrated circuits
JPH1074760A (ja) * 1996-08-30 1998-03-17 Sony Corp 配線形成方法
US6077780A (en) * 1997-12-03 2000-06-20 Advanced Micro Devices, Inc. Method for filling high aspect ratio openings of an integrated circuit to minimize electromigration failure
KR100259357B1 (ko) * 1998-02-07 2000-06-15 김영환 반도체 소자의 배선형성방법
US6184137B1 (en) * 1998-11-25 2001-02-06 Applied Materials, Inc. Structure and method for improving low temperature copper reflow in semiconductor features
KR100465063B1 (ko) * 2002-04-01 2005-01-06 주식회사 하이닉스반도체 반도체 소자의 금속배선 형성방법
JP4760236B2 (ja) * 2005-05-27 2011-08-31 日立化成工業株式会社 単結晶の熱処理方法
JP2008071850A (ja) * 2006-09-13 2008-03-27 Sony Corp 半導体装置の製造方法
CN101399220A (zh) * 2007-09-27 2009-04-01 力晶半导体股份有限公司 金属互连的制造方法
KR100975652B1 (ko) * 2007-10-05 2010-08-17 한국과학기술원 아연 및 아연합금을 이용한 비아 및 그의 형성 방법, 그를3차원 다중 칩 스택 패키지 제조 방법
US20090194875A1 (en) * 2008-01-31 2009-08-06 International Business Machines Corporation HIGH PURITY Cu STRUCTURE FOR INTERCONNECT APPLICATIONS
KR20130053338A (ko) * 2011-11-15 2013-05-23 삼성전자주식회사 Ｔｓｖ 구조를 구비한 집적회로 소자
US8637957B1 (en) * 2012-07-18 2014-01-28 International Business Machines Corporation Low cost anti-fuse structure

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002075994A (ja) * 2000-08-24 2002-03-15 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
US20060216930A1 (en) * 2004-03-30 2006-09-28 Hsien-Ping Feng Post ECP multi-step anneal/H2 treatment to reduce film impurity

Also Published As

Publication number Publication date
WO2013047323A1 (ja) 2013-04-04
TW201324683A (zh) 2013-06-16
CN103620746A (zh) 2014-03-05
JPWO2013047323A1 (ja) 2015-03-26
KR20140070503A (ko) 2014-06-10
US20150221552A1 (en) 2015-08-06
US9337092B2 (en) 2016-05-10

Similar Documents

Publication Publication Date Title
US10325803B2 (en) Semiconductor wafer and method for processing a semiconductor wafer
TWI449128B (zh) 積體電路結構及其製造方法
JP2000174026A (ja) 半導体フィ―チャの低温銅リフロ―を改善する構造と方法
JP2011091242A (ja) 半導体装置の製造方法
TWI479599B (zh) 半導體裝置之製造方法、半導體裝置
TW201703148A (zh) Ｃｕ配線形成方法及半導體裝置之製造方法、記憶媒體
TW200952080A (en) A process for selective growth of films during ECP plating
TWI651807B (zh) Ｃｕ配線之製造方法
JP2020534702A (ja) 基板のフィーチャをコバルトで充填する方法および装置
JP2013171940A (ja) 半導体装置の製造方法
TWI503926B (zh) 半導體裝置之製造方法、半導體裝置
JP2013105753A (ja) 半導体装置の製造方法
JP2013077631A (ja) 半導体装置の製造方法、半導体装置
TWI435386B (zh) 被膜表面處理方法
JP5965628B2 (ja) Ｃｕ層形成方法及び半導体装置の製造方法
JP5794905B2 (ja) リフロー法及び半導体装置の製造方法
JP2015018839A (ja) Ｃｕ配線構造の形成方法
WO2011034092A1 (ja) バリアメタル膜の形成方法
JP5616605B2 (ja) 銅薄膜の形成方法
JP2013074173A (ja) 半導体装置の製造方法、半導体装置
JP2013080779A (ja) 半導体装置の製造方法、半導体装置
JP2004221494A (ja) 半導体デバイス用配線構造
JP2014086537A (ja) Ｃｕ層形成方法及び半導体装置の製造方法
JPH0426769A (ja) 銅薄膜の形成方法
WO2011034089A1 (ja) 成膜方法