CN103620746A - 半导体装置的制造方法及半导体装置 - Google Patents

半导体装置的制造方法及半导体装置 Download PDF

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CN103620746A
CN103620746A CN201280028713.8A CN201280028713A CN103620746A CN 103620746 A CN103620746 A CN 103620746A CN 201280028713 A CN201280028713 A CN 201280028713A CN 103620746 A CN103620746 A CN 103620746A
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seed layer
slot part
matrix
forms
semiconductor device
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滨口纯一
小平周司
坂本勇太
佐野昭文
镰田恒吉
门仓好之
广石城司
沼田幸展
铃木康司
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Ulvac Inc
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Abstract

本发明的半导体装置的制造方法，具备：槽部形成工序，在基体形成槽部；阻挡层形成工序，形成至少覆盖所述槽部的内壁面的阻挡层；种子层形成工序，形成覆盖所述阻挡层的种子层；以及种子层熔化工序，通过回流法使所述种子层熔化，所述种子层由Cu构成。

Description

半导体装置的制造方法及半导体装置
技术领域
本发明涉及半导体装置的制造方法及半导体装置，更详细地涉及高精度地形成微细配线的技术。
本申请基于2011年9月30日在日本申请的日本专利申请2011-215847号主张优先权，并在此援用其内容。
背景技术
以往，作为在基板形成的半导体元件等的微细配线材料，使用了铝、铝合金。但是，由于铝的熔点低且耐迁移性差，因此难以应对半导体元件的高集成化、高速化。
为此，近年来作为配线材料，使用铜。铜与铝相比熔点高且电阻率也低，因此作为LSI配线材料是有力的。但是，作为配线材料使用铜时，存在难以进行微细加工的问题。例如，专利文献1中提出有如下方法：通过在绝缘层形成槽，在该槽的内部埋入铜，之后去除从槽露出的剩余的铜，从而在微细的槽内形成铜配线。
专利文献1：日本特公平6-103681号公报
然而，在专利文献1中记载的发明中，存在难以将铜无缝隙地埋入槽的内部的问题。
即，通过溅射将铜层压在槽的内部的情况下，铜不会堆积至微细的槽的内部，而槽的内部保持空洞的状态下仅在槽的开口端附近堆积铜。
另外，存在如下问题：通过回流法来熔化的铜埋入槽的内部的情况下，对于在槽的内壁面预先形成的阻挡金属层，与熔化的铜的润湿性差，在槽的内部产生空洞的状态下铜进行固化。
这样在槽的内部形成的铜配线中产生空洞时，铜配线的电阻值变高，也有可能断线。
发明内容
本发明所涉及的方式是为了解决上述问题而提出的，其目的在于，提供一种在微细的槽部的内部无缝隙地埋入导电材料，从而能够得到导电性优异的配线的半导体装置的制造方法及半导体装置。
为了解决上述问题，本发明采用如下的半导体装置的制造方法及半导体装置。
（1）本发明所涉及的一方式的半导体装置的制造方法，具备：槽部形成工序，在基体形成槽部；阻挡层形成工序，形成至少覆盖所述槽部的内壁面的阻挡层；种子层形成工序，形成覆盖所述阻挡层的种子层；以及种子层熔化工序，通过回流法使所述种子层熔化，所述种子层由Cu构成。
（2）上述（1）的方式中，所述种子层形成工序具有：形成覆盖所述阻挡层的Cu薄膜的工序；以及对所述Cu薄膜进行热处理的工序，所述热处理也可以在100℃以上400℃以下的温度范围内进行。
（3）上述（1）或（2）的方式中，不仅仅在一次所述种子层形成工序及所述种子层熔化工序中埋入槽内部，也可以重复进行两次以上所述种子层形成工序及所述种子层熔化工序。
（4）上述（1）至（3）的任一个所述的方式中，所述阻挡层也可以采用由含有Ta、Ti、W、Ru、V、Co和Nb中的至少一种的材料构成的结构。
（5）上述（1）至（4）的任一个所述的方式中，所述基体可以采用由半导体基板和在所述半导体基板的一面形成的绝缘层构成的结构。
（6）本发明所涉及的一方式的半导体装置，具备：形成在基体的槽部；覆盖所述槽部的内壁面的阻挡层；以及被埋入在所述阻挡层的内侧区域的导电体，所述导电体是通过回流法使覆盖所述阻挡层的由Cu构成的种子层熔化而形成。
根据本发明所涉及的上述方式的半导体装置的制造方法及半导体装置，由于通过回流法使覆盖阻挡层的由Cu构成的种子层熔化，因此导电材料Cu均匀地遍布槽部的各个角落，而不在内部产生空洞，能够得到无局部断线部分的高精度导电体。
附图说明
图1为示出本发明所涉及的一实施方式的半导体装置的主要部分放大剖视图。
图2为按步骤示出本发明所涉及的一实施方式的半导体装置的制造方法的主要部分放大剖视图。
图3为按步骤示出本发明所涉及的一实施方式的半导体装置的制造方法的主要部分放大剖视图。
图4为示出本发明所涉及的实施方式中使用的溅射装置（成膜装置）的一例的示意图。
具体实施方式
下面，基于附图对本发明所涉及的实施方式的半导体装置的制造方法及半导体装置进行说明。此外，本实施方式为了更好地理解发明的宗旨而举出一例进行说明，只要没有特别的指定，不限定本发明。另外，以下说明中使用的附图，为了容易理解本发明的特征，方便起见，有时放大示出构成主要部分的部分，各组成部件的尺寸比率等不一定与实际相同。
（半导体装置）
图1为示出本发明所涉及的一实施方式的半导体装置的主要部分放大剖视图。
半导体装置10具备基体11。基体11由绝缘性基板例如玻璃基板、树脂基板等构成。此外，该基体11的一部分也可以形成有例如半导体元件等。
在基体11的一面11a形成有槽部（沟）12。槽部12例如由从基体11的一面11a向基体11的厚度方向挖掘的宽度窄且深的微细槽构成。槽部12的底部的宽度W形成为例如20nm～50nm左右。另外，槽部12的深度D形成为例如80nm～200nm左右。这种槽部12的内侧区域形成有例如构成半导体元件的电路配线的导电体。
在槽部12形成有阻挡层（阻挡金属）13，以覆盖内壁面12a。阻挡层13例如由Ta（钽）氮化物、Ta硅化物、Ta碳化物、Ti（钛）氮化物、Ti硅化物、Ti碳化物、W（钨）氮化物、W硅化物、W碳化物、Ru（钌）、及Ru氧化物、V（钒）氧化物、Co（钴）氧化物、Nb（铌）氧化物等构成。
阻挡层（阻挡金属）13以厚度t1例如为1nm～3nm左右的方式形成。
进一步，在槽部12中的阻挡层（阻挡金属）13的内侧区域形成有由导电材料构成的导电体14。导电体14由Cu（铜）构成。该导电体14通过在阻挡层（阻挡金属）13的内侧区域形成种子层，熔化（回流）该种子层，埋入槽部12来形成。
导电体14例如成为在基体11形成的半导体元件的电路配线。
根据这种结构的半导体装置10，通过在阻挡层（阻挡金属）13的内侧区域形成由Cu构成的种子层，熔化（回流）该种子层来形成导电体14，从而在形成导电体14时，导电材料无缝隙地埋入槽部12的内侧。因此，能够实现具备电阻均匀且没有断线等担忧的由Cu构成的导电体（电路配线）14的半导体装置10。
（半导体装置的制造方法）
图2和图3为按步骤示出本发明所涉及的一实施方式的半导体装置的制造方法主要部分放大剖视图。
在制造本发明所涉及的实施方式的半导体装置时，首先，准备基体11（参见图2的（a））。作为基体11，可以使用绝缘性基板、半导体基板。作为绝缘性基板，例如可以举出玻璃基板、树脂基板。另外，作为半导体基板，例如可以举出硅晶片、SiC晶片等。在基体11例如预先形成有半导体元件（省略图示）。
接着，在该基体11的一面11a形成规定深度的槽部12（参见图2的（b）：槽部形成工序）。槽部12例如以仿照半导体元件的电路配线的图案的方式形成。作为在基体11的一面11a形成槽部12的方法，例如能够使用基于光刻法的蚀刻加工、通过激光进行的加工。
接着，在包括槽部12的内壁面12a的基体11的一面11a形成规定厚度的阻挡层（阻挡金属）13（参见图2的（c）：阻挡层形成工序）。阻挡层（阻挡金属）13例如使用包括Ta、Ti、W、Ru、V、Co和Nb中的至少一种的材料形成。阻挡层13的形成例如优选使用溅射法、CVD法等。另外，阻挡层（阻挡金属）13以厚度t1例如为1nm～3nm左右的方式形成。
图4示出用于形成阻挡层的溅射装置（成膜装置）的一例。
溅射装置（成膜装置）1具有：真空槽2；分别配置在真空槽2内部的基板架7；以及靶5。
真空槽2连接有真空排气系统9和气体供给系统4，对真空槽2内部进行真空排气，一边进行真空排气一边从气体供给系统4导入溅射气体和化学结构中含有氮或氧的反应气体（例如反应气体为氧的情况下，流量为0.1sccm以上5sccm以下），在真空槽2内部形成比大气压低的成膜气氛（例如总压在10-4Pa以上10-1Pa以下）。
然后，在将基体11的形成有槽部12的一面11a侧朝向靶5的状态下保持在基板架7。在真空槽2的外部分别配置溅射电源8和偏置电源6，靶5连接到溅射电源8，基板架7连接到偏置电源6。
真空槽2的外部配置有磁场形成单元3，使真空槽2处于接地电位，一边维持真空槽2内部的成膜气氛，一边对靶施加负电压，则靶5被磁控溅射。靶5的主成分为上述阻挡层（阻挡金属）13的形成材料。
然后，当靶5被磁控溅射时，阻挡层13的形成材料以溅射粒子的方式被释放。
被释放的溅射粒子和反应气体入射到基体11的形成有槽部12的一面11a，形成阻挡层13，以覆盖包括槽部12的内壁面12a的基体11的一面11a。
接着，以覆盖阻挡层13的方式形成种子层15（参见图3的（a）：种子层形成工序）。该种子层15在下一工序中被回流，成为埋入槽部12的导电材料。种子层15由Cu构成。种子层15与上述阻挡层13一样使用溅射法形成。种子层15例如以厚度为15nm～55nm左右的方式形成。
对使用溅射装置（成膜装置）1的种子层15的形成方法进行说明。
首先，在基板架7上配置基体11的状态下，通过真空排气系统9对真空槽2内部进行真空排气，一边进行真空排气一边从气体供给系统4导入溅射气体以及化学结构中含有氮或氧的反应气体（例如反应气体为氧的情况下，流量为0.1sccm以上5sccm以下），在真空槽2内部形成比大气压低的成膜气氛（例如总压在10-4Pa以上10-1Pa以下）。
导入溅射气体，真空槽2内部稳定到规定的压力（例如4.0×10-2Pa的压力）后，启动溅射电源8，通过向阴极电极（省略图示）施加负电压，开始放电，将靶5设为Cu，在靶5的表面附近产生等离子体。
然后，进行规定时间的基于溅射的成膜，形成铜薄膜以覆盖阻挡层13后，从真空槽2搬出基体11。
此外，上述溅射装置1的基板架7内设有温度调节单元（省略图示），在形成铜薄膜时，将基体11的温度调节到规定的温度（例如-20℃）。
在溅射装置1中，磁场形成单元3构成为能够与靶5的表面平行地移动和旋转，能够使靶5表面的被溅射区域（腐蚀区域）形成在靶上的任意位置。
接着，将形成种子层15的基体11加热到种子层15的熔化温度以上，从而进行回流（参见图3的（b）：种子层熔化工序）。由此，种子层15熔化而在槽部12的内侧、即阻挡层13的内侧区域埋入由Cu构成的导电材料M。
将种子层15的熔化温度例如设为100℃以上400℃以下。
此外，向阻挡层13的内侧区域的由Cu构成的导电材料M的填充不充分的情况下，优选重复进行两次以上种子层形成工序及种子层熔化工序。由此，能够更可靠地向阻挡层13的内侧区域填充由Cu构成的导电材料M。
此后，去除层压在除了槽部12之外的基体11的一面11a的阻挡层13和导电材料M（参见图3的（c））。由此，在各个槽部12形成埋入槽部12的导电体14、即电路配线。
实施例
下面，用实验例更具体地说明本发明所涉及的实施方式，但本发明不限于以下的实验例。
（实验例1）
作为基体准备厚度0.775mm的附有硅氧化膜的硅基板。
接着，在该基体的一面通过基于光刻法的蚀刻加工形成深度100nm的槽部。
接着，在包括槽部的内壁面的基体的一面通过溅射法形成厚度3nm的由Ta构成的阻挡层。
接着，通过溅射法形成厚度25nm的种子层铜薄膜，以覆盖阻挡层。在形成铜薄膜时，将基体的温度调节到-20℃。
接着，将形成种子层的基体加热到400℃来熔化种子层，从而在槽部的内侧、即阻挡层的内侧区域埋入由Cu构成的导电材料。
在阻挡层的内侧区域埋入由Cu构成的导电材料后，对于该基体，使用扫描式电子显微镜（SEM）调查了槽部的填充率（槽部由Cu填充的比例，体积%）。
此外，将填充率为90%以上的情况评价为○，将填充率为80%以上不满90%的情况评价为△，将填充率不满80%的情况评价为×。
将结果示于表1中。
（实验例2）
除了形成厚度35nm的由Cu构成的种子层之外，与实验例1同样地在基体的槽部内填充了Cu。
另外，与实验例1同样地调查了槽部的填充率。
将结果示于表1中。
（实验例3）
除了形成厚度45nm的由Cu构成的种子层之外，与实验例1同样地在基体的槽部内填充了Cu。
另外，与实验例1同样地调查了槽部的填充率。
将结果示于表1中。
（实验例4）
将形成种子层的基体加热到300℃来熔化种子层而将Cu埋入槽部的内侧，除此之外，与实验例1同样地在基体的槽部内填充了导电体。
另外，与实验例1同样地调查了槽部的填充率。
将结果示于表1中。
（实验例5）
形成厚度35nm的由Cu构成的种子层，将形成种子层的基体加热到300℃来熔化种子层而将Cu埋入槽部的内侧，除此之外，与实验例1同样地在基体的槽部内填充了导电体。
另外，与实验例1同样地调查了槽部的填充率。
将结果示于表1中。
（实验例6）
形成厚度45nm的由Cu构成的种子层，将形成种子层的基体加热到300℃来熔化种子层而将Cu埋入槽部的内侧，除此之外，与实验例1同样地在基体的槽部内填充了导电体。
另外，与实验例1同样地调查了槽部的填充率。
将结果示于表1中。
（实验例7）
形成厚度55nm的由Cu构成的种子层，将形成种子层的基体加热到300℃来熔化种子层而将Cu埋入槽部的内侧，除此之外，与实验例1同样地在基体的槽部内填充了导电体。
另外，与实验例1同样地调查了槽部的填充率。
将结果示于表1中。
（实验例8）
将形成种子层的基体加热到200℃来熔化种子层而将Cu埋入槽部的内侧，除此之外，与实验例1同样地在基体的槽部内填充了导电体。
另外，与实验例1同样地调查了槽部的填充率。
将结果示于表1中。
（实验例9）
形成厚度35nm的由Cu构成的种子层，将形成种子层的基体加热到200℃来熔化种子层而将Cu埋入槽部的内侧，除此之外，与实验例1同样地在基体的槽部内填充了导电体。
另外，与实验例1同样地调查了槽部的填充率。
将结果示于表1中。
（实验例10）
形成厚度45nm的由Cu构成的种子层，将形成种子层的基体加热到200℃来熔化种子层而将Cu埋入槽部的内侧，除此之外，与实验例1同样地在基体的槽部内填充了导电体。
另外，与实验例1同样地调查了槽部的填充率。
将结果示于表1中。
（实验例11）
作为基体准备厚度0.775mm的附有硅氧化膜的硅基板。
接着，在该基体的一面通过基于光刻法的蚀刻加工形成深度100nm的槽部。
接着，在包括槽部的内壁面的基体的一面通过溅射法形成厚度3nm的由Ta构成的阻挡层。
接着，通过溅射法形成厚度25nm的铜薄膜，以覆盖阻挡层。在形成铜薄膜时，将基体的温度调节到-20℃。
接着，将形成种子层的基体加热到400℃来熔化种子层，从而在槽部的内侧、即阻挡层的内侧区域埋入由Cu构成的导电材料。
再次，在阻挡层的内侧区域通过溅射法形成铜薄膜。在形成铜薄膜时，将基体的温度调节到-20℃。
接着，将形成种子层的基体加热到400℃来熔化种子层，从而在槽部的内侧埋入由Cu构成的导电材料。
此后，与实验例1同样地调查了槽部的填充率。
将结果示于表2中。
（实验例12）
将形成种子层的基体加热到350℃来熔化种子层而将Cu埋入槽部的内侧，除此之外，与实验例11同样地在基体的槽部内填充了导电体。
另外，与实验例1同样地调查了槽部的填充率。
将结果示于表2中。
（实验例13）
形成厚度35nm的由Cu构成的种子层，将形成种子层的基体加热到350℃来熔化种子层而将Cu埋入槽部的内侧，除此之外，与实验例11同样地在基体的槽部内填充了导电体。
另外，与实验例1同样地调查了槽部的填充率。
将结果示于表2中。
（实验例14）
形成厚度40nm的由Cu构成的种子层，将形成种子层的基体加热到350℃来熔化种子层而将Cu埋入槽部的内侧，除此之外，与实验例11同样地在基体的槽部内填充了导电体。
另外，与实验例1同样地调查了槽部的填充率。
将结果示于表2中。
（实验例15）
形成厚度15nm的由Cu构成的种子层，将形成种子层的基体加热到300℃来熔化种子层而将Cu埋入槽部的内侧，除此之外，与实验例11同样地在基体的槽部内填充了导电体。
另外，与实验例1同样地调查了槽部的填充率。
将结果示于表2中。
（实验例16）
将形成种子层的基体加热到300℃来熔化种子层而将Cu埋入槽部的内侧，除此之外，与实验例11同样地在基体的槽部内填充了导电体。
另外，与实验例1同样地调查了槽部的填充率。
将结果示于表2中。
（实验例17）
形成厚度35nm的由Cu构成的种子层，将形成种子层的基体加热到300℃来熔化种子层而将Cu埋入槽部的内侧，除此之外，与实验例11同样地在基体的槽部内填充了导电体。
另外，与实验例1同样地调查了槽部的填充率。
将结果示于表2中。
（实验例18）
形成厚度40nm的由Cu构成的种子层，将形成种子层的基体加热到300℃来熔化种子层而将Cu埋入槽部的内侧，除此之外，与实验例11同样地在基体的槽部内填充了导电体。
另外，与实验例1同样地调查了槽部的填充率。
将结果示于表2中。
（实验例19）
形成厚度45nm的由Cu构成的种子层，将形成种子层的基体加热到300℃来熔化种子层而将Cu埋入槽部的内侧，除此之外，与实验例11同样地在基体的槽部内填充了导电体。
另外，与实验例1同样地调查了槽部的填充率。
将结果示于表2中。
（实验例20）
将形成种子层的基体加热到250℃来熔化种子层而将Cu埋入槽部的内侧，除此之外，与实验例11同样地在基体的槽部内填充了导电体。
另外，与实验例1同样地调查了槽部的填充率。
将结果示于表2中。
（实验例21）
形成厚度35nm的由Cu构成的种子层，将形成种子层的基体加热到250℃来熔化种子层而将Cu埋入槽部的内侧，除此之外，与实验例11同样地在基体的槽部内填充了导电体。
另外，与实验例1同样地调查了槽部的填充率。
将结果示于表2中。
（实验例22）
形成厚度40nm的由Cu构成的种子层，将形成种子层的基体加热到250℃来熔化种子层而将Cu埋入槽部的内侧，除此之外，与实验例11同样地在基体的槽部内填充了导电体。
另外，与实验例1同样地调查了槽部的填充率。
将结果示于表2中。
[表1]
Figure BDA0000434908200000101
[表2]
Figure BDA0000434908200000102
从表1的结果可知，只要将种子层的厚度设在35nm以上，将种子层的熔化温度设在300℃以上，则对于槽部的导电材料（Cu）的填充性提高。
从表2的结果可知，在重复进行两次种子层形成工序及种子层熔化工序的情况下，只要将种子层的厚度设在35nm以上，将种子层的熔化温度设在250℃以上，则对于槽部，能够充分地填充导电材料（Cu）。
符号说明
10     半导体装置
11     基体
12     槽部（沟）
13     阻挡层（阻挡金属）
14     导电体（电路配线）
15     种子层

Claims (6)

1.一种半导体装置的制造方法，其特征在于，具备：
槽部形成工序，在基体形成槽部；
阻挡层形成工序，形成至少覆盖所述槽部的内壁面的阻挡层；
种子层形成工序，形成覆盖所述阻挡层的种子层；以及
种子层熔化工序，通过回流法使所述种子层熔化，
所述种子层由Cu构成。
2.根据权利要求1所述的半导体装置的制造方法，其特征在于，
所述种子层形成工序具有：形成覆盖所述阻挡层的Cu薄膜的工序；以及对所述Cu薄膜进行热处理的工序，
所述热处理在100℃以上400℃以下的温度范围内进行。
3.根据权利要求1所述的半导体装置的制造方法，其特征在于，
重复进行两次以上所述种子层形成工序及所述种子层熔化工序。
4.根据权利要求1所述的半导体装置的制造方法，其特征在于，
所述阻挡层由含有Ta、Ti、W、Ru、V、Co和Nb中的至少一种的材料构成。
5.根据权利要求1所述的半导体装置的制造方法，其特征在于，
所述基体由半导体基板和在所述半导体基板的一面形成的绝缘层构成。
6.一种半导体装置，其特征在于，
具备：形成在基体的槽部；覆盖所述槽部的内壁面的阻挡层；以及被埋入在所述阻挡层的内侧区域的导电体，
所述导电体是通过回流法使覆盖所述阻挡层的由Cu构成的种子层熔化而形成。
CN201280028713.8A 2011-09-30 2012-09-20 半导体装置的制造方法及半导体装置 Pending CN103620746A (zh)

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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10681778B2 (en) * 2017-11-21 2020-06-09 Watlow Electric Manufacturing Company Integrated heater and method of manufacture
US11527437B2 (en) 2020-09-15 2022-12-13 Applied Materials, Inc. Methods and apparatus for intermixing layer for enhanced metal reflow

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1074760A (ja) * 1996-08-30 1998-03-17 Sony Corp 配線形成方法
US5891803A (en) * 1996-06-26 1999-04-06 Intel Corporation Rapid reflow of conductive layers by directional sputtering for interconnections in integrated circuits
KR100259357B1 (ko) * 1998-02-07 2000-06-15 김영환 반도체 소자의 배선형성방법
JP2002075994A (ja) * 2000-08-24 2002-03-15 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
US20030139033A1 (en) * 1993-12-28 2003-07-24 Gardner Donald S. Copper reflow process
CN101399220A (zh) * 2007-09-27 2009-04-01 力晶半导体股份有限公司 金属互连的制造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06103681A (ja) 1992-09-18 1994-04-15 Nec Home Electron Ltd 磁気ディスク装置
JP3337876B2 (ja) * 1994-06-21 2002-10-28 株式会社東芝 半導体装置の製造方法
US5654232A (en) * 1994-08-24 1997-08-05 Intel Corporation Wetting layer sidewalls to promote copper reflow into grooves
JPH08264535A (ja) * 1995-03-27 1996-10-11 Fujitsu Ltd 半導体装置の製造方法
US6077780A (en) * 1997-12-03 2000-06-20 Advanced Micro Devices, Inc. Method for filling high aspect ratio openings of an integrated circuit to minimize electromigration failure
US6184137B1 (en) * 1998-11-25 2001-02-06 Applied Materials, Inc. Structure and method for improving low temperature copper reflow in semiconductor features
KR100465063B1 (ko) * 2002-04-01 2005-01-06 주식회사 하이닉스반도체 반도체 소자의 금속배선 형성방법
US7030016B2 (en) 2004-03-30 2006-04-18 Taiwan Semiconductor Manufacturing Co., Ltd. Post ECP multi-step anneal/H2 treatment to reduce film impurity
JP4760236B2 (ja) * 2005-05-27 2011-08-31 日立化成工業株式会社 単結晶の熱処理方法
JP2008071850A (ja) * 2006-09-13 2008-03-27 Sony Corp 半導体装置の製造方法
KR100975652B1 (ko) * 2007-10-05 2010-08-17 한국과학기술원 아연 및 아연합금을 이용한 비아 및 그의 형성 방법, 그를3차원 다중 칩 스택 패키지 제조 방법
US20090194875A1 (en) * 2008-01-31 2009-08-06 International Business Machines Corporation HIGH PURITY Cu STRUCTURE FOR INTERCONNECT APPLICATIONS
KR20130053338A (ko) * 2011-11-15 2013-05-23 삼성전자주식회사 Ｔｓｖ 구조를 구비한 집적회로 소자
US8637957B1 (en) * 2012-07-18 2014-01-28 International Business Machines Corporation Low cost anti-fuse structure

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030139033A1 (en) * 1993-12-28 2003-07-24 Gardner Donald S. Copper reflow process
US5891803A (en) * 1996-06-26 1999-04-06 Intel Corporation Rapid reflow of conductive layers by directional sputtering for interconnections in integrated circuits
JPH1074760A (ja) * 1996-08-30 1998-03-17 Sony Corp 配線形成方法
KR100259357B1 (ko) * 1998-02-07 2000-06-15 김영환 반도체 소자의 배선형성방법
JP2002075994A (ja) * 2000-08-24 2002-03-15 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
CN101399220A (zh) * 2007-09-27 2009-04-01 力晶半导体股份有限公司 金属互连的制造方法

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