WO2012147803A1 - ノイズ抑制構造を有する回路基板 - Google Patents
ノイズ抑制構造を有する回路基板 Download PDFInfo
- Publication number
- WO2012147803A1 WO2012147803A1 PCT/JP2012/061107 JP2012061107W WO2012147803A1 WO 2012147803 A1 WO2012147803 A1 WO 2012147803A1 JP 2012061107 W JP2012061107 W JP 2012061107W WO 2012147803 A1 WO2012147803 A1 WO 2012147803A1
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- WIPO (PCT)
- Prior art keywords
- circuit board
- conductor
- line
- ground plane
- island electrode
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P7/00—Resonators of the waveguide type
- H01P7/08—Strip line resonators
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P1/00—Auxiliary devices
- H01P1/20—Frequency-selective devices, e.g. filters
- H01P1/201—Filters for transverse electromagnetic waves
- H01P1/203—Strip line filters
- H01P1/20327—Electromagnetic interstage coupling
- H01P1/20336—Comb or interdigital filters
- H01P1/20345—Multilayer filters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P7/00—Resonators of the waveguide type
- H01P7/08—Strip line resonators
- H01P7/082—Microstripline resonators
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
- H05K1/0224—Patterned shielding planes, ground planes or power planes
- H05K1/0225—Single or multiple openings in a shielding, ground or power plane
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/0243—Printed circuits associated with mounted high frequency components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
- H05K1/0253—Impedance adaptations of transmission lines by special lay-out of power planes, e.g. providing openings
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
- H05K1/165—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed inductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09263—Meander
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/0929—Conductive planes
- H05K2201/09336—Signal conductors in same plane as power plane
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
Definitions
- the present invention relates to a circuit board having a noise suppression structure applied to a wireless communication device and an electronic device.
- circuit boards for example, printed circuit boards
- electronic devices for example, mobile phones, personal computers with wireless functions, and portable information terminals
- an electromagnetic wave generated by each component affects other components as electromagnetic noise and causes a malfunction.
- the power distribution system may propagate noise and affect the electronic circuit, or noise may directly affect the signal wiring.
- FIG. 12 is a perspective view of a circuit board 101 on which a plurality of integrated circuits (LSI circuits) 102 to 105 are mounted.
- LSI circuits integrated circuits
- signal lines 106 and 107 are wired between the integrated circuits 102 and 103 and between the integrated circuits 104 and 105.
- a plurality of bypass capacitors 108 are mounted on the circuit board 101.
- a ground plane GND is formed on the surface of the circuit board 101.
- a power plane (not shown) is formed in the inner layer of the circuit board 101.
- a power source 109 is mounted on the circuit board 101 and connected to the power plane and the ground plane GND.
- FIG. 13 is an equivalent circuit diagram of the circuit board 101 on which the bypass capacitor 108 is not mounted.
- a signal flows from the integrated circuit 102 to the integrated circuit 103
- a charge / discharge current I flows from the power supply 109 to the power supply terminal or the ground plane GND in accordance with on / off switching of a transistor (not shown).
- a voltage drop occurs between the integrated circuits 102 and 104 due to the inductance parasitic on the power plane or the ground plane GND, and the power supply voltage is lowered correspondingly, and the influence of the power supply noise N appears on the integrated circuit 104.
- FIG. 14 is an equivalent circuit diagram of the circuit board 101 on which the bypass capacitor 108 is mounted.
- capacitors 108 are connected between the power supply terminals and the ground terminals of the integrated circuits 102 to 105, respectively.
- the charge / discharge current I is supplied to the bypass capacitor 108 in the vicinity of the integrated circuit 102 via a path indicated by a one-dot chain line. For this reason, no high frequency current flows outside the loop formed by the integrated circuit 102 and the bypass capacitor 108, so that the influence of the charge / discharge current I on the other integrated circuits 103 to 105 can be reduced.
- FIG. 15 is a perspective view of the circuit board 101 on which a plurality of integrated circuits 102 to 105 are mounted.
- signal lines 106 and 107 are wired between the integrated circuits 102 and 103 and between the integrated circuits 104 and 105.
- An electromagnetic field may be generated in the signal line 106 that propagates the signal and may be electromagnetically coupled to the signal line 107 via the surrounding space or the circuit board 101. For this reason, the electromagnetic influence of the signal line 106 is superimposed on the signal S 1 output from the integrated circuit 104 as noise N, and the deteriorated signal S 2 is transmitted to the integrated circuit 105.
- a filter is inserted into the signal wiring to remove noise N coupled to the signal wiring.
- a plurality of chip inductors 109 are inserted in series with the signal wiring 107 and a chip capacitor 110 is inserted in parallel to form a T-type filter. Since this T-type filter functions as a low-pass filter (LPF), high-frequency noise can be removed.
- LPF low-pass filter
- FIGS. 16A to 16E show configuration examples of LPFs using inductors and capacitors.
- FIG. 16A shows an LPF that connects the inductor 120 in series with the signal wiring.
- FIG. 16B shows an LPF in which the capacitor 130 is inserted in parallel between the signal wiring and the ground.
- FIG. 16C shows an L-type LPF in which the inductor 121 is connected in series to the signal wiring, and the capacitor 131 is inserted in parallel between the signal wiring and the ground.
- FIG. 16D shows a T-type LPF composed of inductors 122 and 123 and a capacitor 132.
- FIG. 16E shows a ⁇ -type LPF composed of an inductor 124 and capacitors 133 and 134. In such an equivalent circuit shown in FIG.
- Patent Document 1 discloses a noise suppression structure for a multilayer printed circuit board.
- the first conductor through which the high-frequency current flows and the noise suppression layer are electromagnetically coupled via the insulating layer, and further, the noise suppression layer is electromagnetically coupled via the second conductor and the insulating layer. ing.
- Patent Document 2 discloses a method for reducing noise in a circuit board.
- high frequency noise generated in the integrated circuit (IC) flows from the IC ground terminal through the IC ground pattern formed on the surface wiring layer into the first via hole, and from the first via hole to the first ground.
- Flows into the pattern flows from the first ground pattern through the second via hole, flows into the third ground pattern formed in the bottom wiring layer, and passes through the third via hole from the third ground pattern. Furthermore, it is emitted to the outside via the second ground pattern.
- Patent Document 3 discloses a noise radiation suppression memory module.
- the multilayer printed board includes a plurality of signal wirings or power supply patterns and a surrounding ground pattern, and the surrounding ground patterns are connected by connection vias. Also, noise emission from the multilayer printed circuit board is suppressed by generating electric fields in opposite directions by the operation of the planar antenna constituted by the surrounding ground pattern.
- the noise suppression structure disclosed in Patent Document 1 has a multilayer structure in which a single noise suppression layer is electromagnetically coupled between the first and second conductors via an insulating layer. In order to obtain a noise suppression effect, it is necessary to form a noise suppression layer having a certain area. In particular, in wireless communication devices that are becoming smaller and thinner, a noise suppression structure with a small mounting area on a circuit board is desired. However, since the noise suppression structure of Patent Document 1 includes a resonator on the same plane, the mounting area increases in order to suppress low-frequency noise.
- the present invention has been made in consideration of the above-described circumstances, and its purpose is to eliminate power distribution system noise and noise propagating through signal lines without mounting additional circuit components, and to achieve a compact size. It is to provide a circuit board that can be realized.
- a noise suppression structure is formed on a circuit board in which a transmission line is constituted by a first conductor (for example, a signal line) and a second conductor (for example, a ground plane) arranged opposite to each other in different wiring layers.
- a circular slit is formed in the second conductor, and an island electrode separated from the second conductor is formed inside the slit.
- a third conductor (for example, a resonance line) is formed in a wiring layer different from the second conductor, and the third conductor is connected to the second conductor and the island electrode by a plurality of interlayer connection vias.
- the present invention it is possible to effectively remove the power distribution system noise and the noise propagating through the signal line with a simple and small configuration without mounting additional components on the circuit board.
- FIG. 3 is an equivalent circuit diagram for explaining the function of the noise suppression structure according to the first embodiment.
- 6 is a cross-sectional view and an exploded view of a circuit board according to a first modification of the first embodiment.
- 6 is a cross-sectional view and an exploded view of a circuit board according to a second modification of the first embodiment.
- 3 is a perspective view of a circuit board according to an application example of Example 1.
- FIG. It is a graph which shows the result of having performed the electromagnetic field analysis on the transmission characteristic of the signal wire
- FIG. 13 is a circuit diagram for explaining a power supply noise suppression operation by a bypass capacitor in the circuit board of FIG. 12. It is a perspective view of the circuit board which has arrange
- FIG. 16 is a simplified circuit diagram showing an LPF applicable to the circuit board of FIG. 15.
- FIG. 16 is a simplified circuit diagram showing a configuration in which LPFs are arranged between integrated circuits in the circuit board of FIG. 15. It is sectional drawing and the exploded view of the circuit board which concerns on the modification 3 of Example 1 which extended the right end side of the resonance line. It is sectional drawing and the exploded view of the circuit board which concerns on the modification 4 of Example 1 which expanded the width
- FIG. 1 shows a circuit board 11 having a noise suppression structure 10 according to a first embodiment of the present invention.
- 1A is a sectional view of the circuit board 11, and
- FIG. 1B is an exploded view of the circuit board 11.
- the circuit board 11 has first, second, and third wiring layers.
- a signal line 12 is formed in the first wiring layer, and a resonance line 13 is formed in the third wiring layer.
- a ground plane 14 and island electrodes 15 separated inward by a circular slit 18 are formed in the second wiring layer.
- the left end of the resonance line 13 is connected to the island electrode 15 via the interlayer connection via 17, and the right end of the resonance line 13 is connected to the ground plane 14 via the interlayer connection via 16.
- FIG. 2 is an equivalent circuit diagram for explaining the function of the noise suppression structure 10 according to the first embodiment.
- the equivalent circuit diagram of the noise suppression structure shows the wiring system of the circuit board 11, and the cylindrical elements denoted by reference numerals 21 to 24 are transmission circuit models showing transmission paths in the circuit board 11.
- signal lines are connected to both left and right ends, and a reference terminal is connected to the lower end.
- the solid line connecting the transmission circuit models 21 to 24 means an electrical connection, and does not represent the electrical characteristics (such as wiring length).
- the transmission circuit model 21 represents a microstrip line composed of the signal line 12 and the ground plane 14 or the island electrode 15 in the region on the left side of the right end of the slit 18 shown in FIG.
- the transmission circuit model 22 represents a microstrip line composed of the signal line 12 and the ground plane 14 in a region on the right side of the right end of the slit 18.
- the transmission circuit model 23 represents a parallel plate type transmission line composed of the resonance line 13 and the island electrode 15, and the two transmission circuit models 24 are formed by a slit 18 between the ground plane 14 and the island electrode 15. The slot line to be formed is shown.
- the transmission circuit models 23 and 24 form a composite resonator 25 having a common input section.
- the two transmission circuit models are connected in a circular manner, and the terminal 26 on the left side of the transmission circuit model 23 is short-circuited to the ground 27.
- the reference terminal 28 of the transmission circuit model 21 and the 22 reference terminals 29 from which the transmission circuit also comes out are separated, and these reference terminals 28 and 29 are connected to the input portion of the composite resonator 25.
- a general-purpose board can be used as the circuit board 11.
- a substrate using an organic material epoxy, polyimide, fluororesin, PPE resin, phenol resin, or the like
- a substrate using an insulating material ceramic, glass, silicon, composite material, or the like
- etching, a lithography printing technique, or the like can be employed.
- a method of forming the interlayer connection vias 16 and 17 of the circuit board holes are formed in the insulating material by laser irradiation or drilling, and conductive portions are formed by filling with metal paste or plating.
- circuit board 11 according to the first embodiment has a three-layer structure, it need not be limited to this. You may produce the circuit board 11 which consists of multiple layers more than three layers. For example, a noise reduction effect may be obtained by fabricating a circuit board having four or more wiring layers and applying the structure of the first embodiment to three of the wiring layers.
- the slit 18 and the island electrode 15 are formed in a rectangular shape, but it is not necessary to limit to this, and other shapes can be adopted.
- the slit 18 and the island electrode 15 may be circular, elliptical, or polygonal. Whatever the shape, if there is no other electrode between the slit 18 and the island electrode 15 and a slot line can be formed by both, a noise suppressing effect can be obtained.
- the interlayer connection vias 16 and 17 are arranged at a position in contact with the slit 18 separating the ground plane 14 and the island electrode 15, and most of the resonance line 13 is connected to the island electrode 15. Although it overlaps with planar view and hardly overlaps with the ground plane 14, it is not necessary to limit to this.
- the resonance line 13 and the interlayer connection vias 16 and 17 are translated as shown in FIG. 3 so that the resonance line 13 overlaps the ground plane 14 in plan view. Can do.
- the first modification includes three resonators: a loop-type slot line resonator, a short-circuited termination resonator of the transmission line of the resonance line 13 and the island electrode 15, and a short-circuited termination resonator of the transmission line of the resonance line 13 and the ground plane 14.
- a composite resonator including
- the signal line 12 is disposed so as to straddle the slit 18 twice as shown in FIG. 1, but it is not necessary to limit to this.
- the signal line 12 may be rearranged so as to straddle the circular slit 18 once as shown in FIG. In FIG. 4, the signal line 12 is connected to the integrated circuit IC disposed above the island electrode 15 and terminated at that position.
- the part where the signal line 12 straddles the slit 18 between the island electrode 15 and the ground plane 14 serves as an input part of the resonance line 13 so that the resonator functions and suppresses noise at the resonance frequency. Can do.
- the left end of the resonance line 13 is connected to the island electrode 15 by the interlayer connection via 17, while the right end of the resonance line 13 is connected to the ground plane 14 by the interlayer connection via 16.
- . 18 shows a circuit board according to a third modification of the first embodiment, in which the right end side of the resonance line 13 is extended as compared with the circuit board 11 shown in FIG.
- the left end of the resonance line 13 is connected to the island electrode 15 by the interlayer connection via 17, while the predetermined position on the right end side of the resonance line 13 is connected to the ground plane 14 by the interlayer connection via 16.
- the right end side of the resonance line 13 is extended, but the left end side of the resonance line 13 may be extended or both end sides of the resonance line 13 may be extended.
- FIG. 19 shows a circuit board according to the fourth modification of the first embodiment.
- the width of the resonance line 13 is expanded as compared with the circuit board 11 shown in FIG. 1, and the left end of the resonance line 13 has two layers.
- the connection via 17 is connected to the island electrode 15, while the right end of the resonance line 13 is connected to the ground plane 14 by two interlayer connection vias 16.
- FIG. 5 is a perspective view of a circuit board 31 as an application example of the first embodiment.
- integrated circuits (LSI circuits) 32 to 35 are mounted on the circuit board 31.
- a signal line 38 is formed between the integrated circuits 32 and 33, and a signal line 37 is formed between the integrated circuits 34 and 35.
- a clock signal having a frequency of 1.2 GHz is transmitted between the integrated circuits 32 and 33 via the signal line 38, while a 500 Mbps digital signal is transmitted between the integrated circuits 34 and 35 via the signal line 37.
- a part of the output signal of the integrated circuit 32 is coupled to the signal line 37 as noise N.
- the noise suppression structure 10 shown in FIG. 1 is applied to a region B indicated by a dotted line on the circuit board 31.
- the circuit board 31 having the noise suppression structure 10 has a three-layer structure with a relative dielectric constant ( ⁇ r ) of 4.4.
- the substrate thickness a between the first and second wiring layers is 60 ⁇ m
- the substrate thickness b between the second and third wiring layers is 150 ⁇ m
- the thickness of the resonance line 13 is 20 ⁇ m
- the width c of the resonance line 13 is
- the length d between 1 mm and the interlayer connection vias 16 and 17 is 18 mm.
- the entire length of the signal line 37 is 40 mm
- the distance between the right end of the resonance line 13 and the integrated circuit 35 is 5 mm
- the distance between the left end of the resonance line 13 and the integrated circuit 34 is 15 mm.
- FIG. 6 is a graph showing the result of electromagnetic field analysis of the transmission characteristics of the signal line 37 using a three-dimensional electromagnetic field simulator.
- This graph represents S21 indicating insertion loss among S parameters of the signal line 37, and this represents the ratio of the amplitude of the input signal of the integrated circuit 35 to the output signal of the integrated circuit 34.
- S21 is remarkably small at the resonance frequency (1.2 GHz or the like) of the composite resonator, but at other frequencies, S21 is a value close to approximately 0 dB.
- the graph of FIG. 6 shows that a signal with a specific frequency is significantly attenuated to prevent signal propagation, but signals with other frequencies are transmitted without being attenuated. That is, the signal line 37 behaves as a band elimination filter. Since the signal line 37 has the resonance structure shown in FIG. 1 in the middle region, the 500 Mbps digital signal output from the integrated circuit 34 reaches the integrated circuit 35, but the 1.2 GHz signal coming from the integrated circuit 32. Noise N is removed. Thereby, the signal line 37 can perform good signal transmission.
- the resonance line 13 forms a transmission line connecting the ground plane 14 and the island electrode 15.
- the part straddling the slot line becomes the input part, and the part connected by the interlayer connection vias 16 and 17 becomes the short-circuit termination, so the length from the input part to the short-circuit termination becomes 1/4 of the wavelength.
- the impedance of the input part of the resonator becomes a very large value due to resonance at the frequency at which the two resonators described above are complexly resonated. Can be suppressed.
- the frequency at which the two resonators are complexly resonated is lower than the single resonance frequency of each resonator, low frequency noise can be removed by using the two resonators together. If an attempt is made to lower the resonance frequency of a single resonator, the wavelength becomes longer and the line length increases at a lower frequency, so the shape of the resonator needs to be increased. Therefore, by using a plurality of resonators in combination, the size can be reduced as compared with a structure using a single resonator.
- the noise suppression structure 10 according to the first embodiment can be accommodated in the wiring layer, a large mounting area on the circuit board is not required unlike the conventional noise suppression structure. Further, it is not necessary to mount an inductor or a capacitor on the circuit board as the noise suppression structure 10, thereby reducing component management cost, mounting work process, lead time, installation area on the circuit board, cost, design / manufacturing time, etc. be able to.
- FIG. 7 shows a circuit board 21 having a noise suppression structure 20 according to the second embodiment of the present invention.
- 7A is a sectional view of the circuit board 21, and
- FIG. 7B is an exploded view of the circuit board 21.
- the circuit board 21 has two wiring layers.
- a signal line 22 and a resonance line 23 are formed in the first wiring layer, and a ground plane 24 having a circular slit 28 is formed in the second wiring layer. Is formed.
- An island electrode 25 is formed inside the slit 28.
- the left end of the resonance line 23 is connected to the island electrode 25 by the interlayer connection via 27, and the right end of the resonance line 23 is connected (short-circuited) to the ground plane 24 by the interlayer connection via 26.
- Example 2 Compared with Example 1, the characteristic of Example 2 is that the signal line 22 and the resonance line 23 are formed in the same wiring layer. Similar to the noise suppression structure 10 according to the first embodiment, also in the noise suppression structure 20 according to the second embodiment, a resonator is formed by the resonance line 23 and the island electrode 25, and on the other hand, the island electrode 25 divided by the slit 28 The ground plane 24 forms a loop type slot line resonator. Accordingly, the second embodiment functions similarly to the first embodiment and can effectively suppress noise.
- FIG. 8 shows a circuit board 41 having a noise suppression structure 40 according to the third embodiment.
- 8A is a cross-sectional view of the circuit board 41
- FIG. 8B is an exploded view of the circuit board 41.
- the circuit board 41 has three wiring layers.
- a power plane 42 is formed in the first wiring layer, and a ground plane 44 having a circumferential slit 48 is formed in the second wiring layer.
- a resonance line 43 is formed in the wiring layer.
- An island electrode 45 is formed inside the slit 48. The left end of the resonance line 43 is connected to the island electrode 45 by the interlayer connection via 47, and the right end of the resonance line 43 is connected to the ground plane 44 by the interlayer connection via 46.
- the function of the noise suppression structure 40 according to the third embodiment will be described with reference to FIG. If the power plane 42 is regarded as a signal line, the power distribution system composed of the power plane 42 and the ground plane 44 can be considered as a kind of transmission line. If the signal propagation direction is the left-right direction of FIG. 8, the equivalent circuit of this power distribution system can be expressed by the equivalent circuit diagram of FIG.
- the transmission circuit model 21 represents a parallel plate line composed of a power plane 42 and a ground plane 44 or an island electrode 45 in a region on the left side of the right end of the slit 48.
- the transmission circuit model 22 represents a parallel plate line in a region on the right side of the right end of the slit 48.
- the upper transmission circuit model 24 represents a parallel plate line composed of a resonance line 43 and a ground plane 44.
- the transmission circuit model 23 represents a parallel plate type transmission line composed of a resonance line 43 and an island electrode 45.
- the lower transmission circuit model 24 represents a slot line formed by a slit 48 between the ground plane 44 and the island electrode 45.
- the feature of the third embodiment is that the two transmission circuit models 24 circulate, the terminal 26 on the left side of the transmission circuit model 23 is short-circuited to the ground 27, and the transmission circuit models 23 and 24 have an input section.
- the common composite resonator 25 is formed.
- the reference terminal 28 of the transmission circuit model 21 is separated from the reference terminal 29 of the transmission circuit model 22, and these reference terminals 28 and 29 are connected to the input portion of the composite resonator 25.
- the input impedance of the composite resonator 25 becomes infinite at the resonance frequency, and the signal attenuation of the entire power distribution system increases. Therefore, the circuit board 41 according to the third embodiment behaves as a band elimination filter having the resonance frequency as the center frequency of the attenuation band, and can effectively remove noise in the attenuation band.
- FIG. 9 shows a circuit board 51 having a noise suppression structure 50 according to the fourth embodiment.
- 9A is a cross-sectional view of the circuit board 51
- FIG. 9B is an exploded view of the circuit board 51.
- the circuit board 51 has three wiring layers, a signal line 52 is formed in the first wiring layer, and a ground plane 54 having a circumferential slit 58 is formed in the second wiring layer.
- a meandering resonance line 53 is formed.
- An island electrode 55 is formed inside the slit 58. The left end of the resonance line 53 is connected to the island electrode 55 by the interlayer connection via 57, and the right end of the resonance line 53 is connected to the ground plane 54 by the interlayer connection via 56.
- the resonance line 53 has a meandering shape, so that the line length of the resonator can be gained in a narrow range, so that the third wiring is maintained while maintaining a desired resonance frequency.
- the area occupied by the resonator in the layer can be reduced.
- FIG. 10 shows a circuit board 61 having a noise suppression structure 60 according to the fifth embodiment.
- 10A is a sectional view of the circuit board 61
- FIG. 10B is an exploded view of the circuit board 61.
- the circuit board 61 has three wiring layers.
- a signal line 62 is formed in the first wiring layer, and a ground plane 64 having a circumferential and uneven slit 68 is formed in the second wiring layer.
- the resonance line 63 is formed in the third wiring layer.
- An island electrode 65 is formed inside the slit 68. The left end of the resonance line 63 is connected to the island electrode 65 by the interlayer connection via 67, and the right end of the resonance line 63 is connected to the ground plane 64 by the interlayer connection via 66.
- the slit 68 and the island electrode 65 are not a rectangle but an uneven shape, so that the slot line constituted by the ground plane 64 and the island electrode 65 has a meandering shape and is narrower than the slit 68
- the line length of the one-wavelength loop resonator can be obtained. Therefore, the area occupied by the resonator in the second wiring layer can be reduced while maintaining a desired resonance frequency.
- the noise suppression structure including the ground plane and the resonance line is disposed only in the adjacent wiring layer on the lower side when viewed from the signal line, but the noise is formed on both the upper and lower sides of the signal line. You may make it arrange
- FIG. 11 shows a circuit board 71 having a noise suppression structure 70 according to the sixth embodiment.
- 11A is a cross-sectional view of the circuit board 71
- FIG. 11B is an exploded view of the circuit board 71.
- the circuit board 71 includes five wiring layers. From the upper side, the first wiring layer, the second wiring layer, the third wiring layer (that is, the intermediate wiring layer), and the fourth wiring layer are formed. The wiring layer and the fifth wiring layer are laminated in this order.
- a signal line 72 is formed in the third wiring layer of the circuit board 71, a ground plane 74 having a circumferential slit 78 is formed in the fourth wiring layer, and a resonance line 73 is formed in the fifth wiring layer. Yes.
- An island electrode 75 is formed inside the slit 78.
- the left end of the resonance line 73 is connected to the island electrode 75 by the interlayer connection via 77, and the right end of the resonance line 73 is connected to the ground plane 76 by the interlayer connection via 76.
- a resonance line 81 is formed in the first wiring layer, and a ground plane 83 having a circumferential slit 84 is formed in the second wiring layer.
- An island electrode 82 is formed inside the slit 84. The left end of the resonance line 81 is connected to the island electrode 82 by the interlayer connection via 79, and the right end of the resonance line 81 is connected to the ground plane 83 by the interlayer connection via 80.
- resonators are formed in the upper wiring layer and the lower wiring layer of the signal line 72 of the third wiring layer, and each resonator functions as a filter independently.
- Example 6 the slits 84 of the second wiring layer and the slits 78 of the fourth wiring layer are different in size, the circumferences of the respective slot lines are also different, and the one-wavelength resonance frequencies of the two are also different. Become. Further, since the resonance line 81 of the first wiring layer and the resonance line 73 of the fifth wiring layer are different in length, the resonance frequency of both is also different. Therefore, the composite resonance frequency is different between the upper resonator and the lower resonator of the signal line 72.
- the entire noise suppression structure 70 functions as a noise suppression filter if one of the upper and lower fanatics resonates. Therefore, noise suppression mechanisms having different resonance frequencies are provided on the upper and lower wiring layers of the signal line 72, respectively. By providing, the band removal frequency can be doubled.
- the bandwidth of the frequency to be removed is the same as when the resonator is formed only in one of the upper and lower wiring layers of the signal line 72, and the band is removed. Signal attenuation and bandwidth can be increased.
- the resonator includes a first conductor (for example, a signal line), a second conductor (for example, a ground plane), and a third conductor (for example, a resonance line).
- first conductor for example, a signal line
- second conductor for example, a ground plane
- third conductor for example, a resonance line
- various structures can be employed for the resonator.
- the first conductor may be linear
- the second conductor may be planar.
- both the first conductor and the second conductor may be planar.
- the third conductor may be linear.
- circuit board having the noise suppression structure according to the present invention can be reduced in size with a simple configuration, it can be designed with shapes and dimensions specialized for various electronic devices and communication devices.
- the present invention is applied to a wide range of fields such as personal computers equipped with wireless functions and portable information terminals.
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Abstract
Description
本願は、2011年4月28日に日本国に出願された特願2011-100971号に基づき優先権を主張し、その内容をここに援用する。
図12は、複数の集積回路(LSI回路)102~105が実装された回路基板101の斜視図である。高速信号伝送路として、信号線106、107が集積回路102、103間及び集積回路104、105間に配線されている。また、複数のバイパスコンデンサ108が回路基板101上に実装されている。これらの部品の周囲にはグランドプレーンGNDが回路基板101の表面上に形成されている。また、電源プレーン(不図示)が回路基板101の内層に形成されている。また、電源109が回路基板101上に実装されており、電源プレーンとグランドプレーンGNDに接続されている。
図13は、バイパスコンデンサ108が実装されていない回路基板101の等価回路図である。図13において、集積回路102から集積回路103に信号が流れると、トランジスタ(不図示)のオン/オフスイッチングに伴い、電源109から電源端子又はグランドプレーンGNDに対して充放電電流Iが流れる。このとき、電源プレーン又はグランドプレーンGNDに寄生するインダクタンスにより、集積回路102、104間に電圧降下が発生し、その分、電源電圧が低下し、集積回路104には電源ノイズNの影響が現れる。
図14は、バイパスコンデンサ108を実装した回路基板101の等価回路図である。ここで、集積回路102~105の電源端子とグランド端子との間にコンデンサ108がそれぞれ接続されている。このような回路構成において、例えば、集積回路102から集積回路103に信号が流れた場合、充放電電流Iは一点鎖線で示す経路を介して集積回路102の近傍のバイパスコンデンサ108に供給される。このため、集積回路102とバイパスコンデンサ108とで形成されるループの外側には高周波電流は流れないので、充放電電流Iによる他の集積回路103~105への影響を低減させることができる。
図15は、複数の集積回路102~105が実装された回路基板101の斜視図である。高速信号伝送路として、信号線106、107が集積回路102、103間及び集積回路104、105間に配線されている。信号を伝搬する信号線106に電磁界が発生して、周囲の空間や回路基板101を介して電磁的に信号線107に結合することがある。このため、信号線106の電磁的影響が集積回路104から出力された信号S1にノイズNとして重畳され、劣化した信号S2が集積回路105に伝送されてしまう。
この回路基板11には汎用の基板を用いることができる。例えば、有機材料(エポキシ、ポリイミド、フッ素樹脂、PPE樹脂、フェノール樹脂等)を用いた基板や、絶縁材料(セラミック、ガラス、シリコン、コンポジット材等)を用いた基板を採用することができる。基板の各層のパターンニング形成法として、エッチングやリソグラフィ印刷技術等を採用することができる。回路基板11の層間接続ビア16、17の形成法として、絶縁材料にレーザ照射やドリル加工によって穴を形成し、金属ペーストの充填やメッキによって導通部を形成する。
実施例1では図1に示すように、層間接続ビア16、17がグランドプレーン14と島電極15とを隔てるスリット18に接する位置に配置されており、共振線13の大部分が島電極15と平面視で重複し、グランドプレーン14とは殆ど重複していないが、これに限定する必要はない。実施例1の変形例1として、図3に示すように共振線13と層間接続ビア16、17とを平行移動して、共振線13がグランドプレーン14とも平面視で重複するように配置することができる。この変形例1は、ループ型スロット線路共振器、共振線13と島電極15の伝送路の短絡終端共振器、及び共振線13とグランドプレーン14の伝送路の短絡終端共振器の3つの共振器を包含する複合共振器である。
前述の実施例1乃至実施例5では、信号線から見て下側の隣接配線層のみにグランドプレーンと共振線からなるノイズ抑制構造を配置したが、信号線の上側と下側の両方にノイズ抑制構造を配置するようにしてもよい。
12、22、37、38、52、62、72 信号線
13、23、43、53、63、73、81 共振線
14、24、44、54、64、74、83 グランドプレーン
15、25、45、55、65、75、82 島電極
16、17、26、27、46、47、56、57、66、67、77、79、80 層間接続ビア
18、28、48、58、68、78、84 スリット
32、33、34、35 集積回路
42 電源プレーン
Claims (10)
- 異なる配線層において対抗配置された第1導体と第2導体によって伝送線路を構成した回路基板であって、
前記第2導体に周回状のスリットが形成され、当該スリットの内側に前記第2導体から分離された島電極が形成され、
前記第2導体とは異なる配線層に第3導体が形成され、当該第3導体が複数の層間接続ビアによって前記第2導体と前記島電極に接続されており、
前記第1導体が部分的に平面視で前記島電極と重複するよう配設することによって、前記伝送線路を包含する複合共振器を構成するようにした回路基板。 - 前記島電極と前記第2導体とは前記第3導体を介して接続するようにした請求項1記載の回路基板。
- 前記第3導体は平面視で前記島電極と重複するように配設した請求項1記載の回路基板。
- 前記第3導体は前記島電極と前記第2導体に平面視で重複するように配設した請求項1記載の回路基板。
- 前記第1導体は前記スリットを少なくとも1回跨ぐように配設した請求項1記載の回路基板。
- 前記第3導体は前記第1導体と同じ配線層に形成するようにした請求項1記載の回路基板。
- 前記第3導体は線状かつ蛇行形状で形成するようにした請求項1記載の回路基板。
- 前記スリットは周回状かつ蛇行形状で形成するようにした請求項1記載の回路基板。
- 前記第2導体、前記スリット、及び前記島電極からなる構造体を前記第1導体の上下の配線層にそれぞれ形成するようにした請求項1記載の回路基板。
- 前記第1導体は信号線であり、前記第2導体はグランドプレーンであり、前記第3導体は共振線である請求項1記載の回路基板。
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US14/113,187 US8994470B2 (en) | 2011-04-28 | 2012-04-25 | Circuit substrate having noise suppression structure |
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Also Published As
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US8994470B2 (en) | 2015-03-31 |
US20140049343A1 (en) | 2014-02-20 |
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