WO2012086169A1 - 誘電体デバイスの製造方法及びアッシング方法 - Google Patents
誘電体デバイスの製造方法及びアッシング方法 Download PDFInfo
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- WO2012086169A1 WO2012086169A1 PCT/JP2011/007066 JP2011007066W WO2012086169A1 WO 2012086169 A1 WO2012086169 A1 WO 2012086169A1 JP 2011007066 W JP2011007066 W JP 2011007066W WO 2012086169 A1 WO2012086169 A1 WO 2012086169A1
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- resist mask
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- 238000000034 method Methods 0.000 title claims abstract description 63
- 238000004380 ashing Methods 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 53
- 239000007789 gas Substances 0.000 claims abstract description 50
- 239000001301 oxygen Substances 0.000 claims abstract description 38
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 38
- 239000000463 material Substances 0.000 claims abstract description 15
- -1 oxygen ions Chemical class 0.000 claims abstract description 14
- 239000011368 organic material Substances 0.000 claims abstract description 7
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims description 27
- 239000000460 chlorine Substances 0.000 claims description 15
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 11
- 229910052801 chlorine Inorganic materials 0.000 claims description 11
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims description 11
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 8
- 229910000314 transition metal oxide Inorganic materials 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 abstract description 7
- 239000000376 reactant Substances 0.000 abstract description 7
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 abstract 1
- 239000007795 chemical reaction product Substances 0.000 description 9
- 238000001312 dry etching Methods 0.000 description 8
- 238000004544 sputter deposition Methods 0.000 description 7
- 238000011282 treatment Methods 0.000 description 7
- 239000010936 titanium Substances 0.000 description 6
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 5
- 229910001882 dioxygen Inorganic materials 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 229910052451 lead zirconate titanate Inorganic materials 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910010413 TiO 2 Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- KYKAJFCTULSVSH-UHFFFAOYSA-N chloro(fluoro)methane Chemical compound F[C]Cl KYKAJFCTULSVSH-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 229910052741 iridium Inorganic materials 0.000 description 2
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N zinc oxide Inorganic materials [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- RZEADQZDBXGRSM-UHFFFAOYSA-N bismuth lanthanum Chemical compound [La].[Bi] RZEADQZDBXGRSM-UHFFFAOYSA-N 0.000 description 1
- 229910002115 bismuth titanate Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000003980 solgel method Methods 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
- H01B19/00—Apparatus or processes specially adapted for manufacturing insulators or insulating bodies
- H01B19/04—Treating the surfaces, e.g. applying coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/42—Stripping or agents therefor
- G03F7/427—Stripping or agents therefor using plasma means only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
- H01L21/31122—Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
Definitions
- the present invention relates to a method of manufacturing a dielectric device having a step of removing a resist mask used for etching and a method of ashing a resist mask.
- dielectric devices such as piezoelectric elements and memory elements have a structure in which a dielectric layer is sandwiched between a pair of electrode layers.
- This type of dielectric device is used as a piezoelectric device, a memory cell, or the like by etching the upper electrode layer and the dielectric layer into a predetermined shape.
- dry etching using an organic resist is widely known.
- a chlorine-based gas or a chlorofluorocarbon-based gas is used as an etching gas, and oxygen plasma is widely used for removing a resist mask after etching (for example, see Patent Document 1 below).
- etching using a chlorine-based gas or a chlorofluorocarbon-based gas has a problem that resist residues are easily generated during ashing of the resist mask by oxygen plasma later. It was confirmed that the resist residue was a reaction product of an etching gas generated during etching of the upper electrode layer or the dielectric layer adhered to the surface of the resist mask. Resist residue affects device characteristics. For example, with respect to a resistance change memory element (ReRAM), desired electrical characteristics cannot be stably obtained due to the resist residue.
- ReRAM resistance change memory element
- an object of the present invention is to provide a dielectric device manufacturing method and an ashing method capable of suppressing resist residues.
- a method for manufacturing a dielectric device produces a laminate in which a first electrode, a dielectric layer, and a second electrode layer are sequentially formed on a substrate.
- the process of carrying out is included.
- a resist mask made of an organic material is formed on the second electrode layer.
- the second electrode layer and the dielectric layer are sequentially etched by plasma of chlorine gas or fluorocarbon gas through the resist mask.
- the resist mask is bombarded with oxygen ions.
- the resist mask is removed by oxygen radicals.
- the ashing method includes a step of placing a substrate whose surface is etched with plasma of a chlorine-based gas or a fluorocarbon-based gas in a chamber through a resist mask formed of an organic material. Including. The resist mask is bombarded with oxygen ions in the chamber. The resist mask is removed by oxygen radicals in the chamber.
- the manufacturing method of the dielectric device which concerns on one Embodiment of this invention includes the process of producing the laminated body in which the 1st electrode, the dielectric material layer, and the 2nd electrode layer were formed in order on the base material.
- a resist mask made of an organic material is formed on the second electrode layer.
- the second electrode layer and the dielectric layer are sequentially etched by plasma of chlorine gas or fluorocarbon gas through the resist mask.
- the resist mask is bombarded with oxygen ions.
- the resist mask is removed by oxygen radicals.
- etching reactants attached to the surface of the resist mask are physically removed by bombarding with oxygen ions. Thereby, generation
- a gas containing BCl 3 is used as the chlorine-based gas
- a gas containing any of CF 4 , C 3 F 8 , C 4 F 8 and CHF 3 is used as the fluorocarbon-based gas. Used.
- oxygen is introduced into the chamber and high frequency bias power is applied to the substrate.
- the high frequency bias power generates an oxygen plasma in the chamber and further draws ions in the plasma to the substrate surface. Thereby, the etching reaction product on the resist mask surface is removed by the sputtering effect of ions.
- the base material is exposed to oxygen radicals introduced into the chamber in an electrically non-biased state.
- the resist mask is ashed by contact between the oxygen radicals and the resist mask.
- the base material since the base material is in an electrically non-biased state, it does not receive a sputtering action by ions, and therefore, etching of the first electrode layer as a base is prevented.
- the dielectric layer is appropriately selected according to the type of dielectric device.
- the dielectric device is a resistance change type memory element
- examples of the dielectric layer include CoO, NiO, CuO, Cu 2 O, TiO 2 , ZnO, Al 2 O 3 , LNO, Y 2 O 5 , SrZrO. 2 , transition metal oxides such as Ta 2 O 5 are used.
- examples of the dielectric layer include lead zirconate titanate (PZT: Pb (Zr, Ti) O 3 ), bismuth titanate (BTO: Bi 4 Ti 3 O 12 ).
- Ferroelectric materials such as bismuth lanthanum titanate (BLT: (Bi, La) 4 Ti 3 O 12 ) and lanthanum-doped lead zirconate titanate (PLZT: (PbLa) (ZrTi) O 3 ) may also be used.
- An ashing method includes a step of placing a substrate whose surface is etched with plasma of chlorine-based gas or fluorocarbon-based gas in a chamber through a resist mask formed of an organic material. Including. The resist mask is bombarded with oxygen ions in the chamber. The resist mask is removed by oxygen radicals in the chamber.
- the etching reaction product adhering to the surface of the resist mask is physically removed by bombarding with oxygen ions.
- production of the resist residue resulting from an etching reaction material can be suppressed, and a resist mask can be efficiently removed from the base-material surface.
- FIG. 1 is a schematic process diagram illustrating a dielectric device manufacturing method according to an embodiment of the present invention.
- a resistance change memory element having a structure in which a transition metal oxide layer is sandwiched between a pair of electrodes will be described as an example of a dielectric device.
- the resistance change type memory element refers to a memory element that can record and read information by electrically controlling the resistance state of a dielectric layer.
- a lower electrode made of a conductive material, a dielectric layer made of a transition metal oxide, and an upper electrode made of a conductive material are stacked in this order.
- applying a pulsed positive voltage between both electrodes puts the dielectric layer in a low resistance state
- applying a pulsed negative voltage between both electrodes puts it in a high resistance state
- a sense current is passed in the thickness direction of the dielectric layer, and a resistance value is measured to discriminate between a high resistance state and a low resistance state, thereby reading recorded information.
- FIG. 1A illustrates a manufacturing process of a stacked body.
- the insulating layer 2, the lower electrode layer 3 (first electrode layer), the dielectric layer 4, and the upper electrode layer 5 (second electrode layer) are formed on the substrate 1 (base material).
- a laminated body L having a laminated structure is produced.
- the substrate 1 may be a glass substrate or a semiconductor substrate such as a silicon substrate.
- the insulating layer 2 is made of, for example, SiO 2 .
- the lower electrode layer 3 is formed of a metal material such as Pt (platinum), Ir (iridium), Ta (tantalum), Ti (titanium), TiN (titanium nitride), Al (aluminum), or W (tungsten). .
- the lower electrode layer 3 is formed on the substrate 1 by a thin film forming method such as a sputtering method, a vacuum vapor deposition method, or a CVD method.
- the thickness of the lower electrode layer 3 is not particularly limited, and is, for example, 0.005 to 0.100 ⁇ m.
- the dielectric layer 4 is formed of a transition metal oxide layer.
- the transition metal oxide include CoO, NiO, CuO, Cu 2 O, TiO 2 , ZnO, Al 2 O 3 , LNO, Y 2 O 5 , SrZrO 2 , and Ta 2 O 5 .
- the dielectric layer 4 is formed on the lower electrode layer 3 by a thin film forming method such as a sputtering method, a CVD method, or a sol-gel method.
- the thickness of the dielectric layer 4 is not particularly limited and is, for example, 0.003 to 0.100 ⁇ m.
- the upper electrode layer 5 is formed of a metal material such as Pt, Ir, Ta, Ti, TiN, Al, and W.
- the upper electrode layer 5 is formed on the dielectric layer 4 by a thin film forming method such as sputtering, vacuum deposition, or CVD.
- the thickness of the upper electrode layer 5 is not particularly limited, and is, for example, 0.005 to 0.100 ⁇ m.
- [Upper electrode layer etching process] 1B and 1C show the etching process of the upper electrode layer 5.
- a resist mask 6 having a predetermined shape is formed on the upper electrode layer 5.
- the resist mask 6 is patterned into a predetermined shape through processing such as application of a photosensitive organic photoresist (PR), exposure, and development.
- PR photosensitive organic photoresist
- the photoresist may be a dry film resist.
- the thickness of the resist mask 6 is not particularly limited and is, for example, 0.5 to 10 ⁇ m.
- the etching method of the upper electrode layer 5 may be a dry etching method or a wet etching method.
- a dry etching method is employed, and a chlorine-based gas (for example, a mixed gas of Cl 2 and BCl 3 ) is used as an etching gas.
- the dry etching apparatus 10 has a vacuum chamber 11.
- the vacuum chamber 11 is connected to a vacuum pump 12 and can maintain the inside in a predetermined reduced pressure atmosphere.
- a stage 13 for supporting the substrate 1 on which the laminate L is formed is installed inside the vacuum chamber 11.
- the stage 13 is connected to a high frequency power supply 15 having a frequency of 400 kHz via a matching circuit 14, and a predetermined bias power can be input to the stage 13.
- a chiller 16 is further connected to the stage 13, and the substrate 1 on the stage 13 can be cooled to a predetermined temperature by the cooled He gas.
- the top surface portion of the vacuum chamber 11 facing the upper surface of the stage 13 is covered with a window 17 made of a dielectric material such as quartz, and an antenna coil 18 is installed immediately above the window 17.
- the antenna coil 18 is supplied with electric power from a high frequency power supply 20 having a frequency of 13.56 MHz through a matching circuit 19 and generates plasma of an etching gas introduced into the vacuum chamber 11 through a gas introduction line 21. Thereby, the surface of the substrate 1 on the stage 13 is etched.
- an adhesion preventing plate 22 for preventing the adhesion of the etching reaction product to the inner wall surface of the vacuum chamber 11 is installed.
- a mixed gas of Cl 2 and BCl 3 is used for etching the upper electrode layer 5.
- the etching conditions are not particularly limited.
- the pressure is 0.5 Pa
- the gas introduction amount is Cl 2 : 40 sccm
- BCl 3 10 sccm
- the antenna power (power supplied to the antenna coil 18) is 800 W
- the bias power stage 13
- the chiller temperature substrate temperature
- the etching time is 40 seconds.
- FIG. 1D shows an etching process of the dielectric layer 4.
- the resist mask 6 used as the etching mask for the upper electrode layer 5 may be used as the etching mask for the dielectric layer 4, or a resist mask formed separately may be used.
- the dry etching apparatus 10 shown in FIG. 2 is used.
- a chlorine-based gas is used as an etching gas, and in this embodiment, a mixed gas of Ar and BCl 3 is used.
- Etching conditions are not particularly limited. For example, pressure is 0.5 Pa, gas introduction amount is Ar: 40 sccm, BCl 3 : 10 sccm, antenna power is 800 W, bias power is 150 W, chiller temperature (substrate temperature) is 20 ° C., etching The time is 40 seconds.
- an ashing device 30 configured as shown in FIG. 3 is used.
- the ashing device 30 has a vacuum chamber 31.
- the vacuum chamber 31 is connected to a vacuum pump 32 and can maintain the inside in a predetermined reduced pressure atmosphere.
- a stage 33 for supporting the substrate 1 on which the etching process of the upper electrode layer 5 and the dielectric layer 4 has been completed is installed inside the vacuum chamber 31.
- the stage 33 is connected to a high frequency power source 35 having a frequency of 13.56 MHz via a matching circuit 34, and a predetermined bias power can be input to the stage 33.
- the ashing device 30 includes a plasma chamber 36, an oscillator 37, and a waveguide 38 disposed on the upper portion of the vacuum chamber 11 facing the upper surface of the stage 33.
- the oscillator 37 oscillates a microwave having a predetermined frequency (eg, 2.45 GHz).
- the waveguide 38 guides the microwave oscillated by the oscillator 37 to the plasma chamber 36 and excites the ashing gas introduced into the plasma chamber 36.
- the ashing gas oxygen or a mixed gas containing oxygen is used.
- the removal process of the resist mask 6 includes a first process and a second process.
- the first process is a bombarding process of the resist mask 6 with oxygen ions
- the second process is an ashing process of the resist mask 6 with oxygen radicals.
- the first process and the second process are performed by the common ashing device 30.
- a reaction product of chlorine-based gas or fluorocarbon-based gas generated during etching of the upper electrode layer 5 and the dielectric layer 4 easily deposits on the surface of the substrate 1 because of its low vapor pressure. For this reason, as shown in FIG. 4A, when the etching reactant R adheres to the surface of the resist mask 6, the etching reactant R is not removed by the ashing process using oxygen radicals, and the upper portion as a resist residue. It remains on the surface of the electrode layer 5. Therefore, in this embodiment, before the removal of the resist mask 6 mainly composed of oxygen radicals, the etching reaction product R adhering to the surface of the resist mask 6 is removed by bombarding with oxygen ions.
- oxygen gas is introduced into the vacuum chamber 31, and high frequency power is applied to the stage 33 from a high frequency power source 35.
- Plasma is formed by exciting the oxygen gas introduced into the vacuum chamber 31 by the bias action of the high frequency power applied to the stage 33. Further, ions (oxygen ions) in the plasma are periodically drawn into the stage 33 and struck against the surface of the substrate 1. Thereby, as shown in FIG. 4B, the etching reaction product R adhering to the surface of the resist mask 6 is physically removed.
- the treatment conditions of the first treatment are not particularly limited.
- the pressure is 27 Pa
- the amount of oxygen gas introduced is 200 sccm
- the bias power is 300 W
- the treatment time is 10 seconds.
- the oxygen gas may be introduced directly into the vacuum chamber 31 or may be introduced into the vacuum chamber 31 via the plasma chamber 36.
- the oxygen gas plasma may be formed in the plasma chamber 36 by microwave excitation.
- a second process is performed.
- a mixed gas of oxygen and nitrogen is introduced into the plasma chamber 36 as an ashing gas, and an ashing gas plasma is formed by the microwave oscillated by the oscillator 37.
- High-frequency power is not applied to the stage 33 in the vacuum chamber 31, so that the substrate 1 is in an unbiased state.
- the oxygen radicals in the plasma formed in the plasma chamber 36 flow into the vacuum chamber 31 along the exhaust flow formed by the exhaust action of the vacuum pump 32 (down flow).
- the resist mask 6 on the substrate 1 is exposed to oxygen radicals and removed by a chemical reaction with oxygen radicals (FIG. 4C).
- the treatment conditions of the second treatment are not particularly limited.
- the pressure is 276 Pa
- the gas introduction amount is O 2 : 9000 sccm
- the microwave power is 2000 W
- the treatment time is 120 seconds.
- the resist mask 6 is removed as described above.
- the etching reaction product R adhering to the surface of the resist mask 6 is physically removed by bombarding with oxygen ions. Thereby, generation
- the common vacuum chamber 31 is used in the first process and the second process, the first process and the second process described above can be continuously performed. it can. Thereby, an increase in the processing time of the resist removal process can be suppressed.
- a chlorine-based gas (Cl 2 , BCl 3 ) is used for etching the upper electrode layer 5 and the dielectric layer 4, but instead, a fluorocarbon-based gas (CF 4 , CCl 3 F 8, C 4 F 8 , CHF 3 , etc.) may be used. Even if these gases are used, the etching reaction product tends to adhere to the substrate surface, but the resist mask is removed without generating a residue by performing the ashing method (first and second treatments) described above. be able to.
- a resistance change type memory element As the dielectric device, a resistance change type memory element has been described as an example. However, the present invention is not limited to this, and the present invention is also applied to a method for manufacturing other dielectric devices such as a piezoelectric element, a ferroelectric memory element, and a capacitor in which a chlorine-based gas or a fluorocarbon-based gas is used for etching the upper electrode layer and the dielectric layer. The invention is applicable.
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Abstract
Description
上記第2の電極層の上に、有機材料で形成されたレジストマスクが形成される。
上記第2の電極層及び上記誘電体層は、上記レジストマスクを介して、塩素系ガス又はフッ化炭素系ガスのプラズマで順次エッチングされる。
上記レジストマスクは、酸素イオンによってボンバード処理される。
上記レジストマスクは、酸素ラジカルによって除去される。
上記レジストマスクは、上記チャンバ内で酸素イオンによってボンバード処理される。
上記レジストマスクは、上記チャンバ内で酸素ラジカルによって除去される。
上記第2の電極層の上に、有機材料で形成されたレジストマスクが形成される。
上記第2の電極層及び上記誘電体層は、上記レジストマスクを介して、塩素系ガス又はフッ化炭素系ガスのプラズマで順次エッチングされる。
上記レジストマスクは、酸素イオンによってボンバード処理される。
上記レジストマスクは、酸素ラジカルによって除去される。
上記レジストマスクは、上記チャンバ内で酸素イオンによってボンバード処理される。
上記レジストマスクは、上記チャンバ内で酸素ラジカルによって除去される。
図1(A)は、積層体の作製工程を示している。この工程では、基板1(基材)上に、絶縁層2と、下部電極層3(第1の電極層)と、誘電体層4と、上部電極層5(第2の電極層)との積層構造を有する積層体Lが作製される。基板1は、ガラス基板でもよいし、シリコン基板等の半導体基板でもよい。
図1(B)及び(C)は、上部電極層5のエッチング工程を示している。図1(B)に示すように、上部電極層5の上に、所定形状のレジストマスク6が形成される。レジストマスク6は、感光性有機フォトレジスト(PR)の塗布、露光、現像等の処理を経ることによって所定形状にパターニングされる。上記フォトレジストは、ドライフィルムレジストであってもよい。レジストマスク6の厚みは特に限定されず、例えば0.5~10μmである。
上部電極層5のエッチング工程の終了後、誘電体層4をエッチングし、下部電極層3を露出させる工程が実施される。図1(D)は、誘電体層4のエッチング工程を示している。
次に、図1(E)に示すようにレジストマスク6がアッシングにより除去される。これにより、誘電体デバイスPが製造される。
第1の処理では、真空チャンバ31の内部に酸素ガスが導入され、ステージ33には高周波電源35から高周波電力が印加される。ステージ33へ印加される高周波電力のバイアス作用により、真空チャンバ31に導入された酸素ガスが励起されることでプラズマが形成される。またプラズマ中のイオン(酸素イオン)はステージ33へ周期的に引き込まれて基板1の表面に叩きつけられる。これにより図4(B)に示すように、レジストマスク6の表面に付着したエッチング反応物Rが物理的に除去される。
続いて、第2の処理が実施される。第2の処理では、プラズマチャンバ36の内部にアッシングガスとして酸素と窒素の混合ガスが導入され、発振器37で発振されたマイクロ波によってアッシングガスのプラズマが形成される。真空チャンバ31内のステージ33には高周波電力は印加されず、したがって基板1は無バイアス状態とされる。
2…絶縁層
3…下部電極層
4…誘電体層
5…上部電極層
6…レジストマスク
10…ドライエッチング装置
30…アッシング装置
L…積層体
P…誘電体デバイス
R…エッチング反応物
Claims (6)
- 基材上に第1の電極と誘電体層と第2の電極層とが順に形成された積層体を作製し、
前記第2の電極層の上に、有機材料で形成されたレジストマスクを形成し、
前記レジストマスクを介して、塩素系ガス又はフッ化炭素系ガスのプラズマで前記第2の電極層及び前記誘電体層を順次エッチングし、
酸素イオンによって前記レジストマスクをボンバード処理し、
酸素ラジカルによって前記レジストマスクを除去する
誘電体デバイスの製造方法。 - 請求項1に記載の誘電体デバイスの製造方法であって、
前記塩素系ガスは、BCl3を含むガスあり、
前記フッ化炭素系ガスは、CF4、C3F8、C4F8及びCHF3のいずれかを含むガスである
誘電体デバイスの製造方法。 - 請求項1に記載の誘電体デバイスの製造方法であって、
前記レジストマスクをボンバード処理する工程は、前記チャンバ内に酸素を導入し、前記基材に高周波バイアス電力を印加する
誘電体デバイスの製造方法。 - 請求項3に記載の誘電体デバイスの製造方法であって、
前記レジストマスクを除去する工程は、前記チャンバ内に導入した酸素ラジカルに、電気的に無バイアス状態で前記基材をさらす
誘電体デバイスの製造方法。 - 請求項1に記載の誘電体デバイスの製造方法であって、
前記誘電体層は、遷移金属酸化物層である
誘電体デバイスの製造方法。 - 有機材料で形成されたレジストマスクを介して、塩素系ガス又はフッ化炭素系ガスのプラズマで表面をエッチングした基材をチャンバ内に配置し、
前記チャンバ内で酸素イオンによって前記レジストマスクをボンバード処理し、
前記チャンバ内で酸素ラジカルによって前記レジストマスクを除去する
アッシング方法。
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KR1020137015126A KR20130083469A (ko) | 2010-12-20 | 2011-12-19 | 유전체 디바이스의 제조 방법 및 애싱 방법 |
CN201180060675XA CN103262221A (zh) | 2010-12-20 | 2011-12-19 | 介电器件的制造方法和灰化方法 |
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