CN103262221A - 介电器件的制造方法和灰化方法 - Google Patents
介电器件的制造方法和灰化方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 48
- 238000004380 ashing Methods 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 116
- 239000007789 gas Substances 0.000 claims abstract description 47
- 239000001301 oxygen Substances 0.000 claims abstract description 31
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 31
- 239000000463 material Substances 0.000 claims abstract description 16
- -1 oxygen ions Chemical class 0.000 claims abstract description 14
- 239000011368 organic material Substances 0.000 claims abstract description 7
- 239000000460 chlorine Substances 0.000 claims description 19
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 15
- 229910052801 chlorine Inorganic materials 0.000 claims description 15
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 14
- PRPAGESBURMWTI-UHFFFAOYSA-N [C].[F] Chemical compound [C].[F] PRPAGESBURMWTI-UHFFFAOYSA-N 0.000 claims description 11
- 230000008676 import Effects 0.000 claims description 8
- 229910000314 transition metal oxide Inorganic materials 0.000 claims description 6
- 230000005611 electricity Effects 0.000 claims description 3
- 239000000376 reactant Substances 0.000 abstract description 19
- 150000002500 ions Chemical class 0.000 abstract description 7
- 230000008569 process Effects 0.000 abstract description 5
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 abstract 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 29
- 238000001312 dry etching Methods 0.000 description 8
- 239000010936 titanium Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 239000003595 mist Substances 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 229910052451 lead zirconate titanate Inorganic materials 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 229910010413 TiO 2 Inorganic materials 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910002115 bismuth titanate Inorganic materials 0.000 description 2
- KYKAJFCTULSVSH-UHFFFAOYSA-N chloro(fluoro)methane Chemical compound F[C]Cl KYKAJFCTULSVSH-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052741 iridium Inorganic materials 0.000 description 2
- 229910052746 lanthanum Inorganic materials 0.000 description 2
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 238000001771 vacuum deposition Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- RZEADQZDBXGRSM-UHFFFAOYSA-N bismuth lanthanum Chemical compound [La].[Bi] RZEADQZDBXGRSM-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 230000002000 scavenging effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000003980 solgel method Methods 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
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Abstract
本发明提供了能够抑制抗蚀剂残留物的介电器件的制造方法和灰化方法。在所述灰化方法中,将通过由有机材料形成的抗蚀剂掩模(6)用含氯气体或氟碳类气体的等离子体对表面进行刻蚀的基材配置在腔室内,在所述腔室内通过氧离子对所述抗蚀剂掩模(6)进行轰击处理,在所述腔室内通过氧自由基去除所述抗蚀剂掩模。根据所述灰化方法,通过氧离子进行的轰击处理,物理去除粘附于所述抗蚀剂掩模表面的刻蚀反应物。由此,可抑制由刻蚀反应物引起的抗蚀剂残留物的产生,可有效地从所述基材表面去除所述抗蚀剂掩模。
Description
技术领域
本发明涉及一种包括去除用于刻蚀的抗蚀剂掩模(resist mask)的工序的介电器件的制造方法和抗蚀剂掩模的灰化方法。
背景技术
近年来,介电器件(例如,压电元件和存储元件)均具有介电层夹持在一对电极层之间的结构。在该类介电器件通过将上电极层和介电层刻蚀为预定形状而用作压电器件、存储单元等等。使用有机抗蚀剂的干法刻蚀广泛用作上电极层和介电层的刻蚀。含氯气体或含氯氟烃气体用作刻蚀气体,氧等离子体广泛用于在刻蚀之后去除抗蚀剂掩模(例如,参见下面的专利文献1)。
专利文献1:日本特开2009-206329(段落[0042])
然而,使用含氯气体或含氯氟烃气体的刻蚀的问题在于,在之后由氧等离子体进行抗蚀剂掩模的灰化处理时很容易出现抗蚀剂残留物。已证实抗蚀剂残留物是在上电极层或介电层的刻蚀时产生的刻蚀气体的反应物粘附在抗蚀剂掩模的表面的物质。抗蚀剂残留物影响器件特性。例如,对于电阻随机存取存储器元件(ReRAM),由于抗蚀剂残留物的存在而不能稳定地获得所需的电气特性。
发明内容
鉴于上述情况,本发明的目的在于提供能够抑制抗蚀剂残留物的介电器件的制造方法和灰化方法。
为了达到上述目的,本发明一个实施方式的介电器件的制造方法包括制作在基材上依次形成第一电极、介电层和第二电极层的层压体的工序。
在所述第二电极层上,形成由有机材料形成的抗蚀剂掩模。
通过所述抗蚀剂掩模,由含氯气体或氟碳类气体的等离子体依次刻蚀所述第二电极层和所述介电层。
所述抗蚀剂掩模通过氧离子进行轰击处理。
所述抗蚀剂掩模通过氧自由基而去除。
此外,本发明的一实施方式的灰化方法包括:将通过由有机材料形成的抗蚀剂掩模用含氯气体或氟碳类气体的等离子体对表面进行刻蚀的基材配置在腔室内的工序。
所述抗蚀剂掩模在所述腔室内通过氧离子进行轰击处理。
所述抗蚀剂掩模在所述腔室内通过氧自由基而去除。
附图说明
图1为描述本发明一个实施方式的介电器件制造方法的示意性工序图;
图2为本发明一个实施方式中使用的干法刻蚀装置的示意图;
图3为本发明一个实施方式中使用的灰化装置的示意图;
图4为描述本发明一个实施方式的灰化方法的示意性工序图。
符号说明:
1 衬底
2 绝缘层
3 下电极层
4 介电层
5 上电极层
6 抗蚀剂掩模
10 干法刻蚀装置
30 灰化装置
L 层压体
P 介电器件
R 刻蚀反应物
具体实施方式
本发明的一个实施方式的介电器件的制造方法包括制作在基材上依次形成第一电极、介电层和第二电极层的层压体的工序。
在第二电极层上,形成由有机材料形成的抗蚀剂掩模。
通过所述抗蚀剂掩模,由含氯气体或氟碳类气体的等离子体对所述第二电极层和所述介电层依次进行刻蚀。
所述抗蚀剂掩模通过氧离子进行轰击处理。
所述抗蚀剂掩模通过氧自由基而去除。
在上述介电器件的制造方法中,通过使用氧离子进行的轰击处理,物理去除粘附在抗蚀剂掩模表面的刻蚀反应物。这样,抑制了由刻蚀反应物引起的抗蚀剂残留物的产生,且有效地从基材表面去除抗蚀剂掩模。因此,根据上述方法,可稳定地制造出具有所需特性的介电器件。
上述含氯气体例如可使用含有BCl3的气体,氟碳类气体例如可使用含有CF4、C3F8、C4F8和CHF3中的任一种的气体。
对抗蚀剂掩模进行轰击处理的工序包括将氧气导入到上述腔室中,将高频偏压功率施加于所述基材上。该高频偏压功率在腔室中产生氧等离子体,进而将等离子体中的离子引入基材表面。这样,抗蚀剂掩模表面的刻蚀反应物通过离子的溅射作用而去除。
去除抗蚀剂掩模的工序中,在电的无偏压状态下将基材暴露于导入腔室内的氧自由基。通过氧自由基和抗蚀剂掩模的接触,抗蚀剂掩模被灰化。此时,由于基材处于电的无偏压状态下,因此,该基材不经受离子的溅射作用。因此,避免了作为基部的第一电极层的刻蚀。
上述介电层可根据介电器件的类型适当选择。例如,在介电器件为电阻随机存取存储器元件的情况下,介电层可使用诸如CoO、NiO、CuO、Cu2O、TiO2、ZnO、Al2O3、LNO、Y2O5、SrZrO2和Ta2O5等过渡金属氧化物。
此外,在介电器件为压电元件的情况下,介电层可以是诸如锆钛酸铅(PZT:Pb(Zr,Ti)O3)、钛酸铋(BTO:Bi4Ti3O12)、镧钛酸铋(BLT:(Bi,La)4Ti3O12)和掺镧的锆钛酸铅(PLZT:(PbLa)(ZrTi)O3)等的铁电体。
本发明的一实施方式的灰化方法包括:将通过由有机材料形成的抗蚀剂掩模用含氯气体或氟碳类气体的等离子体对表面进行刻蚀的基材配置在腔室内的工序。
所述抗蚀剂掩模在所述腔室内通过氧离子进行轰击处理。
所述抗蚀剂掩模在所述腔室内通过氧自由基而去除。
在上述灰化方法中,通过使用氧离子进行的轰击处理,物理去除粘附在抗蚀剂掩模表面的刻蚀反应物。这样,可以抑制由刻蚀反应物引起的抗蚀剂残留物的产生,并能够有效地从基材表面去除抗蚀剂掩模。
下面将结合附图对本发明的实施方式进行描述。
图1为描述本发明一个实施方式的介电器件的制造方法的示意性工序图。在该实施方式中,作为介电器件,以具有过渡金属氧化物层夹持在一对电极之间的结构的电阻随机存取存储器元件为例进行说明。
这里,该电阻随机存取存储器元件是指通过电控制介电层的电阻状态可读取信息记录的存储器元件。这种存储器元件依次层压有由导电物质构成的下电极、由过渡金属氧化物构成的介电层和由导电物质构成的上电极。此外,例如通过在上电极为正极且下电极为负极,介电层在该两个电极之间施加脉冲正电压时为低电阻状态,而在该两个电极之间施加脉冲负电压时为高电阻状态,从而记录信息。此外,在介电层的厚度方向上流动感应电流,通过测量电阻值来判别高电阻态和低电阻态,从而读取记录信息。
[层压体的制作工序]
图1(A)示出了层压体的制作工序。在该工序中,制作在衬底1(基材)上具有绝缘层2、下电极层3(第一电极层)、介电层4和上电极层5(第二电极层)的层压结构的层压体L。衬底1可以是玻璃衬底,也可以是硅衬底等的半导体衬底。
绝缘层2例如由SiO2等形成。
下电极层3由铂(Pt)、铱(Ir)、钽(Ta)、钛(Ti)、氮化钛(TiN)、铝(Al)和钨(W)等金属材料形成。下电极层3通过薄膜形成法(例如,溅射法、真空沉积法和CVD法)形成在衬底1上。下电极层3的厚度没有特别限定,例如为0.005至0.100μm。
介电层4由过渡金属氧化物层形成。作为过渡金属氧化物例如使用CoO、NiO、CuO、Cu2O、TiO2、ZnO、Al2O3、LNO、Y2O5、SrZrO2、Ta2O5等等。介电层4通过薄膜形成法(例如,溅射法、CVD法和溶胶-凝胶法)形成在下电极层3上。介电层4的厚度没有特别限定,例如为0.003至0.100μm。
上电极层5由Pt、Ir、Ta、Ti、TiN、Al和W等金属材料形成。上电极层5通过薄膜形成法(例如,溅射法、真空沉积法和CVD法)形成在介电层4上。上电极层5的厚度没有特别限定,例如为0.005至0.100μm。
[上电极层的刻蚀工序]
图1(B)和图1(C)示出上电极层5的刻蚀工序。如图1(B)所示,具有预定形状的抗蚀剂掩模6形成于上电极层5上。抗蚀剂掩模6经过感光性有机光致抗蚀剂(PR)的涂敷、曝光、显影等处理,被图案化为预定形状。上述光致抗蚀剂可以是干膜抗蚀剂。抗蚀剂掩模6的厚度没有特别限定,例如为0.5至10μm。
然后,如图1(C)所示,上电极层5通过抗蚀剂掩模6来刻蚀。上电极层5的刻蚀方法可以是干法刻蚀,也可以是湿法刻蚀。在该实施方式中,采用干法刻蚀,且用含氯气体(例如,Cl2和BCl3的混合气体)作为刻蚀气体。
在上电极层5的刻蚀工序中,使用具有如图2所示结构的干法刻蚀装置。
干法刻蚀装置10包括真空腔室11。真空腔室11连接到真空泵12,可将内部保持规定的减压气氛。在真空腔室11的内部,设置了用于支撑衬底1的载置台13,在该载置台上形成层压体L。载置台13经由匹配电路14连接到频率为400kHz的高频电源15,可将规定的偏压功率输入至载置台13。载置台13还连接到冷却器16,且可通过冷却的氦气将载置台13上的衬底1冷却至规定温度。
与载置台13的上面相对的真空腔室11的顶面部分覆有由石英等介电材料形成的窗口17。在窗口17的直上方,设置有天线线圈18。天线线圈18经由匹配电路19由频率为13.56MHz的高频电源20进行供电,产生经由气体导入管道21导入到真空腔室11内部的刻蚀气体的等离子体。这样,载置台13上的衬底1的表面被刻蚀。载置台13的周围设置有用于防止刻蚀反应物粘附于真空腔室11内壁面的防粘板22。
上电极层5的刻蚀使用Cl2和BCl3的混合气体。刻蚀条件没有特别限定。例如,压强为0.5Pa,气体导入量为40sccm的Cl2和10sccm的BCl3,天线功率(供给天线线圈18的功率)为800W,偏压功率(供给载置台13的功率)为150W,冷却器温度(衬底温度)为20℃,且刻蚀时间为40秒。
[介电层的刻蚀工序]
上电极层5的刻蚀工序完成之后,进行介电层4的刻蚀,实施使下电极层3露出的工序。图1(D)示出介电层4的刻蚀工序。
在该工序中,用作上电极层5的刻蚀掩模的抗蚀剂掩模6可用作介电层4的刻蚀掩模,或者可使用单独形成的抗蚀剂掩模。
在介电层4的刻蚀工序中,例如,使用如图2所示的干法刻蚀装置10。在介电层4的刻蚀中,含氯气体用作刻蚀气体。在该实施方式中,使用Ar和BCl3的混合气体。刻蚀条件没有特别限定。例如,压强为0.5Pa,气体导入量为40sccm的Ar和10sccm的BCl3,天线功率为800W,偏压功率为150W,冷却器温度(衬底温度)为20℃,且刻蚀时间为40秒。
[抗蚀剂掩模的去除工序]
接下来,如图1(E)所示,通过灰化法去除抗蚀剂掩模6。这样,制造出介电器件P。
在抗蚀剂掩模6的去除工序中,使用如图3所示结构的灰化装置30。
灰化装置30包括真空腔室31。真空腔室31连接到真空泵32,将内部保持在规定的减压气氛。在真空腔室31的内部,设置了用于支撑上电极层5和介电层4的刻蚀工序完成后的衬底1的载置台33。载置台33经由匹配电路34连接到频率为13.56MHz的高频电源35,且可将规定的偏压功率输入至载置台33。
灰化装置30包括在与载置台33的上面相对的真空腔室11的上部配置的等离子体腔室36、振荡器37和波导管38。振荡器37发出具有规定频率(例如,2.45GHz)的微波。波导管38将振荡器37发出的微波引导至等离子体腔室36,并对导入等离子体腔室36的灰化气体进行激发。灰化气体使用氧气或包含氧气的混合气体。
抗蚀剂掩模6的去除工序包括第一处理和第二处理。第一处理为通过氧离子对抗蚀剂掩模6进行的轰击处理,第二处理为通过氧自由基对抗蚀剂掩模6进行的灰化处理。通过共同的灰化装置30来实施第一处理和第二处理。
由于蒸汽压低,因此在刻蚀上电极层5和介电层4时产生的含氯气体或氟碳类气体的反应物容易堆积在衬底1的表面上。因此,如图4(A)所示,在刻蚀反应物R粘附于抗蚀剂掩模6表面的情况下,在使用氧自由基的灰化处理中没有去除刻蚀反应物R,作为抗蚀剂残留物保留在上电极层5的表面上。为此,在该实施方式中,在以氧自由基为主体的抗蚀剂掩模6去除之前,通过氧离子进行轰击处理将粘附于抗蚀剂掩模6表面的刻蚀反应物R去除。
(第一处理)
在第一处理中,将氧气引入真空腔室31的内部,将来自高频电源35的高频功率施加于载置台33。通过施加于载置台33的高频功率的偏压作用,导入真空腔室31中的氧气被激发,因而形成等离子体。此外,等离子体中的离子(氧离子)周期性地被引到载置台33处,并对衬底1的表面进行撞击。这样,如图4(B)所示,物理去除粘附于抗蚀剂掩模6表面的刻蚀反应物R。
第一处理的处理条件没有特别限定。例如,压强为27Pa,氧气导入量为200sccm,偏压功率为300W,且处理时间为10秒。偏压功率被设置为高于上述刻蚀条件中的偏压功率,因此可有效地去除刻蚀反应物R。此外,缩短了处理时间,因此通过氧离子的溅射作用对下电极层3的刻蚀可得到抑制。
可以将氧气直接导入真空腔室31,也可经由等离子体腔室36导入入真空腔室31。此外,氧气的等离子体可通过微波激发在等离子体腔室36中形成。
(第二处理)
接着,实施第二处理。在该第二处理中,将氧和氮的混合气体作为灰化气体导入等离子体腔室36的内部,由振荡器37发出的微波形成灰化气体的等离子体。未对真空腔室31中的载置台33施加高频功率,因而衬底1处于无偏压状态。
等离子体腔室36形成的等离子体中的氧自由基沿着由真空泵32的排气作用形成的排气流流入真空腔室31(向下流动)。这样,衬底1上的抗蚀剂掩模6暴露于氧自由基,并通过与氧自由基的化学反应而去除(图4(C))。
第二处理的处理条件没有特别限定。例如,压强为276Pa,气体导入量为9000sccm的氧气和480sccm的氮气,微波的功率为2000W,且处理时间为120秒。处理中,通过使衬底1处于无偏压状态,可以控制等离子体中的离子不到达衬底1,且避免离子对下电极层3的溅射作用。此外,第二处理的处理时间设置为长于第一处理的处理时间。这样,可保证有足够的时间去除抗蚀剂掩模6。
如上所述,去除了抗蚀剂掩模6。在这一实施方式中,通过氧离子进行的轰击处理物理去除粘附于抗蚀剂掩模6表面的刻蚀反应物R。这样,可抑制由刻蚀反应物R引起的抗蚀剂残留物的产生,可有效地从基材表面去除抗蚀剂掩模6。因此,根据该实施方式,可稳定地制造出具有所需特性的介电器件P(图1(E)和图4(C))。
此外,根据该实施方式,由于上述的第一处理和第二处理使用了共同的真空腔室31,因此可连续实施上述的第一处理和第二处理。这样,抗蚀剂去除工序的处理时间的增加可得到抑制。
上文描述了本发明的实施方式,但本发明并不限于上述实施方式,毫无疑问,可在不背离本发明主旨的情况下进行各种修改。
例如,在上述实施方式中,上电极层5和介电层4的刻蚀使用含氯气体(Cl2、BCl3),但代替其,可使用氟碳类气体(CF4、C3F8、C4F8、CHF3等等)。使用这些气体也存在刻蚀反应物粘附衬底表面的倾向,但通过实施上述灰化方法(第一处理和第二处理),可在不产生残留物的情况下去除抗蚀剂掩模。
作为介电器件以电阻随机存取存储器元件为例进行了说明。本发明不限于此,也适用于对电极层和介电层的刻蚀使用含氯气体或氟碳类气体的其他介电器件(例如,压电元件、铁电存储元件和电容器)的制造方法。
Claims (6)
1.一种介电器件的制造方法,包括:
制作在基材上依次形成第一电极、介电层和第二电极层的层压体;
在所述第二电极层上形成由有机材料形成的抗蚀剂掩模;
通过所述抗蚀剂掩模,由含氯气体或氟碳类气体的等离子体依次刻蚀所述第二电极层和所述介电层;
通过氧离子对所述抗蚀剂掩模进行轰击处理;以及
通过氧自由基去除所述抗蚀剂掩模。
2.根据权利要求1所述的介电器件的制造方法,其中,
所述含氯气体为包含BCl3的气体,以及
所述氟碳类气体为包含CF4、C3F8、C4F8和CHF3中任一种的气体。
3.根据权利要求1所述的介电器件的制造方法,其中,
对所述抗蚀剂掩模进行轰击处理的工序包括将氧气导入所述腔室内,对所述基材施加高频偏压功率。
4.根据权利要求3所述的介电器件的制造方法,其中,
去除所述抗蚀剂掩模的工序包括将所述基材在电的无偏压状态下暴露于导入所述腔室内的氧自由基。
5.根据权利要求1所述的介电器件的制造方法,其中,
所述介电层为过渡金属氧化物层。
6.一种灰化方法,包括:
将通过由有机材料形成的抗蚀剂掩模用含氯气体或氟碳类气体的等离子体对表面进行刻蚀的基材配置在腔室内;
在所述腔室内通过氧离子对所述抗蚀剂掩模进行轰击处理;以及
在所述腔室内通过氧自由基去除所述抗蚀剂掩模。
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JP5205164B2 (ja) | 2008-07-29 | 2013-06-05 | 株式会社日立製作所 | ファイルシステム管理装置及び方法 |
JP2010123853A (ja) * | 2008-11-21 | 2010-06-03 | Nagaoka Univ Of Technology | 有機物の除去方法及び有機物の除去装置 |
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2011
- 2011-12-19 JP JP2012549628A patent/JPWO2012086169A1/ja active Pending
- 2011-12-19 US US13/995,846 patent/US20130284701A1/en not_active Abandoned
- 2011-12-19 WO PCT/JP2011/007066 patent/WO2012086169A1/ja active Application Filing
- 2011-12-19 KR KR1020137015126A patent/KR20130083469A/ko not_active Application Discontinuation
- 2011-12-19 CN CN201180060675XA patent/CN103262221A/zh active Pending
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US6743730B1 (en) * | 1999-09-29 | 2004-06-01 | Tokyo Electron Limited | Plasma processing method |
CN101118873A (zh) * | 2006-08-04 | 2008-02-06 | 联华电子股份有限公司 | 半导体元件及其制造方法 |
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KR20130083469A (ko) | 2013-07-22 |
WO2012086169A1 (ja) | 2012-06-28 |
US20130284701A1 (en) | 2013-10-31 |
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