WO2012055143A1 - 晶体管及其制造方法 - Google Patents

晶体管及其制造方法 Download PDF

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Publication number
WO2012055143A1
WO2012055143A1 PCT/CN2011/000263 CN2011000263W WO2012055143A1 WO 2012055143 A1 WO2012055143 A1 WO 2012055143A1 CN 2011000263 W CN2011000263 W CN 2011000263W WO 2012055143 A1 WO2012055143 A1 WO 2012055143A1
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Prior art keywords
source
drain regions
transistor
region
dislocations
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PCT/CN2011/000263
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English (en)
French (fr)
Inventor
尹海洲
朱慧珑
骆志炯
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中国科学院微电子研究所
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Application filed by 中国科学院微电子研究所 filed Critical 中国科学院微电子研究所
Priority to CN201190000074.5U priority Critical patent/CN203573956U/zh
Priority to US13/112,993 priority patent/US8507958B2/en
Publication of WO2012055143A1 publication Critical patent/WO2012055143A1/zh
Priority to US13/961,819 priority patent/US8828820B2/en

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    • H—ELECTRICITY
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H01L29/41783—Raised source or drain electrodes self aligned with the gate
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
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    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
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    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
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    • H01L21/2654—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
    • H01L21/26546—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds of electrically active species
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
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    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Definitions

  • the present invention relates to the field of semiconductor device fabrication, and more particularly to a transistor and a method of fabricating the same. Background technique
  • an integrated circuit includes a combination of an NMOS (n-type metal-oxide-semiconductor) transistor and a PMOS (p-type metal-oxide-semiconductor) transistor formed on a substrate.
  • NMOS n-type metal-oxide-semiconductor
  • PMOS p-type metal-oxide-semiconductor
  • U.S. Patent Application Serial No. 20100038685A discloses a transistor in which a dislocation is formed between a channel region and a source/drain region of the transistor, which generates a tensile stress which increases the electron mobility in the channel. Thereby the drive current of the transistor is increased.
  • Figure l la-l lc shows the formation of such dislocations.
  • silicon implantation is performed on the semiconductor substrate 1 on which the gate dielectric 2 and the gate 3 have been formed, thereby forming an amorphous region as shown by the hatched portion in the figure.
  • FIG. 1 ib the semiconductor substrate 1 is annealed to recrystallize the amorphous region. During the recrystallization process, two different crystal growth front ends in the horizontal direction and the vertical direction meet, as shown by the arrow in the figure. This shows that the dislocations shown in Fig. 11c are formed. Summary of the invention
  • the free surface is lower than the horizontal plane of the conductive channel or on the horizontal plane of the conductive channel, the tensile stress generated by the dislocations is significantly reduced.
  • metal silicide is formed over the source and drain regions.
  • the formation of silicide involves the movement of silicon and metal, which is equivalent to the creation of a free surface on the underside of the silicide that, if at the level of the conductive channel, causes tensile stresses from dislocations. Reduced.
  • the transistor of the present invention includes:
  • Source and drain regions located in the semiconductor substrate and respectively on both sides of the gate, wherein at least one of the source and drain regions includes at least one dislocation;
  • the method of manufacturing a transistor of the present invention includes the following steps:
  • a metal layer is formed on the semiconductor layer and annealed to form a metal silicide, wherein a bottom surface of the metal silicide is higher than a conductive channel between the source and drain regions.
  • a silicon-containing semiconductor layer is formed over the source and drain regions, and a metal is deposited on the semiconductor layer to form a metal silicide such that the bottom of the metal silicide is above the conductive channel.
  • the contact resistance of the source contact and the drain contact is reduced by forming a metal silicide on the one hand; on the other hand, by making the bottom of the metal silicide above the conductive channel, the source region and/or the drain region are avoided.
  • the tensile stress generated by the formed dislocations is significantly reduced.
  • Fig. 1 shows a schematic view of a transistor in accordance with a first embodiment of the present invention.
  • FIGS 2a-2b show schematic diagrams of some of the steps in fabricating the transistor of Figure 1.
  • Figure 3 shows a schematic diagram of an exemplary transistor in accordance with a second embodiment of the present invention.
  • Figures 4a-4d show schematic diagrams of some of the steps in fabricating the transistor of Figure 3.
  • Figure 5 shows a schematic diagram of another exemplary transistor in accordance with a second embodiment of the present invention.
  • FIG. 6 shows a schematic diagram of one of the steps of manufacturing the transistor shown in Fig. 5.
  • FIG. 7 shows a schematic diagram of a transistor in accordance with a third embodiment of the present invention.
  • FIGS 8a-8b show schematic diagrams of some of the steps in fabricating the transistor of Figure 7.
  • Fig. 9a schematically shows one of the steps of a transistor manufacturing method according to an example of the fourth embodiment of the present invention.
  • Fig. 9b schematically shows a crystal tube according to an example of a fourth embodiment of the present invention.
  • Fig. 10a schematically shows one of the steps of a method of manufacturing a transistor according to another example of the fourth embodiment of the present invention.
  • Fig. 10b schematically shows a crystal tube according to another example of the fourth embodiment of the present invention.
  • FIG. 1 shows a schematic diagram of a transistor in accordance with a first embodiment of the present invention.
  • transistor 100 includes a semiconductor substrate 102, a gate dielectric 104 formed on the semiconductor substrate 102, a gate 106 formed on the gate dielectric 104, and a semiconductor substrate 102 on the semiconductor substrate 102.
  • the source region 108 and the drain region 110 are located on both sides of the gate 106, respectively, and the channel region 112, which is located between the source region 108 and the drain region 110 and at the gate dielectric 104.
  • the source region 108 and the drain region 110 include dislocations 101 adjacent to the channel region 1 12 .
  • the dislocations apply tensile stress to the channel region 1 12 (as indicated by the arrows in the figure), and this tensile stress increases the electron mobility of the channel region.
  • the transistor 100 further includes: sidewall spacers 1 16 formed on the sidewalls of the gate dielectric 104 and the gate 106, a semiconductor layer 181 formed on the source region 108 and the drain region 110, and on the semiconductor layer Metal silicide layer 122.
  • the semiconductor layer 181 may be Si, SiGe or Si: C layer.
  • transistor 100 also includes source and drain contacts, as these are well known to those of ordinary skill in the art and are therefore not shown and described herein.
  • the method of forming the transistor 100 includes first forming dislocations in the source region 108 and the drain region 110 as shown in FIGS. 1 la-c, and then forming spacers 116 on the sidewalls of the gate dielectric 104 and the gate 106, And then the semiconductor layer 118 is formed on the source region 108 and the drain region 110, resulting in a structure as shown in Fig. 2a.
  • the semiconductor layer 118 can be formed by epitaxial growth, such as by sputtering, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and/or other suitable processes.
  • the semiconductor layer 118 can be typically doped.
  • a metal layer 120 such as a Ni layer, a Ti layer or a Co layer, is deposited over the semiconductor layer 118, as shown in Figure 2b.
  • a metal layer 120 such as a Ni layer, a Ti layer or a Co layer.
  • the structure obtained in FIG. 2b is annealed such that the metal in the metal layer 120 reacts with the semiconductor layer 118 to form a metal silicide layer 122, and then the unreacted portion of the metal layer 120 is removed, thereby obtaining a pattern.
  • the metal silicide bottom is above the conductive channel, and the contact resistance of the source contact and the drain contact is reduced, and the tensile stress generated by the dislocation formed in the source and drain regions is significantly reduced.
  • FIG. 3 shows an exemplary transistor 200a in accordance with a second embodiment of the present invention.
  • the transistor 200a differs from the transistor 100 of the first embodiment in that both the source region 108 and the drain region 110 contain two dislocations.
  • the dislocations are shown in Figure 3 to be disjoint, the dislocations may also be intersected.
  • Figures 4a-d illustrate some of the stages in the fabrication of transistor 200a.
  • a mask layer 114 is first formed over the semiconductor substrate 102 on which the gate dielectric 104 and the gate 106 are formed.
  • the mask layer 14 may be formed of a photoresist or a hard mask layer formed of a dielectric material such as silicon oxide and/or silicon nitride.
  • the mask layer 14 is shown as covering the gate 106 in FIG. 1, the present invention is not limited thereto, and the mask layer 114 may be formed to be flush with or lower than the gate 106.
  • the mask layer 1 14 is patterned such that both the source region 108 and the drain region 110 are partially exposed, as shown in Figure 4b.
  • the patterned mask layer 114 can be implemented by a lithography process well known in the art and is not described in detail herein.
  • the exposed portions of the source region 108 and the drain region 110 are advanced. Row ion implantation is performed to form an amorphous region 1 13 as shown in Figure 4c.
  • the mask layer 14 is removed and the resulting structure is annealed to form two dislocations in both the source region 108 and the drain region 110, as shown in Figure 4d.
  • the mask layer 14 is a hard mask, it is also possible to remove the mask layer 14 after annealing.
  • sidewalls 1 16 are formed on the sidewalls of the gate dielectric 104 and the gate 106, and after forming the spacers 166, the same steps as those shown in Figures 2a and 2b above are performed, thereby A semiconductor layer 182 and a metal silicide layer 122 are formed over the region 108 and the drain region 110. Thus, the transistor 300a shown in Fig. 3 is obtained.
  • Fig. 5 shows another exemplary transistor 200b in accordance with the present embodiment, wherein source region 108 and drain region 110 each comprise three dislocations.
  • the method of forming the transistor 200b differs from the method of forming the transistor 200a only in the step shown in FIG. 4b, that is, when the mask layer 14 is patterned, two of the source region 108 and the drain region 110 are caused. The portions are exposed and the mask layer between the two exposed portions is not removed.
  • Figure 6 shows a schematic diagram of the method steps corresponding to Figure 4b when transistor 200b is fabricated. Based on the above description, those skilled in the art will appreciate that the source region 108 and the drain region 110 are more partially exposed by patterning the mask layer 14 (the mask layer 14 between adjacent exposed portions is not Remove), more dislocations can be formed in the source and drain regions.
  • dislocations are symmetrically formed in the source region 108 and the drain region 1 10 as described above, the present invention is not limited thereto.
  • dislocations may be asymmetrically formed in source region 108 and drain region 109, which may be patterned by mask layer 141 over source region 108 and drain region 109 by employing different lithographic patterns. to realise.
  • only at least a portion of the source region 108 may be exposed while the drain region 109 is covered by the mask layer 14 to form dislocations only in the source region 108, which may avoid an increase in junction leakage current.
  • the present embodiment is also advantageous in that more dislocations are formed parallel to the surface of the substrate, so that the tensile stress acting on the channel region is enhanced, thereby the carrier mobility. Further increases are called possibilities.
  • Figure ⁇ shows a schematic diagram of a transistor in accordance with a third embodiment of the present invention.
  • the transistor 300 shown in FIG. 7 differs from the transistor 100 of FIG. 1 in that the source region 108 and the drain region 110 include adjacent channel regions 112, arranged in a direction perpendicular to the surface of the semiconductor substrate 102.
  • a set of two bits ⁇ " Accordingly, the method of manufacturing the transistor 300 in the present embodiment further includes, after performing the annealing step of the method according to the first embodiment, the source region 108 and the method of manufacturing the transistor 100 in the first embodiment.
  • the drain region 109 performs a second ion implantation step to form an amorphous region, and the second ion implantation depth d2 is smaller than the first depth dl described above, as shown in FIG. 8a.
  • Annealing is again performed after the second ion implantation step, thereby forming another dislocation 103 in the source region 108 and the drain region 110, as shown in Fig. 8b.
  • the ion implantation depth can be controlled by adjusting the ion implantation energy and dose.
  • sidewall spacers 16 may be formed on the sidewalls of the gate dielectric 104 and the gate 106. After the sidewall spacers 16 are formed, the same steps as those shown in Figs. 2a and 2b described above are performed, thereby forming the semiconductor layer 18 and the metal silicide layer 122 on the source region 108 and the drain region 110.
  • the transistor 300 shown in Fig. 7 is obtained.
  • FIG. 7 shows that the source region 108 and the drain region 1 10 respectively contain a set of two dislocations.
  • the present invention is not limited thereto, and the source region 108 and the drain region 1 10 may include a group of more than two dislocations arranged adjacent to the channel region 1 12 in a direction perpendicular to the surface of the semiconductor substrate 102. Accordingly, the more dislocations are formed by performing a plurality of ion implantation steps having different implantation depths, wherein the implantation depth in the post ion implantation step is smaller than the implantation depth of the previous ion implantation step.
  • the present embodiment is also advantageous in that a greater number of dislocations can be formed in the source region 108 and the drain region 110 as needed adjacent to the channel region, further enhancing the effect on the trench.
  • the tensile stress of the channel region correspondingly, further increases in the electron mobility of the channel region.
  • the fourth embodiment is a combination of the second embodiment and the third embodiment.
  • the transistor manufacturing method in the present embodiment may selectively select a mask layer 1 14 to be selectively formed on at least one of the source region 108 and the drain region 110 before one or more of the ion implantation steps. A portion or at least two portions thereof are exposed, in the latter case, a portion of the source region 108 and/or the drain region 110 between adjacent exposed portions is covered by the mask layer 144. In a preferred embodiment at least the source region 08 and/or the drain region 1 10 are exposed adjacent portions of the gate 106.
  • the selective formation of the mask layer can be achieved, for example, by a photolithography process well known in the art.
  • the pattern of the mask layer formed each time may be the same or different, or a mask layer formed on the source and drain regions The pattern can also be different.
  • the The mask layer is formed of a dielectric material such as silicon oxide and/or silicon nitride, so that it is not necessary to remove the mask layer during the annealing process, so that only one step of selectively forming the mask layer is performed, and it may be parallel to the liner While forming a plurality of dislocations in the direction of the bottom surface, a plurality of dislocations are formed in a direction perpendicular to the surface of the substrate by a plurality of injection-annealing steps.
  • a second ion implantation step is performed to obtain a structure as shown in FIG. 9a, and the implantation depth d2 of the second ion implantation step is obtained. , less than the first injection depth dl.
  • the mask layer 1 14 is removed after the second ion implantation step and annealed to form dislocations.
  • sidewalls 1 16 are formed on the sidewalls of the gate dielectric 104 and the gate 106, after the sidewalls 16 are formed. The same steps as those shown in Figs.
  • the transistor 400a shown in Fig. 9b is obtained. It is preferable to use a hard mask layer as the mask layer 1 14 in this example so that it is not necessary to remove the mask layer 14 in the annealing step for forming the device structure shown in Fig. 4d, thereby performing the second ion implantation step. The mask layer 14 is still retained.
  • the mask layer 1 14 is selectively formed before the second ion implantation step is performed such that the two portions of the source region 108 Upon exposure, portions of source region 108 between adjacent exposed portions are covered by mask layer 144; and drain region 110 has a portion exposed.
  • Fig. 10a shows the structure obtained after the second ion implantation step is performed after the mask layer 14 is formed. The mask layer 14 is then removed and the resulting structure is annealed, and the mask layer 14 can be removed before or after annealing as desired.
  • sidewall spacers 16 are formed on the sidewalls of gate dielectric 104 and gate 106. Thereafter, the same steps as those shown in Figs. 2a and 2b described above are performed, thereby forming a semiconductor layer '18 and a metal silicide layer 122 on the source region 108 and the drain region 110. Thereby, the transistor 400b shown in Fig. 10b is obtained.
  • the transistor in the present embodiment has at least another dislocation in the source region and/or the drain region, the at least another dislocation being farther from the channel region than the dislocation formed in the third embodiment.
  • the direction parallel to the surface of the substrate is defined as the lateral direction of the transistor, and the direction perpendicular to the surface of the substrate is defined as the longitudinal direction of the transistor.
  • the fourth embodiment can obtain more dislocations in both the longitudinal direction and the lateral direction of the transistor. Therefore, in addition to having the same advantages as the first embodiment, the tensile stress acting on the channel region (and thus the electron mobility of the channel region) in the present embodiment is further advanced Increase is possible.
  • the mask layer 14 is completely covered by the drain region 1 10 before each ion implantation step, so that no dislocations are generated in the drain region 10 to avoid an increase in junction leakage current.
  • the transistors in the above first to fourth embodiments may be NMOS transistors.
  • the semiconductor substrate may include an NMOS device region and a PMOS device region, wherein the transistor fabrication method according to the present invention is performed only in the NMOS device region.
  • the transistor may further include a semiconductor layer (not shown) over the source region 108, such as Si, silicon carbide, silicon germanium or germanium, the semiconductor layer
  • a semiconductor layer such as Si, silicon carbide, silicon germanium or germanium
  • the dislocations are not exposed to free surfaces. To prevent a reduction in tensile stress that may be caused by exposure to a free surface due to misalignment.
  • the ions implanted in the ion implantation step may be, for example, one of silicon, germanium, phosphorus, boron or arsenic or a combination thereof.
  • the annealing temperature may be more than 400 ° C, preferably 500 to 900 ° C, and the annealing time may be several seconds to several minutes.
  • steps such as sidewall formation and source/drain contact formation well known in the art can be performed to form a complete device.
  • the source and drain doping processes are performed after the formation of the dislocations
  • the present invention is not limited thereto, and the dislocations may be formed at any appropriate stage, for example, the formation source may be performed.
  • the dislocations are formed after doping with the drain.
  • the semiconductor substrate described above may be a Si substrate, a SiGe substrate, a SiC substrate, or a III-V semiconductor substrate (eg, GaAs, GaN, etc.).
  • the gate dielectric may be one of Si0 2 , ⁇ 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, A1 2 0 3 , La 2 0 3 , Zr0 2 , LaA10 or a combination thereof, and the material of the gate may be selected from the group consisting of Poly-Si, Ti, Co, Ni, Al, W, an alloy of the above metals or a metal silicide.

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Description

晶体管及其制造方法 技术领域
本发明涉及半导体器件制造领域， 尤其涉及晶体管及其制造方法。 背景技术
通常， 集成电路包含形成在衬底上的 NMOS ( n型金属 -氧化物-半 导体） 晶体管和 PMOS ( p型金属 -氧化物-半导体） 晶体管的组合。 集 成电路的性能与其所包含的晶体管的性能有直接关系。 因此， 希望提 高晶体管的驱动电流以增强其性能。
美国专利申请 NO.20100038685A公开了一种晶体管， 在该晶体管 的沟道区与源 /漏区之间形成位错， 这种位错产生拉应力， 该拉应力提 高了沟道中的电子迁移率，由此晶体管的驱动电流得以增加。图 l la-l lc 示出了这种位错的形成。 在图 1 1a 中， 对已经形成了栅极电介质 2和 栅极 3 的半导体衬底 1 进行硅注入， 从而形成非晶区域， 如图中阴影 部分所示。 在图 l ib 中， 对该半导体衬底 1 进行退火， 使得非晶区域 再结晶， 在再结晶过程中， 水平方向和竖直方向上的两个不同的晶体 生长前端相遇， 如图中箭头所示， 从而形成了图 11c所示的位错。 发明内容
当 自由表面低于导电沟道的水平面或者在导电沟道的水平面上 时， 由位错产生的拉应力会显著减小。 通常， 为了减小源极和漏极接 触的接触电阻， 会在源区和漏区上方形成金属硅化物。 然而， 硅化物 的形成涉及硅和金属的移动， 这等效于在硅化物底面产生了某种自由 表面， 这种自由表面如果在导电沟道的水平面上时， 会导致由位错产 生拉应力减小。
本发明的目的是提供一种晶体管以及一种晶体管的制造方法。
本发明的晶体管包括：
半导体衬底； ，
形成在所述半导体衬底上的栅极电介质；
形成在所述栅极电介质上的栅极； 位于所述半导体衬底中、 且分别在所述栅极两侧的源区和漏区 其中至少所述源区和漏区之一包含至少一个位错；
位于所述源区和漏区上方的含硅外延半导体层； 以及
位于所述外延半导体层上方的金属硅化物层。
本发明的制造晶体管的方法包括如下步骤：
在形成了栅极的半导体衬底上形成掩膜层， 所述掩膜层覆盖所述 栅极以及所述半导体衬底；
图形化该掩膜层， 使得至少源区和漏区之一的至少一部分暴露； 对源区和 /或漏区的暴露部分进行第一离子注入步骤；
对所述半导体衬底进行退火以在源区和 /或漏区的暴露部分形成位 错；
在源区和漏区上形成含有硅的半导体层；
在所述半导体层上形成金属层并进行退火以形成金属硅化物， 其中所述金属硅化物的底面高于位于所述源区和漏区之间的导电 沟道。
在本发明的晶体管中， 在源区和漏区上方形成含硅的半导体层， 并且在该半导体层上沉积金属以形成金属硅化物， 使得金属硅化物的 底部位于导电沟道上方。 根据本发明， 一方面通过形成金属硅化物减 小了源极接触和漏极接触的接触电阻； 另一方面通过使金属硅化物底 部在导电沟道上方， 避免了源区和 /或漏区中形成的位错产生的拉应力 显著减小。
本发明的其它方面和优点将在以下结合附图更详细地描述。 附图说明
图 1示出了根据本发明第一实施方式的晶体管的示意图。
图 2a-2b示出了制造图 1所示晶体管的一些步骤的示意图。
图 3 示出了根据本发明第二实施方式的一个示例性晶体管的示意 图。
图 4a-4d示出了制造图 3所示晶体管的一些步骤的示意图。
图 5 示出根据本发明第二实施方式的另一个示例性晶体管的示意 图。
图 6示出了制造图 5所示晶体管的步骤之一的示意图。 图 7示出了根据本发明的第三实施方式的晶体管的示意图。
图 8a-8b示出了制造图 7所示的晶体管的一些步骤的示意图。
图 9a示意性示出了根据本发明第四实施方式的一个例子的晶体管 制造方法的步骤之一。
图 9b 示意性示出了根据本发明第四实施方式的一个例子的晶体 管。
图 10a 示意性示出了根据本发明第四实施方式的另一个例子的晶 体管制造方法的步驟之一。
图 10b 示意性示出了根据本发明第四实施方式的另一个例子的晶 体管。
图 l la-l lc示出了现有技术中位错的形成。 具体实施方式
以下结合附图描述本发明的优选实施例。 附图是示意性的并未按 比例绘制， 且只是为了说明本发明的实施例而并不意图限制本发明的 保护范围。 贯穿附图相同的附图标记表示相同或相似的部件。 为了使 本发明的技术方案更加清楚， 本领域熟知的工艺步骤及器件结构在此 省略。 <第一实施方式 >
图 1 示出了根据本发明第一实施方式的晶体管的示意图。 如图 1 所示， 晶体管 100包括半导体衬底 102、 形成在所述半导体衬底 102上 的栅极电介质 104、 形成在所述栅极电介质 104上的栅极 106、 在所述 半导体衬底 102中且分别位于栅极 106两侧的源区 108和漏区 1 10、 以 及沟道区 1 12，所述沟道区 1 12位于源区 108和漏区 1 10之间且在栅极 电介质 104下方。 在图 1 所示的晶体管 100中， 所述源区 108和漏区 1 10包含毗邻所述沟道区 1 12的位错 101。 所述位错对沟道区 1 12施加 拉应力 （如图中箭头所示） ， 这种拉应力使得沟道区的电子迁移率增 加。
晶体管 100还包括： 形成在栅极电介质 104和栅极 106侧壁上的 侧墙 1 16 , 形成在所述源区 108和漏区 1 10上的半导体层 1 18， 以及位 于所述半导体层上的金属硅化物层 122。 所述半导体层 1 18可以是 Si、 SiGe或 Si:C层。 实际上， 晶体管 100还包括源极接触和漏极接触， 由 于这些都是本领域普通技术人员所熟知的， 因此在此并未示出和描述。
形成该晶体管 100的方法包括， 首先如图 l la-c中所示在源区 108 和漏区 1 10中形成位错， 然后在栅极电介质 104和栅极 106侧壁上形 成侧墙 116, 并且随后在源区 108和漏区 1 10上形成半导体层 118, 得 到如图 2a所示的结构。该半导体层 118可以通过外延生长的方式形成， 例如通过溅射， 化学气相沉积 （CVD ) 、 物理气相沉积 （PVD ) 、 原 子层沉积 （ALD ) 、 及 /或其他合适的工艺等方法形成。 所述半导体层 118 可以是典型掺杂的。 接下来， 在所述半导体层 118 上沉积金属层 120 , 例如， Ni层、 Ti层或 Co层， 如图 2b所示。 最后， 对图 2b中所 得到的结构进行退火， 使得金属层 120 中的金属与所述半导体层 118 反应生成金属硅化物层 122，并且之后除去金属层 120的未反应的部分， 从而得到如图 1所示的晶体管。
根据本实施方式， 金属硅化物底部在导电沟道上方， 在减小源极 接触和漏极接触的接触电阻的同时， 避免了源区和漏区中形成的位错 产生的拉应力显著减小。 <第二实施方式 >
图 3示出了根据本发明的第二实施方式的一个示例性晶体管 200a。 如图 3所示， 该晶体管 200a与第一实施方式的晶体管 100的区别在于， 在所述源区 108和漏区 1 10中均包含两个位错。 尽管图 3中示出所述位错 不相交， 但所述位错也可以是相交的。
图 4a-d示出了晶体管 200a的制造过程中的一些阶段。 如图 4a所 示， 首先在形成了栅极电介质 104和栅极 106的半导体衬底 102上形 成掩膜层 114。 该掩膜层 1 14可以由光刻胶形成， 或者是由诸如氧化硅 和 /或氮化硅的电介质材料形成的硬掩膜层。 尽管在图 1 中示出所述掩 膜层 1 14形成为覆盖栅极 106， 但是本发明不限于此， 掩膜层 114也可 以形成为与栅极 106齐平或者低于栅极 106。
接下来， 图形化所述掩膜层 1 14, 使得源区 108和漏区 110都有一部 分暴露， 如图 4b所示。 图形化掩膜层 114可以通过本领域熟知的光刻工 艺实现， 在此并未详细描述。
在图形化掩膜层 1 14之后， 对所述源区 108和漏区 1 10的暴露部分进 行离子注入， 以形成非晶区 1 13 , 如图 4c所示。
再接下来， 除去所述掩膜层 1 14并对所得到的结构进行退火， 从而 在源区 108和漏区 1 10中都形成两个位错， 如图 4d所示。 在掩膜层 1 14是 硬掩膜的情况下， 也可以选择在退火之后除去掩膜层 1 14。
最后， 在所述栅极电介质 104和栅极 106的侧壁上形成侧墙 1 16 , 在 形成侧墙 1 16之后， 执行与上述图 2a和 2b所示的相同的步骤， 从而在所 述源区 108和漏区 1 10上形成半导体层 1 18以及金属硅化物层 122。 由此 得到图 3所示的晶体管 300 a。
图 5示出了根据本实施方式的另一个示例性的晶体管 200b , 其中源 区 108和漏区 1 10每一个均包含三个位错。 相应地， 形成晶体管 200b的 方法与形成晶体管 200a的方法的不同之处仅在于图 4b所示的步骤， 即， 在图形化掩膜层 1 14时， 使得源区 108和漏区 1 10的两个部分暴露， 这两 个暴露部分之间的掩膜层未被除去。 图 6示出了制造晶体管 200b时与图 4b相对应的方法步骤的示意图。 基于以上的描述， 本领域技术人员可 以理解， 通过图形化掩膜层 1 14使得源区 108和漏区 1 10有更多部分暴露 (相邻的暴露部分之间的掩膜层 1 14未被除去） ， 可以在源区和漏区中 形成更多的位错。
尽管如上所述在源区 108和漏区 1 10中对称地形成位错 , 但是本发 明不限于此。 在一种变型中， 可以在源区 108和漏区 109中不对称地形 成位错， 这可以通过采用不同的光刻图案对源区 108和漏区 109上方的 掩膜层 1 14进行图形化来实现。 此外， 优选地， 可以仅使得源区 108的 至少一部分暴露而保持漏区 109被掩膜层 1 14覆盖， 从而仅在源区 108中 形成位错， 这样做可以避免结漏电流增加。
除了与上述第一实施方式相同的优点外， 本实施方式的优点还在 于平行于衬底表面形成了更多的位错， 使得作用于沟道区的拉应力增 强， 从而载流子迁移率的进一步增加称为可能。
<第三实施方式 >
图 Ί 示出了根据本发明的第三实施方式的晶体管的示意图。 图 7 所示晶体管 300与图 1所示晶体管 100的区别在于， 所述源区 108和 漏区 1 10包括毗邻沟道区 1 12、在垂直于半导体^"底 1 02的表面的方向 上排列的一组两个位^"。 相应地， 与第一实施方式中制造晶体管 100的方法相比较， 本实施 方式中制造晶体管 300的方法还包括， 在进行根据第一实施方式的方法 的退火步骤之后， 对所述源区 108和漏区 109执行第二离子注入步骤， 以形成非晶区， 该第二离子注入的深度 d2小于上述第一深度 dl , 如图 8a所示。 在该第二离子注入步骤之后再次进行退火， 从而在源区 108和 漏区 1 10中形成另一位错 103， 如图 8b所示。 可以通过调节离子注入能 量和剂量来控制离子注入深度。 之后， 可以在所述栅极电介质 104和栅 极 106的侧壁上形成侧墙 1 16。 在形成侧墙 1 16之后， 执行与上述图 2a和 2b所示的相同的步骤， 从而在所述源区 108和漏区 1 10上形成半导体层 1 18以及金属硅化物层 122。 由此得到图 7所示的晶体管 300。
虽然图 7示出了源区 108和漏区 1 10分别包含一组两个位错。 但 是本发明不限于此， 源区 108和漏区 1 10可以包括毗邻沟道区 1 12、 在 垂直于半导体衬底 102 的表面的方向上排列的一组不止两个位错。 相 应地， 通过执行更多个注入深度不同的离子注入步骤来形成所述更多 的位错， 其中在后离子注入步骤的注入深度小于先前离子注入步骤的 注入深度。
除了与第一实施方式相同的优点外， 本实施方式的优点还在于可 以在源区 108和漏区 1 10中根据需要毗邻沟道区形成更多数目的位错， 更进一步增强了作用于沟道区的拉应力， 相应地， 沟道区的电子迁移 率进一步增加也成为可能。
<第四实施方式〉
第四实施方式是第二实施方式和第三实施方式的组合。 本实施方 式中的晶体管制造方法可以选择在所述离子注入步驟中的一个或多个 之前，在至少所述源区 108和漏区 1 10之一上选择性地形成掩膜层 1 14 以使其一部分或至少两个部分暴露， 在后一种情况下， 相邻的暴露部 分之间的源区 108和 /或漏区 1 10的部分被掩膜层 1 14覆盖。 在一个优 选实施例中至少使得源区 】08和 /或漏区 1 10毗邻所述栅极 106的部分 暴露。 选择性地形成掩膜层例如可以通过本领域熟知的光刻工艺实现。
在所述离子注入步骤中的多个之前选择性地形成掩膜层的情况 下， 每一次所形成的掩膜层的图案可以相同或不同， 或者源区和漏区 上所形成的掩膜层的图案也可以是不同的。 在一个优选方案中， 所述 掩膜层由诸如氧化硅和 /或氮化硅的电介质材料形成， 这样在退火过程 中无需除去掩膜层， 从而仅需执行一次选择性地形成掩膜层的步骤， 就可以在平行于衬底表面的方向上形成多个位错的同时， 通过多次注 入-退火步骤在垂直于衬底表面的方向上形成多个位错。
作为一个非限制性的例子， 在第二实施方式中形成了图 4d所示的 器件结构之后进行第二离子注入步驟， 得到如图 9a所示的结构， 该第 二离子注入步骤的注入深度 d2，小于第一注入深度 dl。在该第二离子注 入步骤之后除去掩膜层 1 14 并且进行退火以形成位错。 然后， 在所述 栅极电介质 104和栅极 106的侧壁上形成侧墙 1 16,在形成侧墙 1 16之 后。 执行与上述图 2a和 2b所示的相同的步骤， 从而在所述源区 108 和漏区 1 10上形成半导体层 1 18 以及金属硅化物层 122， 得到了图 9b 所示的晶体管 400a。 优选在该例子中使用硬掩膜层作为掩膜层 1 14, 使得在为形成图 4d所示的器件结构执 的退火步骤中无需除去掩膜层 1 14 , 从而在进行第二离子注入步驟时仍保留所述掩膜层 1 14。
作为另一个非限制性的例子， 除了执行第三实施方式中的方法步 骤之外， 还在执行第二离子注入步骤之前， 选择性地形成掩膜层 1 14, 使得源区 108的两个部分暴露， 相邻的暴露部分之间的源区 108的部 分被掩膜层 1 14所覆盖； 而漏区 1 10有一个部分暴露。 图 10a示出了 在形成该掩膜层 1 14 后进行第二离子注入步骤后所得到的结构。 然后 除去掩膜层 1 14并且对所得到的结构进行退火， 掩膜层 1 14可以根据 需要在退火之前或之后除去。 再接下来， 在栅极电介质 104和栅极 106 的侧壁上形成侧墙 1 16。之后执行与上述图 2a和 2b所示的相同的步骤， 从而在所述源区 108和漏区 1 10上形成半导体层' 1 18 以及金属硅化物 层 122。 由此， 得到图 10b所示的晶体管 400b。
由此， 本实施方式中的晶体管在源区和 /或漏区具有至少另一个位 错， 该至少另一个位错相比于第三实施方式中形成的位错更远离所述 沟道区。
将平行于衬底表面的方向规定为晶体管的横向， 将垂直于村底表 面的方向规定为晶体管的纵向。 相比于第一、 第二、 第三实施方式， 该第四实施方式可以在晶体管的纵向上以及横向上都得到更多的位 错。 因此， 除了具有与第一实施方式相同的优点之外， 在本实施方式 中作用于沟道区的拉应力 （并且因此沟道区的电子迁移率） 更进一步 增加成为可能。
此外， 优选在该实施方式中， 在每一次离子注入步骤之前都使得 掩膜层 1 14完全覆盖漏区 1 10, 从而在漏区 1 10中不产生位错， 以避免 结漏电流增加。
上述第一至四实施方式中的晶体管可以是 NMOS晶体管。
上述第一至四实施方式所述的晶体管制造方法中， 所述半导体衬 底可以包括 NMOS器件区和 PMOS器件区，其中仅在 NMOS器件区执 行根据本发明的晶体管制造方法。
上述第一至四实施方式中： 晶体管还可以包括位于所述源区 108 上方的半导体层 （未示出） ， 该半导体层例如是 Si、 碳化硅、 硅锗或 者锗层， 该半导体层使得所述位错不暴露于自由表面。 以防止由于错 位暴露于自由表面而可能导致的拉应力减小。
在上述第一至四实施方式中， 离子注入步骤中注入的离子例如可 以是硅、 锗、 磷、 硼或砷中的一种或其组合。
在上述第一至四实施方式中， 退火温度可以大于 400 °C , 优选为 500-900°C , 退火时间可以为数秒至数分钟。
在上述第一至四实施方式所描述的方法步骤之后， 可以执行本领 域熟知的侧墙形成以及源极 /漏极接触的形成等步骤， 以形成完整的器 件。
尽管在上面的描述中， 在形成位错之后再进行形成源和漏的掺杂 工艺， 然而， 本发明不限于此， 可以在任何适当的阶段形成所述位错， 例如， 可以在进行形成源和漏的掺杂之后形成所述位错。
此外， 上文所描述的半导体衬底可以是 Si衬底、 SiGe衬底、 SiC 衬底、 或 III-V半导体衬底 （例如， GaAs、 GaN等等） 。 栅极电介质 可以使用 Si02、 ΗίΌ2、 HfSiO, HfSiON, HfTaO、 HfTiO、 HfZrO、 A1203、 La203、Zr02、LaA10中的一种或其组合，栅极的材料可以选自 Poly-Si 、 Ti 、 Co、 Ni、 Al、 W, 上述金属的合金或者金属硅化物。
以上通过示例性实施例描述了本发明的晶体管及制造晶体管的方 法， 然而， 这并不意图限制本发明的保护范围。 本领域技术人员可以 想到的上述实施例的任何修改或变型都落入由所附权利要求限定的本 发明的范围内。

Claims

权 利 要 求
1. 一种晶体管的制造方法， 该方法包括如下步骤：
在形成了栅极的半导体衬底上形成掩膜层， 所述掩膜层覆盖所述 栅极以及所述半导体衬底；
图形化该掩膜层， 使得至少源区和漏区之一的至少一部分暴露； 对源区和 /或漏区的暴露部分进行第一离子注入步骤；
对所述半导体衬底进行退火以在源区和 /或漏区的暴露部分形成位 错；
在源区和漏区上形成含有硅的半导体层；
在所述半导体层上形成金属层并进行退火以形成金属硅化物， 其中所述金属硅化物的底面高于位于所述源区和漏区之间的导电 沟道。
2. 根据权利要求 1的方法，其中图形化掩膜层使得至少源区和漏区 之一部分暴露包括： 至少使得毗邻所述栅极的至少源区和漏区之一的 一部分暴露， 或者使得至少源区和漏区之一具有至少两个暴露部分， 相邻的暴露部分之间的掩膜层未被除去。
3. 根据权利要求 1的方法， 其中在所述退火步骤之后， 进行至少一 次另外的离子注入步骤， 该至少一次另外的离子注入步骤的注入深度 小于所述第一离子注入步骤的注入深度， 并且执行多次另外的离子注 入步骤的情况下， 在后的离子注入步骤的注入深度小于在前的离子注 入步骤的注入深度；
在该至少一次另外的离子注入步驟中的每一次之后进行退火， 以 形成位错。
4. 根据权利要求 3的方法，其中在所述至少一次另外的离子注入步 骤中的一个或多个之前， 可以在源区和 /或漏区上方选择性地形成掩膜 层， 使得所述源区和 /或漏区的一部分或多个部分被覆盖， 所述多个部 分中相邻的部分之间未被所述掩膜层覆盖， 使得仅对所述源区的未被 掩膜层覆盖的区域执行离子注入。
5. 根据权利要求 1-4之一所述的方法， 所述半导体衬底包括 NMOS 器件区和 PMOS器件区， 其中仅在 NMOS器件区内执行该方法。
6. 根据权利要求 1-4之一所述的方法， 其中所述位错对位于所述源 区和漏区之间的沟道区施加拉应力， 使得沟道区的电子迁移率增加。
7. 根据权利要求 1-4之一所迷的方法， 其中在图形化掩膜层的步骤 中， 不除去漏区上方的掩膜层， 从而使得仅在所述源区形成位错。
8. 根据权利要求 1-6之一所述的方法， 其中所述半导体衬底是 Si衬 5 底、 SiGe衬底、 SiC衬底、 GaAs衬底或 GaN衬底。
9. 一种晶体管的制造方法， 包括如下步骤：
在半导体衬底上形成栅极电介质；
在所述栅极电介质上形成栅极； 10 区和漏区进 4亍离子注人；
在该离子注入之后进行退火， 使得在所述源区和漏区中均形成位 错；
在所述源区和漏区上形成含有硅的半导体层；
在所述半导体层上形成金属层并进行退火以形成金属硅化物，
1 5 其中所述金属硅化物的底面高于位于所述源区和漏区之间的导电 沟道。
10. 一种晶体管， 包括：
半导体衬底；
形成在所述半导体衬底上的栅极电介质；
0 形成在所述栅极电介质上的栅极；
位于所述半导体衬底,中、 且分别在所述栅极两侧的源区和漏区， 其中至少所述源区和漏区之一包含至少一个位错；
位于所述源区和漏区上方的含硅外延半导体层； 以及
位于所述外延半导体层上方的金属硅化物层。
5 1 1. 根据权利要求 10所述的晶体管，至少所述源区和漏区之一包括 位错， 该第一组位错包含至少两个位错。
'
12. 根据权利要求 1 1所述的晶体管，其中至少所述源区和漏区之一 还含有至少另一个位错， 该至少另一个位错相比于所述第一组位错更0 远离所述沟道区。
13. 根据权利要求 1 1所述的晶体管，其中至少所述源区和漏区之一 错， 该至少另一组位错包含至少两个位错， 且相比于所述第一组位错 更远离所述沟道区。
14. 根据权利要求 10所述的晶体管，其中至少所述源区和漏区之一 包含在平行于衬底表面的方向上排列的多个位错。
15. 根据权利要求 10-14中任一项所述的晶体管， 其中所述位错对 位于源区和漏区之间的沟道区施加拉应力， 使得所述沟道区的电子迁 移率增加。
16. 根据权利要求 10-14中任一项所述的晶体管， 其中所述晶体管 为 NMOS晶体管。 、
17. 根据权利要求 10- 14中任一项所述的晶体管， 其中所述漏区中 不含有位错。
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